drivers/scsi/mvsas/mv_init.c

   1 /*
   2  * Marvell 88SE64xx/88SE94xx pci init
   3  *
   4  * Copyright 2007 Red Hat, Inc.
   5  * Copyright 2008 Marvell. <kewei@marvell.com>
   6  * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
   7  *
   8  * This file is licensed under GPLv2.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; version 2 of the
  13  * License.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  18  * General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
  23  * USA
  24 */
  25
  26
  27 #include "mv_sas.h"
  28
  29 int interrupt_coalescing = 0x80;
  30
  31 static struct scsi_transport_template *mvs_stt;
  32 static const struct mvs_chip_info mvs_chips[] = {
  33         [chip_6320] =   { 1, 2, 0x400, 17, 16, 6,  9, &mvs_64xx_dispatch, },
  34         [chip_6440] =   { 1, 4, 0x400, 17, 16, 6,  9, &mvs_64xx_dispatch, },
  35         [chip_6485] =   { 1, 8, 0x800, 33, 32, 6, 10, &mvs_64xx_dispatch, },
  36         [chip_9180] =   { 2, 4, 0x800, 17, 64, 8,  9, &mvs_94xx_dispatch, },
  37         [chip_9480] =   { 2, 4, 0x800, 17, 64, 8,  9, &mvs_94xx_dispatch, },
  38         [chip_9445] =   { 1, 4, 0x800, 17, 64, 8, 11, &mvs_94xx_dispatch, },
  39         [chip_9485] =   { 2, 4, 0x800, 17, 64, 8, 11, &mvs_94xx_dispatch, },
  40         [chip_1300] =   { 1, 4, 0x400, 17, 16, 6,  9, &mvs_64xx_dispatch, },
  41         [chip_1320] =   { 2, 4, 0x800, 17, 64, 8,  9, &mvs_94xx_dispatch, },
  42 };
  43
  44 struct device_attribute *mvst_host_attrs[];
  45
  46 #define SOC_SAS_NUM 2
  47
  48 static struct scsi_host_template mvs_sht = {
  49         .module                 = THIS_MODULE,
  50         .name                   = DRV_NAME,
  51         .queuecommand           = sas_queuecommand,
  52         .target_alloc           = sas_target_alloc,
  53         .slave_configure        = sas_slave_configure,
  54         .scan_finished          = mvs_scan_finished,
  55         .scan_start             = mvs_scan_start,
  56         .change_queue_depth     = sas_change_queue_depth,
  57         .bios_param             = sas_bios_param,
  58         .can_queue              = 1,
  59         .this_id                = -1,
  60         .sg_tablesize           = SG_ALL,
  61         .max_sectors            = SCSI_DEFAULT_MAX_SECTORS,
  62         .use_clustering         = ENABLE_CLUSTERING,
  63         .eh_device_reset_handler = sas_eh_device_reset_handler,
  64         .eh_bus_reset_handler   = sas_eh_bus_reset_handler,
  65         .target_destroy         = sas_target_destroy,
  66         .ioctl                  = sas_ioctl,
  67         .shost_attrs            = mvst_host_attrs,
  68         .use_blk_tags           = 1,
  69         .track_queue_depth      = 1,
  70 };
  71
  72 static struct sas_domain_function_template mvs_transport_ops = {
  73         .lldd_dev_found         = mvs_dev_found,
  74         .lldd_dev_gone          = mvs_dev_gone,
  75         .lldd_execute_task      = mvs_queue_command,
  76         .lldd_control_phy       = mvs_phy_control,
  77
  78         .lldd_abort_task        = mvs_abort_task,
  79         .lldd_abort_task_set    = mvs_abort_task_set,
  80         .lldd_clear_aca         = mvs_clear_aca,
  81         .lldd_clear_task_set    = mvs_clear_task_set,
  82         .lldd_I_T_nexus_reset   = mvs_I_T_nexus_reset,
  83         .lldd_lu_reset          = mvs_lu_reset,
  84         .lldd_query_task        = mvs_query_task,
  85         .lldd_port_formed       = mvs_port_formed,
  86         .lldd_port_deformed     = mvs_port_deformed,
  87
  88 };
  89
  90 static void mvs_phy_init(struct mvs_info *mvi, int phy_id)
  91 {
  92         struct mvs_phy *phy = &mvi->phy[phy_id];
  93         struct asd_sas_phy *sas_phy = &phy->sas_phy;
  94
  95         phy->mvi = mvi;
  96         phy->port = NULL;
  97         init_timer(&phy->timer);
  98         sas_phy->enabled = (phy_id < mvi->chip->n_phy) ? 1 : 0;
  99         sas_phy->class = SAS;
 100         sas_phy->iproto = SAS_PROTOCOL_ALL;
 101         sas_phy->tproto = 0;
 102         sas_phy->type = PHY_TYPE_PHYSICAL;
 103         sas_phy->role = PHY_ROLE_INITIATOR;
 104         sas_phy->oob_mode = OOB_NOT_CONNECTED;
 105         sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN;
 106
 107         sas_phy->id = phy_id;
 108         sas_phy->sas_addr = &mvi->sas_addr[0];
 109         sas_phy->frame_rcvd = &phy->frame_rcvd[0];
 110         sas_phy->ha = (struct sas_ha_struct *)mvi->shost->hostdata;
 111         sas_phy->lldd_phy = phy;
 112 }
 113
 114 static void mvs_free(struct mvs_info *mvi)
 115 {
 116         struct mvs_wq *mwq;
 117         int slot_nr;
 118
 119         if (!mvi)
 120                 return;
 121
 122         if (mvi->flags & MVF_FLAG_SOC)
 123                 slot_nr = MVS_SOC_SLOTS;
 124         else
 125                 slot_nr = MVS_CHIP_SLOT_SZ;
 126
 127         if (mvi->dma_pool)
 128                 pci_pool_destroy(mvi->dma_pool);
 129
 130         if (mvi->tx)
 131                 dma_free_coherent(mvi->dev,
 132                                   sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ,
 133                                   mvi->tx, mvi->tx_dma);
 134         if (mvi->rx_fis)
 135                 dma_free_coherent(mvi->dev, MVS_RX_FISL_SZ,
 136                                   mvi->rx_fis, mvi->rx_fis_dma);
 137         if (mvi->rx)
 138                 dma_free_coherent(mvi->dev,
 139                                   sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1),
 140                                   mvi->rx, mvi->rx_dma);
 141         if (mvi->slot)
 142                 dma_free_coherent(mvi->dev,
 143                                   sizeof(*mvi->slot) * slot_nr,
 144                                   mvi->slot, mvi->slot_dma);
 145
 146         if (mvi->bulk_buffer)
 147                 dma_free_coherent(mvi->dev, TRASH_BUCKET_SIZE,
 148                                   mvi->bulk_buffer, mvi->bulk_buffer_dma);
 149         if (mvi->bulk_buffer1)
 150                 dma_free_coherent(mvi->dev, TRASH_BUCKET_SIZE,
 151                                   mvi->bulk_buffer1, mvi->bulk_buffer_dma1);
 152
 153         MVS_CHIP_DISP->chip_iounmap(mvi);
 154         if (mvi->shost)
 155                 scsi_host_put(mvi->shost);
 156         list_for_each_entry(mwq, &mvi->wq_list, entry)
 157                 cancel_delayed_work(&mwq->work_q);
 158         kfree(mvi->tags);
 159         kfree(mvi);
 160 }
 161
 162 #ifdef CONFIG_SCSI_MVSAS_TASKLET
 163 static void mvs_tasklet(unsigned long opaque)
 164 {
 165         u32 stat;
 166         u16 core_nr, i = 0;
 167
 168         struct mvs_info *mvi;
 169         struct sas_ha_struct *sha = (struct sas_ha_struct *)opaque;
 170
 171         core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
 172         mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];
 173
 174         if (unlikely(!mvi))
 175                 BUG_ON(1);
 176
 177         stat = MVS_CHIP_DISP->isr_status(mvi, mvi->pdev->irq);
 178         if (!stat)
 179                 goto out;
 180
 181         for (i = 0; i < core_nr; i++) {
 182                 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];
 183                 MVS_CHIP_DISP->isr(mvi, mvi->pdev->irq, stat);
 184         }
 185 out:
 186         MVS_CHIP_DISP->interrupt_enable(mvi);
 187
 188 }
 189 #endif
 190
 191 static irqreturn_t mvs_interrupt(int irq, void *opaque)
 192 {
 193         u32 core_nr;
 194         u32 stat;
 195         struct mvs_info *mvi;
 196         struct sas_ha_struct *sha = opaque;
 197 #ifndef CONFIG_SCSI_MVSAS_TASKLET
 198         u32 i;
 199 #endif
 200
 201         core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
 202         mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];
 203
 204         if (unlikely(!mvi))
 205                 return IRQ_NONE;
 206 #ifdef CONFIG_SCSI_MVSAS_TASKLET
 207         MVS_CHIP_DISP->interrupt_disable(mvi);
 208 #endif
 209
 210         stat = MVS_CHIP_DISP->isr_status(mvi, irq);
 211         if (!stat) {
 212         #ifdef CONFIG_SCSI_MVSAS_TASKLET
 213                 MVS_CHIP_DISP->interrupt_enable(mvi);
 214         #endif
 215                 return IRQ_NONE;
 216         }
 217
 218 #ifdef CONFIG_SCSI_MVSAS_TASKLET
 219         tasklet_schedule(&((struct mvs_prv_info *)sha->lldd_ha)->mv_tasklet);
 220 #else
 221         for (i = 0; i < core_nr; i++) {
 222                 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];
 223                 MVS_CHIP_DISP->isr(mvi, irq, stat);
 224         }
 225 #endif
 226         return IRQ_HANDLED;
 227 }
 228
 229 static int mvs_alloc(struct mvs_info *mvi, struct Scsi_Host *shost)
 230 {
 231         int i = 0, slot_nr;
 232         char pool_name[32];
 233
 234         if (mvi->flags & MVF_FLAG_SOC)
 235                 slot_nr = MVS_SOC_SLOTS;
 236         else
 237                 slot_nr = MVS_CHIP_SLOT_SZ;
 238
 239         spin_lock_init(&mvi->lock);
 240         for (i = 0; i < mvi->chip->n_phy; i++) {
 241                 mvs_phy_init(mvi, i);
 242                 mvi->port[i].wide_port_phymap = 0;
 243                 mvi->port[i].port_attached = 0;
 244                 INIT_LIST_HEAD(&mvi->port[i].list);
 245         }
 246         for (i = 0; i < MVS_MAX_DEVICES; i++) {
 247                 mvi->devices[i].taskfileset = MVS_ID_NOT_MAPPED;
 248                 mvi->devices[i].dev_type = SAS_PHY_UNUSED;
 249                 mvi->devices[i].device_id = i;
 250                 mvi->devices[i].dev_status = MVS_DEV_NORMAL;
 251                 init_timer(&mvi->devices[i].timer);
 252         }
 253
 254         /*
 255          * alloc and init our DMA areas
 256          */
 257         mvi->tx = dma_alloc_coherent(mvi->dev,
 258                                      sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ,
 259                                      &mvi->tx_dma, GFP_KERNEL);
 260         if (!mvi->tx)
 261                 goto err_out;
 262         memset(mvi->tx, 0, sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ);
 263         mvi->rx_fis = dma_alloc_coherent(mvi->dev, MVS_RX_FISL_SZ,
 264                                          &mvi->rx_fis_dma, GFP_KERNEL);
 265         if (!mvi->rx_fis)
 266                 goto err_out;
 267         memset(mvi->rx_fis, 0, MVS_RX_FISL_SZ);
 268
 269         mvi->rx = dma_alloc_coherent(mvi->dev,
 270                                      sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1),
 271                                      &mvi->rx_dma, GFP_KERNEL);
 272         if (!mvi->rx)
 273                 goto err_out;
 274         memset(mvi->rx, 0, sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1));
 275         mvi->rx[0] = cpu_to_le32(0xfff);
 276         mvi->rx_cons = 0xfff;
 277
 278         mvi->slot = dma_alloc_coherent(mvi->dev,
 279                                        sizeof(*mvi->slot) * slot_nr,
 280                                        &mvi->slot_dma, GFP_KERNEL);
 281         if (!mvi->slot)
 282                 goto err_out;
 283         memset(mvi->slot, 0, sizeof(*mvi->slot) * slot_nr);
 284
 285         mvi->bulk_buffer = dma_alloc_coherent(mvi->dev,
 286                                        TRASH_BUCKET_SIZE,
 287                                        &mvi->bulk_buffer_dma, GFP_KERNEL);
 288         if (!mvi->bulk_buffer)
 289                 goto err_out;
 290
 291         mvi->bulk_buffer1 = dma_alloc_coherent(mvi->dev,
 292                                        TRASH_BUCKET_SIZE,
 293                                        &mvi->bulk_buffer_dma1, GFP_KERNEL);
 294         if (!mvi->bulk_buffer1)
 295                 goto err_out;
 296
 297         sprintf(pool_name, "%s%d", "mvs_dma_pool", mvi->id);
 298         mvi->dma_pool = pci_pool_create(pool_name, mvi->pdev, MVS_SLOT_BUF_SZ, 16, 0);
 299         if (!mvi->dma_pool) {
 300                         printk(KERN_DEBUG "failed to create dma pool %s.\n", pool_name);
 301                         goto err_out;
 302         }
 303         mvi->tags_num = slot_nr;
 304
 305         /* Initialize tags */
 306         mvs_tag_init(mvi);
 307         return 0;
 308 err_out:
 309         return 1;
 310 }
 311
 312
 313 int mvs_ioremap(struct mvs_info *mvi, int bar, int bar_ex)
 314 {
 315         unsigned long res_start, res_len, res_flag, res_flag_ex = 0;
 316         struct pci_dev *pdev = mvi->pdev;
 317         if (bar_ex != -1) {
 318                 /*
 319                  * ioremap main and peripheral registers
 320                  */
 321                 res_start = pci_resource_start(pdev, bar_ex);
 322                 res_len = pci_resource_len(pdev, bar_ex);
 323                 if (!res_start || !res_len)
 324                         goto err_out;
 325
 326                 res_flag_ex = pci_resource_flags(pdev, bar_ex);
 327                 if (res_flag_ex & IORESOURCE_MEM) {
 328                         if (res_flag_ex & IORESOURCE_CACHEABLE)
 329                                 mvi->regs_ex = ioremap(res_start, res_len);
 330                         else
 331                                 mvi->regs_ex = ioremap_nocache(res_start,
 332                                                 res_len);
 333                 } else
 334                         mvi->regs_ex = (void *)res_start;
 335                 if (!mvi->regs_ex)
 336                         goto err_out;
 337         }
 338
 339         res_start = pci_resource_start(pdev, bar);
 340         res_len = pci_resource_len(pdev, bar);
 341         if (!res_start || !res_len)
 342                 goto err_out;
 343
 344         res_flag = pci_resource_flags(pdev, bar);
 345         if (res_flag & IORESOURCE_CACHEABLE)
 346                 mvi->regs = ioremap(res_start, res_len);
 347         else
 348                 mvi->regs = ioremap_nocache(res_start, res_len);
 349
 350         if (!mvi->regs) {
 351                 if (mvi->regs_ex && (res_flag_ex & IORESOURCE_MEM))
 352                         iounmap(mvi->regs_ex);
 353                 mvi->regs_ex = NULL;
 354                 goto err_out;
 355         }
 356
 357         return 0;
 358 err_out:
 359         return -1;
 360 }
 361
 362 void mvs_iounmap(void __iomem *regs)
 363 {
 364         iounmap(regs);
 365 }
 366
 367 static struct mvs_info *mvs_pci_alloc(struct pci_dev *pdev,
 368                                 const struct pci_device_id *ent,
 369                                 struct Scsi_Host *shost, unsigned int id)
 370 {
 371         struct mvs_info *mvi = NULL;
 372         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
 373
 374         mvi = kzalloc(sizeof(*mvi) +
 375                 (1L << mvs_chips[ent->driver_data].slot_width) *
 376                 sizeof(struct mvs_slot_info), GFP_KERNEL);
 377         if (!mvi)
 378                 return NULL;
 379
 380         mvi->pdev = pdev;
 381         mvi->dev = &pdev->dev;
 382         mvi->chip_id = ent->driver_data;
 383         mvi->chip = &mvs_chips[mvi->chip_id];
 384         INIT_LIST_HEAD(&mvi->wq_list);
 385
 386         ((struct mvs_prv_info *)sha->lldd_ha)->mvi[id] = mvi;
 387         ((struct mvs_prv_info *)sha->lldd_ha)->n_phy = mvi->chip->n_phy;
 388
 389         mvi->id = id;
 390         mvi->sas = sha;
 391         mvi->shost = shost;
 392
 393         mvi->tags = kzalloc(MVS_CHIP_SLOT_SZ>>3, GFP_KERNEL);
 394         if (!mvi->tags)
 395                 goto err_out;
 396
 397         if (MVS_CHIP_DISP->chip_ioremap(mvi))
 398                 goto err_out;
 399         if (!mvs_alloc(mvi, shost))
 400                 return mvi;
 401 err_out:
 402         mvs_free(mvi);
 403         return NULL;
 404 }
 405
 406 static int pci_go_64(struct pci_dev *pdev)
 407 {
 408         int rc;
 409
 410         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
 411                 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
 412                 if (rc) {
 413                         rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
 414                         if (rc) {
 415                                 dev_printk(KERN_ERR, &pdev->dev,
 416                                            "64-bit DMA enable failed\n");
 417                                 return rc;
 418                         }
 419                 }
 420         } else {
 421                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
 422                 if (rc) {
 423                         dev_printk(KERN_ERR, &pdev->dev,
 424                                    "32-bit DMA enable failed\n");
 425                         return rc;
 426                 }
 427                 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
 428                 if (rc) {
 429                         dev_printk(KERN_ERR, &pdev->dev,
 430                                    "32-bit consistent DMA enable failed\n");
 431                         return rc;
 432                 }
 433         }
 434
 435         return rc;
 436 }
 437
 438 static int mvs_prep_sas_ha_init(struct Scsi_Host *shost,
 439                                 const struct mvs_chip_info *chip_info)
 440 {
 441         int phy_nr, port_nr; unsigned short core_nr;
 442         struct asd_sas_phy **arr_phy;
 443         struct asd_sas_port **arr_port;
 444         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
 445
 446         core_nr = chip_info->n_host;
 447         phy_nr  = core_nr * chip_info->n_phy;
 448         port_nr = phy_nr;
 449
 450         memset(sha, 0x00, sizeof(struct sas_ha_struct));
 451         arr_phy  = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL);
 452         arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL);
 453         if (!arr_phy || !arr_port)
 454                 goto exit_free;
 455
 456         sha->sas_phy = arr_phy;
 457         sha->sas_port = arr_port;
 458         sha->core.shost = shost;
 459
 460         sha->lldd_ha = kzalloc(sizeof(struct mvs_prv_info), GFP_KERNEL);
 461         if (!sha->lldd_ha)
 462                 goto exit_free;
 463
 464         ((struct mvs_prv_info *)sha->lldd_ha)->n_host = core_nr;
 465
 466         shost->transportt = mvs_stt;
 467         shost->max_id = MVS_MAX_DEVICES;
 468         shost->max_lun = ~0;
 469         shost->max_channel = 1;
 470         shost->max_cmd_len = 16;
 471
 472         return 0;
 473 exit_free:
 474         kfree(arr_phy);
 475         kfree(arr_port);
 476         return -1;
 477
 478 }
 479
 480 static void  mvs_post_sas_ha_init(struct Scsi_Host *shost,
 481                         const struct mvs_chip_info *chip_info)
 482 {
 483         int can_queue, i = 0, j = 0;
 484         struct mvs_info *mvi = NULL;
 485         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
 486         unsigned short nr_core = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
 487
 488         for (j = 0; j < nr_core; j++) {
 489                 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[j];
 490                 for (i = 0; i < chip_info->n_phy; i++) {
 491                         sha->sas_phy[j * chip_info->n_phy  + i] =
 492                                 &mvi->phy[i].sas_phy;
 493                         sha->sas_port[j * chip_info->n_phy + i] =
 494                                 &mvi->port[i].sas_port;
 495                 }
 496         }
 497
 498         sha->sas_ha_name = DRV_NAME;
 499         sha->dev = mvi->dev;
 500         sha->lldd_module = THIS_MODULE;
 501         sha->sas_addr = &mvi->sas_addr[0];
 502
 503         sha->num_phys = nr_core * chip_info->n_phy;
 504
 505         if (mvi->flags & MVF_FLAG_SOC)
 506                 can_queue = MVS_SOC_CAN_QUEUE;
 507         else
 508                 can_queue = MVS_CHIP_SLOT_SZ;
 509
 510         shost->sg_tablesize = min_t(u16, SG_ALL, MVS_MAX_SG);
 511         shost->can_queue = can_queue;
 512         mvi->shost->cmd_per_lun = MVS_QUEUE_SIZE;
 513         sha->core.shost = mvi->shost;
 514 }
 515
 516 static void mvs_init_sas_add(struct mvs_info *mvi)
 517 {
 518         u8 i;
 519         for (i = 0; i < mvi->chip->n_phy; i++) {
 520                 mvi->phy[i].dev_sas_addr = 0x5005043011ab0000ULL;
 521                 mvi->phy[i].dev_sas_addr =
 522                         cpu_to_be64((u64)(*(u64 *)&mvi->phy[i].dev_sas_addr));
 523         }
 524
 525         memcpy(mvi->sas_addr, &mvi->phy[0].dev_sas_addr, SAS_ADDR_SIZE);
 526 }
 527
 528 static int mvs_pci_init(struct pci_dev *pdev, const struct pci_device_id *ent)
 529 {
 530         unsigned int rc, nhost = 0;
 531         struct mvs_info *mvi;
 532         struct mvs_prv_info *mpi;
 533         irq_handler_t irq_handler = mvs_interrupt;
 534         struct Scsi_Host *shost = NULL;
 535         const struct mvs_chip_info *chip;
 536
 537         dev_printk(KERN_INFO, &pdev->dev,
 538                 "mvsas: driver version %s\n", DRV_VERSION);
 539         rc = pci_enable_device(pdev);
 540         if (rc)
 541                 goto err_out_enable;
 542
 543         pci_set_master(pdev);
 544
 545         rc = pci_request_regions(pdev, DRV_NAME);
 546         if (rc)
 547                 goto err_out_disable;
 548
 549         rc = pci_go_64(pdev);
 550         if (rc)
 551                 goto err_out_regions;
 552
 553         shost = scsi_host_alloc(&mvs_sht, sizeof(void *));
 554         if (!shost) {
 555                 rc = -ENOMEM;
 556                 goto err_out_regions;
 557         }
 558
 559         chip = &mvs_chips[ent->driver_data];
 560         SHOST_TO_SAS_HA(shost) =
 561                 kcalloc(1, sizeof(struct sas_ha_struct), GFP_KERNEL);
 562         if (!SHOST_TO_SAS_HA(shost)) {
 563                 kfree(shost);
 564                 rc = -ENOMEM;
 565                 goto err_out_regions;
 566         }
 567
 568         rc = mvs_prep_sas_ha_init(shost, chip);
 569         if (rc) {
 570                 kfree(shost);
 571                 rc = -ENOMEM;
 572                 goto err_out_regions;
 573         }
 574
 575         pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost));
 576
 577         do {
 578                 mvi = mvs_pci_alloc(pdev, ent, shost, nhost);
 579                 if (!mvi) {
 580                         rc = -ENOMEM;
 581                         goto err_out_regions;
 582                 }
 583
 584                 memset(&mvi->hba_info_param, 0xFF,
 585                         sizeof(struct hba_info_page));
 586
 587                 mvs_init_sas_add(mvi);
 588
 589                 mvi->instance = nhost;
 590                 rc = MVS_CHIP_DISP->chip_init(mvi);
 591                 if (rc) {
 592                         mvs_free(mvi);
 593                         goto err_out_regions;
 594                 }
 595                 nhost++;
 596         } while (nhost < chip->n_host);
 597         mpi = (struct mvs_prv_info *)(SHOST_TO_SAS_HA(shost)->lldd_ha);
 598 #ifdef CONFIG_SCSI_MVSAS_TASKLET
 599         tasklet_init(&(mpi->mv_tasklet), mvs_tasklet,
 600                      (unsigned long)SHOST_TO_SAS_HA(shost));
 601 #endif
 602
 603         mvs_post_sas_ha_init(shost, chip);
 604
 605         rc = scsi_add_host(shost, &pdev->dev);
 606         if (rc)
 607                 goto err_out_shost;
 608
 609         rc = sas_register_ha(SHOST_TO_SAS_HA(shost));
 610         if (rc)
 611                 goto err_out_shost;
 612         rc = request_irq(pdev->irq, irq_handler, IRQF_SHARED,
 613                 DRV_NAME, SHOST_TO_SAS_HA(shost));
 614         if (rc)
 615                 goto err_not_sas;
 616
 617         MVS_CHIP_DISP->interrupt_enable(mvi);
 618
 619         scsi_scan_host(mvi->shost);
 620
 621         return 0;
 622
 623 err_not_sas:
 624         sas_unregister_ha(SHOST_TO_SAS_HA(shost));
 625 err_out_shost:
 626         scsi_remove_host(mvi->shost);
 627 err_out_regions:
 628         pci_release_regions(pdev);
 629 err_out_disable:
 630         pci_disable_device(pdev);
 631 err_out_enable:
 632         return rc;
 633 }
 634
 635 static void mvs_pci_remove(struct pci_dev *pdev)
 636 {
 637         unsigned short core_nr, i = 0;
 638         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
 639         struct mvs_info *mvi = NULL;
 640
 641         core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
 642         mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];
 643
 644 #ifdef CONFIG_SCSI_MVSAS_TASKLET
 645         tasklet_kill(&((struct mvs_prv_info *)sha->lldd_ha)->mv_tasklet);
 646 #endif
 647
 648         sas_unregister_ha(sha);
 649         sas_remove_host(mvi->shost);
 650         scsi_remove_host(mvi->shost);
 651
 652         MVS_CHIP_DISP->interrupt_disable(mvi);
 653         free_irq(mvi->pdev->irq, sha);
 654         for (i = 0; i < core_nr; i++) {
 655                 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];
 656                 mvs_free(mvi);
 657         }
 658         kfree(sha->sas_phy);
 659         kfree(sha->sas_port);
 660         kfree(sha);
 661         pci_release_regions(pdev);
 662         pci_disable_device(pdev);
 663         return;
 664 }
 665
 666 static struct pci_device_id mvs_pci_table[] = {
 667         { PCI_VDEVICE(MARVELL, 0x6320), chip_6320 },
 668         { PCI_VDEVICE(MARVELL, 0x6340), chip_6440 },
 669         {
 670                 .vendor         = PCI_VENDOR_ID_MARVELL,
 671                 .device         = 0x6440,
 672                 .subvendor      = PCI_ANY_ID,
 673                 .subdevice      = 0x6480,
 674                 .class          = 0,
 675                 .class_mask     = 0,
 676                 .driver_data    = chip_6485,
 677         },
 678         { PCI_VDEVICE(MARVELL, 0x6440), chip_6440 },
 679         { PCI_VDEVICE(MARVELL, 0x6485), chip_6485 },
 680         { PCI_VDEVICE(MARVELL, 0x9480), chip_9480 },
 681         { PCI_VDEVICE(MARVELL, 0x9180), chip_9180 },
 682         { PCI_VDEVICE(ARECA, PCI_DEVICE_ID_ARECA_1300), chip_1300 },
 683         { PCI_VDEVICE(ARECA, PCI_DEVICE_ID_ARECA_1320), chip_1320 },
 684         { PCI_VDEVICE(ADAPTEC2, 0x0450), chip_6440 },
 685         { PCI_VDEVICE(TTI, 0x2710), chip_9480 },
 686         { PCI_VDEVICE(TTI, 0x2720), chip_9480 },
 687         { PCI_VDEVICE(TTI, 0x2721), chip_9480 },
 688         { PCI_VDEVICE(TTI, 0x2722), chip_9480 },
 689         { PCI_VDEVICE(TTI, 0x2740), chip_9480 },
 690         { PCI_VDEVICE(TTI, 0x2744), chip_9480 },
 691         { PCI_VDEVICE(TTI, 0x2760), chip_9480 },
 692         {
 693                 .vendor         = PCI_VENDOR_ID_MARVELL_EXT,
 694                 .device         = 0x9480,
 695                 .subvendor      = PCI_ANY_ID,
 696                 .subdevice      = 0x9480,
 697                 .class          = 0,
 698                 .class_mask     = 0,
 699                 .driver_data    = chip_9480,
 700         },
 701         {
 702                 .vendor         = PCI_VENDOR_ID_MARVELL_EXT,
 703                 .device         = 0x9445,
 704                 .subvendor      = PCI_ANY_ID,
 705                 .subdevice      = 0x9480,
 706                 .class          = 0,
 707                 .class_mask     = 0,
 708                 .driver_data    = chip_9445,
 709         },
 710         {
 711                 .vendor         = PCI_VENDOR_ID_MARVELL_EXT,
 712                 .device         = 0x9485,
 713                 .subvendor      = PCI_ANY_ID,
 714                 .subdevice      = 0x9480,
 715                 .class          = 0,
 716                 .class_mask     = 0,
 717                 .driver_data    = chip_9485,
 718         },
 719         {
 720                 .vendor         = PCI_VENDOR_ID_MARVELL_EXT,
 721                 .device         = 0x9485,
 722                 .subvendor      = PCI_ANY_ID,
 723                 .subdevice      = 0x9485,
 724                 .class          = 0,
 725                 .class_mask     = 0,
 726                 .driver_data    = chip_9485,
 727         },
 728         { PCI_VDEVICE(OCZ, 0x1021), chip_9485}, /* OCZ RevoDrive3 */
 729         { PCI_VDEVICE(OCZ, 0x1022), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
 730         { PCI_VDEVICE(OCZ, 0x1040), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
 731         { PCI_VDEVICE(OCZ, 0x1041), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
 732         { PCI_VDEVICE(OCZ, 0x1042), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
 733         { PCI_VDEVICE(OCZ, 0x1043), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
 734         { PCI_VDEVICE(OCZ, 0x1044), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
 735         { PCI_VDEVICE(OCZ, 0x1080), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
 736         { PCI_VDEVICE(OCZ, 0x1083), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
 737         { PCI_VDEVICE(OCZ, 0x1084), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
 738
 739         { }     /* terminate list */
 740 };
 741
 742 static struct pci_driver mvs_pci_driver = {
 743         .name           = DRV_NAME,
 744         .id_table       = mvs_pci_table,
 745         .probe          = mvs_pci_init,
 746         .remove         = mvs_pci_remove,
 747 };
 748
 749 static ssize_t
 750 mvs_show_driver_version(struct device *cdev,
 751                 struct device_attribute *attr,  char *buffer)
 752 {
 753         return snprintf(buffer, PAGE_SIZE, "%s\n", DRV_VERSION);
 754 }
 755
 756 static DEVICE_ATTR(driver_version,
 757                          S_IRUGO,
 758                          mvs_show_driver_version,
 759                          NULL);
 760
 761 static ssize_t
 762 mvs_store_interrupt_coalescing(struct device *cdev,
 763                         struct device_attribute *attr,
 764                         const char *buffer, size_t size)
 765 {
 766         int val = 0;
 767         struct mvs_info *mvi = NULL;
 768         struct Scsi_Host *shost = class_to_shost(cdev);
 769         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
 770         u8 i, core_nr;
 771         if (buffer == NULL)
 772                 return size;
 773
 774         if (sscanf(buffer, "%d", &val) != 1)
 775                 return -EINVAL;
 776
 777         if (val >= 0x10000) {
 778                 mv_dprintk("interrupt coalescing timer %d us is"
 779                         "too long\n", val);
 780                 return strlen(buffer);
 781         }
 782
 783         interrupt_coalescing = val;
 784
 785         core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
 786         mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];
 787
 788         if (unlikely(!mvi))
 789                 return -EINVAL;
 790
 791         for (i = 0; i < core_nr; i++) {
 792                 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];
 793                 if (MVS_CHIP_DISP->tune_interrupt)
 794                         MVS_CHIP_DISP->tune_interrupt(mvi,
 795                                 interrupt_coalescing);
 796         }
 797         mv_dprintk("set interrupt coalescing time to %d us\n",
 798                 interrupt_coalescing);
 799         return strlen(buffer);
 800 }
 801
 802 static ssize_t mvs_show_interrupt_coalescing(struct device *cdev,
 803                         struct device_attribute *attr, char *buffer)
 804 {
 805         return snprintf(buffer, PAGE_SIZE, "%d\n", interrupt_coalescing);
 806 }
 807
 808 static DEVICE_ATTR(interrupt_coalescing,
 809                          S_IRUGO|S_IWUSR,
 810                          mvs_show_interrupt_coalescing,
 811                          mvs_store_interrupt_coalescing);
 812
 813 /* task handler */
 814 struct task_struct *mvs_th;
 815 static int __init mvs_init(void)
 816 {
 817         int rc;
 818         mvs_stt = sas_domain_attach_transport(&mvs_transport_ops);
 819         if (!mvs_stt)
 820                 return -ENOMEM;
 821
 822         rc = pci_register_driver(&mvs_pci_driver);
 823         if (rc)
 824                 goto err_out;
 825
 826         return 0;
 827
 828 err_out:
 829         sas_release_transport(mvs_stt);
 830         return rc;
 831 }
 832
 833 static void __exit mvs_exit(void)
 834 {
 835         pci_unregister_driver(&mvs_pci_driver);
 836         sas_release_transport(mvs_stt);
 837 }
 838
 839 struct device_attribute *mvst_host_attrs[] = {
 840         &dev_attr_driver_version,
 841         &dev_attr_interrupt_coalescing,
 842         NULL,
 843 };
 844
 845 module_init(mvs_init);
 846 module_exit(mvs_exit);
 847
 848 MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>");
 849 MODULE_DESCRIPTION("Marvell 88SE6440 SAS/SATA controller driver");
 850 MODULE_VERSION(DRV_VERSION);
 851 MODULE_LICENSE("GPL");
 852 #ifdef CONFIG_PCI
 853 MODULE_DEVICE_TABLE(pci, mvs_pci_table);
 854 #endif