drivers/scsi/qla2xxx/qla_nx2.c

   1 /*
   2  * QLogic Fibre Channel HBA Driver
   3  * Copyright (c)  2003-2014 QLogic Corporation
   4  *
   5  * See LICENSE.qla2xxx for copyright and licensing details.
   6  */
   7
   8 #include <linux/vmalloc.h>
   9 #include <linux/delay.h>
  10
  11 #include "qla_def.h"
  12 #include "qla_gbl.h"
  13
  14 #include <linux/delay.h>
  15
  16 #define TIMEOUT_100_MS 100
  17
  18 /* 8044 Flash Read/Write functions */
  19 uint32_t
  20 qla8044_rd_reg(struct qla_hw_data *ha, ulong addr)
  21 {
  22         return readl((void __iomem *) (ha->nx_pcibase + addr));
  23 }
  24
  25 void
  26 qla8044_wr_reg(struct qla_hw_data *ha, ulong addr, uint32_t val)
  27 {
  28         writel(val, (void __iomem *)((ha)->nx_pcibase + addr));
  29 }
  30
  31 int
  32 qla8044_rd_direct(struct scsi_qla_host *vha,
  33         const uint32_t crb_reg)
  34 {
  35         struct qla_hw_data *ha = vha->hw;
  36
  37         if (crb_reg < CRB_REG_INDEX_MAX)
  38                 return qla8044_rd_reg(ha, qla8044_reg_tbl[crb_reg]);
  39         else
  40                 return QLA_FUNCTION_FAILED;
  41 }
  42
  43 void
  44 qla8044_wr_direct(struct scsi_qla_host *vha,
  45         const uint32_t crb_reg,
  46         const uint32_t value)
  47 {
  48         struct qla_hw_data *ha = vha->hw;
  49
  50         if (crb_reg < CRB_REG_INDEX_MAX)
  51                 qla8044_wr_reg(ha, qla8044_reg_tbl[crb_reg], value);
  52 }
  53
  54 static int
  55 qla8044_set_win_base(scsi_qla_host_t *vha, uint32_t addr)
  56 {
  57         uint32_t val;
  58         int ret_val = QLA_SUCCESS;
  59         struct qla_hw_data *ha = vha->hw;
  60
  61         qla8044_wr_reg(ha, QLA8044_CRB_WIN_FUNC(ha->portnum), addr);
  62         val = qla8044_rd_reg(ha, QLA8044_CRB_WIN_FUNC(ha->portnum));
  63
  64         if (val != addr) {
  65                 ql_log(ql_log_warn, vha, 0xb087,
  66                     "%s: Failed to set register window : "
  67                     "addr written 0x%x, read 0x%x!\n",
  68                     __func__, addr, val);
  69                 ret_val = QLA_FUNCTION_FAILED;
  70         }
  71         return ret_val;
  72 }
  73
  74 static int
  75 qla8044_rd_reg_indirect(scsi_qla_host_t *vha, uint32_t addr, uint32_t *data)
  76 {
  77         int ret_val = QLA_SUCCESS;
  78         struct qla_hw_data *ha = vha->hw;
  79
  80         ret_val = qla8044_set_win_base(vha, addr);
  81         if (!ret_val)
  82                 *data = qla8044_rd_reg(ha, QLA8044_WILDCARD);
  83         else
  84                 ql_log(ql_log_warn, vha, 0xb088,
  85                     "%s: failed read of addr 0x%x!\n", __func__, addr);
  86         return ret_val;
  87 }
  88
  89 static int
  90 qla8044_wr_reg_indirect(scsi_qla_host_t *vha, uint32_t addr, uint32_t data)
  91 {
  92         int ret_val = QLA_SUCCESS;
  93         struct qla_hw_data *ha = vha->hw;
  94
  95         ret_val = qla8044_set_win_base(vha, addr);
  96         if (!ret_val)
  97                 qla8044_wr_reg(ha, QLA8044_WILDCARD, data);
  98         else
  99                 ql_log(ql_log_warn, vha, 0xb089,
 100                     "%s: failed wrt to addr 0x%x, data 0x%x\n",
 101                     __func__, addr, data);
 102         return ret_val;
 103 }
 104
 105 /*
 106  * qla8044_read_write_crb_reg - Read from raddr and write value to waddr.
 107  *
 108  * @ha : Pointer to adapter structure
 109  * @raddr : CRB address to read from
 110  * @waddr : CRB address to write to
 111  *
 112  */
 113 static void
 114 qla8044_read_write_crb_reg(struct scsi_qla_host *vha,
 115         uint32_t raddr, uint32_t waddr)
 116 {
 117         uint32_t value;
 118
 119         qla8044_rd_reg_indirect(vha, raddr, &value);
 120         qla8044_wr_reg_indirect(vha, waddr, value);
 121 }
 122
 123 static int
 124 qla8044_poll_wait_for_ready(struct scsi_qla_host *vha, uint32_t addr1,
 125         uint32_t mask)
 126 {
 127         unsigned long timeout;
 128         uint32_t temp;
 129
 130         /* jiffies after 100ms */
 131         timeout = jiffies + msecs_to_jiffies(TIMEOUT_100_MS);
 132         do {
 133                 qla8044_rd_reg_indirect(vha, addr1, &temp);
 134                 if ((temp & mask) != 0)
 135                         break;
 136                 if (time_after_eq(jiffies, timeout)) {
 137                         ql_log(ql_log_warn, vha, 0xb151,
 138                                 "Error in processing rdmdio entry\n");
 139                         return -1;
 140                 }
 141         } while (1);
 142
 143         return 0;
 144 }
 145
 146 static uint32_t
 147 qla8044_ipmdio_rd_reg(struct scsi_qla_host *vha,
 148         uint32_t addr1, uint32_t addr3, uint32_t mask, uint32_t addr)
 149 {
 150         uint32_t temp;
 151         int ret = 0;
 152
 153         ret = qla8044_poll_wait_for_ready(vha, addr1, mask);
 154         if (ret == -1)
 155                 return -1;
 156
 157         temp = (0x40000000 | addr);
 158         qla8044_wr_reg_indirect(vha, addr1, temp);
 159
 160         ret = qla8044_poll_wait_for_ready(vha, addr1, mask);
 161         if (ret == -1)
 162                 return 0;
 163
 164         qla8044_rd_reg_indirect(vha, addr3, &ret);
 165
 166         return ret;
 167 }
 168
 169
 170 static int
 171 qla8044_poll_wait_ipmdio_bus_idle(struct scsi_qla_host *vha,
 172         uint32_t addr1, uint32_t addr2, uint32_t addr3, uint32_t mask)
 173 {
 174         unsigned long timeout;
 175         uint32_t temp;
 176
 177         /* jiffies after 100 msecs */
 178         timeout = jiffies + (HZ / 1000) * TIMEOUT_100_MS;
 179         do {
 180                 temp = qla8044_ipmdio_rd_reg(vha, addr1, addr3, mask, addr2);
 181                 if ((temp & 0x1) != 1)
 182                         break;
 183         } while (!time_after_eq(jiffies, timeout));
 184
 185         if (time_after_eq(jiffies, timeout)) {
 186                 ql_log(ql_log_warn, vha, 0xb152,
 187                     "Error in processing mdiobus idle\n");
 188                 return -1;
 189         }
 190
 191         return 0;
 192 }
 193
 194 static int
 195 qla8044_ipmdio_wr_reg(struct scsi_qla_host *vha, uint32_t addr1,
 196         uint32_t addr3, uint32_t mask, uint32_t addr, uint32_t value)
 197 {
 198         int ret = 0;
 199
 200         ret = qla8044_poll_wait_for_ready(vha, addr1, mask);
 201         if (ret == -1)
 202                 return -1;
 203
 204         qla8044_wr_reg_indirect(vha, addr3, value);
 205         qla8044_wr_reg_indirect(vha, addr1, addr);
 206
 207         ret = qla8044_poll_wait_for_ready(vha, addr1, mask);
 208         if (ret == -1)
 209                 return -1;
 210
 211         return 0;
 212 }
 213 /*
 214  * qla8044_rmw_crb_reg - Read value from raddr, AND with test_mask,
 215  * Shift Left,Right/OR/XOR with values RMW header and write value to waddr.
 216  *
 217  * @vha : Pointer to adapter structure
 218  * @raddr : CRB address to read from
 219  * @waddr : CRB address to write to
 220  * @p_rmw_hdr : header with shift/or/xor values.
 221  *
 222  */
 223 static void
 224 qla8044_rmw_crb_reg(struct scsi_qla_host *vha,
 225         uint32_t raddr, uint32_t waddr, struct qla8044_rmw *p_rmw_hdr)
 226 {
 227         uint32_t value;
 228
 229         if (p_rmw_hdr->index_a)
 230                 value = vha->reset_tmplt.array[p_rmw_hdr->index_a];
 231         else
 232                 qla8044_rd_reg_indirect(vha, raddr, &value);
 233         value &= p_rmw_hdr->test_mask;
 234         value <<= p_rmw_hdr->shl;
 235         value >>= p_rmw_hdr->shr;
 236         value |= p_rmw_hdr->or_value;
 237         value ^= p_rmw_hdr->xor_value;
 238         qla8044_wr_reg_indirect(vha, waddr, value);
 239         return;
 240 }
 241
 242 inline void
 243 qla8044_set_qsnt_ready(struct scsi_qla_host *vha)
 244 {
 245         uint32_t qsnt_state;
 246         struct qla_hw_data *ha = vha->hw;
 247
 248         qsnt_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX);
 249         qsnt_state |= (1 << ha->portnum);
 250         qla8044_wr_direct(vha, QLA8044_CRB_DRV_STATE_INDEX, qsnt_state);
 251         ql_log(ql_log_info, vha, 0xb08e, "%s(%ld): qsnt_state: 0x%08x\n",
 252              __func__, vha->host_no, qsnt_state);
 253 }
 254
 255 void
 256 qla8044_clear_qsnt_ready(struct scsi_qla_host *vha)
 257 {
 258         uint32_t qsnt_state;
 259         struct qla_hw_data *ha = vha->hw;
 260
 261         qsnt_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX);
 262         qsnt_state &= ~(1 << ha->portnum);
 263         qla8044_wr_direct(vha, QLA8044_CRB_DRV_STATE_INDEX, qsnt_state);
 264         ql_log(ql_log_info, vha, 0xb08f, "%s(%ld): qsnt_state: 0x%08x\n",
 265             __func__, vha->host_no, qsnt_state);
 266 }
 267
 268 /**
 269  *
 270  * qla8044_lock_recovery - Recovers the idc_lock.
 271  * @ha : Pointer to adapter structure
 272  *
 273  * Lock Recovery Register
 274  * 5-2  Lock recovery owner: Function ID of driver doing lock recovery,
 275  *      valid if bits 1..0 are set by driver doing lock recovery.
 276  * 1-0  1 - Driver intends to force unlock the IDC lock.
 277  *      2 - Driver is moving forward to unlock the IDC lock. Driver clears
 278  *          this field after force unlocking the IDC lock.
 279  *
 280  * Lock Recovery process
 281  * a. Read the IDC_LOCK_RECOVERY register. If the value in bits 1..0 is
 282  *    greater than 0, then wait for the other driver to unlock otherwise
 283  *    move to the next step.
 284  * b. Indicate intent to force-unlock by writing 1h to the IDC_LOCK_RECOVERY
 285  *    register bits 1..0 and also set the function# in bits 5..2.
 286  * c. Read the IDC_LOCK_RECOVERY register again after a delay of 200ms.
 287  *    Wait for the other driver to perform lock recovery if the function
 288  *    number in bits 5..2 has changed, otherwise move to the next step.
 289  * d. Write a value of 2h to the IDC_LOCK_RECOVERY register bits 1..0
 290  *    leaving your function# in bits 5..2.
 291  * e. Force unlock using the DRIVER_UNLOCK register and immediately clear
 292  *    the IDC_LOCK_RECOVERY bits 5..0 by writing 0.
 293  **/
 294 static int
 295 qla8044_lock_recovery(struct scsi_qla_host *vha)
 296 {
 297         uint32_t lock = 0, lockid;
 298         struct qla_hw_data *ha = vha->hw;
 299
 300         lockid = qla8044_rd_reg(ha, QLA8044_DRV_LOCKRECOVERY);
 301
 302         /* Check for other Recovery in progress, go wait */
 303         if ((lockid & IDC_LOCK_RECOVERY_STATE_MASK) != 0)
 304                 return QLA_FUNCTION_FAILED;
 305
 306         /* Intent to Recover */
 307         qla8044_wr_reg(ha, QLA8044_DRV_LOCKRECOVERY,
 308             (ha->portnum <<
 309              IDC_LOCK_RECOVERY_STATE_SHIFT_BITS) | INTENT_TO_RECOVER);
 310         msleep(200);
 311
 312         /* Check Intent to Recover is advertised */
 313         lockid = qla8044_rd_reg(ha, QLA8044_DRV_LOCKRECOVERY);
 314         if ((lockid & IDC_LOCK_RECOVERY_OWNER_MASK) != (ha->portnum <<
 315             IDC_LOCK_RECOVERY_STATE_SHIFT_BITS))
 316                 return QLA_FUNCTION_FAILED;
 317
 318         ql_dbg(ql_dbg_p3p, vha, 0xb08B, "%s:%d: IDC Lock recovery initiated\n"
 319             , __func__, ha->portnum);
 320
 321         /* Proceed to Recover */
 322         qla8044_wr_reg(ha, QLA8044_DRV_LOCKRECOVERY,
 323             (ha->portnum << IDC_LOCK_RECOVERY_STATE_SHIFT_BITS) |
 324             PROCEED_TO_RECOVER);
 325
 326         /* Force Unlock() */
 327         qla8044_wr_reg(ha, QLA8044_DRV_LOCK_ID, 0xFF);
 328         qla8044_rd_reg(ha, QLA8044_DRV_UNLOCK);
 329
 330         /* Clear bits 0-5 in IDC_RECOVERY register*/
 331         qla8044_wr_reg(ha, QLA8044_DRV_LOCKRECOVERY, 0);
 332
 333         /* Get lock() */
 334         lock = qla8044_rd_reg(ha, QLA8044_DRV_LOCK);
 335         if (lock) {
 336                 lockid = qla8044_rd_reg(ha, QLA8044_DRV_LOCK_ID);
 337                 lockid = ((lockid + (1 << 8)) & ~0xFF) | ha->portnum;
 338                 qla8044_wr_reg(ha, QLA8044_DRV_LOCK_ID, lockid);
 339                 return QLA_SUCCESS;
 340         } else
 341                 return QLA_FUNCTION_FAILED;
 342 }
 343
 344 int
 345 qla8044_idc_lock(struct qla_hw_data *ha)
 346 {
 347         uint32_t ret_val = QLA_SUCCESS, timeout = 0, status = 0;
 348         uint32_t lock_id, lock_cnt, func_num, tmo_owner = 0, first_owner = 0;
 349         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
 350
 351         while (status == 0) {
 352                 /* acquire semaphore5 from PCI HW block */
 353                 status = qla8044_rd_reg(ha, QLA8044_DRV_LOCK);
 354
 355                 if (status) {
 356                         /* Increment Counter (8-31) and update func_num (0-7) on
 357                          * getting a successful lock  */
 358                         lock_id = qla8044_rd_reg(ha, QLA8044_DRV_LOCK_ID);
 359                         lock_id = ((lock_id + (1 << 8)) & ~0xFF) | ha->portnum;
 360                         qla8044_wr_reg(ha, QLA8044_DRV_LOCK_ID, lock_id);
 361                         break;
 362                 }
 363
 364                 if (timeout == 0)
 365                         first_owner = qla8044_rd_reg(ha, QLA8044_DRV_LOCK_ID);
 366
 367                 if (++timeout >=
 368                     (QLA8044_DRV_LOCK_TIMEOUT / QLA8044_DRV_LOCK_MSLEEP)) {
 369                         tmo_owner = qla8044_rd_reg(ha, QLA8044_DRV_LOCK_ID);
 370                         func_num = tmo_owner & 0xFF;
 371                         lock_cnt = tmo_owner >> 8;
 372                         ql_log(ql_log_warn, vha, 0xb114,
 373                             "%s: Lock by func %d failed after 2s, lock held "
 374                             "by func %d, lock count %d, first_owner %d\n",
 375                             __func__, ha->portnum, func_num, lock_cnt,
 376                             (first_owner & 0xFF));
 377                         if (first_owner != tmo_owner) {
 378                                 /* Some other driver got lock,
 379                                  * OR same driver got lock again (counter
 380                                  * value changed), when we were waiting for
 381                                  * lock. Retry for another 2 sec */
 382                                 ql_dbg(ql_dbg_p3p, vha, 0xb115,
 383                                     "%s: %d: IDC lock failed\n",
 384                                     __func__, ha->portnum);
 385                                 timeout = 0;
 386                         } else {
 387                                 /* Same driver holding lock > 2sec.
 388                                  * Force Recovery */
 389                                 if (qla8044_lock_recovery(vha) == QLA_SUCCESS) {
 390                                         /* Recovered and got lock */
 391                                         ret_val = QLA_SUCCESS;
 392                                         ql_dbg(ql_dbg_p3p, vha, 0xb116,
 393                                             "%s:IDC lock Recovery by %d"
 394                                             "successful...\n", __func__,
 395                                              ha->portnum);
 396                                 }
 397                                 /* Recovery Failed, some other function
 398                                  * has the lock, wait for 2secs
 399                                  * and retry
 400                                  */
 401                                  ql_dbg(ql_dbg_p3p, vha, 0xb08a,
 402                                      "%s: IDC lock Recovery by %d "
 403                                      "failed, Retrying timout\n", __func__,
 404                                      ha->portnum);
 405                                  timeout = 0;
 406                         }
 407                 }
 408                 msleep(QLA8044_DRV_LOCK_MSLEEP);
 409         }
 410         return ret_val;
 411 }
 412
 413 void
 414 qla8044_idc_unlock(struct qla_hw_data *ha)
 415 {
 416         int id;
 417         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
 418
 419         id = qla8044_rd_reg(ha, QLA8044_DRV_LOCK_ID);
 420
 421         if ((id & 0xFF) != ha->portnum) {
 422                 ql_log(ql_log_warn, vha, 0xb118,
 423                     "%s: IDC Unlock by %d failed, lock owner is %d!\n",
 424                     __func__, ha->portnum, (id & 0xFF));
 425                 return;
 426         }
 427
 428         /* Keep lock counter value, update the ha->func_num to 0xFF */
 429         qla8044_wr_reg(ha, QLA8044_DRV_LOCK_ID, (id | 0xFF));
 430         qla8044_rd_reg(ha, QLA8044_DRV_UNLOCK);
 431 }
 432
 433 /* 8044 Flash Lock/Unlock functions */
 434 static int
 435 qla8044_flash_lock(scsi_qla_host_t *vha)
 436 {
 437         int lock_owner;
 438         int timeout = 0;
 439         uint32_t lock_status = 0;
 440         int ret_val = QLA_SUCCESS;
 441         struct qla_hw_data *ha = vha->hw;
 442
 443         while (lock_status == 0) {
 444                 lock_status = qla8044_rd_reg(ha, QLA8044_FLASH_LOCK);
 445                 if (lock_status)
 446                         break;
 447
 448                 if (++timeout >= QLA8044_FLASH_LOCK_TIMEOUT / 20) {
 449                         lock_owner = qla8044_rd_reg(ha,
 450                             QLA8044_FLASH_LOCK_ID);
 451                         ql_log(ql_log_warn, vha, 0xb113,
 452                             "%s: Simultaneous flash access by following ports, active port = %d: accessing port = %d",
 453                             __func__, ha->portnum, lock_owner);
 454                         ret_val = QLA_FUNCTION_FAILED;
 455                         break;
 456                 }
 457                 msleep(20);
 458         }
 459         qla8044_wr_reg(ha, QLA8044_FLASH_LOCK_ID, ha->portnum);
 460         return ret_val;
 461 }
 462
 463 static void
 464 qla8044_flash_unlock(scsi_qla_host_t *vha)
 465 {
 466         int ret_val;
 467         struct qla_hw_data *ha = vha->hw;
 468
 469         /* Reading FLASH_UNLOCK register unlocks the Flash */
 470         qla8044_wr_reg(ha, QLA8044_FLASH_LOCK_ID, 0xFF);
 471         ret_val = qla8044_rd_reg(ha, QLA8044_FLASH_UNLOCK);
 472 }
 473
 474
 475 static
 476 void qla8044_flash_lock_recovery(struct scsi_qla_host *vha)
 477 {
 478
 479         if (qla8044_flash_lock(vha)) {
 480                 /* Someone else is holding the lock. */
 481                 ql_log(ql_log_warn, vha, 0xb120, "Resetting flash_lock\n");
 482         }
 483
 484         /*
 485          * Either we got the lock, or someone
 486          * else died while holding it.
 487          * In either case, unlock.
 488          */
 489         qla8044_flash_unlock(vha);
 490 }
 491
 492 /*
 493  * Address and length are byte address
 494  */
 495 static int
 496 qla8044_read_flash_data(scsi_qla_host_t *vha,  uint8_t *p_data,
 497         uint32_t flash_addr, int u32_word_count)
 498 {
 499         int i, ret_val = QLA_SUCCESS;
 500         uint32_t u32_word;
 501
 502         if (qla8044_flash_lock(vha) != QLA_SUCCESS) {
 503                 ret_val = QLA_FUNCTION_FAILED;
 504                 goto exit_lock_error;
 505         }
 506
 507         if (flash_addr & 0x03) {
 508                 ql_log(ql_log_warn, vha, 0xb117,
 509                     "%s: Illegal addr = 0x%x\n", __func__, flash_addr);
 510                 ret_val = QLA_FUNCTION_FAILED;
 511                 goto exit_flash_read;
 512         }
 513
 514         for (i = 0; i < u32_word_count; i++) {
 515                 if (qla8044_wr_reg_indirect(vha, QLA8044_FLASH_DIRECT_WINDOW,
 516                     (flash_addr & 0xFFFF0000))) {
 517                         ql_log(ql_log_warn, vha, 0xb119,
 518                             "%s: failed to write addr 0x%x to "
 519                             "FLASH_DIRECT_WINDOW\n! ",
 520                             __func__, flash_addr);
 521                         ret_val = QLA_FUNCTION_FAILED;
 522                         goto exit_flash_read;
 523                 }
 524
 525                 ret_val = qla8044_rd_reg_indirect(vha,
 526                     QLA8044_FLASH_DIRECT_DATA(flash_addr),
 527                     &u32_word);
 528                 if (ret_val != QLA_SUCCESS) {
 529                         ql_log(ql_log_warn, vha, 0xb08c,
 530                             "%s: failed to read addr 0x%x!\n",
 531                             __func__, flash_addr);
 532                         goto exit_flash_read;
 533                 }
 534
 535                 *(uint32_t *)p_data = u32_word;
 536                 p_data = p_data + 4;
 537                 flash_addr = flash_addr + 4;
 538         }
 539
 540 exit_flash_read:
 541         qla8044_flash_unlock(vha);
 542
 543 exit_lock_error:
 544         return ret_val;
 545 }
 546
 547 /*
 548  * Address and length are byte address
 549  */
 550 uint8_t *
 551 qla8044_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
 552         uint32_t offset, uint32_t length)
 553 {
 554         scsi_block_requests(vha->host);
 555         if (qla8044_read_flash_data(vha, (uint8_t *)buf, offset, length / 4)
 556             != QLA_SUCCESS) {
 557                 ql_log(ql_log_warn, vha,  0xb08d,
 558                     "%s: Failed to read from flash\n",
 559                     __func__);
 560         }
 561         scsi_unblock_requests(vha->host);
 562         return buf;
 563 }
 564
 565 inline int
 566 qla8044_need_reset(struct scsi_qla_host *vha)
 567 {
 568         uint32_t drv_state, drv_active;
 569         int rval;
 570         struct qla_hw_data *ha = vha->hw;
 571
 572         drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX);
 573         drv_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX);
 574
 575         rval = drv_state & (1 << ha->portnum);
 576
 577         if (ha->flags.eeh_busy && drv_active)
 578                 rval = 1;
 579         return rval;
 580 }
 581
 582 /*
 583  * qla8044_write_list - Write the value (p_entry->arg2) to address specified
 584  * by p_entry->arg1 for all entries in header with delay of p_hdr->delay between
 585  * entries.
 586  *
 587  * @vha : Pointer to adapter structure
 588  * @p_hdr : reset_entry header for WRITE_LIST opcode.
 589  *
 590  */
 591 static void
 592 qla8044_write_list(struct scsi_qla_host *vha,
 593         struct qla8044_reset_entry_hdr *p_hdr)
 594 {
 595         struct qla8044_entry *p_entry;
 596         uint32_t i;
 597
 598         p_entry = (struct qla8044_entry *)((char *)p_hdr +
 599             sizeof(struct qla8044_reset_entry_hdr));
 600
 601         for (i = 0; i < p_hdr->count; i++, p_entry++) {
 602                 qla8044_wr_reg_indirect(vha, p_entry->arg1, p_entry->arg2);
 603                 if (p_hdr->delay)
 604                         udelay((uint32_t)(p_hdr->delay));
 605         }
 606 }
 607
 608 /*
 609  * qla8044_read_write_list - Read from address specified by p_entry->arg1,
 610  * write value read to address specified by p_entry->arg2, for all entries in
 611  * header with delay of p_hdr->delay between entries.
 612  *
 613  * @vha : Pointer to adapter structure
 614  * @p_hdr : reset_entry header for READ_WRITE_LIST opcode.
 615  *
 616  */
 617 static void
 618 qla8044_read_write_list(struct scsi_qla_host *vha,
 619         struct qla8044_reset_entry_hdr *p_hdr)
 620 {
 621         struct qla8044_entry *p_entry;
 622         uint32_t i;
 623
 624         p_entry = (struct qla8044_entry *)((char *)p_hdr +
 625             sizeof(struct qla8044_reset_entry_hdr));
 626
 627         for (i = 0; i < p_hdr->count; i++, p_entry++) {
 628                 qla8044_read_write_crb_reg(vha, p_entry->arg1,
 629                     p_entry->arg2);
 630                 if (p_hdr->delay)
 631                         udelay((uint32_t)(p_hdr->delay));
 632         }
 633 }
 634
 635 /*
 636  * qla8044_poll_reg - Poll the given CRB addr for duration msecs till
 637  * value read ANDed with test_mask is equal to test_result.
 638  *
 639  * @ha : Pointer to adapter structure
 640  * @addr : CRB register address
 641  * @duration : Poll for total of "duration" msecs
 642  * @test_mask : Mask value read with "test_mask"
 643  * @test_result : Compare (value&test_mask) with test_result.
 644  *
 645  * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED
 646  */
 647 static int
 648 qla8044_poll_reg(struct scsi_qla_host *vha, uint32_t addr,
 649         int duration, uint32_t test_mask, uint32_t test_result)
 650 {
 651         uint32_t value;
 652         int timeout_error;
 653         uint8_t retries;
 654         int ret_val = QLA_SUCCESS;
 655
 656         ret_val = qla8044_rd_reg_indirect(vha, addr, &value);
 657         if (ret_val == QLA_FUNCTION_FAILED) {
 658                 timeout_error = 1;
 659                 goto exit_poll_reg;
 660         }
 661
 662         /* poll every 1/10 of the total duration */
 663         retries = duration/10;
 664
 665         do {
 666                 if ((value & test_mask) != test_result) {
 667                         timeout_error = 1;
 668                         msleep(duration/10);
 669                         ret_val = qla8044_rd_reg_indirect(vha, addr, &value);
 670                         if (ret_val == QLA_FUNCTION_FAILED) {
 671                                 timeout_error = 1;
 672                                 goto exit_poll_reg;
 673                         }
 674                 } else {
 675                         timeout_error = 0;
 676                         break;
 677                 }
 678         } while (retries--);
 679
 680 exit_poll_reg:
 681         if (timeout_error) {
 682                 vha->reset_tmplt.seq_error++;
 683                 ql_log(ql_log_fatal, vha, 0xb090,
 684                     "%s: Poll Failed: 0x%08x 0x%08x 0x%08x\n",
 685                     __func__, value, test_mask, test_result);
 686         }
 687
 688         return timeout_error;
 689 }
 690
 691 /*
 692  * qla8044_poll_list - For all entries in the POLL_LIST header, poll read CRB
 693  * register specified by p_entry->arg1 and compare (value AND test_mask) with
 694  * test_result to validate it. Wait for p_hdr->delay between processing entries.
 695  *
 696  * @ha : Pointer to adapter structure
 697  * @p_hdr : reset_entry header for POLL_LIST opcode.
 698  *
 699  */
 700 static void
 701 qla8044_poll_list(struct scsi_qla_host *vha,
 702         struct qla8044_reset_entry_hdr *p_hdr)
 703 {
 704         long delay;
 705         struct qla8044_entry *p_entry;
 706         struct qla8044_poll *p_poll;
 707         uint32_t i;
 708         uint32_t value;
 709
 710         p_poll = (struct qla8044_poll *)
 711                 ((char *)p_hdr + sizeof(struct qla8044_reset_entry_hdr));
 712
 713         /* Entries start after 8 byte qla8044_poll, poll header contains
 714          * the test_mask, test_value.
 715          */
 716         p_entry = (struct qla8044_entry *)((char *)p_poll +
 717             sizeof(struct qla8044_poll));
 718
 719         delay = (long)p_hdr->delay;
 720
 721         if (!delay) {
 722                 for (i = 0; i < p_hdr->count; i++, p_entry++)
 723                         qla8044_poll_reg(vha, p_entry->arg1,
 724                             delay, p_poll->test_mask, p_poll->test_value);
 725         } else {
 726                 for (i = 0; i < p_hdr->count; i++, p_entry++) {
 727                         if (delay) {
 728                                 if (qla8044_poll_reg(vha,
 729                                     p_entry->arg1, delay,
 730                                     p_poll->test_mask,
 731                                     p_poll->test_value)) {
 732                                         /*If
 733                                         * (data_read&test_mask != test_value)
 734                                         * read TIMEOUT_ADDR (arg1) and
 735                                         * ADDR (arg2) registers
 736                                         */
 737                                         qla8044_rd_reg_indirect(vha,
 738                                             p_entry->arg1, &value);
 739                                         qla8044_rd_reg_indirect(vha,
 740                                             p_entry->arg2, &value);
 741                                 }
 742                         }
 743                 }
 744         }
 745 }
 746
 747 /*
 748  * qla8044_poll_write_list - Write dr_value, ar_value to dr_addr/ar_addr,
 749  * read ar_addr, if (value& test_mask != test_mask) re-read till timeout
 750  * expires.
 751  *
 752  * @vha : Pointer to adapter structure
 753  * @p_hdr : reset entry header for POLL_WRITE_LIST opcode.
 754  *
 755  */
 756 static void
 757 qla8044_poll_write_list(struct scsi_qla_host *vha,
 758         struct qla8044_reset_entry_hdr *p_hdr)
 759 {
 760         long delay;
 761         struct qla8044_quad_entry *p_entry;
 762         struct qla8044_poll *p_poll;
 763         uint32_t i;
 764
 765         p_poll = (struct qla8044_poll *)((char *)p_hdr +
 766             sizeof(struct qla8044_reset_entry_hdr));
 767
 768         p_entry = (struct qla8044_quad_entry *)((char *)p_poll +
 769             sizeof(struct qla8044_poll));
 770
 771         delay = (long)p_hdr->delay;
 772
 773         for (i = 0; i < p_hdr->count; i++, p_entry++) {
 774                 qla8044_wr_reg_indirect(vha,
 775                     p_entry->dr_addr, p_entry->dr_value);
 776                 qla8044_wr_reg_indirect(vha,
 777                     p_entry->ar_addr, p_entry->ar_value);
 778                 if (delay) {
 779                         if (qla8044_poll_reg(vha,
 780                             p_entry->ar_addr, delay,
 781                             p_poll->test_mask,
 782                             p_poll->test_value)) {
 783                                 ql_dbg(ql_dbg_p3p, vha, 0xb091,
 784                                     "%s: Timeout Error: poll list, ",
 785                                     __func__);
 786                                 ql_dbg(ql_dbg_p3p, vha, 0xb092,
 787                                     "item_num %d, entry_num %d\n", i,
 788                                     vha->reset_tmplt.seq_index);
 789                         }
 790                 }
 791         }
 792 }
 793
 794 /*
 795  * qla8044_read_modify_write - Read value from p_entry->arg1, modify the
 796  * value, write value to p_entry->arg2. Process entries with p_hdr->delay
 797  * between entries.
 798  *
 799  * @vha : Pointer to adapter structure
 800  * @p_hdr : header with shift/or/xor values.
 801  *
 802  */
 803 static void
 804 qla8044_read_modify_write(struct scsi_qla_host *vha,
 805         struct qla8044_reset_entry_hdr *p_hdr)
 806 {
 807         struct qla8044_entry *p_entry;
 808         struct qla8044_rmw *p_rmw_hdr;
 809         uint32_t i;
 810
 811         p_rmw_hdr = (struct qla8044_rmw *)((char *)p_hdr +
 812             sizeof(struct qla8044_reset_entry_hdr));
 813
 814         p_entry = (struct qla8044_entry *)((char *)p_rmw_hdr +
 815             sizeof(struct qla8044_rmw));
 816
 817         for (i = 0; i < p_hdr->count; i++, p_entry++) {
 818                 qla8044_rmw_crb_reg(vha, p_entry->arg1,
 819                     p_entry->arg2, p_rmw_hdr);
 820                 if (p_hdr->delay)
 821                         udelay((uint32_t)(p_hdr->delay));
 822         }
 823 }
 824
 825 /*
 826  * qla8044_pause - Wait for p_hdr->delay msecs, called between processing
 827  * two entries of a sequence.
 828  *
 829  * @vha : Pointer to adapter structure
 830  * @p_hdr : Common reset entry header.
 831  *
 832  */
 833 static
 834 void qla8044_pause(struct scsi_qla_host *vha,
 835         struct qla8044_reset_entry_hdr *p_hdr)
 836 {
 837         if (p_hdr->delay)
 838                 mdelay((uint32_t)((long)p_hdr->delay));
 839 }
 840
 841 /*
 842  * qla8044_template_end - Indicates end of reset sequence processing.
 843  *
 844  * @vha : Pointer to adapter structure
 845  * @p_hdr : Common reset entry header.
 846  *
 847  */
 848 static void
 849 qla8044_template_end(struct scsi_qla_host *vha,
 850         struct qla8044_reset_entry_hdr *p_hdr)
 851 {
 852         vha->reset_tmplt.template_end = 1;
 853
 854         if (vha->reset_tmplt.seq_error == 0) {
 855                 ql_dbg(ql_dbg_p3p, vha, 0xb093,
 856                     "%s: Reset sequence completed SUCCESSFULLY.\n", __func__);
 857         } else {
 858                 ql_log(ql_log_fatal, vha, 0xb094,
 859                     "%s: Reset sequence completed with some timeout "
 860                     "errors.\n", __func__);
 861         }
 862 }
 863
 864 /*
 865  * qla8044_poll_read_list - Write ar_value to ar_addr register, read ar_addr,
 866  * if (value & test_mask != test_value) re-read till timeout value expires,
 867  * read dr_addr register and assign to reset_tmplt.array.
 868  *
 869  * @vha : Pointer to adapter structure
 870  * @p_hdr : Common reset entry header.
 871  *
 872  */
 873 static void
 874 qla8044_poll_read_list(struct scsi_qla_host *vha,
 875         struct qla8044_reset_entry_hdr *p_hdr)
 876 {
 877         long delay;
 878         int index;
 879         struct qla8044_quad_entry *p_entry;
 880         struct qla8044_poll *p_poll;
 881         uint32_t i;
 882         uint32_t value;
 883
 884         p_poll = (struct qla8044_poll *)
 885                 ((char *)p_hdr + sizeof(struct qla8044_reset_entry_hdr));
 886
 887         p_entry = (struct qla8044_quad_entry *)
 888                 ((char *)p_poll + sizeof(struct qla8044_poll));
 889
 890         delay = (long)p_hdr->delay;
 891
 892         for (i = 0; i < p_hdr->count; i++, p_entry++) {
 893                 qla8044_wr_reg_indirect(vha, p_entry->ar_addr,
 894                     p_entry->ar_value);
 895                 if (delay) {
 896                         if (qla8044_poll_reg(vha, p_entry->ar_addr, delay,
 897                             p_poll->test_mask, p_poll->test_value)) {
 898                                 ql_dbg(ql_dbg_p3p, vha, 0xb095,
 899                                     "%s: Timeout Error: poll "
 900                                     "list, ", __func__);
 901                                 ql_dbg(ql_dbg_p3p, vha, 0xb096,
 902                                     "Item_num %d, "
 903                                     "entry_num %d\n", i,
 904                                     vha->reset_tmplt.seq_index);
 905                         } else {
 906                                 index = vha->reset_tmplt.array_index;
 907                                 qla8044_rd_reg_indirect(vha,
 908                                     p_entry->dr_addr, &value);
 909                                 vha->reset_tmplt.array[index++] = value;
 910                                 if (index == QLA8044_MAX_RESET_SEQ_ENTRIES)
 911                                         vha->reset_tmplt.array_index = 1;
 912                         }
 913                 }
 914         }
 915 }
 916
 917 /*
 918  * qla8031_process_reset_template - Process all entries in reset template
 919  * till entry with SEQ_END opcode, which indicates end of the reset template
 920  * processing. Each entry has a Reset Entry header, entry opcode/command, with
 921  * size of the entry, number of entries in sub-sequence and delay in microsecs
 922  * or timeout in millisecs.
 923  *
 924  * @ha : Pointer to adapter structure
 925  * @p_buff : Common reset entry header.
 926  *
 927  */
 928 static void
 929 qla8044_process_reset_template(struct scsi_qla_host *vha,
 930         char *p_buff)
 931 {
 932         int index, entries;
 933         struct qla8044_reset_entry_hdr *p_hdr;
 934         char *p_entry = p_buff;
 935
 936         vha->reset_tmplt.seq_end = 0;
 937         vha->reset_tmplt.template_end = 0;
 938         entries = vha->reset_tmplt.hdr->entries;
 939         index = vha->reset_tmplt.seq_index;
 940
 941         for (; (!vha->reset_tmplt.seq_end) && (index  < entries); index++) {
 942                 p_hdr = (struct qla8044_reset_entry_hdr *)p_entry;
 943                 switch (p_hdr->cmd) {
 944                 case OPCODE_NOP:
 945                         break;
 946                 case OPCODE_WRITE_LIST:
 947                         qla8044_write_list(vha, p_hdr);
 948                         break;
 949                 case OPCODE_READ_WRITE_LIST:
 950                         qla8044_read_write_list(vha, p_hdr);
 951                         break;
 952                 case OPCODE_POLL_LIST:
 953                         qla8044_poll_list(vha, p_hdr);
 954                         break;
 955                 case OPCODE_POLL_WRITE_LIST:
 956                         qla8044_poll_write_list(vha, p_hdr);
 957                         break;
 958                 case OPCODE_READ_MODIFY_WRITE:
 959                         qla8044_read_modify_write(vha, p_hdr);
 960                         break;
 961                 case OPCODE_SEQ_PAUSE:
 962                         qla8044_pause(vha, p_hdr);
 963                         break;
 964                 case OPCODE_SEQ_END:
 965                         vha->reset_tmplt.seq_end = 1;
 966                         break;
 967                 case OPCODE_TMPL_END:
 968                         qla8044_template_end(vha, p_hdr);
 969                         break;
 970                 case OPCODE_POLL_READ_LIST:
 971                         qla8044_poll_read_list(vha, p_hdr);
 972                         break;
 973                 default:
 974                         ql_log(ql_log_fatal, vha, 0xb097,
 975                             "%s: Unknown command ==> 0x%04x on "
 976                             "entry = %d\n", __func__, p_hdr->cmd, index);
 977                         break;
 978                 }
 979                 /*
 980                  *Set pointer to next entry in the sequence.
 981                 */
 982                 p_entry += p_hdr->size;
 983         }
 984         vha->reset_tmplt.seq_index = index;
 985 }
 986
 987 static void
 988 qla8044_process_init_seq(struct scsi_qla_host *vha)
 989 {
 990         qla8044_process_reset_template(vha,
 991             vha->reset_tmplt.init_offset);
 992         if (vha->reset_tmplt.seq_end != 1)
 993                 ql_log(ql_log_fatal, vha, 0xb098,
 994                     "%s: Abrupt INIT Sub-Sequence end.\n",
 995                     __func__);
 996 }
 997
 998 static void
 999 qla8044_process_stop_seq(struct scsi_qla_host *vha)
1000 {
1001         vha->reset_tmplt.seq_index = 0;
1002         qla8044_process_reset_template(vha, vha->reset_tmplt.stop_offset);
1003         if (vha->reset_tmplt.seq_end != 1)
1004                 ql_log(ql_log_fatal, vha, 0xb099,
1005                     "%s: Abrupt STOP Sub-Sequence end.\n", __func__);
1006 }
1007
1008 static void
1009 qla8044_process_start_seq(struct scsi_qla_host *vha)
1010 {
1011         qla8044_process_reset_template(vha, vha->reset_tmplt.start_offset);
1012         if (vha->reset_tmplt.template_end != 1)
1013                 ql_log(ql_log_fatal, vha, 0xb09a,
1014                     "%s: Abrupt START Sub-Sequence end.\n",
1015                     __func__);
1016 }
1017
1018 static int
1019 qla8044_lockless_flash_read_u32(struct scsi_qla_host *vha,
1020         uint32_t flash_addr, uint8_t *p_data, int u32_word_count)
1021 {
1022         uint32_t i;
1023         uint32_t u32_word;
1024         uint32_t flash_offset;
1025         uint32_t addr = flash_addr;
1026         int ret_val = QLA_SUCCESS;
1027
1028         flash_offset = addr & (QLA8044_FLASH_SECTOR_SIZE - 1);
1029
1030         if (addr & 0x3) {
1031                 ql_log(ql_log_fatal, vha, 0xb09b, "%s: Illegal addr = 0x%x\n",
1032                     __func__, addr);
1033                 ret_val = QLA_FUNCTION_FAILED;
1034                 goto exit_lockless_read;
1035         }
1036
1037         ret_val = qla8044_wr_reg_indirect(vha,
1038             QLA8044_FLASH_DIRECT_WINDOW, (addr));
1039
1040         if (ret_val != QLA_SUCCESS) {
1041                 ql_log(ql_log_fatal, vha, 0xb09c,
1042                     "%s: failed to write addr 0x%x to FLASH_DIRECT_WINDOW!\n",
1043                     __func__, addr);
1044                 goto exit_lockless_read;
1045         }
1046
1047         /* Check if data is spread across multiple sectors  */
1048         if ((flash_offset + (u32_word_count * sizeof(uint32_t))) >
1049             (QLA8044_FLASH_SECTOR_SIZE - 1)) {
1050                 /* Multi sector read */
1051                 for (i = 0; i < u32_word_count; i++) {
1052                         ret_val = qla8044_rd_reg_indirect(vha,
1053                             QLA8044_FLASH_DIRECT_DATA(addr), &u32_word);
1054                         if (ret_val != QLA_SUCCESS) {
1055                                 ql_log(ql_log_fatal, vha, 0xb09d,
1056                                     "%s: failed to read addr 0x%x!\n",
1057                                     __func__, addr);
1058                                 goto exit_lockless_read;
1059                         }
1060                         *(uint32_t *)p_data  = u32_word;
1061                         p_data = p_data + 4;
1062                         addr = addr + 4;
1063                         flash_offset = flash_offset + 4;
1064                         if (flash_offset > (QLA8044_FLASH_SECTOR_SIZE - 1)) {
1065                                 /* This write is needed once for each sector */
1066                                 ret_val = qla8044_wr_reg_indirect(vha,
1067                                     QLA8044_FLASH_DIRECT_WINDOW, (addr));
1068                                 if (ret_val != QLA_SUCCESS) {
1069                                         ql_log(ql_log_fatal, vha, 0xb09f,
1070                                             "%s: failed to write addr "
1071                                             "0x%x to FLASH_DIRECT_WINDOW!\n",
1072                                             __func__, addr);
1073                                         goto exit_lockless_read;
1074                                 }
1075                                 flash_offset = 0;
1076                         }
1077                 }
1078         } else {
1079                 /* Single sector read */
1080                 for (i = 0; i < u32_word_count; i++) {
1081                         ret_val = qla8044_rd_reg_indirect(vha,
1082                             QLA8044_FLASH_DIRECT_DATA(addr), &u32_word);
1083                         if (ret_val != QLA_SUCCESS) {
1084                                 ql_log(ql_log_fatal, vha, 0xb0a0,
1085                                     "%s: failed to read addr 0x%x!\n",
1086                                     __func__, addr);
1087                                 goto exit_lockless_read;
1088                         }
1089                         *(uint32_t *)p_data = u32_word;
1090                         p_data = p_data + 4;
1091                         addr = addr + 4;
1092                 }
1093         }
1094
1095 exit_lockless_read:
1096         return ret_val;
1097 }
1098
1099 /*
1100  * qla8044_ms_mem_write_128b - Writes data to MS/off-chip memory
1101  *
1102  * @vha : Pointer to adapter structure
1103  * addr : Flash address to write to
1104  * data : Data to be written
1105  * count : word_count to be written
1106  *
1107  * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED
1108  */
1109 static int
1110 qla8044_ms_mem_write_128b(struct scsi_qla_host *vha,
1111         uint64_t addr, uint32_t *data, uint32_t count)
1112 {
1113         int i, j, ret_val = QLA_SUCCESS;
1114         uint32_t agt_ctrl;
1115         unsigned long flags;
1116         struct qla_hw_data *ha = vha->hw;
1117
1118         /* Only 128-bit aligned access */
1119         if (addr & 0xF) {
1120                 ret_val = QLA_FUNCTION_FAILED;
1121                 goto exit_ms_mem_write;
1122         }
1123         write_lock_irqsave(&ha->hw_lock, flags);
1124
1125         /* Write address */
1126         ret_val = qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_ADDR_HI, 0);
1127         if (ret_val == QLA_FUNCTION_FAILED) {
1128                 ql_log(ql_log_fatal, vha, 0xb0a1,
1129                     "%s: write to AGT_ADDR_HI failed!\n", __func__);
1130                 goto exit_ms_mem_write_unlock;
1131         }
1132
1133         for (i = 0; i < count; i++, addr += 16) {
1134                 if (!((QLA8044_ADDR_IN_RANGE(addr, QLA8044_ADDR_QDR_NET,
1135                     QLA8044_ADDR_QDR_NET_MAX)) ||
1136                     (QLA8044_ADDR_IN_RANGE(addr, QLA8044_ADDR_DDR_NET,
1137                         QLA8044_ADDR_DDR_NET_MAX)))) {
1138                         ret_val = QLA_FUNCTION_FAILED;
1139                         goto exit_ms_mem_write_unlock;
1140                 }
1141
1142                 ret_val = qla8044_wr_reg_indirect(vha,
1143                     MD_MIU_TEST_AGT_ADDR_LO, addr);
1144
1145                 /* Write data */
1146                 ret_val += qla8044_wr_reg_indirect(vha,
1147                     MD_MIU_TEST_AGT_WRDATA_LO, *data++);
1148                 ret_val += qla8044_wr_reg_indirect(vha,
1149                     MD_MIU_TEST_AGT_WRDATA_HI, *data++);
1150                 ret_val += qla8044_wr_reg_indirect(vha,
1151                     MD_MIU_TEST_AGT_WRDATA_ULO, *data++);
1152                 ret_val += qla8044_wr_reg_indirect(vha,
1153                     MD_MIU_TEST_AGT_WRDATA_UHI, *data++);
1154                 if (ret_val == QLA_FUNCTION_FAILED) {
1155                         ql_log(ql_log_fatal, vha, 0xb0a2,
1156                             "%s: write to AGT_WRDATA failed!\n",
1157                             __func__);
1158                         goto exit_ms_mem_write_unlock;
1159                 }
1160
1161                 /* Check write status */
1162                 ret_val = qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_CTRL,
1163                     MIU_TA_CTL_WRITE_ENABLE);
1164                 ret_val += qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_CTRL,
1165                     MIU_TA_CTL_WRITE_START);
1166                 if (ret_val == QLA_FUNCTION_FAILED) {
1167                         ql_log(ql_log_fatal, vha, 0xb0a3,
1168                             "%s: write to AGT_CTRL failed!\n", __func__);
1169                         goto exit_ms_mem_write_unlock;
1170                 }
1171
1172                 for (j = 0; j < MAX_CTL_CHECK; j++) {
1173                         ret_val = qla8044_rd_reg_indirect(vha,
1174                             MD_MIU_TEST_AGT_CTRL, &agt_ctrl);
1175                         if (ret_val == QLA_FUNCTION_FAILED) {
1176                                 ql_log(ql_log_fatal, vha, 0xb0a4,
1177                                     "%s: failed to read "
1178                                     "MD_MIU_TEST_AGT_CTRL!\n", __func__);
1179                                 goto exit_ms_mem_write_unlock;
1180                         }
1181                         if ((agt_ctrl & MIU_TA_CTL_BUSY) == 0)
1182                                 break;
1183                 }
1184
1185                 /* Status check failed */
1186                 if (j >= MAX_CTL_CHECK) {
1187                         ql_log(ql_log_fatal, vha, 0xb0a5,
1188                             "%s: MS memory write failed!\n",
1189                            __func__);
1190                         ret_val = QLA_FUNCTION_FAILED;
1191                         goto exit_ms_mem_write_unlock;
1192                 }
1193         }
1194
1195 exit_ms_mem_write_unlock:
1196         write_unlock_irqrestore(&ha->hw_lock, flags);
1197
1198 exit_ms_mem_write:
1199         return ret_val;
1200 }
1201
1202 static int
1203 qla8044_copy_bootloader(struct scsi_qla_host *vha)
1204 {
1205         uint8_t *p_cache;
1206         uint32_t src, count, size;
1207         uint64_t dest;
1208         int ret_val = QLA_SUCCESS;
1209         struct qla_hw_data *ha = vha->hw;
1210
1211         src = QLA8044_BOOTLOADER_FLASH_ADDR;
1212         dest = qla8044_rd_reg(ha, QLA8044_BOOTLOADER_ADDR);
1213         size = qla8044_rd_reg(ha, QLA8044_BOOTLOADER_SIZE);
1214
1215         /* 128 bit alignment check */
1216         if (size & 0xF)
1217                 size = (size + 16) & ~0xF;
1218
1219         /* 16 byte count */
1220         count = size/16;
1221
1222         p_cache = vmalloc(size);
1223         if (p_cache == NULL) {
1224                 ql_log(ql_log_fatal, vha, 0xb0a6,
1225                     "%s: Failed to allocate memory for "
1226                     "boot loader cache\n", __func__);
1227                 ret_val = QLA_FUNCTION_FAILED;
1228                 goto exit_copy_bootloader;
1229         }
1230
1231         ret_val = qla8044_lockless_flash_read_u32(vha, src,
1232             p_cache, size/sizeof(uint32_t));
1233         if (ret_val == QLA_FUNCTION_FAILED) {
1234                 ql_log(ql_log_fatal, vha, 0xb0a7,
1235                     "%s: Error reading F/W from flash!!!\n", __func__);
1236                 goto exit_copy_error;
1237         }
1238         ql_dbg(ql_dbg_p3p, vha, 0xb0a8, "%s: Read F/W from flash!\n",
1239             __func__);
1240
1241         /* 128 bit/16 byte write to MS memory */
1242         ret_val = qla8044_ms_mem_write_128b(vha, dest,
1243             (uint32_t *)p_cache, count);
1244         if (ret_val == QLA_FUNCTION_FAILED) {
1245                 ql_log(ql_log_fatal, vha, 0xb0a9,
1246                     "%s: Error writing F/W to MS !!!\n", __func__);
1247                 goto exit_copy_error;
1248         }
1249         ql_dbg(ql_dbg_p3p, vha, 0xb0aa,
1250             "%s: Wrote F/W (size %d) to MS !!!\n",
1251             __func__, size);
1252
1253 exit_copy_error:
1254         vfree(p_cache);
1255
1256 exit_copy_bootloader:
1257         return ret_val;
1258 }
1259
1260 static int
1261 qla8044_restart(struct scsi_qla_host *vha)
1262 {
1263         int ret_val = QLA_SUCCESS;
1264         struct qla_hw_data *ha = vha->hw;
1265
1266         qla8044_process_stop_seq(vha);
1267
1268         /* Collect minidump */
1269         if (ql2xmdenable)
1270                 qla8044_get_minidump(vha);
1271         else
1272                 ql_log(ql_log_fatal, vha, 0xb14c,
1273                     "Minidump disabled.\n");
1274
1275         qla8044_process_init_seq(vha);
1276
1277         if (qla8044_copy_bootloader(vha)) {
1278                 ql_log(ql_log_fatal, vha, 0xb0ab,
1279                     "%s: Copy bootloader, firmware restart failed!\n",
1280                     __func__);
1281                 ret_val = QLA_FUNCTION_FAILED;
1282                 goto exit_restart;
1283         }
1284
1285         /*
1286          *  Loads F/W from flash
1287          */
1288         qla8044_wr_reg(ha, QLA8044_FW_IMAGE_VALID, QLA8044_BOOT_FROM_FLASH);
1289
1290         qla8044_process_start_seq(vha);
1291
1292 exit_restart:
1293         return ret_val;
1294 }
1295
1296 /*
1297  * qla8044_check_cmd_peg_status - Check peg status to see if Peg is
1298  * initialized.
1299  *
1300  * @ha : Pointer to adapter structure
1301  *
1302  * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED
1303  */
1304 static int
1305 qla8044_check_cmd_peg_status(struct scsi_qla_host *vha)
1306 {
1307         uint32_t val, ret_val = QLA_FUNCTION_FAILED;
1308         int retries = CRB_CMDPEG_CHECK_RETRY_COUNT;
1309         struct qla_hw_data *ha = vha->hw;
1310
1311         do {
1312                 val = qla8044_rd_reg(ha, QLA8044_CMDPEG_STATE);
1313                 if (val == PHAN_INITIALIZE_COMPLETE) {
1314                         ql_dbg(ql_dbg_p3p, vha, 0xb0ac,
1315                             "%s: Command Peg initialization "
1316                             "complete! state=0x%x\n", __func__, val);
1317                         ret_val = QLA_SUCCESS;
1318                         break;
1319                 }
1320                 msleep(CRB_CMDPEG_CHECK_DELAY);
1321         } while (--retries);
1322
1323         return ret_val;
1324 }
1325
1326 static int
1327 qla8044_start_firmware(struct scsi_qla_host *vha)
1328 {
1329         int ret_val = QLA_SUCCESS;
1330
1331         if (qla8044_restart(vha)) {
1332                 ql_log(ql_log_fatal, vha, 0xb0ad,
1333                     "%s: Restart Error!!!, Need Reset!!!\n",
1334                     __func__);
1335                 ret_val = QLA_FUNCTION_FAILED;
1336                 goto exit_start_fw;
1337         } else
1338                 ql_dbg(ql_dbg_p3p, vha, 0xb0af,
1339                     "%s: Restart done!\n", __func__);
1340
1341         ret_val = qla8044_check_cmd_peg_status(vha);
1342         if (ret_val) {
1343                 ql_log(ql_log_fatal, vha, 0xb0b0,
1344                     "%s: Peg not initialized!\n", __func__);
1345                 ret_val = QLA_FUNCTION_FAILED;
1346         }
1347
1348 exit_start_fw:
1349         return ret_val;
1350 }
1351
1352 void
1353 qla8044_clear_drv_active(struct qla_hw_data *ha)
1354 {
1355         uint32_t drv_active;
1356         struct scsi_qla_host *vha = pci_get_drvdata(ha->pdev);
1357
1358         drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX);
1359         drv_active &= ~(1 << (ha->portnum));
1360
1361         ql_log(ql_log_info, vha, 0xb0b1,
1362             "%s(%ld): drv_active: 0x%08x\n",
1363             __func__, vha->host_no, drv_active);
1364
1365         qla8044_wr_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX, drv_active);
1366 }
1367
1368 /*
1369  * qla8044_device_bootstrap - Initialize device, set DEV_READY, start fw
1370  * @ha: pointer to adapter structure
1371  *
1372  * Note: IDC lock must be held upon entry
1373  **/
1374 static int
1375 qla8044_device_bootstrap(struct scsi_qla_host *vha)
1376 {
1377         int rval = QLA_FUNCTION_FAILED;
1378         int i;
1379         uint32_t old_count = 0, count = 0;
1380         int need_reset = 0;
1381         uint32_t idc_ctrl;
1382         struct qla_hw_data *ha = vha->hw;
1383
1384         need_reset = qla8044_need_reset(vha);
1385
1386         if (!need_reset) {
1387                 old_count = qla8044_rd_direct(vha,
1388                     QLA8044_PEG_ALIVE_COUNTER_INDEX);
1389
1390                 for (i = 0; i < 10; i++) {
1391                         msleep(200);
1392
1393                         count = qla8044_rd_direct(vha,
1394                             QLA8044_PEG_ALIVE_COUNTER_INDEX);
1395                         if (count != old_count) {
1396                                 rval = QLA_SUCCESS;
1397                                 goto dev_ready;
1398                         }
1399                 }
1400                 qla8044_flash_lock_recovery(vha);
1401         } else {
1402                 /* We are trying to perform a recovery here. */
1403                 if (ha->flags.isp82xx_fw_hung)
1404                         qla8044_flash_lock_recovery(vha);
1405         }
1406
1407         /* set to DEV_INITIALIZING */
1408         ql_log(ql_log_info, vha, 0xb0b2,
1409             "%s: HW State: INITIALIZING\n", __func__);
1410         qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX,
1411             QLA8XXX_DEV_INITIALIZING);
1412
1413         qla8044_idc_unlock(ha);
1414         rval = qla8044_start_firmware(vha);
1415         qla8044_idc_lock(ha);
1416
1417         if (rval != QLA_SUCCESS) {
1418                 ql_log(ql_log_info, vha, 0xb0b3,
1419                      "%s: HW State: FAILED\n", __func__);
1420                 qla8044_clear_drv_active(ha);
1421                 qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX,
1422                     QLA8XXX_DEV_FAILED);
1423                 return rval;
1424         }
1425
1426         /* For ISP8044, If IDC_CTRL GRACEFUL_RESET_BIT1 is set , reset it after
1427          * device goes to INIT state. */
1428         idc_ctrl = qla8044_rd_reg(ha, QLA8044_IDC_DRV_CTRL);
1429         if (idc_ctrl & GRACEFUL_RESET_BIT1) {
1430                 qla8044_wr_reg(ha, QLA8044_IDC_DRV_CTRL,
1431                     (idc_ctrl & ~GRACEFUL_RESET_BIT1));
1432                 ha->fw_dumped = 0;
1433         }
1434
1435 dev_ready:
1436         ql_log(ql_log_info, vha, 0xb0b4,
1437             "%s: HW State: READY\n", __func__);
1438         qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX, QLA8XXX_DEV_READY);
1439
1440         return rval;
1441 }
1442
1443 /*-------------------------Reset Sequence Functions-----------------------*/
1444 static void
1445 qla8044_dump_reset_seq_hdr(struct scsi_qla_host *vha)
1446 {
1447         u8 *phdr;
1448
1449         if (!vha->reset_tmplt.buff) {
1450                 ql_log(ql_log_fatal, vha, 0xb0b5,
1451                     "%s: Error Invalid reset_seq_template\n", __func__);
1452                 return;
1453         }
1454
1455         phdr = vha->reset_tmplt.buff;
1456         ql_dbg(ql_dbg_p3p, vha, 0xb0b6,
1457             "Reset Template :\n\t0x%X 0x%X 0x%X 0x%X"
1458             "0x%X 0x%X 0x%X 0x%X 0x%X 0x%X\n"
1459             "\t0x%X 0x%X 0x%X 0x%X 0x%X 0x%X\n\n",
1460             *phdr, *(phdr+1), *(phdr+2), *(phdr+3), *(phdr+4),
1461             *(phdr+5), *(phdr+6), *(phdr+7), *(phdr + 8),
1462             *(phdr+9), *(phdr+10), *(phdr+11), *(phdr+12),
1463             *(phdr+13), *(phdr+14), *(phdr+15));
1464 }
1465
1466 /*
1467  * qla8044_reset_seq_checksum_test - Validate Reset Sequence template.
1468  *
1469  * @ha : Pointer to adapter structure
1470  *
1471  * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED
1472  */
1473 static int
1474 qla8044_reset_seq_checksum_test(struct scsi_qla_host *vha)
1475 {
1476         uint32_t sum =  0;
1477         uint16_t *buff = (uint16_t *)vha->reset_tmplt.buff;
1478         int u16_count =  vha->reset_tmplt.hdr->size / sizeof(uint16_t);
1479
1480         while (u16_count-- > 0)
1481                 sum += *buff++;
1482
1483         while (sum >> 16)
1484                 sum = (sum & 0xFFFF) +  (sum >> 16);
1485
1486         /* checksum of 0 indicates a valid template */
1487         if (~sum) {
1488                 return QLA_SUCCESS;
1489         } else {
1490                 ql_log(ql_log_fatal, vha, 0xb0b7,
1491                     "%s: Reset seq checksum failed\n", __func__);
1492                 return QLA_FUNCTION_FAILED;
1493         }
1494 }
1495
1496 /*
1497  * qla8044_read_reset_template - Read Reset Template from Flash, validate
1498  * the template and store offsets of stop/start/init offsets in ha->reset_tmplt.
1499  *
1500  * @ha : Pointer to adapter structure
1501  */
1502 void
1503 qla8044_read_reset_template(struct scsi_qla_host *vha)
1504 {
1505         uint8_t *p_buff;
1506         uint32_t addr, tmplt_hdr_def_size, tmplt_hdr_size;
1507
1508         vha->reset_tmplt.seq_error = 0;
1509         vha->reset_tmplt.buff = vmalloc(QLA8044_RESTART_TEMPLATE_SIZE);
1510         if (vha->reset_tmplt.buff == NULL) {
1511                 ql_log(ql_log_fatal, vha, 0xb0b8,
1512                     "%s: Failed to allocate reset template resources\n",
1513                     __func__);
1514                 goto exit_read_reset_template;
1515         }
1516
1517         p_buff = vha->reset_tmplt.buff;
1518         addr = QLA8044_RESET_TEMPLATE_ADDR;
1519
1520         tmplt_hdr_def_size =
1521             sizeof(struct qla8044_reset_template_hdr) / sizeof(uint32_t);
1522
1523         ql_dbg(ql_dbg_p3p, vha, 0xb0b9,
1524             "%s: Read template hdr size %d from Flash\n",
1525             __func__, tmplt_hdr_def_size);
1526
1527         /* Copy template header from flash */
1528         if (qla8044_read_flash_data(vha, p_buff, addr, tmplt_hdr_def_size)) {
1529                 ql_log(ql_log_fatal, vha, 0xb0ba,
1530                     "%s: Failed to read reset template\n", __func__);
1531                 goto exit_read_template_error;
1532         }
1533
1534         vha->reset_tmplt.hdr =
1535          (struct qla8044_reset_template_hdr *) vha->reset_tmplt.buff;
1536
1537         /* Validate the template header size and signature */
1538         tmplt_hdr_size = vha->reset_tmplt.hdr->hdr_size/sizeof(uint32_t);
1539         if ((tmplt_hdr_size != tmplt_hdr_def_size) ||
1540             (vha->reset_tmplt.hdr->signature != RESET_TMPLT_HDR_SIGNATURE)) {
1541                 ql_log(ql_log_fatal, vha, 0xb0bb,
1542                     "%s: Template Header size invalid %d "
1543                     "tmplt_hdr_def_size %d!!!\n", __func__,
1544                     tmplt_hdr_size, tmplt_hdr_def_size);
1545                 goto exit_read_template_error;
1546         }
1547
1548         addr = QLA8044_RESET_TEMPLATE_ADDR + vha->reset_tmplt.hdr->hdr_size;
1549         p_buff = vha->reset_tmplt.buff + vha->reset_tmplt.hdr->hdr_size;
1550         tmplt_hdr_def_size = (vha->reset_tmplt.hdr->size -
1551             vha->reset_tmplt.hdr->hdr_size)/sizeof(uint32_t);
1552
1553         ql_dbg(ql_dbg_p3p, vha, 0xb0bc,
1554             "%s: Read rest of the template size %d\n",
1555             __func__, vha->reset_tmplt.hdr->size);
1556
1557         /* Copy rest of the template */
1558         if (qla8044_read_flash_data(vha, p_buff, addr, tmplt_hdr_def_size)) {
1559                 ql_log(ql_log_fatal, vha, 0xb0bd,
1560                     "%s: Failed to read reset tempelate\n", __func__);
1561                 goto exit_read_template_error;
1562         }
1563
1564         /* Integrity check */
1565         if (qla8044_reset_seq_checksum_test(vha)) {
1566                 ql_log(ql_log_fatal, vha, 0xb0be,
1567                     "%s: Reset Seq checksum failed!\n", __func__);
1568                 goto exit_read_template_error;
1569         }
1570
1571         ql_dbg(ql_dbg_p3p, vha, 0xb0bf,
1572             "%s: Reset Seq checksum passed! Get stop, "
1573             "start and init seq offsets\n", __func__);
1574
1575         /* Get STOP, START, INIT sequence offsets */
1576         vha->reset_tmplt.init_offset = vha->reset_tmplt.buff +
1577             vha->reset_tmplt.hdr->init_seq_offset;
1578
1579         vha->reset_tmplt.start_offset = vha->reset_tmplt.buff +
1580             vha->reset_tmplt.hdr->start_seq_offset;
1581
1582         vha->reset_tmplt.stop_offset = vha->reset_tmplt.buff +
1583             vha->reset_tmplt.hdr->hdr_size;
1584
1585         qla8044_dump_reset_seq_hdr(vha);
1586
1587         goto exit_read_reset_template;
1588
1589 exit_read_template_error:
1590         vfree(vha->reset_tmplt.buff);
1591
1592 exit_read_reset_template:
1593         return;
1594 }
1595
1596 void
1597 qla8044_set_idc_dontreset(struct scsi_qla_host *vha)
1598 {
1599         uint32_t idc_ctrl;
1600         struct qla_hw_data *ha = vha->hw;
1601
1602         idc_ctrl = qla8044_rd_reg(ha, QLA8044_IDC_DRV_CTRL);
1603         idc_ctrl |= DONTRESET_BIT0;
1604         ql_dbg(ql_dbg_p3p, vha, 0xb0c0,
1605             "%s: idc_ctrl = %d\n", __func__, idc_ctrl);
1606         qla8044_wr_reg(ha, QLA8044_IDC_DRV_CTRL, idc_ctrl);
1607 }
1608
1609 inline void
1610 qla8044_set_rst_ready(struct scsi_qla_host *vha)
1611 {
1612         uint32_t drv_state;
1613         struct qla_hw_data *ha = vha->hw;
1614
1615         drv_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX);
1616
1617         /* For ISP8044, drv_active register has 1 bit per function,
1618          * shift 1 by func_num to set a bit for the function.*/
1619         drv_state |= (1 << ha->portnum);
1620
1621         ql_log(ql_log_info, vha, 0xb0c1,
1622             "%s(%ld): drv_state: 0x%08x\n",
1623             __func__, vha->host_no, drv_state);
1624         qla8044_wr_direct(vha, QLA8044_CRB_DRV_STATE_INDEX, drv_state);
1625 }
1626
1627 /**
1628  * qla8044_need_reset_handler - Code to start reset sequence
1629  * @ha: pointer to adapter structure
1630  *
1631  * Note: IDC lock must be held upon entry
1632  **/
1633 static void
1634 qla8044_need_reset_handler(struct scsi_qla_host *vha)
1635 {
1636         uint32_t dev_state = 0, drv_state, drv_active;
1637         unsigned long reset_timeout, dev_init_timeout;
1638         struct qla_hw_data *ha = vha->hw;
1639
1640         ql_log(ql_log_fatal, vha, 0xb0c2,
1641             "%s: Performing ISP error recovery\n", __func__);
1642
1643         if (vha->flags.online) {
1644                 qla8044_idc_unlock(ha);
1645                 qla2x00_abort_isp_cleanup(vha);
1646                 ha->isp_ops->get_flash_version(vha, vha->req->ring);
1647                 ha->isp_ops->nvram_config(vha);
1648                 qla8044_idc_lock(ha);
1649         }
1650
1651         drv_state = qla8044_rd_direct(vha,
1652             QLA8044_CRB_DRV_STATE_INDEX);
1653         drv_active = qla8044_rd_direct(vha,
1654             QLA8044_CRB_DRV_ACTIVE_INDEX);
1655
1656         ql_log(ql_log_info, vha, 0xb0c5,
1657             "%s(%ld): drv_state = 0x%x, drv_active = 0x%x\n",
1658             __func__, vha->host_no, drv_state, drv_active);
1659
1660         if (!ha->flags.nic_core_reset_owner) {
1661                 ql_dbg(ql_dbg_p3p, vha, 0xb0c3,
1662                     "%s(%ld): reset acknowledged\n",
1663                     __func__, vha->host_no);
1664                 qla8044_set_rst_ready(vha);
1665
1666                 /* Non-reset owners ACK Reset and wait for device INIT state
1667                  * as part of Reset Recovery by Reset Owner
1668                  */
1669                 dev_init_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
1670
1671                 do {
1672                         if (time_after_eq(jiffies, dev_init_timeout)) {
1673                                 ql_log(ql_log_info, vha, 0xb0c4,
1674                                     "%s: Non Reset owner: Reset Ack Timeout!\n",
1675                                     __func__);
1676                                 break;
1677                         }
1678
1679                         qla8044_idc_unlock(ha);
1680                         msleep(1000);
1681                         qla8044_idc_lock(ha);
1682
1683                         dev_state = qla8044_rd_direct(vha,
1684                                         QLA8044_CRB_DEV_STATE_INDEX);
1685                 } while (((drv_state & drv_active) != drv_active) &&
1686                     (dev_state == QLA8XXX_DEV_NEED_RESET));
1687         } else {
1688                 qla8044_set_rst_ready(vha);
1689
1690                 /* wait for 10 seconds for reset ack from all functions */
1691                 reset_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
1692
1693                 while ((drv_state & drv_active) != drv_active) {
1694                         if (time_after_eq(jiffies, reset_timeout)) {
1695                                 ql_log(ql_log_info, vha, 0xb0c6,
1696                                     "%s: RESET TIMEOUT!"
1697                                     "drv_state: 0x%08x, drv_active: 0x%08x\n",
1698                                     QLA2XXX_DRIVER_NAME, drv_state, drv_active);
1699                                 break;
1700                         }
1701
1702                         qla8044_idc_unlock(ha);
1703                         msleep(1000);
1704                         qla8044_idc_lock(ha);
1705
1706                         drv_state = qla8044_rd_direct(vha,
1707                             QLA8044_CRB_DRV_STATE_INDEX);
1708                         drv_active = qla8044_rd_direct(vha,
1709                             QLA8044_CRB_DRV_ACTIVE_INDEX);
1710                 }
1711
1712                 if (drv_state != drv_active) {
1713                         ql_log(ql_log_info, vha, 0xb0c7,
1714                             "%s(%ld): Reset_owner turning off drv_active "
1715                             "of non-acking function 0x%x\n", __func__,
1716                             vha->host_no, (drv_active ^ drv_state));
1717                         drv_active = drv_active & drv_state;
1718                         qla8044_wr_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX,
1719                             drv_active);
1720                 }
1721
1722                 /*
1723                 * Clear RESET OWNER, will be set at next reset
1724                 * by next RST_OWNER
1725                 */
1726                 ha->flags.nic_core_reset_owner = 0;
1727
1728                 /* Start Reset Recovery */
1729                 qla8044_device_bootstrap(vha);
1730         }
1731 }
1732
1733 static void
1734 qla8044_set_drv_active(struct scsi_qla_host *vha)
1735 {
1736         uint32_t drv_active;
1737         struct qla_hw_data *ha = vha->hw;
1738
1739         drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX);
1740
1741         /* For ISP8044, drv_active register has 1 bit per function,
1742          * shift 1 by func_num to set a bit for the function.*/
1743         drv_active |= (1 << ha->portnum);
1744
1745         ql_log(ql_log_info, vha, 0xb0c8,
1746             "%s(%ld): drv_active: 0x%08x\n",
1747             __func__, vha->host_no, drv_active);
1748         qla8044_wr_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX, drv_active);
1749 }
1750
1751 static int
1752 qla8044_check_drv_active(struct scsi_qla_host *vha)
1753 {
1754         uint32_t drv_active;
1755         struct qla_hw_data *ha = vha->hw;
1756
1757         drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX);
1758         if (drv_active & (1 << ha->portnum))
1759                 return QLA_SUCCESS;
1760         else
1761                 return QLA_TEST_FAILED;
1762 }
1763
1764 static void
1765 qla8044_clear_idc_dontreset(struct scsi_qla_host *vha)
1766 {
1767         uint32_t idc_ctrl;
1768         struct qla_hw_data *ha = vha->hw;
1769
1770         idc_ctrl = qla8044_rd_reg(ha, QLA8044_IDC_DRV_CTRL);
1771         idc_ctrl &= ~DONTRESET_BIT0;
1772         ql_log(ql_log_info, vha, 0xb0c9,
1773             "%s: idc_ctrl = %d\n", __func__,
1774             idc_ctrl);
1775         qla8044_wr_reg(ha, QLA8044_IDC_DRV_CTRL, idc_ctrl);
1776 }
1777
1778 static int
1779 qla8044_set_idc_ver(struct scsi_qla_host *vha)
1780 {
1781         int idc_ver;
1782         uint32_t drv_active;
1783         int rval = QLA_SUCCESS;
1784         struct qla_hw_data *ha = vha->hw;
1785
1786         drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX);
1787         if (drv_active == (1 << ha->portnum)) {
1788                 idc_ver = qla8044_rd_direct(vha,
1789                     QLA8044_CRB_DRV_IDC_VERSION_INDEX);
1790                 idc_ver &= (~0xFF);
1791                 idc_ver |= QLA8044_IDC_VER_MAJ_VALUE;
1792                 qla8044_wr_direct(vha, QLA8044_CRB_DRV_IDC_VERSION_INDEX,
1793                     idc_ver);
1794                 ql_log(ql_log_info, vha, 0xb0ca,
1795                     "%s: IDC version updated to %d\n",
1796                     __func__, idc_ver);
1797         } else {
1798                 idc_ver = qla8044_rd_direct(vha,
1799                     QLA8044_CRB_DRV_IDC_VERSION_INDEX);
1800                 idc_ver &= 0xFF;
1801                 if (QLA8044_IDC_VER_MAJ_VALUE != idc_ver) {
1802                         ql_log(ql_log_info, vha, 0xb0cb,
1803                             "%s: qla4xxx driver IDC version %d "
1804                             "is not compatible with IDC version %d "
1805                             "of other drivers!\n",
1806                             __func__, QLA8044_IDC_VER_MAJ_VALUE,
1807                             idc_ver);
1808                         rval = QLA_FUNCTION_FAILED;
1809                         goto exit_set_idc_ver;
1810                 }
1811         }
1812
1813         /* Update IDC_MINOR_VERSION */
1814         idc_ver = qla8044_rd_reg(ha, QLA8044_CRB_IDC_VER_MINOR);
1815         idc_ver &= ~(0x03 << (ha->portnum * 2));
1816         idc_ver |= (QLA8044_IDC_VER_MIN_VALUE << (ha->portnum * 2));
1817         qla8044_wr_reg(ha, QLA8044_CRB_IDC_VER_MINOR, idc_ver);
1818
1819 exit_set_idc_ver:
1820         return rval;
1821 }
1822
1823 static int
1824 qla8044_update_idc_reg(struct scsi_qla_host *vha)
1825 {
1826         uint32_t drv_active;
1827         int rval = QLA_SUCCESS;
1828         struct qla_hw_data *ha = vha->hw;
1829
1830         if (vha->flags.init_done)
1831                 goto exit_update_idc_reg;
1832
1833         qla8044_idc_lock(ha);
1834         qla8044_set_drv_active(vha);
1835
1836         drv_active = qla8044_rd_direct(vha,
1837             QLA8044_CRB_DRV_ACTIVE_INDEX);
1838
1839         /* If we are the first driver to load and
1840          * ql2xdontresethba is not set, clear IDC_CTRL BIT0. */
1841         if ((drv_active == (1 << ha->portnum)) && !ql2xdontresethba)
1842                 qla8044_clear_idc_dontreset(vha);
1843
1844         rval = qla8044_set_idc_ver(vha);
1845         if (rval == QLA_FUNCTION_FAILED)
1846                 qla8044_clear_drv_active(ha);
1847         qla8044_idc_unlock(ha);
1848
1849 exit_update_idc_reg:
1850         return rval;
1851 }
1852
1853 /**
1854  * qla8044_need_qsnt_handler - Code to start qsnt
1855  * @ha: pointer to adapter structure
1856  **/
1857 static void
1858 qla8044_need_qsnt_handler(struct scsi_qla_host *vha)
1859 {
1860         unsigned long qsnt_timeout;
1861         uint32_t drv_state, drv_active, dev_state;
1862         struct qla_hw_data *ha = vha->hw;
1863
1864         if (vha->flags.online)
1865                 qla2x00_quiesce_io(vha);
1866         else
1867                 return;
1868
1869         qla8044_set_qsnt_ready(vha);
1870
1871         /* Wait for 30 secs for all functions to ack qsnt mode */
1872         qsnt_timeout = jiffies + (QSNT_ACK_TOV * HZ);
1873         drv_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX);
1874         drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX);
1875
1876         /* Shift drv_active by 1 to match drv_state. As quiescent ready bit
1877            position is at bit 1 and drv active is at bit 0 */
1878         drv_active = drv_active << 1;
1879
1880         while (drv_state != drv_active) {
1881                 if (time_after_eq(jiffies, qsnt_timeout)) {
1882                         /* Other functions did not ack, changing state to
1883                          * DEV_READY
1884                          */
1885                         clear_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags);
1886                         qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX,
1887                                             QLA8XXX_DEV_READY);
1888                         qla8044_clear_qsnt_ready(vha);
1889                         ql_log(ql_log_info, vha, 0xb0cc,
1890                             "Timeout waiting for quiescent ack!!!\n");
1891                         return;
1892                 }
1893                 qla8044_idc_unlock(ha);
1894                 msleep(1000);
1895                 qla8044_idc_lock(ha);
1896
1897                 drv_state = qla8044_rd_direct(vha,
1898                     QLA8044_CRB_DRV_STATE_INDEX);
1899                 drv_active = qla8044_rd_direct(vha,
1900                     QLA8044_CRB_DRV_ACTIVE_INDEX);
1901                 drv_active = drv_active << 1;
1902         }
1903
1904         /* All functions have Acked. Set quiescent state */
1905         dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX);
1906
1907         if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
1908                 qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX,
1909                     QLA8XXX_DEV_QUIESCENT);
1910                 ql_log(ql_log_info, vha, 0xb0cd,
1911                     "%s: HW State: QUIESCENT\n", __func__);
1912         }
1913 }
1914
1915 /*
1916  * qla8044_device_state_handler - Adapter state machine
1917  * @ha: pointer to host adapter structure.
1918  *
1919  * Note: IDC lock must be UNLOCKED upon entry
1920  **/
1921 int
1922 qla8044_device_state_handler(struct scsi_qla_host *vha)
1923 {
1924         uint32_t dev_state;
1925         int rval = QLA_SUCCESS;
1926         unsigned long dev_init_timeout;
1927         struct qla_hw_data *ha = vha->hw;
1928
1929         rval = qla8044_update_idc_reg(vha);
1930         if (rval == QLA_FUNCTION_FAILED)
1931                 goto exit_error;
1932
1933         dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX);
1934         ql_dbg(ql_dbg_p3p, vha, 0xb0ce,
1935             "Device state is 0x%x = %s\n",
1936             dev_state, dev_state < MAX_STATES ?
1937             qdev_state(dev_state) : "Unknown");
1938
1939         /* wait for 30 seconds for device to go ready */
1940         dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
1941
1942         qla8044_idc_lock(ha);
1943
1944         while (1) {
1945                 if (time_after_eq(jiffies, dev_init_timeout)) {
1946                         if (qla8044_check_drv_active(vha) == QLA_SUCCESS) {
1947                                 ql_log(ql_log_warn, vha, 0xb0cf,
1948                                     "%s: Device Init Failed 0x%x = %s\n",
1949                                     QLA2XXX_DRIVER_NAME, dev_state,
1950                                     dev_state < MAX_STATES ?
1951                                     qdev_state(dev_state) : "Unknown");
1952                                 qla8044_wr_direct(vha,
1953                                     QLA8044_CRB_DEV_STATE_INDEX,
1954                                     QLA8XXX_DEV_FAILED);
1955                         }
1956                 }
1957
1958                 dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX);
1959                 ql_log(ql_log_info, vha, 0xb0d0,
1960                     "Device state is 0x%x = %s\n",
1961                     dev_state, dev_state < MAX_STATES ?
1962                     qdev_state(dev_state) : "Unknown");
1963
1964                 /* NOTE: Make sure idc unlocked upon exit of switch statement */
1965                 switch (dev_state) {
1966                 case QLA8XXX_DEV_READY:
1967                         ha->flags.nic_core_reset_owner = 0;
1968                         goto exit;
1969                 case QLA8XXX_DEV_COLD:
1970                         rval = qla8044_device_bootstrap(vha);
1971                         break;
1972                 case QLA8XXX_DEV_INITIALIZING:
1973                         qla8044_idc_unlock(ha);
1974                         msleep(1000);
1975                         qla8044_idc_lock(ha);
1976                         break;
1977                 case QLA8XXX_DEV_NEED_RESET:
1978                         /* For ISP8044, if NEED_RESET is set by any driver,
1979                          * it should be honored, irrespective of IDC_CTRL
1980                          * DONTRESET_BIT0 */
1981                         qla8044_need_reset_handler(vha);
1982                         break;
1983                 case QLA8XXX_DEV_NEED_QUIESCENT:
1984                         /* idc locked/unlocked in handler */
1985                         qla8044_need_qsnt_handler(vha);
1986
1987                         /* Reset the init timeout after qsnt handler */
1988                         dev_init_timeout = jiffies +
1989                             (ha->fcoe_reset_timeout * HZ);
1990                         break;
1991                 case QLA8XXX_DEV_QUIESCENT:
1992                         ql_log(ql_log_info, vha, 0xb0d1,
1993                             "HW State: QUIESCENT\n");
1994
1995                         qla8044_idc_unlock(ha);
1996                         msleep(1000);
1997                         qla8044_idc_lock(ha);
1998
1999                         /* Reset the init timeout after qsnt handler */
2000                         dev_init_timeout = jiffies +
2001                             (ha->fcoe_reset_timeout * HZ);
2002                         break;
2003                 case QLA8XXX_DEV_FAILED:
2004                         ha->flags.nic_core_reset_owner = 0;
2005                         qla8044_idc_unlock(ha);
2006                         qla8xxx_dev_failed_handler(vha);
2007                         rval = QLA_FUNCTION_FAILED;
2008                         qla8044_idc_lock(ha);
2009                         goto exit;
2010                 default:
2011                         qla8044_idc_unlock(ha);
2012                         qla8xxx_dev_failed_handler(vha);
2013                         rval = QLA_FUNCTION_FAILED;
2014                         qla8044_idc_lock(ha);
2015                         goto exit;
2016                 }
2017         }
2018 exit:
2019         qla8044_idc_unlock(ha);
2020
2021 exit_error:
2022         return rval;
2023 }
2024
2025 /**
2026  * qla4_8xxx_check_temp - Check the ISP82XX temperature.
2027  * @ha: adapter block pointer.
2028  *
2029  * Note: The caller should not hold the idc lock.
2030  **/
2031 static int
2032 qla8044_check_temp(struct scsi_qla_host *vha)
2033 {
2034         uint32_t temp, temp_state, temp_val;
2035         int status = QLA_SUCCESS;
2036
2037         temp = qla8044_rd_direct(vha, QLA8044_CRB_TEMP_STATE_INDEX);
2038         temp_state = qla82xx_get_temp_state(temp);
2039         temp_val = qla82xx_get_temp_val(temp);
2040
2041         if (temp_state == QLA82XX_TEMP_PANIC) {
2042                 ql_log(ql_log_warn, vha, 0xb0d2,
2043                     "Device temperature %d degrees C"
2044                     " exceeds maximum allowed. Hardware has been shut"
2045                     " down\n", temp_val);
2046                 status = QLA_FUNCTION_FAILED;
2047                 return status;
2048         } else if (temp_state == QLA82XX_TEMP_WARN) {
2049                 ql_log(ql_log_warn, vha, 0xb0d3,
2050                     "Device temperature %d"
2051                     " degrees C exceeds operating range."
2052                     " Immediate action needed.\n", temp_val);
2053         }
2054         return 0;
2055 }
2056
2057 int qla8044_read_temperature(scsi_qla_host_t *vha)
2058 {
2059         uint32_t temp;
2060
2061         temp = qla8044_rd_direct(vha, QLA8044_CRB_TEMP_STATE_INDEX);
2062         return qla82xx_get_temp_val(temp);
2063 }
2064
2065 /**
2066  * qla8044_check_fw_alive  - Check firmware health
2067  * @ha: Pointer to host adapter structure.
2068  *
2069  * Context: Interrupt
2070  **/
2071 int
2072 qla8044_check_fw_alive(struct scsi_qla_host *vha)
2073 {
2074         uint32_t fw_heartbeat_counter;
2075         uint32_t halt_status1, halt_status2;
2076         int status = QLA_SUCCESS;
2077
2078         fw_heartbeat_counter = qla8044_rd_direct(vha,
2079             QLA8044_PEG_ALIVE_COUNTER_INDEX);
2080
2081         /* If PEG_ALIVE_COUNTER is 0xffffffff, AER/EEH is in progress, ignore */
2082         if (fw_heartbeat_counter == 0xffffffff) {
2083                 ql_dbg(ql_dbg_p3p, vha, 0xb0d4,
2084                     "scsi%ld: %s: Device in frozen "
2085                     "state, QLA82XX_PEG_ALIVE_COUNTER is 0xffffffff\n",
2086                     vha->host_no, __func__);
2087                 return status;
2088         }
2089
2090         if (vha->fw_heartbeat_counter == fw_heartbeat_counter) {
2091                 vha->seconds_since_last_heartbeat++;
2092                 /* FW not alive after 2 seconds */
2093                 if (vha->seconds_since_last_heartbeat == 2) {
2094                         vha->seconds_since_last_heartbeat = 0;
2095                         halt_status1 = qla8044_rd_direct(vha,
2096                             QLA8044_PEG_HALT_STATUS1_INDEX);
2097                         halt_status2 = qla8044_rd_direct(vha,
2098                             QLA8044_PEG_HALT_STATUS2_INDEX);
2099
2100                         ql_log(ql_log_info, vha, 0xb0d5,
2101                             "scsi(%ld): %s, ISP8044 "
2102                             "Dumping hw/fw registers:\n"
2103                             " PEG_HALT_STATUS1: 0x%x, "
2104                             "PEG_HALT_STATUS2: 0x%x,\n",
2105                             vha->host_no, __func__, halt_status1,
2106                             halt_status2);
2107                         status = QLA_FUNCTION_FAILED;
2108                 }
2109         } else
2110                 vha->seconds_since_last_heartbeat = 0;
2111
2112         vha->fw_heartbeat_counter = fw_heartbeat_counter;
2113         return status;
2114 }
2115
2116 void
2117 qla8044_watchdog(struct scsi_qla_host *vha)
2118 {
2119         uint32_t dev_state, halt_status;
2120         int halt_status_unrecoverable = 0;
2121         struct qla_hw_data *ha = vha->hw;
2122
2123         /* don't poll if reset is going on or FW hang in quiescent state */
2124         if (!(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) ||
2125             test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))) {
2126                 dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX);
2127
2128                 if (qla8044_check_fw_alive(vha)) {
2129                         ha->flags.isp82xx_fw_hung = 1;
2130                         ql_log(ql_log_warn, vha, 0xb10a,
2131                             "Firmware hung.\n");
2132                         qla82xx_clear_pending_mbx(vha);
2133                 }
2134
2135                 if (qla8044_check_temp(vha)) {
2136                         set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags);
2137                         ha->flags.isp82xx_fw_hung = 1;
2138                         qla2xxx_wake_dpc(vha);
2139                 } else if (dev_state == QLA8XXX_DEV_NEED_RESET &&
2140                            !test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) {
2141                         ql_log(ql_log_info, vha, 0xb0d6,
2142                             "%s: HW State: NEED RESET!\n",
2143                             __func__);
2144                         set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2145                         qla2xxx_wake_dpc(vha);
2146                 } else if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT &&
2147                     !test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) {
2148                         ql_log(ql_log_info, vha, 0xb0d7,
2149                             "%s: HW State: NEED QUIES detected!\n",
2150                             __func__);
2151                         set_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags);
2152                         qla2xxx_wake_dpc(vha);
2153                 } else  {
2154                         /* Check firmware health */
2155                         if (ha->flags.isp82xx_fw_hung) {
2156                                 halt_status = qla8044_rd_direct(vha,
2157                                         QLA8044_PEG_HALT_STATUS1_INDEX);
2158                                 if (halt_status &
2159                                     QLA8044_HALT_STATUS_FW_RESET) {
2160                                         ql_log(ql_log_fatal, vha,
2161                                             0xb0d8, "%s: Firmware "
2162                                             "error detected device "
2163                                             "is being reset\n",
2164                                             __func__);
2165                                 } else if (halt_status &
2166                                             QLA8044_HALT_STATUS_UNRECOVERABLE) {
2167                                                 halt_status_unrecoverable = 1;
2168                                 }
2169
2170                                 /* Since we cannot change dev_state in interrupt
2171                                  * context, set appropriate DPC flag then wakeup
2172                                  *  DPC */
2173                                 if (halt_status_unrecoverable) {
2174                                         set_bit(ISP_UNRECOVERABLE,
2175                                             &vha->dpc_flags);
2176                                 } else {
2177                                         if (dev_state ==
2178                                             QLA8XXX_DEV_QUIESCENT) {
2179                                                 set_bit(FCOE_CTX_RESET_NEEDED,
2180                                                     &vha->dpc_flags);
2181                                                 ql_log(ql_log_info, vha, 0xb0d9,
2182                                                     "%s: FW CONTEXT Reset "
2183                                                     "needed!\n", __func__);
2184                                         } else {
2185                                                 ql_log(ql_log_info, vha,
2186                                                     0xb0da, "%s: "
2187                                                     "detect abort needed\n",
2188                                                     __func__);
2189                                                 set_bit(ISP_ABORT_NEEDED,
2190                                                     &vha->dpc_flags);
2191                                         }
2192                                 }
2193                                 qla2xxx_wake_dpc(vha);
2194                         }
2195                 }
2196
2197         }
2198 }
2199
2200 static int
2201 qla8044_minidump_process_control(struct scsi_qla_host *vha,
2202                                  struct qla8044_minidump_entry_hdr *entry_hdr)
2203 {
2204         struct qla8044_minidump_entry_crb *crb_entry;
2205         uint32_t read_value, opcode, poll_time, addr, index;
2206         uint32_t crb_addr, rval = QLA_SUCCESS;
2207         unsigned long wtime;
2208         struct qla8044_minidump_template_hdr *tmplt_hdr;
2209         int i;
2210         struct qla_hw_data *ha = vha->hw;
2211
2212         ql_dbg(ql_dbg_p3p, vha, 0xb0dd, "Entering fn: %s\n", __func__);
2213         tmplt_hdr = (struct qla8044_minidump_template_hdr *)
2214                 ha->md_tmplt_hdr;
2215         crb_entry = (struct qla8044_minidump_entry_crb *)entry_hdr;
2216
2217         crb_addr = crb_entry->addr;
2218         for (i = 0; i < crb_entry->op_count; i++) {
2219                 opcode = crb_entry->crb_ctrl.opcode;
2220
2221                 if (opcode & QLA82XX_DBG_OPCODE_WR) {
2222                         qla8044_wr_reg_indirect(vha, crb_addr,
2223                             crb_entry->value_1);
2224                         opcode &= ~QLA82XX_DBG_OPCODE_WR;
2225                 }
2226
2227                 if (opcode & QLA82XX_DBG_OPCODE_RW) {
2228                         qla8044_rd_reg_indirect(vha, crb_addr, &read_value);
2229                         qla8044_wr_reg_indirect(vha, crb_addr, read_value);
2230                         opcode &= ~QLA82XX_DBG_OPCODE_RW;
2231                 }
2232
2233                 if (opcode & QLA82XX_DBG_OPCODE_AND) {
2234                         qla8044_rd_reg_indirect(vha, crb_addr, &read_value);
2235                         read_value &= crb_entry->value_2;
2236                         opcode &= ~QLA82XX_DBG_OPCODE_AND;
2237                         if (opcode & QLA82XX_DBG_OPCODE_OR) {
2238                                 read_value |= crb_entry->value_3;
2239                                 opcode &= ~QLA82XX_DBG_OPCODE_OR;
2240                         }
2241                         qla8044_wr_reg_indirect(vha, crb_addr, read_value);
2242                 }
2243                 if (opcode & QLA82XX_DBG_OPCODE_OR) {
2244                         qla8044_rd_reg_indirect(vha, crb_addr, &read_value);
2245                         read_value |= crb_entry->value_3;
2246                         qla8044_wr_reg_indirect(vha, crb_addr, read_value);
2247                         opcode &= ~QLA82XX_DBG_OPCODE_OR;
2248                 }
2249                 if (opcode & QLA82XX_DBG_OPCODE_POLL) {
2250                         poll_time = crb_entry->crb_strd.poll_timeout;
2251                         wtime = jiffies + poll_time;
2252                         qla8044_rd_reg_indirect(vha, crb_addr, &read_value);
2253
2254                         do {
2255                                 if ((read_value & crb_entry->value_2) ==
2256                                     crb_entry->value_1) {
2257                                         break;
2258                                 } else if (time_after_eq(jiffies, wtime)) {
2259                                         /* capturing dump failed */
2260                                         rval = QLA_FUNCTION_FAILED;
2261                                         break;
2262                                 } else {
2263                                         qla8044_rd_reg_indirect(vha,
2264                                             crb_addr, &read_value);
2265                                 }
2266                         } while (1);
2267                         opcode &= ~QLA82XX_DBG_OPCODE_POLL;
2268                 }
2269
2270                 if (opcode & QLA82XX_DBG_OPCODE_RDSTATE) {
2271                         if (crb_entry->crb_strd.state_index_a) {
2272                                 index = crb_entry->crb_strd.state_index_a;
2273                                 addr = tmplt_hdr->saved_state_array[index];
2274                         } else {
2275                                 addr = crb_addr;
2276                         }
2277
2278                         qla8044_rd_reg_indirect(vha, addr, &read_value);
2279                         index = crb_entry->crb_ctrl.state_index_v;
2280                         tmplt_hdr->saved_state_array[index] = read_value;
2281                         opcode &= ~QLA82XX_DBG_OPCODE_RDSTATE;
2282                 }
2283
2284                 if (opcode & QLA82XX_DBG_OPCODE_WRSTATE) {
2285                         if (crb_entry->crb_strd.state_index_a) {
2286                                 index = crb_entry->crb_strd.state_index_a;
2287                                 addr = tmplt_hdr->saved_state_array[index];
2288                         } else {
2289                                 addr = crb_addr;
2290                         }
2291
2292                         if (crb_entry->crb_ctrl.state_index_v) {
2293                                 index = crb_entry->crb_ctrl.state_index_v;
2294                                 read_value =
2295                                     tmplt_hdr->saved_state_array[index];
2296                         } else {
2297                                 read_value = crb_entry->value_1;
2298                         }
2299
2300                         qla8044_wr_reg_indirect(vha, addr, read_value);
2301                         opcode &= ~QLA82XX_DBG_OPCODE_WRSTATE;
2302                 }
2303
2304                 if (opcode & QLA82XX_DBG_OPCODE_MDSTATE) {
2305                         index = crb_entry->crb_ctrl.state_index_v;
2306                         read_value = tmplt_hdr->saved_state_array[index];
2307                         read_value <<= crb_entry->crb_ctrl.shl;
2308                         read_value >>= crb_entry->crb_ctrl.shr;
2309                         if (crb_entry->value_2)
2310                                 read_value &= crb_entry->value_2;
2311                         read_value |= crb_entry->value_3;
2312                         read_value += crb_entry->value_1;
2313                         tmplt_hdr->saved_state_array[index] = read_value;
2314                         opcode &= ~QLA82XX_DBG_OPCODE_MDSTATE;
2315                 }
2316                 crb_addr += crb_entry->crb_strd.addr_stride;
2317         }
2318         return rval;
2319 }
2320
2321 static void
2322 qla8044_minidump_process_rdcrb(struct scsi_qla_host *vha,
2323         struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
2324 {
2325         uint32_t r_addr, r_stride, loop_cnt, i, r_value;
2326         struct qla8044_minidump_entry_crb *crb_hdr;
2327         uint32_t *data_ptr = *d_ptr;
2328
2329         ql_dbg(ql_dbg_p3p, vha, 0xb0de, "Entering fn: %s\n", __func__);
2330         crb_hdr = (struct qla8044_minidump_entry_crb *)entry_hdr;
2331         r_addr = crb_hdr->addr;
2332         r_stride = crb_hdr->crb_strd.addr_stride;
2333         loop_cnt = crb_hdr->op_count;
2334
2335         for (i = 0; i < loop_cnt; i++) {
2336                 qla8044_rd_reg_indirect(vha, r_addr, &r_value);
2337                 *data_ptr++ = r_addr;
2338                 *data_ptr++ = r_value;
2339                 r_addr += r_stride;
2340         }
2341         *d_ptr = data_ptr;
2342 }
2343
2344 static int
2345 qla8044_minidump_process_rdmem(struct scsi_qla_host *vha,
2346         struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
2347 {
2348         uint32_t r_addr, r_value, r_data;
2349         uint32_t i, j, loop_cnt;
2350         struct qla8044_minidump_entry_rdmem *m_hdr;
2351         unsigned long flags;
2352         uint32_t *data_ptr = *d_ptr;
2353         struct qla_hw_data *ha = vha->hw;
2354
2355         ql_dbg(ql_dbg_p3p, vha, 0xb0df, "Entering fn: %s\n", __func__);
2356         m_hdr = (struct qla8044_minidump_entry_rdmem *)entry_hdr;
2357         r_addr = m_hdr->read_addr;
2358         loop_cnt = m_hdr->read_data_size/16;
2359
2360         ql_dbg(ql_dbg_p3p, vha, 0xb0f0,
2361             "[%s]: Read addr: 0x%x, read_data_size: 0x%x\n",
2362             __func__, r_addr, m_hdr->read_data_size);
2363
2364         if (r_addr & 0xf) {
2365                 ql_dbg(ql_dbg_p3p, vha, 0xb0f1,
2366                     "[%s]: Read addr 0x%x not 16 bytes aligned\n",
2367                     __func__, r_addr);
2368                 return QLA_FUNCTION_FAILED;
2369         }
2370
2371         if (m_hdr->read_data_size % 16) {
2372                 ql_dbg(ql_dbg_p3p, vha, 0xb0f2,
2373                     "[%s]: Read data[0x%x] not multiple of 16 bytes\n",
2374                     __func__, m_hdr->read_data_size);
2375                 return QLA_FUNCTION_FAILED;
2376         }
2377
2378         ql_dbg(ql_dbg_p3p, vha, 0xb0f3,
2379             "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n",
2380             __func__, r_addr, m_hdr->read_data_size, loop_cnt);
2381
2382         write_lock_irqsave(&ha->hw_lock, flags);
2383         for (i = 0; i < loop_cnt; i++) {
2384                 qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_ADDR_LO, r_addr);
2385                 r_value = 0;
2386                 qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_ADDR_HI, r_value);
2387                 r_value = MIU_TA_CTL_ENABLE;
2388                 qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_CTRL, r_value);
2389                 r_value = MIU_TA_CTL_START_ENABLE;
2390                 qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_CTRL, r_value);
2391
2392                 for (j = 0; j < MAX_CTL_CHECK; j++) {
2393                         qla8044_rd_reg_indirect(vha, MD_MIU_TEST_AGT_CTRL,
2394                             &r_value);
2395                         if ((r_value & MIU_TA_CTL_BUSY) == 0)
2396                                 break;
2397                 }
2398
2399                 if (j >= MAX_CTL_CHECK) {
2400                         printk_ratelimited(KERN_ERR
2401                             "%s: failed to read through agent\n", __func__);
2402                         write_unlock_irqrestore(&ha->hw_lock, flags);
2403                         return QLA_SUCCESS;
2404                 }
2405
2406                 for (j = 0; j < 4; j++) {
2407                         qla8044_rd_reg_indirect(vha, MD_MIU_TEST_AGT_RDDATA[j],
2408                             &r_data);
2409                         *data_ptr++ = r_data;
2410                 }
2411
2412                 r_addr += 16;
2413         }
2414         write_unlock_irqrestore(&ha->hw_lock, flags);
2415
2416         ql_dbg(ql_dbg_p3p, vha, 0xb0f4,
2417             "Leaving fn: %s datacount: 0x%x\n",
2418              __func__, (loop_cnt * 16));
2419
2420         *d_ptr = data_ptr;
2421         return QLA_SUCCESS;
2422 }
2423
2424 /* ISP83xx flash read for _RDROM _BOARD */
2425 static uint32_t
2426 qla8044_minidump_process_rdrom(struct scsi_qla_host *vha,
2427         struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
2428 {
2429         uint32_t fl_addr, u32_count, rval;
2430         struct qla8044_minidump_entry_rdrom *rom_hdr;
2431         uint32_t *data_ptr = *d_ptr;
2432
2433         rom_hdr = (struct qla8044_minidump_entry_rdrom *)entry_hdr;
2434         fl_addr = rom_hdr->read_addr;
2435         u32_count = (rom_hdr->read_data_size)/sizeof(uint32_t);
2436
2437         ql_dbg(ql_dbg_p3p, vha, 0xb0f5, "[%s]: fl_addr: 0x%x, count: 0x%x\n",
2438             __func__, fl_addr, u32_count);
2439
2440         rval = qla8044_lockless_flash_read_u32(vha, fl_addr,
2441             (u8 *)(data_ptr), u32_count);
2442
2443         if (rval != QLA_SUCCESS) {
2444                 ql_log(ql_log_fatal, vha, 0xb0f6,
2445                     "%s: Flash Read Error,Count=%d\n", __func__, u32_count);
2446                 return QLA_FUNCTION_FAILED;
2447         } else {
2448                 data_ptr += u32_count;
2449                 *d_ptr = data_ptr;
2450                 return QLA_SUCCESS;
2451         }
2452 }
2453
2454 static void
2455 qla8044_mark_entry_skipped(struct scsi_qla_host *vha,
2456         struct qla8044_minidump_entry_hdr *entry_hdr, int index)
2457 {
2458         entry_hdr->d_ctrl.driver_flags |= QLA82XX_DBG_SKIPPED_FLAG;
2459
2460         ql_log(ql_log_info, vha, 0xb0f7,
2461             "scsi(%ld): Skipping entry[%d]: ETYPE[0x%x]-ELEVEL[0x%x]\n",
2462             vha->host_no, index, entry_hdr->entry_type,
2463             entry_hdr->d_ctrl.entry_capture_mask);
2464 }
2465
2466 static int
2467 qla8044_minidump_process_l2tag(struct scsi_qla_host *vha,
2468         struct qla8044_minidump_entry_hdr *entry_hdr,
2469                                  uint32_t **d_ptr)
2470 {
2471         uint32_t addr, r_addr, c_addr, t_r_addr;
2472         uint32_t i, k, loop_count, t_value, r_cnt, r_value;
2473         unsigned long p_wait, w_time, p_mask;
2474         uint32_t c_value_w, c_value_r;
2475         struct qla8044_minidump_entry_cache *cache_hdr;
2476         int rval = QLA_FUNCTION_FAILED;
2477         uint32_t *data_ptr = *d_ptr;
2478
2479         ql_dbg(ql_dbg_p3p, vha, 0xb0f8, "Entering fn: %s\n", __func__);
2480         cache_hdr = (struct qla8044_minidump_entry_cache *)entry_hdr;
2481
2482         loop_count = cache_hdr->op_count;
2483         r_addr = cache_hdr->read_addr;
2484         c_addr = cache_hdr->control_addr;
2485         c_value_w = cache_hdr->cache_ctrl.write_value;
2486
2487         t_r_addr = cache_hdr->tag_reg_addr;
2488         t_value = cache_hdr->addr_ctrl.init_tag_value;
2489         r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
2490         p_wait = cache_hdr->cache_ctrl.poll_wait;
2491         p_mask = cache_hdr->cache_ctrl.poll_mask;
2492
2493         for (i = 0; i < loop_count; i++) {
2494                 qla8044_wr_reg_indirect(vha, t_r_addr, t_value);
2495                 if (c_value_w)
2496                         qla8044_wr_reg_indirect(vha, c_addr, c_value_w);
2497
2498                 if (p_mask) {
2499                         w_time = jiffies + p_wait;
2500                         do {
2501                                 qla8044_rd_reg_indirect(vha, c_addr,
2502                                     &c_value_r);
2503                                 if ((c_value_r & p_mask) == 0) {
2504                                         break;
2505                                 } else if (time_after_eq(jiffies, w_time)) {
2506                                         /* capturing dump failed */
2507                                         return rval;
2508                                 }
2509                         } while (1);
2510                 }
2511
2512                 addr = r_addr;
2513                 for (k = 0; k < r_cnt; k++) {
2514                         qla8044_rd_reg_indirect(vha, addr, &r_value);
2515                         *data_ptr++ = r_value;
2516                         addr += cache_hdr->read_ctrl.read_addr_stride;
2517                 }
2518                 t_value += cache_hdr->addr_ctrl.tag_value_stride;
2519         }
2520         *d_ptr = data_ptr;
2521         return QLA_SUCCESS;
2522 }
2523
2524 static void
2525 qla8044_minidump_process_l1cache(struct scsi_qla_host *vha,
2526         struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
2527 {
2528         uint32_t addr, r_addr, c_addr, t_r_addr;
2529         uint32_t i, k, loop_count, t_value, r_cnt, r_value;
2530         uint32_t c_value_w;
2531         struct qla8044_minidump_entry_cache *cache_hdr;
2532         uint32_t *data_ptr = *d_ptr;
2533
2534         cache_hdr = (struct qla8044_minidump_entry_cache *)entry_hdr;
2535         loop_count = cache_hdr->op_count;
2536         r_addr = cache_hdr->read_addr;
2537         c_addr = cache_hdr->control_addr;
2538         c_value_w = cache_hdr->cache_ctrl.write_value;
2539
2540         t_r_addr = cache_hdr->tag_reg_addr;
2541         t_value = cache_hdr->addr_ctrl.init_tag_value;
2542         r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
2543
2544         for (i = 0; i < loop_count; i++) {
2545                 qla8044_wr_reg_indirect(vha, t_r_addr, t_value);
2546                 qla8044_wr_reg_indirect(vha, c_addr, c_value_w);
2547                 addr = r_addr;
2548                 for (k = 0; k < r_cnt; k++) {
2549                         qla8044_rd_reg_indirect(vha, addr, &r_value);
2550                         *data_ptr++ = r_value;
2551                         addr += cache_hdr->read_ctrl.read_addr_stride;
2552                 }
2553                 t_value += cache_hdr->addr_ctrl.tag_value_stride;
2554         }
2555         *d_ptr = data_ptr;
2556 }
2557
2558 static void
2559 qla8044_minidump_process_rdocm(struct scsi_qla_host *vha,
2560         struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
2561 {
2562         uint32_t r_addr, r_stride, loop_cnt, i, r_value;
2563         struct qla8044_minidump_entry_rdocm *ocm_hdr;
2564         uint32_t *data_ptr = *d_ptr;
2565         struct qla_hw_data *ha = vha->hw;
2566
2567         ql_dbg(ql_dbg_p3p, vha, 0xb0f9, "Entering fn: %s\n", __func__);
2568
2569         ocm_hdr = (struct qla8044_minidump_entry_rdocm *)entry_hdr;
2570         r_addr = ocm_hdr->read_addr;
2571         r_stride = ocm_hdr->read_addr_stride;
2572         loop_cnt = ocm_hdr->op_count;
2573
2574         ql_dbg(ql_dbg_p3p, vha, 0xb0fa,
2575             "[%s]: r_addr: 0x%x, r_stride: 0x%x, loop_cnt: 0x%x\n",
2576             __func__, r_addr, r_stride, loop_cnt);
2577
2578         for (i = 0; i < loop_cnt; i++) {
2579                 r_value = readl((void __iomem *)(r_addr + ha->nx_pcibase));
2580                 *data_ptr++ = r_value;
2581                 r_addr += r_stride;
2582         }
2583         ql_dbg(ql_dbg_p3p, vha, 0xb0fb, "Leaving fn: %s datacount: 0x%lx\n",
2584             __func__, (long unsigned int) (loop_cnt * sizeof(uint32_t)));
2585
2586         *d_ptr = data_ptr;
2587 }
2588
2589 static void
2590 qla8044_minidump_process_rdmux(struct scsi_qla_host *vha,
2591         struct qla8044_minidump_entry_hdr *entry_hdr,
2592         uint32_t **d_ptr)
2593 {
2594         uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value;
2595         struct qla8044_minidump_entry_mux *mux_hdr;
2596         uint32_t *data_ptr = *d_ptr;
2597
2598         ql_dbg(ql_dbg_p3p, vha, 0xb0fc, "Entering fn: %s\n", __func__);
2599
2600         mux_hdr = (struct qla8044_minidump_entry_mux *)entry_hdr;
2601         r_addr = mux_hdr->read_addr;
2602         s_addr = mux_hdr->select_addr;
2603         s_stride = mux_hdr->select_value_stride;
2604         s_value = mux_hdr->select_value;
2605         loop_cnt = mux_hdr->op_count;
2606
2607         for (i = 0; i < loop_cnt; i++) {
2608                 qla8044_wr_reg_indirect(vha, s_addr, s_value);
2609                 qla8044_rd_reg_indirect(vha, r_addr, &r_value);
2610                 *data_ptr++ = s_value;
2611                 *data_ptr++ = r_value;
2612                 s_value += s_stride;
2613         }
2614         *d_ptr = data_ptr;
2615 }
2616
2617 static void
2618 qla8044_minidump_process_queue(struct scsi_qla_host *vha,
2619         struct qla8044_minidump_entry_hdr *entry_hdr,
2620         uint32_t **d_ptr)
2621 {
2622         uint32_t s_addr, r_addr;
2623         uint32_t r_stride, r_value, r_cnt, qid = 0;
2624         uint32_t i, k, loop_cnt;
2625         struct qla8044_minidump_entry_queue *q_hdr;
2626         uint32_t *data_ptr = *d_ptr;
2627
2628         ql_dbg(ql_dbg_p3p, vha, 0xb0fd, "Entering fn: %s\n", __func__);
2629         q_hdr = (struct qla8044_minidump_entry_queue *)entry_hdr;
2630         s_addr = q_hdr->select_addr;
2631         r_cnt = q_hdr->rd_strd.read_addr_cnt;
2632         r_stride = q_hdr->rd_strd.read_addr_stride;
2633         loop_cnt = q_hdr->op_count;
2634
2635         for (i = 0; i < loop_cnt; i++) {
2636                 qla8044_wr_reg_indirect(vha, s_addr, qid);
2637                 r_addr = q_hdr->read_addr;
2638                 for (k = 0; k < r_cnt; k++) {
2639                         qla8044_rd_reg_indirect(vha, r_addr, &r_value);
2640                         *data_ptr++ = r_value;
2641                         r_addr += r_stride;
2642                 }
2643                 qid += q_hdr->q_strd.queue_id_stride;
2644         }
2645         *d_ptr = data_ptr;
2646 }
2647
2648 /* ISP83xx functions to process new minidump entries... */
2649 static uint32_t
2650 qla8044_minidump_process_pollrd(struct scsi_qla_host *vha,
2651         struct qla8044_minidump_entry_hdr *entry_hdr,
2652         uint32_t **d_ptr)
2653 {
2654         uint32_t r_addr, s_addr, s_value, r_value, poll_wait, poll_mask;
2655         uint16_t s_stride, i;
2656         struct qla8044_minidump_entry_pollrd *pollrd_hdr;
2657         uint32_t *data_ptr = *d_ptr;
2658
2659         pollrd_hdr = (struct qla8044_minidump_entry_pollrd *) entry_hdr;
2660         s_addr = pollrd_hdr->select_addr;
2661         r_addr = pollrd_hdr->read_addr;
2662         s_value = pollrd_hdr->select_value;
2663         s_stride = pollrd_hdr->select_value_stride;
2664
2665         poll_wait = pollrd_hdr->poll_wait;
2666         poll_mask = pollrd_hdr->poll_mask;
2667
2668         for (i = 0; i < pollrd_hdr->op_count; i++) {
2669                 qla8044_wr_reg_indirect(vha, s_addr, s_value);
2670                 poll_wait = pollrd_hdr->poll_wait;
2671                 while (1) {
2672                         qla8044_rd_reg_indirect(vha, s_addr, &r_value);
2673                         if ((r_value & poll_mask) != 0) {
2674                                 break;
2675                         } else {
2676                                 usleep_range(1000, 1100);
2677                                 if (--poll_wait == 0) {
2678                                         ql_log(ql_log_fatal, vha, 0xb0fe,
2679                                             "%s: TIMEOUT\n", __func__);
2680                                         goto error;
2681                                 }
2682                         }
2683                 }
2684                 qla8044_rd_reg_indirect(vha, r_addr, &r_value);
2685                 *data_ptr++ = s_value;
2686                 *data_ptr++ = r_value;
2687
2688                 s_value += s_stride;
2689         }
2690         *d_ptr = data_ptr;
2691         return QLA_SUCCESS;
2692
2693 error:
2694         return QLA_FUNCTION_FAILED;
2695 }
2696
2697 static void
2698 qla8044_minidump_process_rdmux2(struct scsi_qla_host *vha,
2699         struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
2700 {
2701         uint32_t sel_val1, sel_val2, t_sel_val, data, i;
2702         uint32_t sel_addr1, sel_addr2, sel_val_mask, read_addr;
2703         struct qla8044_minidump_entry_rdmux2 *rdmux2_hdr;
2704         uint32_t *data_ptr = *d_ptr;
2705
2706         rdmux2_hdr = (struct qla8044_minidump_entry_rdmux2 *) entry_hdr;
2707         sel_val1 = rdmux2_hdr->select_value_1;
2708         sel_val2 = rdmux2_hdr->select_value_2;
2709         sel_addr1 = rdmux2_hdr->select_addr_1;
2710         sel_addr2 = rdmux2_hdr->select_addr_2;
2711         sel_val_mask = rdmux2_hdr->select_value_mask;
2712         read_addr = rdmux2_hdr->read_addr;
2713
2714         for (i = 0; i < rdmux2_hdr->op_count; i++) {
2715                 qla8044_wr_reg_indirect(vha, sel_addr1, sel_val1);
2716                 t_sel_val = sel_val1 & sel_val_mask;
2717                 *data_ptr++ = t_sel_val;
2718
2719                 qla8044_wr_reg_indirect(vha, sel_addr2, t_sel_val);
2720                 qla8044_rd_reg_indirect(vha, read_addr, &data);
2721
2722                 *data_ptr++ = data;
2723
2724                 qla8044_wr_reg_indirect(vha, sel_addr1, sel_val2);
2725                 t_sel_val = sel_val2 & sel_val_mask;
2726                 *data_ptr++ = t_sel_val;
2727
2728                 qla8044_wr_reg_indirect(vha, sel_addr2, t_sel_val);
2729                 qla8044_rd_reg_indirect(vha, read_addr, &data);
2730
2731                 *data_ptr++ = data;
2732
2733                 sel_val1 += rdmux2_hdr->select_value_stride;
2734                 sel_val2 += rdmux2_hdr->select_value_stride;
2735         }
2736
2737         *d_ptr = data_ptr;
2738 }
2739
2740 static uint32_t
2741 qla8044_minidump_process_pollrdmwr(struct scsi_qla_host *vha,
2742         struct qla8044_minidump_entry_hdr *entry_hdr,
2743         uint32_t **d_ptr)
2744 {
2745         uint32_t poll_wait, poll_mask, r_value, data;
2746         uint32_t addr_1, addr_2, value_1, value_2;
2747         struct qla8044_minidump_entry_pollrdmwr *poll_hdr;
2748         uint32_t *data_ptr = *d_ptr;
2749
2750         poll_hdr = (struct qla8044_minidump_entry_pollrdmwr *) entry_hdr;
2751         addr_1 = poll_hdr->addr_1;
2752         addr_2 = poll_hdr->addr_2;
2753         value_1 = poll_hdr->value_1;
2754         value_2 = poll_hdr->value_2;
2755         poll_mask = poll_hdr->poll_mask;
2756
2757         qla8044_wr_reg_indirect(vha, addr_1, value_1);
2758
2759         poll_wait = poll_hdr->poll_wait;
2760         while (1) {
2761                 qla8044_rd_reg_indirect(vha, addr_1, &r_value);
2762
2763                 if ((r_value & poll_mask) != 0) {
2764                         break;
2765                 } else {
2766                         usleep_range(1000, 1100);
2767                         if (--poll_wait == 0) {
2768                                 ql_log(ql_log_fatal, vha, 0xb0ff,
2769                                     "%s: TIMEOUT\n", __func__);
2770                                 goto error;
2771                         }
2772                 }
2773         }
2774
2775         qla8044_rd_reg_indirect(vha, addr_2, &data);
2776         data &= poll_hdr->modify_mask;
2777         qla8044_wr_reg_indirect(vha, addr_2, data);
2778         qla8044_wr_reg_indirect(vha, addr_1, value_2);
2779
2780         poll_wait = poll_hdr->poll_wait;
2781         while (1) {
2782                 qla8044_rd_reg_indirect(vha, addr_1, &r_value);
2783
2784                 if ((r_value & poll_mask) != 0) {
2785                         break;
2786                 } else {
2787                         usleep_range(1000, 1100);
2788                         if (--poll_wait == 0) {
2789                                 ql_log(ql_log_fatal, vha, 0xb100,
2790                                     "%s: TIMEOUT2\n", __func__);
2791                                 goto error;
2792                         }
2793                 }
2794         }
2795
2796         *data_ptr++ = addr_2;
2797         *data_ptr++ = data;
2798
2799         *d_ptr = data_ptr;
2800
2801         return QLA_SUCCESS;
2802
2803 error:
2804         return QLA_FUNCTION_FAILED;
2805 }
2806
2807 #define ISP8044_PEX_DMA_ENGINE_INDEX            8
2808 #define ISP8044_PEX_DMA_BASE_ADDRESS            0x77320000
2809 #define ISP8044_PEX_DMA_NUM_OFFSET              0x10000
2810 #define ISP8044_PEX_DMA_CMD_ADDR_LOW            0x0
2811 #define ISP8044_PEX_DMA_CMD_ADDR_HIGH           0x04
2812 #define ISP8044_PEX_DMA_CMD_STS_AND_CNTRL       0x08
2813
2814 #define ISP8044_PEX_DMA_READ_SIZE       (16 * 1024)
2815 #define ISP8044_PEX_DMA_MAX_WAIT        (100 * 100) /* Max wait of 100 msecs */
2816
2817 static int
2818 qla8044_check_dma_engine_state(struct scsi_qla_host *vha)
2819 {
2820         struct qla_hw_data *ha = vha->hw;
2821         int rval = QLA_SUCCESS;
2822         uint32_t dma_eng_num = 0, cmd_sts_and_cntrl = 0;
2823         uint64_t dma_base_addr = 0;
2824         struct qla8044_minidump_template_hdr *tmplt_hdr = NULL;
2825
2826         tmplt_hdr = ha->md_tmplt_hdr;
2827         dma_eng_num =
2828             tmplt_hdr->saved_state_array[ISP8044_PEX_DMA_ENGINE_INDEX];
2829         dma_base_addr = ISP8044_PEX_DMA_BASE_ADDRESS +
2830                 (dma_eng_num * ISP8044_PEX_DMA_NUM_OFFSET);
2831
2832         /* Read the pex-dma's command-status-and-control register. */
2833         rval = qla8044_rd_reg_indirect(vha,
2834             (dma_base_addr + ISP8044_PEX_DMA_CMD_STS_AND_CNTRL),
2835             &cmd_sts_and_cntrl);
2836         if (rval)
2837                 return QLA_FUNCTION_FAILED;
2838
2839         /* Check if requested pex-dma engine is available. */
2840         if (cmd_sts_and_cntrl & BIT_31)
2841                 return QLA_SUCCESS;
2842
2843         return QLA_FUNCTION_FAILED;
2844 }
2845
2846 static int
2847 qla8044_start_pex_dma(struct scsi_qla_host *vha,
2848         struct qla8044_minidump_entry_rdmem_pex_dma *m_hdr)
2849 {
2850         struct qla_hw_data *ha = vha->hw;
2851         int rval = QLA_SUCCESS, wait = 0;
2852         uint32_t dma_eng_num = 0, cmd_sts_and_cntrl = 0;
2853         uint64_t dma_base_addr = 0;
2854         struct qla8044_minidump_template_hdr *tmplt_hdr = NULL;
2855
2856         tmplt_hdr = ha->md_tmplt_hdr;
2857         dma_eng_num =
2858             tmplt_hdr->saved_state_array[ISP8044_PEX_DMA_ENGINE_INDEX];
2859         dma_base_addr = ISP8044_PEX_DMA_BASE_ADDRESS +
2860                 (dma_eng_num * ISP8044_PEX_DMA_NUM_OFFSET);
2861
2862         rval = qla8044_wr_reg_indirect(vha,
2863             dma_base_addr + ISP8044_PEX_DMA_CMD_ADDR_LOW,
2864             m_hdr->desc_card_addr);
2865         if (rval)
2866                 goto error_exit;
2867
2868         rval = qla8044_wr_reg_indirect(vha,
2869             dma_base_addr + ISP8044_PEX_DMA_CMD_ADDR_HIGH, 0);
2870         if (rval)
2871                 goto error_exit;
2872
2873         rval = qla8044_wr_reg_indirect(vha,
2874             dma_base_addr + ISP8044_PEX_DMA_CMD_STS_AND_CNTRL,
2875             m_hdr->start_dma_cmd);
2876         if (rval)
2877                 goto error_exit;
2878
2879         /* Wait for dma operation to complete. */
2880         for (wait = 0; wait < ISP8044_PEX_DMA_MAX_WAIT; wait++) {
2881                 rval = qla8044_rd_reg_indirect(vha,
2882                     (dma_base_addr + ISP8044_PEX_DMA_CMD_STS_AND_CNTRL),
2883                     &cmd_sts_and_cntrl);
2884                 if (rval)
2885                         goto error_exit;
2886
2887                 if ((cmd_sts_and_cntrl & BIT_1) == 0)
2888                         break;
2889
2890                 udelay(10);
2891         }
2892
2893         /* Wait a max of 100 ms, otherwise fallback to rdmem entry read */
2894         if (wait >= ISP8044_PEX_DMA_MAX_WAIT) {
2895                 rval = QLA_FUNCTION_FAILED;
2896                 goto error_exit;
2897         }
2898
2899 error_exit:
2900         return rval;
2901 }
2902
2903 static int
2904 qla8044_minidump_pex_dma_read(struct scsi_qla_host *vha,
2905         struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
2906 {
2907         struct qla_hw_data *ha = vha->hw;
2908         int rval = QLA_SUCCESS;
2909         struct qla8044_minidump_entry_rdmem_pex_dma *m_hdr = NULL;
2910         uint32_t chunk_size, read_size;
2911         uint8_t *data_ptr = (uint8_t *)*d_ptr;
2912         void *rdmem_buffer = NULL;
2913         dma_addr_t rdmem_dma;
2914         struct qla8044_pex_dma_descriptor dma_desc;
2915
2916         rval = qla8044_check_dma_engine_state(vha);
2917         if (rval != QLA_SUCCESS) {
2918                 ql_dbg(ql_dbg_p3p, vha, 0xb147,
2919                     "DMA engine not available. Fallback to rdmem-read.\n");
2920                 return QLA_FUNCTION_FAILED;
2921         }
2922
2923         m_hdr = (void *)entry_hdr;
2924
2925         rdmem_buffer = dma_alloc_coherent(&ha->pdev->dev,
2926             ISP8044_PEX_DMA_READ_SIZE, &rdmem_dma, GFP_KERNEL);
2927         if (!rdmem_buffer) {
2928                 ql_dbg(ql_dbg_p3p, vha, 0xb148,
2929                     "Unable to allocate rdmem dma buffer\n");
2930                 return QLA_FUNCTION_FAILED;
2931         }
2932
2933         /* Prepare pex-dma descriptor to be written to MS memory. */
2934         /* dma-desc-cmd layout:
2935          *              0-3: dma-desc-cmd 0-3
2936          *              4-7: pcid function number
2937          *              8-15: dma-desc-cmd 8-15
2938          * dma_bus_addr: dma buffer address
2939          * cmd.read_data_size: amount of data-chunk to be read.
2940          */
2941         dma_desc.cmd.dma_desc_cmd = (m_hdr->dma_desc_cmd & 0xff0f);
2942         dma_desc.cmd.dma_desc_cmd |=
2943             ((PCI_FUNC(ha->pdev->devfn) & 0xf) << 0x4);
2944
2945         dma_desc.dma_bus_addr = rdmem_dma;
2946         dma_desc.cmd.read_data_size = chunk_size = ISP8044_PEX_DMA_READ_SIZE;
2947         read_size = 0;
2948
2949         /*
2950          * Perform rdmem operation using pex-dma.
2951          * Prepare dma in chunks of ISP8044_PEX_DMA_READ_SIZE.
2952          */
2953         while (read_size < m_hdr->read_data_size) {
2954                 if (m_hdr->read_data_size - read_size <
2955                     ISP8044_PEX_DMA_READ_SIZE) {
2956                         chunk_size = (m_hdr->read_data_size - read_size);
2957                         dma_desc.cmd.read_data_size = chunk_size;
2958                 }
2959
2960                 dma_desc.src_addr = m_hdr->read_addr + read_size;
2961
2962                 /* Prepare: Write pex-dma descriptor to MS memory. */
2963                 rval = qla8044_ms_mem_write_128b(vha,
2964                     m_hdr->desc_card_addr, (void *)&dma_desc,
2965                     (sizeof(struct qla8044_pex_dma_descriptor)/16));
2966                 if (rval) {
2967                         ql_log(ql_log_warn, vha, 0xb14a,
2968                             "%s: Error writing rdmem-dma-init to MS !!!\n",
2969                             __func__);
2970                         goto error_exit;
2971                 }
2972                 ql_dbg(ql_dbg_p3p, vha, 0xb14b,
2973                     "%s: Dma-descriptor: Instruct for rdmem dma "
2974                     "(chunk_size 0x%x).\n", __func__, chunk_size);
2975
2976                 /* Execute: Start pex-dma operation. */
2977                 rval = qla8044_start_pex_dma(vha, m_hdr);
2978                 if (rval)
2979                         goto error_exit;
2980
2981                 memcpy(data_ptr, rdmem_buffer, chunk_size);
2982                 data_ptr += chunk_size;
2983                 read_size += chunk_size;
2984         }
2985
2986         *d_ptr = (void *)data_ptr;
2987
2988 error_exit:
2989         if (rdmem_buffer)
2990                 dma_free_coherent(&ha->pdev->dev, ISP8044_PEX_DMA_READ_SIZE,
2991                     rdmem_buffer, rdmem_dma);
2992
2993         return rval;
2994 }
2995
2996 static uint32_t
2997 qla8044_minidump_process_rddfe(struct scsi_qla_host *vha,
2998         struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
2999 {
3000         int loop_cnt;
3001         uint32_t addr1, addr2, value, data, temp, wrVal;
3002         uint8_t stride, stride2;
3003         uint16_t count;
3004         uint32_t poll, mask, data_size, modify_mask;
3005         uint32_t wait_count = 0;
3006
3007         uint32_t *data_ptr = *d_ptr;
3008
3009         struct qla8044_minidump_entry_rddfe *rddfe;
3010         rddfe = (struct qla8044_minidump_entry_rddfe *) entry_hdr;
3011
3012         addr1 = rddfe->addr_1;
3013         value = rddfe->value;
3014         stride = rddfe->stride;
3015         stride2 = rddfe->stride2;
3016         count = rddfe->count;
3017
3018         poll = rddfe->poll;
3019         mask = rddfe->mask;
3020         modify_mask = rddfe->modify_mask;
3021         data_size = rddfe->data_size;
3022
3023         addr2 = addr1 + stride;
3024
3025         for (loop_cnt = 0x0; loop_cnt < count; loop_cnt++) {
3026                 qla8044_wr_reg_indirect(vha, addr1, (0x40000000 | value));
3027
3028                 wait_count = 0;
3029                 while (wait_count < poll) {
3030                         qla8044_rd_reg_indirect(vha, addr1, &temp);
3031                         if ((temp & mask) != 0)
3032                                 break;
3033                         wait_count++;
3034                 }
3035
3036                 if (wait_count == poll) {
3037                         ql_log(ql_log_warn, vha, 0xb153,
3038                             "%s: TIMEOUT\n", __func__);
3039                         goto error;
3040                 } else {
3041                         qla8044_rd_reg_indirect(vha, addr2, &temp);
3042                         temp = temp & modify_mask;
3043                         temp = (temp | ((loop_cnt << 16) | loop_cnt));
3044                         wrVal = ((temp << 16) | temp);
3045
3046                         qla8044_wr_reg_indirect(vha, addr2, wrVal);
3047                         qla8044_wr_reg_indirect(vha, addr1, value);
3048
3049                         wait_count = 0;
3050                         while (wait_count < poll) {
3051                                 qla8044_rd_reg_indirect(vha, addr1, &temp);
3052                                 if ((temp & mask) != 0)
3053                                         break;
3054                                 wait_count++;
3055                         }
3056                         if (wait_count == poll) {
3057                                 ql_log(ql_log_warn, vha, 0xb154,
3058                                     "%s: TIMEOUT\n", __func__);
3059                                 goto error;
3060                         }
3061
3062                         qla8044_wr_reg_indirect(vha, addr1,
3063                             ((0x40000000 | value) + stride2));
3064                         wait_count = 0;
3065                         while (wait_count < poll) {
3066                                 qla8044_rd_reg_indirect(vha, addr1, &temp);
3067                                 if ((temp & mask) != 0)
3068                                         break;
3069                                 wait_count++;
3070                         }
3071
3072                         if (wait_count == poll) {
3073                                 ql_log(ql_log_warn, vha, 0xb155,
3074                                     "%s: TIMEOUT\n", __func__);
3075                                 goto error;
3076                         }
3077
3078                         qla8044_rd_reg_indirect(vha, addr2, &data);
3079
3080                         *data_ptr++ = wrVal;
3081                         *data_ptr++ = data;
3082                 }
3083
3084         }
3085
3086         *d_ptr = data_ptr;
3087         return QLA_SUCCESS;
3088
3089 error:
3090         return -1;
3091
3092 }
3093
3094 static uint32_t
3095 qla8044_minidump_process_rdmdio(struct scsi_qla_host *vha,
3096         struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
3097 {
3098         int ret = 0;
3099         uint32_t addr1, addr2, value1, value2, data, selVal;
3100         uint8_t stride1, stride2;
3101         uint32_t addr3, addr4, addr5, addr6, addr7;
3102         uint16_t count, loop_cnt;
3103         uint32_t poll, mask;
3104         uint32_t *data_ptr = *d_ptr;
3105
3106         struct qla8044_minidump_entry_rdmdio *rdmdio;
3107
3108         rdmdio = (struct qla8044_minidump_entry_rdmdio *) entry_hdr;
3109
3110         addr1 = rdmdio->addr_1;
3111         addr2 = rdmdio->addr_2;
3112         value1 = rdmdio->value_1;
3113         stride1 = rdmdio->stride_1;
3114         stride2 = rdmdio->stride_2;
3115         count = rdmdio->count;
3116
3117         poll = rdmdio->poll;
3118         mask = rdmdio->mask;
3119         value2 = rdmdio->value_2;
3120
3121         addr3 = addr1 + stride1;
3122
3123         for (loop_cnt = 0; loop_cnt < count; loop_cnt++) {
3124                 ret = qla8044_poll_wait_ipmdio_bus_idle(vha, addr1, addr2,
3125                     addr3, mask);
3126                 if (ret == -1)
3127                         goto error;
3128
3129                 addr4 = addr2 - stride1;
3130                 ret = qla8044_ipmdio_wr_reg(vha, addr1, addr3, mask, addr4,
3131                     value2);
3132                 if (ret == -1)
3133                         goto error;
3134
3135                 addr5 = addr2 - (2 * stride1);
3136                 ret = qla8044_ipmdio_wr_reg(vha, addr1, addr3, mask, addr5,
3137                     value1);
3138                 if (ret == -1)
3139                         goto error;
3140
3141                 addr6 = addr2 - (3 * stride1);
3142                 ret = qla8044_ipmdio_wr_reg(vha, addr1, addr3, mask,
3143                     addr6, 0x2);
3144                 if (ret == -1)
3145                         goto error;
3146
3147                 ret = qla8044_poll_wait_ipmdio_bus_idle(vha, addr1, addr2,
3148                     addr3, mask);
3149                 if (ret == -1)
3150                         goto error;
3151
3152                 addr7 = addr2 - (4 * stride1);
3153                         data = qla8044_ipmdio_rd_reg(vha, addr1, addr3,
3154                             mask, addr7);
3155                 if (data == -1)
3156                         goto error;
3157
3158                 selVal = (value2 << 18) | (value1 << 2) | 2;
3159
3160                 stride2 = rdmdio->stride_2;
3161                 *data_ptr++ = selVal;
3162                 *data_ptr++ = data;
3163
3164                 value1 = value1 + stride2;
3165                 *d_ptr = data_ptr;
3166         }
3167
3168         return 0;
3169
3170 error:
3171         return -1;
3172 }
3173
3174 static uint32_t qla8044_minidump_process_pollwr(struct scsi_qla_host *vha,
3175                 struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
3176 {
3177         uint32_t addr1, addr2, value1, value2, poll, mask, r_value;
3178         uint32_t wait_count = 0;
3179         struct qla8044_minidump_entry_pollwr *pollwr_hdr;
3180
3181         pollwr_hdr = (struct qla8044_minidump_entry_pollwr *)entry_hdr;
3182         addr1 = pollwr_hdr->addr_1;
3183         addr2 = pollwr_hdr->addr_2;
3184         value1 = pollwr_hdr->value_1;
3185         value2 = pollwr_hdr->value_2;
3186
3187         poll = pollwr_hdr->poll;
3188         mask = pollwr_hdr->mask;
3189
3190         while (wait_count < poll) {
3191                 qla8044_rd_reg_indirect(vha, addr1, &r_value);
3192
3193                 if ((r_value & poll) != 0)
3194                         break;
3195                 wait_count++;
3196         }
3197
3198         if (wait_count == poll) {
3199                 ql_log(ql_log_warn, vha, 0xb156, "%s: TIMEOUT\n", __func__);
3200                 goto error;
3201         }
3202
3203         qla8044_wr_reg_indirect(vha, addr2, value2);
3204         qla8044_wr_reg_indirect(vha, addr1, value1);
3205
3206         wait_count = 0;
3207         while (wait_count < poll) {
3208                 qla8044_rd_reg_indirect(vha, addr1, &r_value);
3209
3210                 if ((r_value & poll) != 0)
3211                         break;
3212                 wait_count++;
3213         }
3214
3215         return QLA_SUCCESS;
3216
3217 error:
3218         return -1;
3219 }
3220
3221 /*
3222  *
3223  * qla8044_collect_md_data - Retrieve firmware minidump data.
3224  * @ha: pointer to adapter structure
3225  **/
3226 int
3227 qla8044_collect_md_data(struct scsi_qla_host *vha)
3228 {
3229         int num_entry_hdr = 0;
3230         struct qla8044_minidump_entry_hdr *entry_hdr;
3231         struct qla8044_minidump_template_hdr *tmplt_hdr;
3232         uint32_t *data_ptr;
3233         uint32_t data_collected = 0, f_capture_mask;
3234         int i, rval = QLA_FUNCTION_FAILED;
3235         uint64_t now;
3236         uint32_t timestamp, idc_control;
3237         struct qla_hw_data *ha = vha->hw;
3238
3239         if (!ha->md_dump) {
3240                 ql_log(ql_log_info, vha, 0xb101,
3241                     "%s(%ld) No buffer to dump\n",
3242                     __func__, vha->host_no);
3243                 return rval;
3244         }
3245
3246         if (ha->fw_dumped) {
3247                 ql_log(ql_log_warn, vha, 0xb10d,
3248                     "Firmware has been previously dumped (%p) "
3249                     "-- ignoring request.\n", ha->fw_dump);
3250                 goto md_failed;
3251         }
3252
3253         ha->fw_dumped = 0;
3254
3255         if (!ha->md_tmplt_hdr || !ha->md_dump) {
3256                 ql_log(ql_log_warn, vha, 0xb10e,
3257                     "Memory not allocated for minidump capture\n");
3258                 goto md_failed;
3259         }
3260
3261         qla8044_idc_lock(ha);
3262         idc_control = qla8044_rd_reg(ha, QLA8044_IDC_DRV_CTRL);
3263         if (idc_control & GRACEFUL_RESET_BIT1) {
3264                 ql_log(ql_log_warn, vha, 0xb112,
3265                     "Forced reset from application, "
3266                     "ignore minidump capture\n");
3267                 qla8044_wr_reg(ha, QLA8044_IDC_DRV_CTRL,
3268                     (idc_control & ~GRACEFUL_RESET_BIT1));
3269                 qla8044_idc_unlock(ha);
3270
3271                 goto md_failed;
3272         }
3273         qla8044_idc_unlock(ha);
3274
3275         if (qla82xx_validate_template_chksum(vha)) {
3276                 ql_log(ql_log_info, vha, 0xb109,
3277                     "Template checksum validation error\n");
3278                 goto md_failed;
3279         }
3280
3281         tmplt_hdr = (struct qla8044_minidump_template_hdr *)
3282                 ha->md_tmplt_hdr;
3283         data_ptr = (uint32_t *)((uint8_t *)ha->md_dump);
3284         num_entry_hdr = tmplt_hdr->num_of_entries;
3285
3286         ql_dbg(ql_dbg_p3p, vha, 0xb11a,
3287             "Capture Mask obtained: 0x%x\n", tmplt_hdr->capture_debug_level);
3288
3289         f_capture_mask = tmplt_hdr->capture_debug_level & 0xFF;
3290
3291         /* Validate whether required debug level is set */
3292         if ((f_capture_mask & 0x3) != 0x3) {
3293                 ql_log(ql_log_warn, vha, 0xb10f,
3294                     "Minimum required capture mask[0x%x] level not set\n",
3295                     f_capture_mask);
3296
3297         }
3298         tmplt_hdr->driver_capture_mask = ql2xmdcapmask;
3299         ql_log(ql_log_info, vha, 0xb102,
3300             "[%s]: starting data ptr: %p\n",
3301            __func__, data_ptr);
3302         ql_log(ql_log_info, vha, 0xb10b,
3303            "[%s]: no of entry headers in Template: 0x%x\n",
3304            __func__, num_entry_hdr);
3305         ql_log(ql_log_info, vha, 0xb10c,
3306             "[%s]: Total_data_size 0x%x, %d obtained\n",
3307            __func__, ha->md_dump_size, ha->md_dump_size);
3308
3309         /* Update current timestamp before taking dump */
3310         now = get_jiffies_64();
3311         timestamp = (u32)(jiffies_to_msecs(now) / 1000);
3312         tmplt_hdr->driver_timestamp = timestamp;
3313
3314         entry_hdr = (struct qla8044_minidump_entry_hdr *)
3315                 (((uint8_t *)ha->md_tmplt_hdr) + tmplt_hdr->first_entry_offset);
3316         tmplt_hdr->saved_state_array[QLA8044_SS_OCM_WNDREG_INDEX] =
3317             tmplt_hdr->ocm_window_reg[ha->portnum];
3318
3319         /* Walk through the entry headers - validate/perform required action */
3320         for (i = 0; i < num_entry_hdr; i++) {
3321                 if (data_collected > ha->md_dump_size) {
3322                         ql_log(ql_log_info, vha, 0xb103,
3323                             "Data collected: [0x%x], "
3324                             "Total Dump size: [0x%x]\n",
3325                             data_collected, ha->md_dump_size);
3326                         return rval;
3327                 }
3328
3329                 if (!(entry_hdr->d_ctrl.entry_capture_mask &
3330                       ql2xmdcapmask)) {
3331                         entry_hdr->d_ctrl.driver_flags |=
3332                             QLA82XX_DBG_SKIPPED_FLAG;
3333                         goto skip_nxt_entry;
3334                 }
3335
3336                 ql_dbg(ql_dbg_p3p, vha, 0xb104,
3337                     "Data collected: [0x%x], Dump size left:[0x%x]\n",
3338                     data_collected,
3339                     (ha->md_dump_size - data_collected));
3340
3341                 /* Decode the entry type and take required action to capture
3342                  * debug data
3343                  */
3344                 switch (entry_hdr->entry_type) {
3345                 case QLA82XX_RDEND:
3346                         qla8044_mark_entry_skipped(vha, entry_hdr, i);
3347                         break;
3348                 case QLA82XX_CNTRL:
3349                         rval = qla8044_minidump_process_control(vha,
3350                             entry_hdr);
3351                         if (rval != QLA_SUCCESS) {
3352                                 qla8044_mark_entry_skipped(vha, entry_hdr, i);
3353                                 goto md_failed;
3354                         }
3355                         break;
3356                 case QLA82XX_RDCRB:
3357                         qla8044_minidump_process_rdcrb(vha,
3358                             entry_hdr, &data_ptr);
3359                         break;
3360                 case QLA82XX_RDMEM:
3361                         rval = qla8044_minidump_pex_dma_read(vha,
3362                             entry_hdr, &data_ptr);
3363                         if (rval != QLA_SUCCESS) {
3364                                 rval = qla8044_minidump_process_rdmem(vha,
3365                                     entry_hdr, &data_ptr);
3366                                 if (rval != QLA_SUCCESS) {
3367                                         qla8044_mark_entry_skipped(vha,
3368                                             entry_hdr, i);
3369                                         goto md_failed;
3370                                 }
3371                         }
3372                         break;
3373                 case QLA82XX_BOARD:
3374                 case QLA82XX_RDROM:
3375                         rval = qla8044_minidump_process_rdrom(vha,
3376                             entry_hdr, &data_ptr);
3377                         if (rval != QLA_SUCCESS) {
3378                                 qla8044_mark_entry_skipped(vha,
3379                                     entry_hdr, i);
3380                         }
3381                         break;
3382                 case QLA82XX_L2DTG:
3383                 case QLA82XX_L2ITG:
3384                 case QLA82XX_L2DAT:
3385                 case QLA82XX_L2INS:
3386                         rval = qla8044_minidump_process_l2tag(vha,
3387                             entry_hdr, &data_ptr);
3388                         if (rval != QLA_SUCCESS) {
3389                                 qla8044_mark_entry_skipped(vha, entry_hdr, i);
3390                                 goto md_failed;
3391                         }
3392                         break;
3393                 case QLA8044_L1DTG:
3394                 case QLA8044_L1ITG:
3395                 case QLA82XX_L1DAT:
3396                 case QLA82XX_L1INS:
3397                         qla8044_minidump_process_l1cache(vha,
3398                             entry_hdr, &data_ptr);
3399                         break;
3400                 case QLA82XX_RDOCM:
3401                         qla8044_minidump_process_rdocm(vha,
3402                             entry_hdr, &data_ptr);
3403                         break;
3404                 case QLA82XX_RDMUX:
3405                         qla8044_minidump_process_rdmux(vha,
3406                             entry_hdr, &data_ptr);
3407                         break;
3408                 case QLA82XX_QUEUE:
3409                         qla8044_minidump_process_queue(vha,
3410                             entry_hdr, &data_ptr);
3411                         break;
3412                 case QLA8044_POLLRD:
3413                         rval = qla8044_minidump_process_pollrd(vha,
3414                             entry_hdr, &data_ptr);
3415                         if (rval != QLA_SUCCESS)
3416                                 qla8044_mark_entry_skipped(vha, entry_hdr, i);
3417                         break;
3418                 case QLA8044_RDMUX2:
3419                         qla8044_minidump_process_rdmux2(vha,
3420                             entry_hdr, &data_ptr);
3421                         break;
3422                 case QLA8044_POLLRDMWR:
3423                         rval = qla8044_minidump_process_pollrdmwr(vha,
3424                             entry_hdr, &data_ptr);
3425                         if (rval != QLA_SUCCESS)
3426                                 qla8044_mark_entry_skipped(vha, entry_hdr, i);
3427                         break;
3428                 case QLA8044_RDDFE:
3429                         rval = qla8044_minidump_process_rddfe(vha, entry_hdr,
3430                             &data_ptr);
3431                         if (rval != QLA_SUCCESS)
3432                                 qla8044_mark_entry_skipped(vha, entry_hdr, i);
3433                         break;
3434                 case QLA8044_RDMDIO:
3435                         rval = qla8044_minidump_process_rdmdio(vha, entry_hdr,
3436                             &data_ptr);
3437                         if (rval != QLA_SUCCESS)
3438                                 qla8044_mark_entry_skipped(vha, entry_hdr, i);
3439                         break;
3440                 case QLA8044_POLLWR:
3441                         rval = qla8044_minidump_process_pollwr(vha, entry_hdr,
3442                             &data_ptr);
3443                         if (rval != QLA_SUCCESS)
3444                                 qla8044_mark_entry_skipped(vha, entry_hdr, i);
3445                         break;
3446                 case QLA82XX_RDNOP:
3447                 default:
3448                         qla8044_mark_entry_skipped(vha, entry_hdr, i);
3449                         break;
3450                 }
3451
3452                 data_collected = (uint8_t *)data_ptr -
3453                     (uint8_t *)((uint8_t *)ha->md_dump);
3454 skip_nxt_entry:
3455                 /*
3456                  * next entry in the template
3457                  */
3458                 entry_hdr = (struct qla8044_minidump_entry_hdr *)
3459                     (((uint8_t *)entry_hdr) + entry_hdr->entry_size);
3460         }
3461
3462         if (data_collected != ha->md_dump_size) {
3463                 ql_log(ql_log_info, vha, 0xb105,
3464                     "Dump data mismatch: Data collected: "
3465                     "[0x%x], total_data_size:[0x%x]\n",
3466                     data_collected, ha->md_dump_size);
3467                 rval = QLA_FUNCTION_FAILED;
3468                 goto md_failed;
3469         }
3470
3471         ql_log(ql_log_info, vha, 0xb110,
3472             "Firmware dump saved to temp buffer (%ld/%p %ld/%p).\n",
3473             vha->host_no, ha->md_tmplt_hdr, vha->host_no, ha->md_dump);
3474         ha->fw_dumped = 1;
3475         qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP);
3476
3477
3478         ql_log(ql_log_info, vha, 0xb106,
3479             "Leaving fn: %s Last entry: 0x%x\n",
3480             __func__, i);
3481 md_failed:
3482         return rval;
3483 }
3484
3485 void
3486 qla8044_get_minidump(struct scsi_qla_host *vha)
3487 {
3488         struct qla_hw_data *ha = vha->hw;
3489
3490         if (!qla8044_collect_md_data(vha)) {
3491                 ha->fw_dumped = 1;
3492                 ha->prev_minidump_failed = 0;
3493         } else {
3494                 ql_log(ql_log_fatal, vha, 0xb0db,
3495                     "%s: Unable to collect minidump\n",
3496                     __func__);
3497                 ha->prev_minidump_failed = 1;
3498         }
3499 }
3500
3501 static int
3502 qla8044_poll_flash_status_reg(struct scsi_qla_host *vha)
3503 {
3504         uint32_t flash_status;
3505         int retries = QLA8044_FLASH_READ_RETRY_COUNT;
3506         int ret_val = QLA_SUCCESS;
3507
3508         while (retries--) {
3509                 ret_val = qla8044_rd_reg_indirect(vha, QLA8044_FLASH_STATUS,
3510                     &flash_status);
3511                 if (ret_val) {
3512                         ql_log(ql_log_warn, vha, 0xb13c,
3513                             "%s: Failed to read FLASH_STATUS reg.\n",
3514                             __func__);
3515                         break;
3516                 }
3517                 if ((flash_status & QLA8044_FLASH_STATUS_READY) ==
3518                     QLA8044_FLASH_STATUS_READY)
3519                         break;
3520                 msleep(QLA8044_FLASH_STATUS_REG_POLL_DELAY);
3521         }
3522
3523         if (!retries)
3524                 ret_val = QLA_FUNCTION_FAILED;
3525
3526         return ret_val;
3527 }
3528
3529 static int
3530 qla8044_write_flash_status_reg(struct scsi_qla_host *vha,
3531                                uint32_t data)
3532 {
3533         int ret_val = QLA_SUCCESS;
3534         uint32_t cmd;
3535
3536         cmd = vha->hw->fdt_wrt_sts_reg_cmd;
3537
3538         ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR,
3539             QLA8044_FLASH_STATUS_WRITE_DEF_SIG | cmd);
3540         if (ret_val) {
3541                 ql_log(ql_log_warn, vha, 0xb125,
3542                     "%s: Failed to write to FLASH_ADDR.\n", __func__);
3543                 goto exit_func;
3544         }
3545
3546         ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_WRDATA, data);
3547         if (ret_val) {
3548                 ql_log(ql_log_warn, vha, 0xb126,
3549                     "%s: Failed to write to FLASH_WRDATA.\n", __func__);
3550                 goto exit_func;
3551         }
3552
3553         ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL,
3554             QLA8044_FLASH_SECOND_ERASE_MS_VAL);
3555         if (ret_val) {
3556                 ql_log(ql_log_warn, vha, 0xb127,
3557                     "%s: Failed to write to FLASH_CONTROL.\n", __func__);
3558                 goto exit_func;
3559         }
3560
3561         ret_val = qla8044_poll_flash_status_reg(vha);
3562         if (ret_val)
3563                 ql_log(ql_log_warn, vha, 0xb128,
3564                     "%s: Error polling flash status reg.\n", __func__);
3565
3566 exit_func:
3567         return ret_val;
3568 }
3569
3570 /*
3571  * This function assumes that the flash lock is held.
3572  */
3573 static int
3574 qla8044_unprotect_flash(scsi_qla_host_t *vha)
3575 {
3576         int ret_val;
3577         struct qla_hw_data *ha = vha->hw;
3578
3579         ret_val = qla8044_write_flash_status_reg(vha, ha->fdt_wrt_enable);
3580         if (ret_val)
3581                 ql_log(ql_log_warn, vha, 0xb139,
3582                     "%s: Write flash status failed.\n", __func__);
3583
3584         return ret_val;
3585 }
3586
3587 /*
3588  * This function assumes that the flash lock is held.
3589  */
3590 static int
3591 qla8044_protect_flash(scsi_qla_host_t *vha)
3592 {
3593         int ret_val;
3594         struct qla_hw_data *ha = vha->hw;
3595
3596         ret_val = qla8044_write_flash_status_reg(vha, ha->fdt_wrt_disable);
3597         if (ret_val)
3598                 ql_log(ql_log_warn, vha, 0xb13b,
3599                     "%s: Write flash status failed.\n", __func__);
3600
3601         return ret_val;
3602 }
3603
3604
3605 static int
3606 qla8044_erase_flash_sector(struct scsi_qla_host *vha,
3607                            uint32_t sector_start_addr)
3608 {
3609         uint32_t reversed_addr;
3610         int ret_val = QLA_SUCCESS;
3611
3612         ret_val = qla8044_poll_flash_status_reg(vha);
3613         if (ret_val) {
3614                 ql_log(ql_log_warn, vha, 0xb12e,
3615                     "%s: Poll flash status after erase failed..\n", __func__);
3616         }
3617
3618         reversed_addr = (((sector_start_addr & 0xFF) << 16) |
3619             (sector_start_addr & 0xFF00) |
3620             ((sector_start_addr & 0xFF0000) >> 16));
3621
3622         ret_val = qla8044_wr_reg_indirect(vha,
3623             QLA8044_FLASH_WRDATA, reversed_addr);
3624         if (ret_val) {
3625                 ql_log(ql_log_warn, vha, 0xb12f,
3626                     "%s: Failed to write to FLASH_WRDATA.\n", __func__);
3627         }
3628         ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR,
3629            QLA8044_FLASH_ERASE_SIG | vha->hw->fdt_erase_cmd);
3630         if (ret_val) {
3631                 ql_log(ql_log_warn, vha, 0xb130,
3632                     "%s: Failed to write to FLASH_ADDR.\n", __func__);
3633         }
3634         ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL,
3635             QLA8044_FLASH_LAST_ERASE_MS_VAL);
3636         if (ret_val) {
3637                 ql_log(ql_log_warn, vha, 0xb131,
3638                     "%s: Failed write to FLASH_CONTROL.\n", __func__);
3639         }
3640         ret_val = qla8044_poll_flash_status_reg(vha);
3641         if (ret_val) {
3642                 ql_log(ql_log_warn, vha, 0xb132,
3643                     "%s: Poll flash status failed.\n", __func__);
3644         }
3645
3646
3647         return ret_val;
3648 }
3649
3650 /*
3651  * qla8044_flash_write_u32 - Write data to flash
3652  *
3653  * @ha : Pointer to adapter structure
3654  * addr : Flash address to write to
3655  * p_data : Data to be written
3656  *
3657  * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED
3658  *
3659  * NOTE: Lock should be held on entry
3660  */
3661 static int
3662 qla8044_flash_write_u32(struct scsi_qla_host *vha, uint32_t addr,
3663                         uint32_t *p_data)
3664 {
3665         int ret_val = QLA_SUCCESS;
3666
3667         ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR,
3668             0x00800000 | (addr >> 2));
3669         if (ret_val) {
3670                 ql_log(ql_log_warn, vha, 0xb134,
3671                     "%s: Failed write to FLASH_ADDR.\n", __func__);
3672                 goto exit_func;
3673         }
3674         ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_WRDATA, *p_data);
3675         if (ret_val) {
3676                 ql_log(ql_log_warn, vha, 0xb135,
3677                     "%s: Failed write to FLASH_WRDATA.\n", __func__);
3678                 goto exit_func;
3679         }
3680         ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL, 0x3D);
3681         if (ret_val) {
3682                 ql_log(ql_log_warn, vha, 0xb136,
3683                     "%s: Failed write to FLASH_CONTROL.\n", __func__);
3684                 goto exit_func;
3685         }
3686         ret_val = qla8044_poll_flash_status_reg(vha);
3687         if (ret_val) {
3688                 ql_log(ql_log_warn, vha, 0xb137,
3689                     "%s: Poll flash status failed.\n", __func__);
3690         }
3691
3692 exit_func:
3693         return ret_val;
3694 }
3695
3696 static int
3697 qla8044_write_flash_buffer_mode(scsi_qla_host_t *vha, uint32_t *dwptr,
3698                                 uint32_t faddr, uint32_t dwords)
3699 {
3700         int ret = QLA_FUNCTION_FAILED;
3701         uint32_t spi_val;
3702
3703         if (dwords < QLA8044_MIN_OPTROM_BURST_DWORDS ||
3704             dwords > QLA8044_MAX_OPTROM_BURST_DWORDS) {
3705                 ql_dbg(ql_dbg_user, vha, 0xb123,
3706                     "Got unsupported dwords = 0x%x.\n",
3707                     dwords);
3708                 return QLA_FUNCTION_FAILED;
3709         }
3710
3711         qla8044_rd_reg_indirect(vha, QLA8044_FLASH_SPI_CONTROL, &spi_val);
3712         qla8044_wr_reg_indirect(vha, QLA8044_FLASH_SPI_CONTROL,
3713             spi_val | QLA8044_FLASH_SPI_CTL);
3714         qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR,
3715             QLA8044_FLASH_FIRST_TEMP_VAL);
3716
3717         /* First DWORD write to FLASH_WRDATA */
3718         ret = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_WRDATA,
3719             *dwptr++);
3720         qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL,
3721             QLA8044_FLASH_FIRST_MS_PATTERN);
3722
3723         ret = qla8044_poll_flash_status_reg(vha);
3724         if (ret) {
3725                 ql_log(ql_log_warn, vha, 0xb124,
3726                     "%s: Failed.\n", __func__);
3727                 goto exit_func;
3728         }
3729
3730         dwords--;
3731
3732         qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR,
3733             QLA8044_FLASH_SECOND_TEMP_VAL);
3734
3735
3736         /* Second to N-1 DWORDS writes */
3737         while (dwords != 1) {
3738                 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_WRDATA, *dwptr++);
3739                 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL,
3740                     QLA8044_FLASH_SECOND_MS_PATTERN);
3741                 ret = qla8044_poll_flash_status_reg(vha);
3742                 if (ret) {
3743                         ql_log(ql_log_warn, vha, 0xb129,
3744                             "%s: Failed.\n", __func__);
3745                         goto exit_func;
3746                 }
3747                 dwords--;
3748         }
3749
3750         qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR,
3751             QLA8044_FLASH_FIRST_TEMP_VAL | (faddr >> 2));
3752
3753         /* Last DWORD write */
3754         qla8044_wr_reg_indirect(vha, QLA8044_FLASH_WRDATA, *dwptr++);
3755         qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL,
3756             QLA8044_FLASH_LAST_MS_PATTERN);
3757         ret = qla8044_poll_flash_status_reg(vha);
3758         if (ret) {
3759                 ql_log(ql_log_warn, vha, 0xb12a,
3760                     "%s: Failed.\n", __func__);
3761                 goto exit_func;
3762         }
3763         qla8044_rd_reg_indirect(vha, QLA8044_FLASH_SPI_STATUS, &spi_val);
3764
3765         if ((spi_val & QLA8044_FLASH_SPI_CTL) == QLA8044_FLASH_SPI_CTL) {
3766                 ql_log(ql_log_warn, vha, 0xb12b,
3767                     "%s: Failed.\n", __func__);
3768                 spi_val = 0;
3769                 /* Operation failed, clear error bit. */
3770                 qla8044_rd_reg_indirect(vha, QLA8044_FLASH_SPI_CONTROL,
3771                     &spi_val);
3772                 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_SPI_CONTROL,
3773                     spi_val | QLA8044_FLASH_SPI_CTL);
3774         }
3775 exit_func:
3776         return ret;
3777 }
3778
3779 static int
3780 qla8044_write_flash_dword_mode(scsi_qla_host_t *vha, uint32_t *dwptr,
3781                                uint32_t faddr, uint32_t dwords)
3782 {
3783         int ret = QLA_FUNCTION_FAILED;
3784         uint32_t liter;
3785
3786         for (liter = 0; liter < dwords; liter++, faddr += 4, dwptr++) {
3787                 ret = qla8044_flash_write_u32(vha, faddr, dwptr);
3788                 if (ret) {
3789                         ql_dbg(ql_dbg_p3p, vha, 0xb141,
3790                             "%s: flash address=%x data=%x.\n", __func__,
3791                              faddr, *dwptr);
3792                         break;
3793                 }
3794         }
3795
3796         return ret;
3797 }
3798
3799 int
3800 qla8044_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
3801                           uint32_t offset, uint32_t length)
3802 {
3803         int rval = QLA_FUNCTION_FAILED, i, burst_iter_count;
3804         int dword_count, erase_sec_count;
3805         uint32_t erase_offset;
3806         uint8_t *p_cache, *p_src;
3807
3808         erase_offset = offset;
3809
3810         p_cache = kcalloc(length, sizeof(uint8_t), GFP_KERNEL);
3811         if (!p_cache)
3812                 return QLA_FUNCTION_FAILED;
3813
3814         memcpy(p_cache, buf, length);
3815         p_src = p_cache;
3816         dword_count = length / sizeof(uint32_t);
3817         /* Since the offset and legth are sector aligned, it will be always
3818          * multiple of burst_iter_count (64)
3819          */
3820         burst_iter_count = dword_count / QLA8044_MAX_OPTROM_BURST_DWORDS;
3821         erase_sec_count = length / QLA8044_SECTOR_SIZE;
3822
3823         /* Suspend HBA. */
3824         scsi_block_requests(vha->host);
3825         /* Lock and enable write for whole operation. */
3826         qla8044_flash_lock(vha);
3827         qla8044_unprotect_flash(vha);
3828
3829         /* Erasing the sectors */
3830         for (i = 0; i < erase_sec_count; i++) {
3831                 rval = qla8044_erase_flash_sector(vha, erase_offset);
3832                 ql_dbg(ql_dbg_user, vha, 0xb138,
3833                     "Done erase of sector=0x%x.\n",
3834                     erase_offset);
3835                 if (rval) {
3836                         ql_log(ql_log_warn, vha, 0xb121,
3837                             "Failed to erase the sector having address: "
3838                             "0x%x.\n", erase_offset);
3839                         goto out;
3840                 }
3841                 erase_offset += QLA8044_SECTOR_SIZE;
3842         }
3843         ql_dbg(ql_dbg_user, vha, 0xb13f,
3844             "Got write for addr = 0x%x length=0x%x.\n",
3845             offset, length);
3846
3847         for (i = 0; i < burst_iter_count; i++) {
3848
3849                 /* Go with write. */
3850                 rval = qla8044_write_flash_buffer_mode(vha, (uint32_t *)p_src,
3851                     offset, QLA8044_MAX_OPTROM_BURST_DWORDS);
3852                 if (rval) {
3853                         /* Buffer Mode failed skip to dword mode */
3854                         ql_log(ql_log_warn, vha, 0xb122,
3855                             "Failed to write flash in buffer mode, "
3856                             "Reverting to slow-write.\n");
3857                         rval = qla8044_write_flash_dword_mode(vha,
3858                             (uint32_t *)p_src, offset,
3859                             QLA8044_MAX_OPTROM_BURST_DWORDS);
3860                 }
3861                 p_src +=  sizeof(uint32_t) * QLA8044_MAX_OPTROM_BURST_DWORDS;
3862                 offset += sizeof(uint32_t) * QLA8044_MAX_OPTROM_BURST_DWORDS;
3863         }
3864         ql_dbg(ql_dbg_user, vha, 0xb133,
3865             "Done writing.\n");
3866
3867 out:
3868         qla8044_protect_flash(vha);
3869         qla8044_flash_unlock(vha);
3870         scsi_unblock_requests(vha->host);
3871         kfree(p_cache);
3872
3873         return rval;
3874 }
3875
3876 #define LEG_INT_PTR_B31         (1 << 31)
3877 #define LEG_INT_PTR_B30         (1 << 30)
3878 #define PF_BITS_MASK            (0xF << 16)
3879 /**
3880  * qla8044_intr_handler() - Process interrupts for the ISP8044
3881  * @irq:
3882  * @dev_id: SCSI driver HA context
3883  *
3884  * Called by system whenever the host adapter generates an interrupt.
3885  *
3886  * Returns handled flag.
3887  */
3888 irqreturn_t
3889 qla8044_intr_handler(int irq, void *dev_id)
3890 {
3891         scsi_qla_host_t *vha;
3892         struct qla_hw_data *ha;
3893         struct rsp_que *rsp;
3894         struct device_reg_82xx __iomem *reg;
3895         int             status = 0;
3896         unsigned long   flags;
3897         unsigned long   iter;
3898         uint32_t        stat;
3899         uint16_t        mb[4];
3900         uint32_t leg_int_ptr = 0, pf_bit;
3901
3902         rsp = (struct rsp_que *) dev_id;
3903         if (!rsp) {
3904                 ql_log(ql_log_info, NULL, 0xb143,
3905                     "%s(): NULL response queue pointer\n", __func__);
3906                 return IRQ_NONE;
3907         }
3908         ha = rsp->hw;
3909         vha = pci_get_drvdata(ha->pdev);
3910
3911         if (unlikely(pci_channel_offline(ha->pdev)))
3912                 return IRQ_HANDLED;
3913
3914         leg_int_ptr = qla8044_rd_reg(ha, LEG_INTR_PTR_OFFSET);
3915
3916         /* Legacy interrupt is valid if bit31 of leg_int_ptr is set */
3917         if (!(leg_int_ptr & (LEG_INT_PTR_B31))) {
3918                 ql_dbg(ql_dbg_p3p, vha, 0xb144,
3919                     "%s: Legacy Interrupt Bit 31 not set, "
3920                     "spurious interrupt!\n", __func__);
3921                 return IRQ_NONE;
3922         }
3923
3924         pf_bit = ha->portnum << 16;
3925         /* Validate the PCIE function ID set in leg_int_ptr bits [19..16] */
3926         if ((leg_int_ptr & (PF_BITS_MASK)) != pf_bit) {
3927                 ql_dbg(ql_dbg_p3p, vha, 0xb145,
3928                     "%s: Incorrect function ID 0x%x in "
3929                     "legacy interrupt register, "
3930                     "ha->pf_bit = 0x%x\n", __func__,
3931                     (leg_int_ptr & (PF_BITS_MASK)), pf_bit);
3932                 return IRQ_NONE;
3933         }
3934
3935         /* To de-assert legacy interrupt, write 0 to Legacy Interrupt Trigger
3936          * Control register and poll till Legacy Interrupt Pointer register
3937          * bit32 is 0.
3938          */
3939         qla8044_wr_reg(ha, LEG_INTR_TRIG_OFFSET, 0);
3940         do {
3941                 leg_int_ptr = qla8044_rd_reg(ha, LEG_INTR_PTR_OFFSET);
3942                 if ((leg_int_ptr & (PF_BITS_MASK)) != pf_bit)
3943                         break;
3944         } while (leg_int_ptr & (LEG_INT_PTR_B30));
3945
3946         reg = &ha->iobase->isp82;
3947         spin_lock_irqsave(&ha->hardware_lock, flags);
3948         for (iter = 1; iter--; ) {
3949
3950                 if (RD_REG_DWORD(&reg->host_int)) {
3951                         stat = RD_REG_DWORD(&reg->host_status);
3952                         if ((stat & HSRX_RISC_INT) == 0)
3953                                 break;
3954
3955                         switch (stat & 0xff) {
3956                         case 0x1:
3957                         case 0x2:
3958                         case 0x10:
3959                         case 0x11:
3960                                 qla82xx_mbx_completion(vha, MSW(stat));
3961                                 status |= MBX_INTERRUPT;
3962                                 break;
3963                         case 0x12:
3964                                 mb[0] = MSW(stat);
3965                                 mb[1] = RD_REG_WORD(&reg->mailbox_out[1]);
3966                                 mb[2] = RD_REG_WORD(&reg->mailbox_out[2]);
3967                                 mb[3] = RD_REG_WORD(&reg->mailbox_out[3]);
3968                                 qla2x00_async_event(vha, rsp, mb);
3969                                 break;
3970                         case 0x13:
3971                                 qla24xx_process_response_queue(vha, rsp);
3972                                 break;
3973                         default:
3974                                 ql_dbg(ql_dbg_p3p, vha, 0xb146,
3975                                     "Unrecognized interrupt type "
3976                                     "(%d).\n", stat & 0xff);
3977                                 break;
3978                         }
3979                 }
3980                 WRT_REG_DWORD(&reg->host_int, 0);
3981         }
3982
3983         qla2x00_handle_mbx_completion(ha, status);
3984         spin_unlock_irqrestore(&ha->hardware_lock, flags);
3985
3986         return IRQ_HANDLED;
3987 }
3988
3989 static int
3990 qla8044_idc_dontreset(struct qla_hw_data *ha)
3991 {
3992         uint32_t idc_ctrl;
3993
3994         idc_ctrl = qla8044_rd_reg(ha, QLA8044_IDC_DRV_CTRL);
3995         return idc_ctrl & DONTRESET_BIT0;
3996 }
3997
3998 static void
3999 qla8044_clear_rst_ready(scsi_qla_host_t *vha)
4000 {
4001         uint32_t drv_state;
4002
4003         drv_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX);
4004
4005         /*
4006          * For ISP8044, drv_active register has 1 bit per function,
4007          * shift 1 by func_num to set a bit for the function.
4008          * For ISP82xx, drv_active has 4 bits per function
4009          */
4010         drv_state &= ~(1 << vha->hw->portnum);
4011
4012         ql_dbg(ql_dbg_p3p, vha, 0xb13d,
4013             "drv_state: 0x%08x\n", drv_state);
4014         qla8044_wr_direct(vha, QLA8044_CRB_DRV_STATE_INDEX, drv_state);
4015 }
4016
4017 int
4018 qla8044_abort_isp(scsi_qla_host_t *vha)
4019 {
4020         int rval;
4021         uint32_t dev_state;
4022         struct qla_hw_data *ha = vha->hw;
4023
4024         qla8044_idc_lock(ha);
4025         dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX);
4026
4027         if (ql2xdontresethba)
4028                 qla8044_set_idc_dontreset(vha);
4029
4030         /* If device_state is NEED_RESET, go ahead with
4031          * Reset,irrespective of ql2xdontresethba. This is to allow a
4032          * non-reset-owner to force a reset. Non-reset-owner sets
4033          * the IDC_CTRL BIT0 to prevent Reset-owner from doing a Reset
4034          * and then forces a Reset by setting device_state to
4035          * NEED_RESET. */
4036         if (dev_state == QLA8XXX_DEV_READY) {
4037                 /* If IDC_CTRL DONTRESETHBA_BIT0 is set don't do reset
4038                  * recovery */
4039                 if (qla8044_idc_dontreset(ha) == DONTRESET_BIT0) {
4040                         ql_dbg(ql_dbg_p3p, vha, 0xb13e,
4041                             "Reset recovery disabled\n");
4042                         rval = QLA_FUNCTION_FAILED;
4043                         goto exit_isp_reset;
4044                 }
4045
4046                 ql_dbg(ql_dbg_p3p, vha, 0xb140,
4047                     "HW State: NEED RESET\n");
4048                 qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX,
4049                     QLA8XXX_DEV_NEED_RESET);
4050         }
4051
4052         /* For ISP8044, Reset owner is NIC, iSCSI or FCOE based on priority
4053          * and which drivers are present. Unlike ISP82XX, the function setting
4054          * NEED_RESET, may not be the Reset owner. */
4055         qla83xx_reset_ownership(vha);
4056
4057         qla8044_idc_unlock(ha);
4058         rval = qla8044_device_state_handler(vha);
4059         qla8044_idc_lock(ha);
4060         qla8044_clear_rst_ready(vha);
4061
4062 exit_isp_reset:
4063         qla8044_idc_unlock(ha);
4064         if (rval == QLA_SUCCESS) {
4065                 ha->flags.isp82xx_fw_hung = 0;
4066                 ha->flags.nic_core_reset_hdlr_active = 0;
4067                 rval = qla82xx_restart_isp(vha);
4068         }
4069
4070         return rval;
4071 }
4072
4073 void
4074 qla8044_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
4075 {
4076         struct qla_hw_data *ha = vha->hw;
4077
4078         if (!ha->allow_cna_fw_dump)
4079                 return;
4080
4081         scsi_block_requests(vha->host);
4082         ha->flags.isp82xx_no_md_cap = 1;
4083         qla8044_idc_lock(ha);
4084         qla82xx_set_reset_owner(vha);
4085         qla8044_idc_unlock(ha);
4086         qla2x00_wait_for_chip_reset(vha);
4087         scsi_unblock_requests(vha->host);
4088 }