drivers/scsi/qla2xxx/qla_nx2.c

   1 /*
   2  * QLogic Fibre Channel HBA Driver
   3  * Copyright (c)  2003-2014 QLogic Corporation
   4  *
   5  * See LICENSE.qla2xxx for copyright and licensing details.
   6  */
   7
   8 #include <linux/vmalloc.h>
   9 #include <linux/delay.h>
  10
  11 #include "qla_def.h"
  12 #include "qla_gbl.h"
  13
  14 #include <linux/delay.h>
  15
  16 #define TIMEOUT_100_MS 100
  17
  18 /* 8044 Flash Read/Write functions */
  19 uint32_t
  20 qla8044_rd_reg(struct qla_hw_data *ha, ulong addr)
  21 {
  22         return readl((void __iomem *) (ha->nx_pcibase + addr));
  23 }
  24
  25 void
  26 qla8044_wr_reg(struct qla_hw_data *ha, ulong addr, uint32_t val)
  27 {
  28         writel(val, (void __iomem *)((ha)->nx_pcibase + addr));
  29 }
  30
  31 int
  32 qla8044_rd_direct(struct scsi_qla_host *vha,
  33         const uint32_t crb_reg)
  34 {
  35         struct qla_hw_data *ha = vha->hw;
  36
  37         if (crb_reg < CRB_REG_INDEX_MAX)
  38                 return qla8044_rd_reg(ha, qla8044_reg_tbl[crb_reg]);
  39         else
  40                 return QLA_FUNCTION_FAILED;
  41 }
  42
  43 void
  44 qla8044_wr_direct(struct scsi_qla_host *vha,
  45         const uint32_t crb_reg,
  46         const uint32_t value)
  47 {
  48         struct qla_hw_data *ha = vha->hw;
  49
  50         if (crb_reg < CRB_REG_INDEX_MAX)
  51                 qla8044_wr_reg(ha, qla8044_reg_tbl[crb_reg], value);
  52 }
  53
  54 static int
  55 qla8044_set_win_base(scsi_qla_host_t *vha, uint32_t addr)
  56 {
  57         uint32_t val;
  58         int ret_val = QLA_SUCCESS;
  59         struct qla_hw_data *ha = vha->hw;
  60
  61         qla8044_wr_reg(ha, QLA8044_CRB_WIN_FUNC(ha->portnum), addr);
  62         val = qla8044_rd_reg(ha, QLA8044_CRB_WIN_FUNC(ha->portnum));
  63
  64         if (val != addr) {
  65                 ql_log(ql_log_warn, vha, 0xb087,
  66                     "%s: Failed to set register window : "
  67                     "addr written 0x%x, read 0x%x!\n",
  68                     __func__, addr, val);
  69                 ret_val = QLA_FUNCTION_FAILED;
  70         }
  71         return ret_val;
  72 }
  73
  74 static int
  75 qla8044_rd_reg_indirect(scsi_qla_host_t *vha, uint32_t addr, uint32_t *data)
  76 {
  77         int ret_val = QLA_SUCCESS;
  78         struct qla_hw_data *ha = vha->hw;
  79
  80         ret_val = qla8044_set_win_base(vha, addr);
  81         if (!ret_val)
  82                 *data = qla8044_rd_reg(ha, QLA8044_WILDCARD);
  83         else
  84                 ql_log(ql_log_warn, vha, 0xb088,
  85                     "%s: failed read of addr 0x%x!\n", __func__, addr);
  86         return ret_val;
  87 }
  88
  89 static int
  90 qla8044_wr_reg_indirect(scsi_qla_host_t *vha, uint32_t addr, uint32_t data)
  91 {
  92         int ret_val = QLA_SUCCESS;
  93         struct qla_hw_data *ha = vha->hw;
  94
  95         ret_val = qla8044_set_win_base(vha, addr);
  96         if (!ret_val)
  97                 qla8044_wr_reg(ha, QLA8044_WILDCARD, data);
  98         else
  99                 ql_log(ql_log_warn, vha, 0xb089,
 100                     "%s: failed wrt to addr 0x%x, data 0x%x\n",
 101                     __func__, addr, data);
 102         return ret_val;
 103 }
 104
 105 /*
 106  * qla8044_read_write_crb_reg - Read from raddr and write value to waddr.
 107  *
 108  * @ha : Pointer to adapter structure
 109  * @raddr : CRB address to read from
 110  * @waddr : CRB address to write to
 111  *
 112  */
 113 static void
 114 qla8044_read_write_crb_reg(struct scsi_qla_host *vha,
 115         uint32_t raddr, uint32_t waddr)
 116 {
 117         uint32_t value;
 118
 119         qla8044_rd_reg_indirect(vha, raddr, &value);
 120         qla8044_wr_reg_indirect(vha, waddr, value);
 121 }
 122
 123 static int
 124 qla8044_poll_wait_for_ready(struct scsi_qla_host *vha, uint32_t addr1,
 125         uint32_t mask)
 126 {
 127         unsigned long timeout;
 128         uint32_t temp;
 129
 130         /* jiffies after 100ms */
 131         timeout = jiffies + msecs_to_jiffies(TIMEOUT_100_MS);
 132         do {
 133                 qla8044_rd_reg_indirect(vha, addr1, &temp);
 134                 if ((temp & mask) != 0)
 135                         break;
 136                 if (time_after_eq(jiffies, timeout)) {
 137                         ql_log(ql_log_warn, vha, 0xb151,
 138                                 "Error in processing rdmdio entry\n");
 139                         return -1;
 140                 }
 141         } while (1);
 142
 143         return 0;
 144 }
 145
 146 static uint32_t
 147 qla8044_ipmdio_rd_reg(struct scsi_qla_host *vha,
 148         uint32_t addr1, uint32_t addr3, uint32_t mask, uint32_t addr)
 149 {
 150         uint32_t temp;
 151         int ret = 0;
 152
 153         ret = qla8044_poll_wait_for_ready(vha, addr1, mask);
 154         if (ret == -1)
 155                 return -1;
 156
 157         temp = (0x40000000 | addr);
 158         qla8044_wr_reg_indirect(vha, addr1, temp);
 159
 160         ret = qla8044_poll_wait_for_ready(vha, addr1, mask);
 161         if (ret == -1)
 162                 return 0;
 163
 164         qla8044_rd_reg_indirect(vha, addr3, &ret);
 165
 166         return ret;
 167 }
 168
 169
 170 static int
 171 qla8044_poll_wait_ipmdio_bus_idle(struct scsi_qla_host *vha,
 172         uint32_t addr1, uint32_t addr2, uint32_t addr3, uint32_t mask)
 173 {
 174         unsigned long timeout;
 175         uint32_t temp;
 176
 177         /* jiffies after 100 msecs */
 178         timeout = jiffies + msecs_to_jiffies(TIMEOUT_100_MS);
 179         do {
 180                 temp = qla8044_ipmdio_rd_reg(vha, addr1, addr3, mask, addr2);
 181                 if ((temp & 0x1) != 1)
 182                         break;
 183                 if (time_after_eq(jiffies, timeout)) {
 184                         ql_log(ql_log_warn, vha, 0xb152,
 185                             "Error in processing mdiobus idle\n");
 186                         return -1;
 187                 }
 188         } while (1);
 189
 190         return 0;
 191 }
 192
 193 static int
 194 qla8044_ipmdio_wr_reg(struct scsi_qla_host *vha, uint32_t addr1,
 195         uint32_t addr3, uint32_t mask, uint32_t addr, uint32_t value)
 196 {
 197         int ret = 0;
 198
 199         ret = qla8044_poll_wait_for_ready(vha, addr1, mask);
 200         if (ret == -1)
 201                 return -1;
 202
 203         qla8044_wr_reg_indirect(vha, addr3, value);
 204         qla8044_wr_reg_indirect(vha, addr1, addr);
 205
 206         ret = qla8044_poll_wait_for_ready(vha, addr1, mask);
 207         if (ret == -1)
 208                 return -1;
 209
 210         return 0;
 211 }
 212 /*
 213  * qla8044_rmw_crb_reg - Read value from raddr, AND with test_mask,
 214  * Shift Left,Right/OR/XOR with values RMW header and write value to waddr.
 215  *
 216  * @vha : Pointer to adapter structure
 217  * @raddr : CRB address to read from
 218  * @waddr : CRB address to write to
 219  * @p_rmw_hdr : header with shift/or/xor values.
 220  *
 221  */
 222 static void
 223 qla8044_rmw_crb_reg(struct scsi_qla_host *vha,
 224         uint32_t raddr, uint32_t waddr, struct qla8044_rmw *p_rmw_hdr)
 225 {
 226         uint32_t value;
 227
 228         if (p_rmw_hdr->index_a)
 229                 value = vha->reset_tmplt.array[p_rmw_hdr->index_a];
 230         else
 231                 qla8044_rd_reg_indirect(vha, raddr, &value);
 232         value &= p_rmw_hdr->test_mask;
 233         value <<= p_rmw_hdr->shl;
 234         value >>= p_rmw_hdr->shr;
 235         value |= p_rmw_hdr->or_value;
 236         value ^= p_rmw_hdr->xor_value;
 237         qla8044_wr_reg_indirect(vha, waddr, value);
 238         return;
 239 }
 240
 241 inline void
 242 qla8044_set_qsnt_ready(struct scsi_qla_host *vha)
 243 {
 244         uint32_t qsnt_state;
 245         struct qla_hw_data *ha = vha->hw;
 246
 247         qsnt_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX);
 248         qsnt_state |= (1 << ha->portnum);
 249         qla8044_wr_direct(vha, QLA8044_CRB_DRV_STATE_INDEX, qsnt_state);
 250         ql_log(ql_log_info, vha, 0xb08e, "%s(%ld): qsnt_state: 0x%08x\n",
 251              __func__, vha->host_no, qsnt_state);
 252 }
 253
 254 void
 255 qla8044_clear_qsnt_ready(struct scsi_qla_host *vha)
 256 {
 257         uint32_t qsnt_state;
 258         struct qla_hw_data *ha = vha->hw;
 259
 260         qsnt_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX);
 261         qsnt_state &= ~(1 << ha->portnum);
 262         qla8044_wr_direct(vha, QLA8044_CRB_DRV_STATE_INDEX, qsnt_state);
 263         ql_log(ql_log_info, vha, 0xb08f, "%s(%ld): qsnt_state: 0x%08x\n",
 264             __func__, vha->host_no, qsnt_state);
 265 }
 266
 267 /**
 268  *
 269  * qla8044_lock_recovery - Recovers the idc_lock.
 270  * @ha : Pointer to adapter structure
 271  *
 272  * Lock Recovery Register
 273  * 5-2  Lock recovery owner: Function ID of driver doing lock recovery,
 274  *      valid if bits 1..0 are set by driver doing lock recovery.
 275  * 1-0  1 - Driver intends to force unlock the IDC lock.
 276  *      2 - Driver is moving forward to unlock the IDC lock. Driver clears
 277  *          this field after force unlocking the IDC lock.
 278  *
 279  * Lock Recovery process
 280  * a. Read the IDC_LOCK_RECOVERY register. If the value in bits 1..0 is
 281  *    greater than 0, then wait for the other driver to unlock otherwise
 282  *    move to the next step.
 283  * b. Indicate intent to force-unlock by writing 1h to the IDC_LOCK_RECOVERY
 284  *    register bits 1..0 and also set the function# in bits 5..2.
 285  * c. Read the IDC_LOCK_RECOVERY register again after a delay of 200ms.
 286  *    Wait for the other driver to perform lock recovery if the function
 287  *    number in bits 5..2 has changed, otherwise move to the next step.
 288  * d. Write a value of 2h to the IDC_LOCK_RECOVERY register bits 1..0
 289  *    leaving your function# in bits 5..2.
 290  * e. Force unlock using the DRIVER_UNLOCK register and immediately clear
 291  *    the IDC_LOCK_RECOVERY bits 5..0 by writing 0.
 292  **/
 293 static int
 294 qla8044_lock_recovery(struct scsi_qla_host *vha)
 295 {
 296         uint32_t lock = 0, lockid;
 297         struct qla_hw_data *ha = vha->hw;
 298
 299         lockid = qla8044_rd_reg(ha, QLA8044_DRV_LOCKRECOVERY);
 300
 301         /* Check for other Recovery in progress, go wait */
 302         if ((lockid & IDC_LOCK_RECOVERY_STATE_MASK) != 0)
 303                 return QLA_FUNCTION_FAILED;
 304
 305         /* Intent to Recover */
 306         qla8044_wr_reg(ha, QLA8044_DRV_LOCKRECOVERY,
 307             (ha->portnum <<
 308              IDC_LOCK_RECOVERY_STATE_SHIFT_BITS) | INTENT_TO_RECOVER);
 309         msleep(200);
 310
 311         /* Check Intent to Recover is advertised */
 312         lockid = qla8044_rd_reg(ha, QLA8044_DRV_LOCKRECOVERY);
 313         if ((lockid & IDC_LOCK_RECOVERY_OWNER_MASK) != (ha->portnum <<
 314             IDC_LOCK_RECOVERY_STATE_SHIFT_BITS))
 315                 return QLA_FUNCTION_FAILED;
 316
 317         ql_dbg(ql_dbg_p3p, vha, 0xb08B, "%s:%d: IDC Lock recovery initiated\n"
 318             , __func__, ha->portnum);
 319
 320         /* Proceed to Recover */
 321         qla8044_wr_reg(ha, QLA8044_DRV_LOCKRECOVERY,
 322             (ha->portnum << IDC_LOCK_RECOVERY_STATE_SHIFT_BITS) |
 323             PROCEED_TO_RECOVER);
 324
 325         /* Force Unlock() */
 326         qla8044_wr_reg(ha, QLA8044_DRV_LOCK_ID, 0xFF);
 327         qla8044_rd_reg(ha, QLA8044_DRV_UNLOCK);
 328
 329         /* Clear bits 0-5 in IDC_RECOVERY register*/
 330         qla8044_wr_reg(ha, QLA8044_DRV_LOCKRECOVERY, 0);
 331
 332         /* Get lock() */
 333         lock = qla8044_rd_reg(ha, QLA8044_DRV_LOCK);
 334         if (lock) {
 335                 lockid = qla8044_rd_reg(ha, QLA8044_DRV_LOCK_ID);
 336                 lockid = ((lockid + (1 << 8)) & ~0xFF) | ha->portnum;
 337                 qla8044_wr_reg(ha, QLA8044_DRV_LOCK_ID, lockid);
 338                 return QLA_SUCCESS;
 339         } else
 340                 return QLA_FUNCTION_FAILED;
 341 }
 342
 343 int
 344 qla8044_idc_lock(struct qla_hw_data *ha)
 345 {
 346         uint32_t ret_val = QLA_SUCCESS, timeout = 0, status = 0;
 347         uint32_t lock_id, lock_cnt, func_num, tmo_owner = 0, first_owner = 0;
 348         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
 349
 350         while (status == 0) {
 351                 /* acquire semaphore5 from PCI HW block */
 352                 status = qla8044_rd_reg(ha, QLA8044_DRV_LOCK);
 353
 354                 if (status) {
 355                         /* Increment Counter (8-31) and update func_num (0-7) on
 356                          * getting a successful lock  */
 357                         lock_id = qla8044_rd_reg(ha, QLA8044_DRV_LOCK_ID);
 358                         lock_id = ((lock_id + (1 << 8)) & ~0xFF) | ha->portnum;
 359                         qla8044_wr_reg(ha, QLA8044_DRV_LOCK_ID, lock_id);
 360                         break;
 361                 }
 362
 363                 if (timeout == 0)
 364                         first_owner = qla8044_rd_reg(ha, QLA8044_DRV_LOCK_ID);
 365
 366                 if (++timeout >=
 367                     (QLA8044_DRV_LOCK_TIMEOUT / QLA8044_DRV_LOCK_MSLEEP)) {
 368                         tmo_owner = qla8044_rd_reg(ha, QLA8044_DRV_LOCK_ID);
 369                         func_num = tmo_owner & 0xFF;
 370                         lock_cnt = tmo_owner >> 8;
 371                         ql_log(ql_log_warn, vha, 0xb114,
 372                             "%s: Lock by func %d failed after 2s, lock held "
 373                             "by func %d, lock count %d, first_owner %d\n",
 374                             __func__, ha->portnum, func_num, lock_cnt,
 375                             (first_owner & 0xFF));
 376                         if (first_owner != tmo_owner) {
 377                                 /* Some other driver got lock,
 378                                  * OR same driver got lock again (counter
 379                                  * value changed), when we were waiting for
 380                                  * lock. Retry for another 2 sec */
 381                                 ql_dbg(ql_dbg_p3p, vha, 0xb115,
 382                                     "%s: %d: IDC lock failed\n",
 383                                     __func__, ha->portnum);
 384                                 timeout = 0;
 385                         } else {
 386                                 /* Same driver holding lock > 2sec.
 387                                  * Force Recovery */
 388                                 if (qla8044_lock_recovery(vha) == QLA_SUCCESS) {
 389                                         /* Recovered and got lock */
 390                                         ret_val = QLA_SUCCESS;
 391                                         ql_dbg(ql_dbg_p3p, vha, 0xb116,
 392                                             "%s:IDC lock Recovery by %d"
 393                                             "successful...\n", __func__,
 394                                              ha->portnum);
 395                                 }
 396                                 /* Recovery Failed, some other function
 397                                  * has the lock, wait for 2secs
 398                                  * and retry
 399                                  */
 400                                  ql_dbg(ql_dbg_p3p, vha, 0xb08a,
 401                                      "%s: IDC lock Recovery by %d "
 402                                      "failed, Retrying timout\n", __func__,
 403                                      ha->portnum);
 404                                  timeout = 0;
 405                         }
 406                 }
 407                 msleep(QLA8044_DRV_LOCK_MSLEEP);
 408         }
 409         return ret_val;
 410 }
 411
 412 void
 413 qla8044_idc_unlock(struct qla_hw_data *ha)
 414 {
 415         int id;
 416         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
 417
 418         id = qla8044_rd_reg(ha, QLA8044_DRV_LOCK_ID);
 419
 420         if ((id & 0xFF) != ha->portnum) {
 421                 ql_log(ql_log_warn, vha, 0xb118,
 422                     "%s: IDC Unlock by %d failed, lock owner is %d!\n",
 423                     __func__, ha->portnum, (id & 0xFF));
 424                 return;
 425         }
 426
 427         /* Keep lock counter value, update the ha->func_num to 0xFF */
 428         qla8044_wr_reg(ha, QLA8044_DRV_LOCK_ID, (id | 0xFF));
 429         qla8044_rd_reg(ha, QLA8044_DRV_UNLOCK);
 430 }
 431
 432 /* 8044 Flash Lock/Unlock functions */
 433 static int
 434 qla8044_flash_lock(scsi_qla_host_t *vha)
 435 {
 436         int lock_owner;
 437         int timeout = 0;
 438         uint32_t lock_status = 0;
 439         int ret_val = QLA_SUCCESS;
 440         struct qla_hw_data *ha = vha->hw;
 441
 442         while (lock_status == 0) {
 443                 lock_status = qla8044_rd_reg(ha, QLA8044_FLASH_LOCK);
 444                 if (lock_status)
 445                         break;
 446
 447                 if (++timeout >= QLA8044_FLASH_LOCK_TIMEOUT / 20) {
 448                         lock_owner = qla8044_rd_reg(ha,
 449                             QLA8044_FLASH_LOCK_ID);
 450                         ql_log(ql_log_warn, vha, 0xb113,
 451                             "%s: Simultaneous flash access by following ports, active port = %d: accessing port = %d",
 452                             __func__, ha->portnum, lock_owner);
 453                         ret_val = QLA_FUNCTION_FAILED;
 454                         break;
 455                 }
 456                 msleep(20);
 457         }
 458         qla8044_wr_reg(ha, QLA8044_FLASH_LOCK_ID, ha->portnum);
 459         return ret_val;
 460 }
 461
 462 static void
 463 qla8044_flash_unlock(scsi_qla_host_t *vha)
 464 {
 465         int ret_val;
 466         struct qla_hw_data *ha = vha->hw;
 467
 468         /* Reading FLASH_UNLOCK register unlocks the Flash */
 469         qla8044_wr_reg(ha, QLA8044_FLASH_LOCK_ID, 0xFF);
 470         ret_val = qla8044_rd_reg(ha, QLA8044_FLASH_UNLOCK);
 471 }
 472
 473
 474 static
 475 void qla8044_flash_lock_recovery(struct scsi_qla_host *vha)
 476 {
 477
 478         if (qla8044_flash_lock(vha)) {
 479                 /* Someone else is holding the lock. */
 480                 ql_log(ql_log_warn, vha, 0xb120, "Resetting flash_lock\n");
 481         }
 482
 483         /*
 484          * Either we got the lock, or someone
 485          * else died while holding it.
 486          * In either case, unlock.
 487          */
 488         qla8044_flash_unlock(vha);
 489 }
 490
 491 /*
 492  * Address and length are byte address
 493  */
 494 static int
 495 qla8044_read_flash_data(scsi_qla_host_t *vha,  uint8_t *p_data,
 496         uint32_t flash_addr, int u32_word_count)
 497 {
 498         int i, ret_val = QLA_SUCCESS;
 499         uint32_t u32_word;
 500
 501         if (qla8044_flash_lock(vha) != QLA_SUCCESS) {
 502                 ret_val = QLA_FUNCTION_FAILED;
 503                 goto exit_lock_error;
 504         }
 505
 506         if (flash_addr & 0x03) {
 507                 ql_log(ql_log_warn, vha, 0xb117,
 508                     "%s: Illegal addr = 0x%x\n", __func__, flash_addr);
 509                 ret_val = QLA_FUNCTION_FAILED;
 510                 goto exit_flash_read;
 511         }
 512
 513         for (i = 0; i < u32_word_count; i++) {
 514                 if (qla8044_wr_reg_indirect(vha, QLA8044_FLASH_DIRECT_WINDOW,
 515                     (flash_addr & 0xFFFF0000))) {
 516                         ql_log(ql_log_warn, vha, 0xb119,
 517                             "%s: failed to write addr 0x%x to "
 518                             "FLASH_DIRECT_WINDOW\n! ",
 519                             __func__, flash_addr);
 520                         ret_val = QLA_FUNCTION_FAILED;
 521                         goto exit_flash_read;
 522                 }
 523
 524                 ret_val = qla8044_rd_reg_indirect(vha,
 525                     QLA8044_FLASH_DIRECT_DATA(flash_addr),
 526                     &u32_word);
 527                 if (ret_val != QLA_SUCCESS) {
 528                         ql_log(ql_log_warn, vha, 0xb08c,
 529                             "%s: failed to read addr 0x%x!\n",
 530                             __func__, flash_addr);
 531                         goto exit_flash_read;
 532                 }
 533
 534                 *(uint32_t *)p_data = u32_word;
 535                 p_data = p_data + 4;
 536                 flash_addr = flash_addr + 4;
 537         }
 538
 539 exit_flash_read:
 540         qla8044_flash_unlock(vha);
 541
 542 exit_lock_error:
 543         return ret_val;
 544 }
 545
 546 /*
 547  * Address and length are byte address
 548  */
 549 uint8_t *
 550 qla8044_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
 551         uint32_t offset, uint32_t length)
 552 {
 553         scsi_block_requests(vha->host);
 554         if (qla8044_read_flash_data(vha, (uint8_t *)buf, offset, length / 4)
 555             != QLA_SUCCESS) {
 556                 ql_log(ql_log_warn, vha,  0xb08d,
 557                     "%s: Failed to read from flash\n",
 558                     __func__);
 559         }
 560         scsi_unblock_requests(vha->host);
 561         return buf;
 562 }
 563
 564 inline int
 565 qla8044_need_reset(struct scsi_qla_host *vha)
 566 {
 567         uint32_t drv_state, drv_active;
 568         int rval;
 569         struct qla_hw_data *ha = vha->hw;
 570
 571         drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX);
 572         drv_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX);
 573
 574         rval = drv_state & (1 << ha->portnum);
 575
 576         if (ha->flags.eeh_busy && drv_active)
 577                 rval = 1;
 578         return rval;
 579 }
 580
 581 /*
 582  * qla8044_write_list - Write the value (p_entry->arg2) to address specified
 583  * by p_entry->arg1 for all entries in header with delay of p_hdr->delay between
 584  * entries.
 585  *
 586  * @vha : Pointer to adapter structure
 587  * @p_hdr : reset_entry header for WRITE_LIST opcode.
 588  *
 589  */
 590 static void
 591 qla8044_write_list(struct scsi_qla_host *vha,
 592         struct qla8044_reset_entry_hdr *p_hdr)
 593 {
 594         struct qla8044_entry *p_entry;
 595         uint32_t i;
 596
 597         p_entry = (struct qla8044_entry *)((char *)p_hdr +
 598             sizeof(struct qla8044_reset_entry_hdr));
 599
 600         for (i = 0; i < p_hdr->count; i++, p_entry++) {
 601                 qla8044_wr_reg_indirect(vha, p_entry->arg1, p_entry->arg2);
 602                 if (p_hdr->delay)
 603                         udelay((uint32_t)(p_hdr->delay));
 604         }
 605 }
 606
 607 /*
 608  * qla8044_read_write_list - Read from address specified by p_entry->arg1,
 609  * write value read to address specified by p_entry->arg2, for all entries in
 610  * header with delay of p_hdr->delay between entries.
 611  *
 612  * @vha : Pointer to adapter structure
 613  * @p_hdr : reset_entry header for READ_WRITE_LIST opcode.
 614  *
 615  */
 616 static void
 617 qla8044_read_write_list(struct scsi_qla_host *vha,
 618         struct qla8044_reset_entry_hdr *p_hdr)
 619 {
 620         struct qla8044_entry *p_entry;
 621         uint32_t i;
 622
 623         p_entry = (struct qla8044_entry *)((char *)p_hdr +
 624             sizeof(struct qla8044_reset_entry_hdr));
 625
 626         for (i = 0; i < p_hdr->count; i++, p_entry++) {
 627                 qla8044_read_write_crb_reg(vha, p_entry->arg1,
 628                     p_entry->arg2);
 629                 if (p_hdr->delay)
 630                         udelay((uint32_t)(p_hdr->delay));
 631         }
 632 }
 633
 634 /*
 635  * qla8044_poll_reg - Poll the given CRB addr for duration msecs till
 636  * value read ANDed with test_mask is equal to test_result.
 637  *
 638  * @ha : Pointer to adapter structure
 639  * @addr : CRB register address
 640  * @duration : Poll for total of "duration" msecs
 641  * @test_mask : Mask value read with "test_mask"
 642  * @test_result : Compare (value&test_mask) with test_result.
 643  *
 644  * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED
 645  */
 646 static int
 647 qla8044_poll_reg(struct scsi_qla_host *vha, uint32_t addr,
 648         int duration, uint32_t test_mask, uint32_t test_result)
 649 {
 650         uint32_t value;
 651         int timeout_error;
 652         uint8_t retries;
 653         int ret_val = QLA_SUCCESS;
 654
 655         ret_val = qla8044_rd_reg_indirect(vha, addr, &value);
 656         if (ret_val == QLA_FUNCTION_FAILED) {
 657                 timeout_error = 1;
 658                 goto exit_poll_reg;
 659         }
 660
 661         /* poll every 1/10 of the total duration */
 662         retries = duration/10;
 663
 664         do {
 665                 if ((value & test_mask) != test_result) {
 666                         timeout_error = 1;
 667                         msleep(duration/10);
 668                         ret_val = qla8044_rd_reg_indirect(vha, addr, &value);
 669                         if (ret_val == QLA_FUNCTION_FAILED) {
 670                                 timeout_error = 1;
 671                                 goto exit_poll_reg;
 672                         }
 673                 } else {
 674                         timeout_error = 0;
 675                         break;
 676                 }
 677         } while (retries--);
 678
 679 exit_poll_reg:
 680         if (timeout_error) {
 681                 vha->reset_tmplt.seq_error++;
 682                 ql_log(ql_log_fatal, vha, 0xb090,
 683                     "%s: Poll Failed: 0x%08x 0x%08x 0x%08x\n",
 684                     __func__, value, test_mask, test_result);
 685         }
 686
 687         return timeout_error;
 688 }
 689
 690 /*
 691  * qla8044_poll_list - For all entries in the POLL_LIST header, poll read CRB
 692  * register specified by p_entry->arg1 and compare (value AND test_mask) with
 693  * test_result to validate it. Wait for p_hdr->delay between processing entries.
 694  *
 695  * @ha : Pointer to adapter structure
 696  * @p_hdr : reset_entry header for POLL_LIST opcode.
 697  *
 698  */
 699 static void
 700 qla8044_poll_list(struct scsi_qla_host *vha,
 701         struct qla8044_reset_entry_hdr *p_hdr)
 702 {
 703         long delay;
 704         struct qla8044_entry *p_entry;
 705         struct qla8044_poll *p_poll;
 706         uint32_t i;
 707         uint32_t value;
 708
 709         p_poll = (struct qla8044_poll *)
 710                 ((char *)p_hdr + sizeof(struct qla8044_reset_entry_hdr));
 711
 712         /* Entries start after 8 byte qla8044_poll, poll header contains
 713          * the test_mask, test_value.
 714          */
 715         p_entry = (struct qla8044_entry *)((char *)p_poll +
 716             sizeof(struct qla8044_poll));
 717
 718         delay = (long)p_hdr->delay;
 719
 720         if (!delay) {
 721                 for (i = 0; i < p_hdr->count; i++, p_entry++)
 722                         qla8044_poll_reg(vha, p_entry->arg1,
 723                             delay, p_poll->test_mask, p_poll->test_value);
 724         } else {
 725                 for (i = 0; i < p_hdr->count; i++, p_entry++) {
 726                         if (delay) {
 727                                 if (qla8044_poll_reg(vha,
 728                                     p_entry->arg1, delay,
 729                                     p_poll->test_mask,
 730                                     p_poll->test_value)) {
 731                                         /*If
 732                                         * (data_read&test_mask != test_value)
 733                                         * read TIMEOUT_ADDR (arg1) and
 734                                         * ADDR (arg2) registers
 735                                         */
 736                                         qla8044_rd_reg_indirect(vha,
 737                                             p_entry->arg1, &value);
 738                                         qla8044_rd_reg_indirect(vha,
 739                                             p_entry->arg2, &value);
 740                                 }
 741                         }
 742                 }
 743         }
 744 }
 745
 746 /*
 747  * qla8044_poll_write_list - Write dr_value, ar_value to dr_addr/ar_addr,
 748  * read ar_addr, if (value& test_mask != test_mask) re-read till timeout
 749  * expires.
 750  *
 751  * @vha : Pointer to adapter structure
 752  * @p_hdr : reset entry header for POLL_WRITE_LIST opcode.
 753  *
 754  */
 755 static void
 756 qla8044_poll_write_list(struct scsi_qla_host *vha,
 757         struct qla8044_reset_entry_hdr *p_hdr)
 758 {
 759         long delay;
 760         struct qla8044_quad_entry *p_entry;
 761         struct qla8044_poll *p_poll;
 762         uint32_t i;
 763
 764         p_poll = (struct qla8044_poll *)((char *)p_hdr +
 765             sizeof(struct qla8044_reset_entry_hdr));
 766
 767         p_entry = (struct qla8044_quad_entry *)((char *)p_poll +
 768             sizeof(struct qla8044_poll));
 769
 770         delay = (long)p_hdr->delay;
 771
 772         for (i = 0; i < p_hdr->count; i++, p_entry++) {
 773                 qla8044_wr_reg_indirect(vha,
 774                     p_entry->dr_addr, p_entry->dr_value);
 775                 qla8044_wr_reg_indirect(vha,
 776                     p_entry->ar_addr, p_entry->ar_value);
 777                 if (delay) {
 778                         if (qla8044_poll_reg(vha,
 779                             p_entry->ar_addr, delay,
 780                             p_poll->test_mask,
 781                             p_poll->test_value)) {
 782                                 ql_dbg(ql_dbg_p3p, vha, 0xb091,
 783                                     "%s: Timeout Error: poll list, ",
 784                                     __func__);
 785                                 ql_dbg(ql_dbg_p3p, vha, 0xb092,
 786                                     "item_num %d, entry_num %d\n", i,
 787                                     vha->reset_tmplt.seq_index);
 788                         }
 789                 }
 790         }
 791 }
 792
 793 /*
 794  * qla8044_read_modify_write - Read value from p_entry->arg1, modify the
 795  * value, write value to p_entry->arg2. Process entries with p_hdr->delay
 796  * between entries.
 797  *
 798  * @vha : Pointer to adapter structure
 799  * @p_hdr : header with shift/or/xor values.
 800  *
 801  */
 802 static void
 803 qla8044_read_modify_write(struct scsi_qla_host *vha,
 804         struct qla8044_reset_entry_hdr *p_hdr)
 805 {
 806         struct qla8044_entry *p_entry;
 807         struct qla8044_rmw *p_rmw_hdr;
 808         uint32_t i;
 809
 810         p_rmw_hdr = (struct qla8044_rmw *)((char *)p_hdr +
 811             sizeof(struct qla8044_reset_entry_hdr));
 812
 813         p_entry = (struct qla8044_entry *)((char *)p_rmw_hdr +
 814             sizeof(struct qla8044_rmw));
 815
 816         for (i = 0; i < p_hdr->count; i++, p_entry++) {
 817                 qla8044_rmw_crb_reg(vha, p_entry->arg1,
 818                     p_entry->arg2, p_rmw_hdr);
 819                 if (p_hdr->delay)
 820                         udelay((uint32_t)(p_hdr->delay));
 821         }
 822 }
 823
 824 /*
 825  * qla8044_pause - Wait for p_hdr->delay msecs, called between processing
 826  * two entries of a sequence.
 827  *
 828  * @vha : Pointer to adapter structure
 829  * @p_hdr : Common reset entry header.
 830  *
 831  */
 832 static
 833 void qla8044_pause(struct scsi_qla_host *vha,
 834         struct qla8044_reset_entry_hdr *p_hdr)
 835 {
 836         if (p_hdr->delay)
 837                 mdelay((uint32_t)((long)p_hdr->delay));
 838 }
 839
 840 /*
 841  * qla8044_template_end - Indicates end of reset sequence processing.
 842  *
 843  * @vha : Pointer to adapter structure
 844  * @p_hdr : Common reset entry header.
 845  *
 846  */
 847 static void
 848 qla8044_template_end(struct scsi_qla_host *vha,
 849         struct qla8044_reset_entry_hdr *p_hdr)
 850 {
 851         vha->reset_tmplt.template_end = 1;
 852
 853         if (vha->reset_tmplt.seq_error == 0) {
 854                 ql_dbg(ql_dbg_p3p, vha, 0xb093,
 855                     "%s: Reset sequence completed SUCCESSFULLY.\n", __func__);
 856         } else {
 857                 ql_log(ql_log_fatal, vha, 0xb094,
 858                     "%s: Reset sequence completed with some timeout "
 859                     "errors.\n", __func__);
 860         }
 861 }
 862
 863 /*
 864  * qla8044_poll_read_list - Write ar_value to ar_addr register, read ar_addr,
 865  * if (value & test_mask != test_value) re-read till timeout value expires,
 866  * read dr_addr register and assign to reset_tmplt.array.
 867  *
 868  * @vha : Pointer to adapter structure
 869  * @p_hdr : Common reset entry header.
 870  *
 871  */
 872 static void
 873 qla8044_poll_read_list(struct scsi_qla_host *vha,
 874         struct qla8044_reset_entry_hdr *p_hdr)
 875 {
 876         long delay;
 877         int index;
 878         struct qla8044_quad_entry *p_entry;
 879         struct qla8044_poll *p_poll;
 880         uint32_t i;
 881         uint32_t value;
 882
 883         p_poll = (struct qla8044_poll *)
 884                 ((char *)p_hdr + sizeof(struct qla8044_reset_entry_hdr));
 885
 886         p_entry = (struct qla8044_quad_entry *)
 887                 ((char *)p_poll + sizeof(struct qla8044_poll));
 888
 889         delay = (long)p_hdr->delay;
 890
 891         for (i = 0; i < p_hdr->count; i++, p_entry++) {
 892                 qla8044_wr_reg_indirect(vha, p_entry->ar_addr,
 893                     p_entry->ar_value);
 894                 if (delay) {
 895                         if (qla8044_poll_reg(vha, p_entry->ar_addr, delay,
 896                             p_poll->test_mask, p_poll->test_value)) {
 897                                 ql_dbg(ql_dbg_p3p, vha, 0xb095,
 898                                     "%s: Timeout Error: poll "
 899                                     "list, ", __func__);
 900                                 ql_dbg(ql_dbg_p3p, vha, 0xb096,
 901                                     "Item_num %d, "
 902                                     "entry_num %d\n", i,
 903                                     vha->reset_tmplt.seq_index);
 904                         } else {
 905                                 index = vha->reset_tmplt.array_index;
 906                                 qla8044_rd_reg_indirect(vha,
 907                                     p_entry->dr_addr, &value);
 908                                 vha->reset_tmplt.array[index++] = value;
 909                                 if (index == QLA8044_MAX_RESET_SEQ_ENTRIES)
 910                                         vha->reset_tmplt.array_index = 1;
 911                         }
 912                 }
 913         }
 914 }
 915
 916 /*
 917  * qla8031_process_reset_template - Process all entries in reset template
 918  * till entry with SEQ_END opcode, which indicates end of the reset template
 919  * processing. Each entry has a Reset Entry header, entry opcode/command, with
 920  * size of the entry, number of entries in sub-sequence and delay in microsecs
 921  * or timeout in millisecs.
 922  *
 923  * @ha : Pointer to adapter structure
 924  * @p_buff : Common reset entry header.
 925  *
 926  */
 927 static void
 928 qla8044_process_reset_template(struct scsi_qla_host *vha,
 929         char *p_buff)
 930 {
 931         int index, entries;
 932         struct qla8044_reset_entry_hdr *p_hdr;
 933         char *p_entry = p_buff;
 934
 935         vha->reset_tmplt.seq_end = 0;
 936         vha->reset_tmplt.template_end = 0;
 937         entries = vha->reset_tmplt.hdr->entries;
 938         index = vha->reset_tmplt.seq_index;
 939
 940         for (; (!vha->reset_tmplt.seq_end) && (index  < entries); index++) {
 941                 p_hdr = (struct qla8044_reset_entry_hdr *)p_entry;
 942                 switch (p_hdr->cmd) {
 943                 case OPCODE_NOP:
 944                         break;
 945                 case OPCODE_WRITE_LIST:
 946                         qla8044_write_list(vha, p_hdr);
 947                         break;
 948                 case OPCODE_READ_WRITE_LIST:
 949                         qla8044_read_write_list(vha, p_hdr);
 950                         break;
 951                 case OPCODE_POLL_LIST:
 952                         qla8044_poll_list(vha, p_hdr);
 953                         break;
 954                 case OPCODE_POLL_WRITE_LIST:
 955                         qla8044_poll_write_list(vha, p_hdr);
 956                         break;
 957                 case OPCODE_READ_MODIFY_WRITE:
 958                         qla8044_read_modify_write(vha, p_hdr);
 959                         break;
 960                 case OPCODE_SEQ_PAUSE:
 961                         qla8044_pause(vha, p_hdr);
 962                         break;
 963                 case OPCODE_SEQ_END:
 964                         vha->reset_tmplt.seq_end = 1;
 965                         break;
 966                 case OPCODE_TMPL_END:
 967                         qla8044_template_end(vha, p_hdr);
 968                         break;
 969                 case OPCODE_POLL_READ_LIST:
 970                         qla8044_poll_read_list(vha, p_hdr);
 971                         break;
 972                 default:
 973                         ql_log(ql_log_fatal, vha, 0xb097,
 974                             "%s: Unknown command ==> 0x%04x on "
 975                             "entry = %d\n", __func__, p_hdr->cmd, index);
 976                         break;
 977                 }
 978                 /*
 979                  *Set pointer to next entry in the sequence.
 980                 */
 981                 p_entry += p_hdr->size;
 982         }
 983         vha->reset_tmplt.seq_index = index;
 984 }
 985
 986 static void
 987 qla8044_process_init_seq(struct scsi_qla_host *vha)
 988 {
 989         qla8044_process_reset_template(vha,
 990             vha->reset_tmplt.init_offset);
 991         if (vha->reset_tmplt.seq_end != 1)
 992                 ql_log(ql_log_fatal, vha, 0xb098,
 993                     "%s: Abrupt INIT Sub-Sequence end.\n",
 994                     __func__);
 995 }
 996
 997 static void
 998 qla8044_process_stop_seq(struct scsi_qla_host *vha)
 999 {
1000         vha->reset_tmplt.seq_index = 0;
1001         qla8044_process_reset_template(vha, vha->reset_tmplt.stop_offset);
1002         if (vha->reset_tmplt.seq_end != 1)
1003                 ql_log(ql_log_fatal, vha, 0xb099,
1004                     "%s: Abrupt STOP Sub-Sequence end.\n", __func__);
1005 }
1006
1007 static void
1008 qla8044_process_start_seq(struct scsi_qla_host *vha)
1009 {
1010         qla8044_process_reset_template(vha, vha->reset_tmplt.start_offset);
1011         if (vha->reset_tmplt.template_end != 1)
1012                 ql_log(ql_log_fatal, vha, 0xb09a,
1013                     "%s: Abrupt START Sub-Sequence end.\n",
1014                     __func__);
1015 }
1016
1017 static int
1018 qla8044_lockless_flash_read_u32(struct scsi_qla_host *vha,
1019         uint32_t flash_addr, uint8_t *p_data, int u32_word_count)
1020 {
1021         uint32_t i;
1022         uint32_t u32_word;
1023         uint32_t flash_offset;
1024         uint32_t addr = flash_addr;
1025         int ret_val = QLA_SUCCESS;
1026
1027         flash_offset = addr & (QLA8044_FLASH_SECTOR_SIZE - 1);
1028
1029         if (addr & 0x3) {
1030                 ql_log(ql_log_fatal, vha, 0xb09b, "%s: Illegal addr = 0x%x\n",
1031                     __func__, addr);
1032                 ret_val = QLA_FUNCTION_FAILED;
1033                 goto exit_lockless_read;
1034         }
1035
1036         ret_val = qla8044_wr_reg_indirect(vha,
1037             QLA8044_FLASH_DIRECT_WINDOW, (addr));
1038
1039         if (ret_val != QLA_SUCCESS) {
1040                 ql_log(ql_log_fatal, vha, 0xb09c,
1041                     "%s: failed to write addr 0x%x to FLASH_DIRECT_WINDOW!\n",
1042                     __func__, addr);
1043                 goto exit_lockless_read;
1044         }
1045
1046         /* Check if data is spread across multiple sectors  */
1047         if ((flash_offset + (u32_word_count * sizeof(uint32_t))) >
1048             (QLA8044_FLASH_SECTOR_SIZE - 1)) {
1049                 /* Multi sector read */
1050                 for (i = 0; i < u32_word_count; i++) {
1051                         ret_val = qla8044_rd_reg_indirect(vha,
1052                             QLA8044_FLASH_DIRECT_DATA(addr), &u32_word);
1053                         if (ret_val != QLA_SUCCESS) {
1054                                 ql_log(ql_log_fatal, vha, 0xb09d,
1055                                     "%s: failed to read addr 0x%x!\n",
1056                                     __func__, addr);
1057                                 goto exit_lockless_read;
1058                         }
1059                         *(uint32_t *)p_data  = u32_word;
1060                         p_data = p_data + 4;
1061                         addr = addr + 4;
1062                         flash_offset = flash_offset + 4;
1063                         if (flash_offset > (QLA8044_FLASH_SECTOR_SIZE - 1)) {
1064                                 /* This write is needed once for each sector */
1065                                 ret_val = qla8044_wr_reg_indirect(vha,
1066                                     QLA8044_FLASH_DIRECT_WINDOW, (addr));
1067                                 if (ret_val != QLA_SUCCESS) {
1068                                         ql_log(ql_log_fatal, vha, 0xb09f,
1069                                             "%s: failed to write addr "
1070                                             "0x%x to FLASH_DIRECT_WINDOW!\n",
1071                                             __func__, addr);
1072                                         goto exit_lockless_read;
1073                                 }
1074                                 flash_offset = 0;
1075                         }
1076                 }
1077         } else {
1078                 /* Single sector read */
1079                 for (i = 0; i < u32_word_count; i++) {
1080                         ret_val = qla8044_rd_reg_indirect(vha,
1081                             QLA8044_FLASH_DIRECT_DATA(addr), &u32_word);
1082                         if (ret_val != QLA_SUCCESS) {
1083                                 ql_log(ql_log_fatal, vha, 0xb0a0,
1084                                     "%s: failed to read addr 0x%x!\n",
1085                                     __func__, addr);
1086                                 goto exit_lockless_read;
1087                         }
1088                         *(uint32_t *)p_data = u32_word;
1089                         p_data = p_data + 4;
1090                         addr = addr + 4;
1091                 }
1092         }
1093
1094 exit_lockless_read:
1095         return ret_val;
1096 }
1097
1098 /*
1099  * qla8044_ms_mem_write_128b - Writes data to MS/off-chip memory
1100  *
1101  * @vha : Pointer to adapter structure
1102  * addr : Flash address to write to
1103  * data : Data to be written
1104  * count : word_count to be written
1105  *
1106  * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED
1107  */
1108 static int
1109 qla8044_ms_mem_write_128b(struct scsi_qla_host *vha,
1110         uint64_t addr, uint32_t *data, uint32_t count)
1111 {
1112         int i, j, ret_val = QLA_SUCCESS;
1113         uint32_t agt_ctrl;
1114         unsigned long flags;
1115         struct qla_hw_data *ha = vha->hw;
1116
1117         /* Only 128-bit aligned access */
1118         if (addr & 0xF) {
1119                 ret_val = QLA_FUNCTION_FAILED;
1120                 goto exit_ms_mem_write;
1121         }
1122         write_lock_irqsave(&ha->hw_lock, flags);
1123
1124         /* Write address */
1125         ret_val = qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_ADDR_HI, 0);
1126         if (ret_val == QLA_FUNCTION_FAILED) {
1127                 ql_log(ql_log_fatal, vha, 0xb0a1,
1128                     "%s: write to AGT_ADDR_HI failed!\n", __func__);
1129                 goto exit_ms_mem_write_unlock;
1130         }
1131
1132         for (i = 0; i < count; i++, addr += 16) {
1133                 if (!((QLA8044_ADDR_IN_RANGE(addr, QLA8044_ADDR_QDR_NET,
1134                     QLA8044_ADDR_QDR_NET_MAX)) ||
1135                     (QLA8044_ADDR_IN_RANGE(addr, QLA8044_ADDR_DDR_NET,
1136                         QLA8044_ADDR_DDR_NET_MAX)))) {
1137                         ret_val = QLA_FUNCTION_FAILED;
1138                         goto exit_ms_mem_write_unlock;
1139                 }
1140
1141                 ret_val = qla8044_wr_reg_indirect(vha,
1142                     MD_MIU_TEST_AGT_ADDR_LO, addr);
1143
1144                 /* Write data */
1145                 ret_val += qla8044_wr_reg_indirect(vha,
1146                     MD_MIU_TEST_AGT_WRDATA_LO, *data++);
1147                 ret_val += qla8044_wr_reg_indirect(vha,
1148                     MD_MIU_TEST_AGT_WRDATA_HI, *data++);
1149                 ret_val += qla8044_wr_reg_indirect(vha,
1150                     MD_MIU_TEST_AGT_WRDATA_ULO, *data++);
1151                 ret_val += qla8044_wr_reg_indirect(vha,
1152                     MD_MIU_TEST_AGT_WRDATA_UHI, *data++);
1153                 if (ret_val == QLA_FUNCTION_FAILED) {
1154                         ql_log(ql_log_fatal, vha, 0xb0a2,
1155                             "%s: write to AGT_WRDATA failed!\n",
1156                             __func__);
1157                         goto exit_ms_mem_write_unlock;
1158                 }
1159
1160                 /* Check write status */
1161                 ret_val = qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_CTRL,
1162                     MIU_TA_CTL_WRITE_ENABLE);
1163                 ret_val += qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_CTRL,
1164                     MIU_TA_CTL_WRITE_START);
1165                 if (ret_val == QLA_FUNCTION_FAILED) {
1166                         ql_log(ql_log_fatal, vha, 0xb0a3,
1167                             "%s: write to AGT_CTRL failed!\n", __func__);
1168                         goto exit_ms_mem_write_unlock;
1169                 }
1170
1171                 for (j = 0; j < MAX_CTL_CHECK; j++) {
1172                         ret_val = qla8044_rd_reg_indirect(vha,
1173                             MD_MIU_TEST_AGT_CTRL, &agt_ctrl);
1174                         if (ret_val == QLA_FUNCTION_FAILED) {
1175                                 ql_log(ql_log_fatal, vha, 0xb0a4,
1176                                     "%s: failed to read "
1177                                     "MD_MIU_TEST_AGT_CTRL!\n", __func__);
1178                                 goto exit_ms_mem_write_unlock;
1179                         }
1180                         if ((agt_ctrl & MIU_TA_CTL_BUSY) == 0)
1181                                 break;
1182                 }
1183
1184                 /* Status check failed */
1185                 if (j >= MAX_CTL_CHECK) {
1186                         ql_log(ql_log_fatal, vha, 0xb0a5,
1187                             "%s: MS memory write failed!\n",
1188                            __func__);
1189                         ret_val = QLA_FUNCTION_FAILED;
1190                         goto exit_ms_mem_write_unlock;
1191                 }
1192         }
1193
1194 exit_ms_mem_write_unlock:
1195         write_unlock_irqrestore(&ha->hw_lock, flags);
1196
1197 exit_ms_mem_write:
1198         return ret_val;
1199 }
1200
1201 static int
1202 qla8044_copy_bootloader(struct scsi_qla_host *vha)
1203 {
1204         uint8_t *p_cache;
1205         uint32_t src, count, size;
1206         uint64_t dest;
1207         int ret_val = QLA_SUCCESS;
1208         struct qla_hw_data *ha = vha->hw;
1209
1210         src = QLA8044_BOOTLOADER_FLASH_ADDR;
1211         dest = qla8044_rd_reg(ha, QLA8044_BOOTLOADER_ADDR);
1212         size = qla8044_rd_reg(ha, QLA8044_BOOTLOADER_SIZE);
1213
1214         /* 128 bit alignment check */
1215         if (size & 0xF)
1216                 size = (size + 16) & ~0xF;
1217
1218         /* 16 byte count */
1219         count = size/16;
1220
1221         p_cache = vmalloc(size);
1222         if (p_cache == NULL) {
1223                 ql_log(ql_log_fatal, vha, 0xb0a6,
1224                     "%s: Failed to allocate memory for "
1225                     "boot loader cache\n", __func__);
1226                 ret_val = QLA_FUNCTION_FAILED;
1227                 goto exit_copy_bootloader;
1228         }
1229
1230         ret_val = qla8044_lockless_flash_read_u32(vha, src,
1231             p_cache, size/sizeof(uint32_t));
1232         if (ret_val == QLA_FUNCTION_FAILED) {
1233                 ql_log(ql_log_fatal, vha, 0xb0a7,
1234                     "%s: Error reading F/W from flash!!!\n", __func__);
1235                 goto exit_copy_error;
1236         }
1237         ql_dbg(ql_dbg_p3p, vha, 0xb0a8, "%s: Read F/W from flash!\n",
1238             __func__);
1239
1240         /* 128 bit/16 byte write to MS memory */
1241         ret_val = qla8044_ms_mem_write_128b(vha, dest,
1242             (uint32_t *)p_cache, count);
1243         if (ret_val == QLA_FUNCTION_FAILED) {
1244                 ql_log(ql_log_fatal, vha, 0xb0a9,
1245                     "%s: Error writing F/W to MS !!!\n", __func__);
1246                 goto exit_copy_error;
1247         }
1248         ql_dbg(ql_dbg_p3p, vha, 0xb0aa,
1249             "%s: Wrote F/W (size %d) to MS !!!\n",
1250             __func__, size);
1251
1252 exit_copy_error:
1253         vfree(p_cache);
1254
1255 exit_copy_bootloader:
1256         return ret_val;
1257 }
1258
1259 static int
1260 qla8044_restart(struct scsi_qla_host *vha)
1261 {
1262         int ret_val = QLA_SUCCESS;
1263         struct qla_hw_data *ha = vha->hw;
1264
1265         qla8044_process_stop_seq(vha);
1266
1267         /* Collect minidump */
1268         if (ql2xmdenable)
1269                 qla8044_get_minidump(vha);
1270         else
1271                 ql_log(ql_log_fatal, vha, 0xb14c,
1272                     "Minidump disabled.\n");
1273
1274         qla8044_process_init_seq(vha);
1275
1276         if (qla8044_copy_bootloader(vha)) {
1277                 ql_log(ql_log_fatal, vha, 0xb0ab,
1278                     "%s: Copy bootloader, firmware restart failed!\n",
1279                     __func__);
1280                 ret_val = QLA_FUNCTION_FAILED;
1281                 goto exit_restart;
1282         }
1283
1284         /*
1285          *  Loads F/W from flash
1286          */
1287         qla8044_wr_reg(ha, QLA8044_FW_IMAGE_VALID, QLA8044_BOOT_FROM_FLASH);
1288
1289         qla8044_process_start_seq(vha);
1290
1291 exit_restart:
1292         return ret_val;
1293 }
1294
1295 /*
1296  * qla8044_check_cmd_peg_status - Check peg status to see if Peg is
1297  * initialized.
1298  *
1299  * @ha : Pointer to adapter structure
1300  *
1301  * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED
1302  */
1303 static int
1304 qla8044_check_cmd_peg_status(struct scsi_qla_host *vha)
1305 {
1306         uint32_t val, ret_val = QLA_FUNCTION_FAILED;
1307         int retries = CRB_CMDPEG_CHECK_RETRY_COUNT;
1308         struct qla_hw_data *ha = vha->hw;
1309
1310         do {
1311                 val = qla8044_rd_reg(ha, QLA8044_CMDPEG_STATE);
1312                 if (val == PHAN_INITIALIZE_COMPLETE) {
1313                         ql_dbg(ql_dbg_p3p, vha, 0xb0ac,
1314                             "%s: Command Peg initialization "
1315                             "complete! state=0x%x\n", __func__, val);
1316                         ret_val = QLA_SUCCESS;
1317                         break;
1318                 }
1319                 msleep(CRB_CMDPEG_CHECK_DELAY);
1320         } while (--retries);
1321
1322         return ret_val;
1323 }
1324
1325 static int
1326 qla8044_start_firmware(struct scsi_qla_host *vha)
1327 {
1328         int ret_val = QLA_SUCCESS;
1329
1330         if (qla8044_restart(vha)) {
1331                 ql_log(ql_log_fatal, vha, 0xb0ad,
1332                     "%s: Restart Error!!!, Need Reset!!!\n",
1333                     __func__);
1334                 ret_val = QLA_FUNCTION_FAILED;
1335                 goto exit_start_fw;
1336         } else
1337                 ql_dbg(ql_dbg_p3p, vha, 0xb0af,
1338                     "%s: Restart done!\n", __func__);
1339
1340         ret_val = qla8044_check_cmd_peg_status(vha);
1341         if (ret_val) {
1342                 ql_log(ql_log_fatal, vha, 0xb0b0,
1343                     "%s: Peg not initialized!\n", __func__);
1344                 ret_val = QLA_FUNCTION_FAILED;
1345         }
1346
1347 exit_start_fw:
1348         return ret_val;
1349 }
1350
1351 void
1352 qla8044_clear_drv_active(struct qla_hw_data *ha)
1353 {
1354         uint32_t drv_active;
1355         struct scsi_qla_host *vha = pci_get_drvdata(ha->pdev);
1356
1357         drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX);
1358         drv_active &= ~(1 << (ha->portnum));
1359
1360         ql_log(ql_log_info, vha, 0xb0b1,
1361             "%s(%ld): drv_active: 0x%08x\n",
1362             __func__, vha->host_no, drv_active);
1363
1364         qla8044_wr_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX, drv_active);
1365 }
1366
1367 /*
1368  * qla8044_device_bootstrap - Initialize device, set DEV_READY, start fw
1369  * @ha: pointer to adapter structure
1370  *
1371  * Note: IDC lock must be held upon entry
1372  **/
1373 static int
1374 qla8044_device_bootstrap(struct scsi_qla_host *vha)
1375 {
1376         int rval = QLA_FUNCTION_FAILED;
1377         int i;
1378         uint32_t old_count = 0, count = 0;
1379         int need_reset = 0;
1380         uint32_t idc_ctrl;
1381         struct qla_hw_data *ha = vha->hw;
1382
1383         need_reset = qla8044_need_reset(vha);
1384
1385         if (!need_reset) {
1386                 old_count = qla8044_rd_direct(vha,
1387                     QLA8044_PEG_ALIVE_COUNTER_INDEX);
1388
1389                 for (i = 0; i < 10; i++) {
1390                         msleep(200);
1391
1392                         count = qla8044_rd_direct(vha,
1393                             QLA8044_PEG_ALIVE_COUNTER_INDEX);
1394                         if (count != old_count) {
1395                                 rval = QLA_SUCCESS;
1396                                 goto dev_ready;
1397                         }
1398                 }
1399                 qla8044_flash_lock_recovery(vha);
1400         } else {
1401                 /* We are trying to perform a recovery here. */
1402                 if (ha->flags.isp82xx_fw_hung)
1403                         qla8044_flash_lock_recovery(vha);
1404         }
1405
1406         /* set to DEV_INITIALIZING */
1407         ql_log(ql_log_info, vha, 0xb0b2,
1408             "%s: HW State: INITIALIZING\n", __func__);
1409         qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX,
1410             QLA8XXX_DEV_INITIALIZING);
1411
1412         qla8044_idc_unlock(ha);
1413         rval = qla8044_start_firmware(vha);
1414         qla8044_idc_lock(ha);
1415
1416         if (rval != QLA_SUCCESS) {
1417                 ql_log(ql_log_info, vha, 0xb0b3,
1418                      "%s: HW State: FAILED\n", __func__);
1419                 qla8044_clear_drv_active(ha);
1420                 qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX,
1421                     QLA8XXX_DEV_FAILED);
1422                 return rval;
1423         }
1424
1425         /* For ISP8044, If IDC_CTRL GRACEFUL_RESET_BIT1 is set , reset it after
1426          * device goes to INIT state. */
1427         idc_ctrl = qla8044_rd_reg(ha, QLA8044_IDC_DRV_CTRL);
1428         if (idc_ctrl & GRACEFUL_RESET_BIT1) {
1429                 qla8044_wr_reg(ha, QLA8044_IDC_DRV_CTRL,
1430                     (idc_ctrl & ~GRACEFUL_RESET_BIT1));
1431                 ha->fw_dumped = 0;
1432         }
1433
1434 dev_ready:
1435         ql_log(ql_log_info, vha, 0xb0b4,
1436             "%s: HW State: READY\n", __func__);
1437         qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX, QLA8XXX_DEV_READY);
1438
1439         return rval;
1440 }
1441
1442 /*-------------------------Reset Sequence Functions-----------------------*/
1443 static void
1444 qla8044_dump_reset_seq_hdr(struct scsi_qla_host *vha)
1445 {
1446         u8 *phdr;
1447
1448         if (!vha->reset_tmplt.buff) {
1449                 ql_log(ql_log_fatal, vha, 0xb0b5,
1450                     "%s: Error Invalid reset_seq_template\n", __func__);
1451                 return;
1452         }
1453
1454         phdr = vha->reset_tmplt.buff;
1455         ql_dbg(ql_dbg_p3p, vha, 0xb0b6,
1456             "Reset Template :\n\t0x%X 0x%X 0x%X 0x%X"
1457             "0x%X 0x%X 0x%X 0x%X 0x%X 0x%X\n"
1458             "\t0x%X 0x%X 0x%X 0x%X 0x%X 0x%X\n\n",
1459             *phdr, *(phdr+1), *(phdr+2), *(phdr+3), *(phdr+4),
1460             *(phdr+5), *(phdr+6), *(phdr+7), *(phdr + 8),
1461             *(phdr+9), *(phdr+10), *(phdr+11), *(phdr+12),
1462             *(phdr+13), *(phdr+14), *(phdr+15));
1463 }
1464
1465 /*
1466  * qla8044_reset_seq_checksum_test - Validate Reset Sequence template.
1467  *
1468  * @ha : Pointer to adapter structure
1469  *
1470  * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED
1471  */
1472 static int
1473 qla8044_reset_seq_checksum_test(struct scsi_qla_host *vha)
1474 {
1475         uint32_t sum =  0;
1476         uint16_t *buff = (uint16_t *)vha->reset_tmplt.buff;
1477         int u16_count =  vha->reset_tmplt.hdr->size / sizeof(uint16_t);
1478
1479         while (u16_count-- > 0)
1480                 sum += *buff++;
1481
1482         while (sum >> 16)
1483                 sum = (sum & 0xFFFF) +  (sum >> 16);
1484
1485         /* checksum of 0 indicates a valid template */
1486         if (~sum) {
1487                 return QLA_SUCCESS;
1488         } else {
1489                 ql_log(ql_log_fatal, vha, 0xb0b7,
1490                     "%s: Reset seq checksum failed\n", __func__);
1491                 return QLA_FUNCTION_FAILED;
1492         }
1493 }
1494
1495 /*
1496  * qla8044_read_reset_template - Read Reset Template from Flash, validate
1497  * the template and store offsets of stop/start/init offsets in ha->reset_tmplt.
1498  *
1499  * @ha : Pointer to adapter structure
1500  */
1501 void
1502 qla8044_read_reset_template(struct scsi_qla_host *vha)
1503 {
1504         uint8_t *p_buff;
1505         uint32_t addr, tmplt_hdr_def_size, tmplt_hdr_size;
1506
1507         vha->reset_tmplt.seq_error = 0;
1508         vha->reset_tmplt.buff = vmalloc(QLA8044_RESTART_TEMPLATE_SIZE);
1509         if (vha->reset_tmplt.buff == NULL) {
1510                 ql_log(ql_log_fatal, vha, 0xb0b8,
1511                     "%s: Failed to allocate reset template resources\n",
1512                     __func__);
1513                 goto exit_read_reset_template;
1514         }
1515
1516         p_buff = vha->reset_tmplt.buff;
1517         addr = QLA8044_RESET_TEMPLATE_ADDR;
1518
1519         tmplt_hdr_def_size =
1520             sizeof(struct qla8044_reset_template_hdr) / sizeof(uint32_t);
1521
1522         ql_dbg(ql_dbg_p3p, vha, 0xb0b9,
1523             "%s: Read template hdr size %d from Flash\n",
1524             __func__, tmplt_hdr_def_size);
1525
1526         /* Copy template header from flash */
1527         if (qla8044_read_flash_data(vha, p_buff, addr, tmplt_hdr_def_size)) {
1528                 ql_log(ql_log_fatal, vha, 0xb0ba,
1529                     "%s: Failed to read reset template\n", __func__);
1530                 goto exit_read_template_error;
1531         }
1532
1533         vha->reset_tmplt.hdr =
1534          (struct qla8044_reset_template_hdr *) vha->reset_tmplt.buff;
1535
1536         /* Validate the template header size and signature */
1537         tmplt_hdr_size = vha->reset_tmplt.hdr->hdr_size/sizeof(uint32_t);
1538         if ((tmplt_hdr_size != tmplt_hdr_def_size) ||
1539             (vha->reset_tmplt.hdr->signature != RESET_TMPLT_HDR_SIGNATURE)) {
1540                 ql_log(ql_log_fatal, vha, 0xb0bb,
1541                     "%s: Template Header size invalid %d "
1542                     "tmplt_hdr_def_size %d!!!\n", __func__,
1543                     tmplt_hdr_size, tmplt_hdr_def_size);
1544                 goto exit_read_template_error;
1545         }
1546
1547         addr = QLA8044_RESET_TEMPLATE_ADDR + vha->reset_tmplt.hdr->hdr_size;
1548         p_buff = vha->reset_tmplt.buff + vha->reset_tmplt.hdr->hdr_size;
1549         tmplt_hdr_def_size = (vha->reset_tmplt.hdr->size -
1550             vha->reset_tmplt.hdr->hdr_size)/sizeof(uint32_t);
1551
1552         ql_dbg(ql_dbg_p3p, vha, 0xb0bc,
1553             "%s: Read rest of the template size %d\n",
1554             __func__, vha->reset_tmplt.hdr->size);
1555
1556         /* Copy rest of the template */
1557         if (qla8044_read_flash_data(vha, p_buff, addr, tmplt_hdr_def_size)) {
1558                 ql_log(ql_log_fatal, vha, 0xb0bd,
1559                     "%s: Failed to read reset tempelate\n", __func__);
1560                 goto exit_read_template_error;
1561         }
1562
1563         /* Integrity check */
1564         if (qla8044_reset_seq_checksum_test(vha)) {
1565                 ql_log(ql_log_fatal, vha, 0xb0be,
1566                     "%s: Reset Seq checksum failed!\n", __func__);
1567                 goto exit_read_template_error;
1568         }
1569
1570         ql_dbg(ql_dbg_p3p, vha, 0xb0bf,
1571             "%s: Reset Seq checksum passed! Get stop, "
1572             "start and init seq offsets\n", __func__);
1573
1574         /* Get STOP, START, INIT sequence offsets */
1575         vha->reset_tmplt.init_offset = vha->reset_tmplt.buff +
1576             vha->reset_tmplt.hdr->init_seq_offset;
1577
1578         vha->reset_tmplt.start_offset = vha->reset_tmplt.buff +
1579             vha->reset_tmplt.hdr->start_seq_offset;
1580
1581         vha->reset_tmplt.stop_offset = vha->reset_tmplt.buff +
1582             vha->reset_tmplt.hdr->hdr_size;
1583
1584         qla8044_dump_reset_seq_hdr(vha);
1585
1586         goto exit_read_reset_template;
1587
1588 exit_read_template_error:
1589         vfree(vha->reset_tmplt.buff);
1590
1591 exit_read_reset_template:
1592         return;
1593 }
1594
1595 void
1596 qla8044_set_idc_dontreset(struct scsi_qla_host *vha)
1597 {
1598         uint32_t idc_ctrl;
1599         struct qla_hw_data *ha = vha->hw;
1600
1601         idc_ctrl = qla8044_rd_reg(ha, QLA8044_IDC_DRV_CTRL);
1602         idc_ctrl |= DONTRESET_BIT0;
1603         ql_dbg(ql_dbg_p3p, vha, 0xb0c0,
1604             "%s: idc_ctrl = %d\n", __func__, idc_ctrl);
1605         qla8044_wr_reg(ha, QLA8044_IDC_DRV_CTRL, idc_ctrl);
1606 }
1607
1608 inline void
1609 qla8044_set_rst_ready(struct scsi_qla_host *vha)
1610 {
1611         uint32_t drv_state;
1612         struct qla_hw_data *ha = vha->hw;
1613
1614         drv_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX);
1615
1616         /* For ISP8044, drv_active register has 1 bit per function,
1617          * shift 1 by func_num to set a bit for the function.*/
1618         drv_state |= (1 << ha->portnum);
1619
1620         ql_log(ql_log_info, vha, 0xb0c1,
1621             "%s(%ld): drv_state: 0x%08x\n",
1622             __func__, vha->host_no, drv_state);
1623         qla8044_wr_direct(vha, QLA8044_CRB_DRV_STATE_INDEX, drv_state);
1624 }
1625
1626 /**
1627  * qla8044_need_reset_handler - Code to start reset sequence
1628  * @ha: pointer to adapter structure
1629  *
1630  * Note: IDC lock must be held upon entry
1631  **/
1632 static void
1633 qla8044_need_reset_handler(struct scsi_qla_host *vha)
1634 {
1635         uint32_t dev_state = 0, drv_state, drv_active;
1636         unsigned long reset_timeout, dev_init_timeout;
1637         struct qla_hw_data *ha = vha->hw;
1638
1639         ql_log(ql_log_fatal, vha, 0xb0c2,
1640             "%s: Performing ISP error recovery\n", __func__);
1641
1642         if (vha->flags.online) {
1643                 qla8044_idc_unlock(ha);
1644                 qla2x00_abort_isp_cleanup(vha);
1645                 ha->isp_ops->get_flash_version(vha, vha->req->ring);
1646                 ha->isp_ops->nvram_config(vha);
1647                 qla8044_idc_lock(ha);
1648         }
1649
1650         drv_state = qla8044_rd_direct(vha,
1651             QLA8044_CRB_DRV_STATE_INDEX);
1652         drv_active = qla8044_rd_direct(vha,
1653             QLA8044_CRB_DRV_ACTIVE_INDEX);
1654
1655         ql_log(ql_log_info, vha, 0xb0c5,
1656             "%s(%ld): drv_state = 0x%x, drv_active = 0x%x\n",
1657             __func__, vha->host_no, drv_state, drv_active);
1658
1659         if (!ha->flags.nic_core_reset_owner) {
1660                 ql_dbg(ql_dbg_p3p, vha, 0xb0c3,
1661                     "%s(%ld): reset acknowledged\n",
1662                     __func__, vha->host_no);
1663                 qla8044_set_rst_ready(vha);
1664
1665                 /* Non-reset owners ACK Reset and wait for device INIT state
1666                  * as part of Reset Recovery by Reset Owner
1667                  */
1668                 dev_init_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
1669
1670                 do {
1671                         if (time_after_eq(jiffies, dev_init_timeout)) {
1672                                 ql_log(ql_log_info, vha, 0xb0c4,
1673                                     "%s: Non Reset owner: Reset Ack Timeout!\n",
1674                                     __func__);
1675                                 break;
1676                         }
1677
1678                         qla8044_idc_unlock(ha);
1679                         msleep(1000);
1680                         qla8044_idc_lock(ha);
1681
1682                         dev_state = qla8044_rd_direct(vha,
1683                                         QLA8044_CRB_DEV_STATE_INDEX);
1684                 } while (((drv_state & drv_active) != drv_active) &&
1685                     (dev_state == QLA8XXX_DEV_NEED_RESET));
1686         } else {
1687                 qla8044_set_rst_ready(vha);
1688
1689                 /* wait for 10 seconds for reset ack from all functions */
1690                 reset_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
1691
1692                 while ((drv_state & drv_active) != drv_active) {
1693                         if (time_after_eq(jiffies, reset_timeout)) {
1694                                 ql_log(ql_log_info, vha, 0xb0c6,
1695                                     "%s: RESET TIMEOUT!"
1696                                     "drv_state: 0x%08x, drv_active: 0x%08x\n",
1697                                     QLA2XXX_DRIVER_NAME, drv_state, drv_active);
1698                                 break;
1699                         }
1700
1701                         qla8044_idc_unlock(ha);
1702                         msleep(1000);
1703                         qla8044_idc_lock(ha);
1704
1705                         drv_state = qla8044_rd_direct(vha,
1706                             QLA8044_CRB_DRV_STATE_INDEX);
1707                         drv_active = qla8044_rd_direct(vha,
1708                             QLA8044_CRB_DRV_ACTIVE_INDEX);
1709                 }
1710
1711                 if (drv_state != drv_active) {
1712                         ql_log(ql_log_info, vha, 0xb0c7,
1713                             "%s(%ld): Reset_owner turning off drv_active "
1714                             "of non-acking function 0x%x\n", __func__,
1715                             vha->host_no, (drv_active ^ drv_state));
1716                         drv_active = drv_active & drv_state;
1717                         qla8044_wr_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX,
1718                             drv_active);
1719                 }
1720
1721                 /*
1722                 * Clear RESET OWNER, will be set at next reset
1723                 * by next RST_OWNER
1724                 */
1725                 ha->flags.nic_core_reset_owner = 0;
1726
1727                 /* Start Reset Recovery */
1728                 qla8044_device_bootstrap(vha);
1729         }
1730 }
1731
1732 static void
1733 qla8044_set_drv_active(struct scsi_qla_host *vha)
1734 {
1735         uint32_t drv_active;
1736         struct qla_hw_data *ha = vha->hw;
1737
1738         drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX);
1739
1740         /* For ISP8044, drv_active register has 1 bit per function,
1741          * shift 1 by func_num to set a bit for the function.*/
1742         drv_active |= (1 << ha->portnum);
1743
1744         ql_log(ql_log_info, vha, 0xb0c8,
1745             "%s(%ld): drv_active: 0x%08x\n",
1746             __func__, vha->host_no, drv_active);
1747         qla8044_wr_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX, drv_active);
1748 }
1749
1750 static int
1751 qla8044_check_drv_active(struct scsi_qla_host *vha)
1752 {
1753         uint32_t drv_active;
1754         struct qla_hw_data *ha = vha->hw;
1755
1756         drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX);
1757         if (drv_active & (1 << ha->portnum))
1758                 return QLA_SUCCESS;
1759         else
1760                 return QLA_TEST_FAILED;
1761 }
1762
1763 static void
1764 qla8044_clear_idc_dontreset(struct scsi_qla_host *vha)
1765 {
1766         uint32_t idc_ctrl;
1767         struct qla_hw_data *ha = vha->hw;
1768
1769         idc_ctrl = qla8044_rd_reg(ha, QLA8044_IDC_DRV_CTRL);
1770         idc_ctrl &= ~DONTRESET_BIT0;
1771         ql_log(ql_log_info, vha, 0xb0c9,
1772             "%s: idc_ctrl = %d\n", __func__,
1773             idc_ctrl);
1774         qla8044_wr_reg(ha, QLA8044_IDC_DRV_CTRL, idc_ctrl);
1775 }
1776
1777 static int
1778 qla8044_set_idc_ver(struct scsi_qla_host *vha)
1779 {
1780         int idc_ver;
1781         uint32_t drv_active;
1782         int rval = QLA_SUCCESS;
1783         struct qla_hw_data *ha = vha->hw;
1784
1785         drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX);
1786         if (drv_active == (1 << ha->portnum)) {
1787                 idc_ver = qla8044_rd_direct(vha,
1788                     QLA8044_CRB_DRV_IDC_VERSION_INDEX);
1789                 idc_ver &= (~0xFF);
1790                 idc_ver |= QLA8044_IDC_VER_MAJ_VALUE;
1791                 qla8044_wr_direct(vha, QLA8044_CRB_DRV_IDC_VERSION_INDEX,
1792                     idc_ver);
1793                 ql_log(ql_log_info, vha, 0xb0ca,
1794                     "%s: IDC version updated to %d\n",
1795                     __func__, idc_ver);
1796         } else {
1797                 idc_ver = qla8044_rd_direct(vha,
1798                     QLA8044_CRB_DRV_IDC_VERSION_INDEX);
1799                 idc_ver &= 0xFF;
1800                 if (QLA8044_IDC_VER_MAJ_VALUE != idc_ver) {
1801                         ql_log(ql_log_info, vha, 0xb0cb,
1802                             "%s: qla4xxx driver IDC version %d "
1803                             "is not compatible with IDC version %d "
1804                             "of other drivers!\n",
1805                             __func__, QLA8044_IDC_VER_MAJ_VALUE,
1806                             idc_ver);
1807                         rval = QLA_FUNCTION_FAILED;
1808                         goto exit_set_idc_ver;
1809                 }
1810         }
1811
1812         /* Update IDC_MINOR_VERSION */
1813         idc_ver = qla8044_rd_reg(ha, QLA8044_CRB_IDC_VER_MINOR);
1814         idc_ver &= ~(0x03 << (ha->portnum * 2));
1815         idc_ver |= (QLA8044_IDC_VER_MIN_VALUE << (ha->portnum * 2));
1816         qla8044_wr_reg(ha, QLA8044_CRB_IDC_VER_MINOR, idc_ver);
1817
1818 exit_set_idc_ver:
1819         return rval;
1820 }
1821
1822 static int
1823 qla8044_update_idc_reg(struct scsi_qla_host *vha)
1824 {
1825         uint32_t drv_active;
1826         int rval = QLA_SUCCESS;
1827         struct qla_hw_data *ha = vha->hw;
1828
1829         if (vha->flags.init_done)
1830                 goto exit_update_idc_reg;
1831
1832         qla8044_idc_lock(ha);
1833         qla8044_set_drv_active(vha);
1834
1835         drv_active = qla8044_rd_direct(vha,
1836             QLA8044_CRB_DRV_ACTIVE_INDEX);
1837
1838         /* If we are the first driver to load and
1839          * ql2xdontresethba is not set, clear IDC_CTRL BIT0. */
1840         if ((drv_active == (1 << ha->portnum)) && !ql2xdontresethba)
1841                 qla8044_clear_idc_dontreset(vha);
1842
1843         rval = qla8044_set_idc_ver(vha);
1844         if (rval == QLA_FUNCTION_FAILED)
1845                 qla8044_clear_drv_active(ha);
1846         qla8044_idc_unlock(ha);
1847
1848 exit_update_idc_reg:
1849         return rval;
1850 }
1851
1852 /**
1853  * qla8044_need_qsnt_handler - Code to start qsnt
1854  * @ha: pointer to adapter structure
1855  **/
1856 static void
1857 qla8044_need_qsnt_handler(struct scsi_qla_host *vha)
1858 {
1859         unsigned long qsnt_timeout;
1860         uint32_t drv_state, drv_active, dev_state;
1861         struct qla_hw_data *ha = vha->hw;
1862
1863         if (vha->flags.online)
1864                 qla2x00_quiesce_io(vha);
1865         else
1866                 return;
1867
1868         qla8044_set_qsnt_ready(vha);
1869
1870         /* Wait for 30 secs for all functions to ack qsnt mode */
1871         qsnt_timeout = jiffies + (QSNT_ACK_TOV * HZ);
1872         drv_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX);
1873         drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX);
1874
1875         /* Shift drv_active by 1 to match drv_state. As quiescent ready bit
1876            position is at bit 1 and drv active is at bit 0 */
1877         drv_active = drv_active << 1;
1878
1879         while (drv_state != drv_active) {
1880                 if (time_after_eq(jiffies, qsnt_timeout)) {
1881                         /* Other functions did not ack, changing state to
1882                          * DEV_READY
1883                          */
1884                         clear_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags);
1885                         qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX,
1886                                             QLA8XXX_DEV_READY);
1887                         qla8044_clear_qsnt_ready(vha);
1888                         ql_log(ql_log_info, vha, 0xb0cc,
1889                             "Timeout waiting for quiescent ack!!!\n");
1890                         return;
1891                 }
1892                 qla8044_idc_unlock(ha);
1893                 msleep(1000);
1894                 qla8044_idc_lock(ha);
1895
1896                 drv_state = qla8044_rd_direct(vha,
1897                     QLA8044_CRB_DRV_STATE_INDEX);
1898                 drv_active = qla8044_rd_direct(vha,
1899                     QLA8044_CRB_DRV_ACTIVE_INDEX);
1900                 drv_active = drv_active << 1;
1901         }
1902
1903         /* All functions have Acked. Set quiescent state */
1904         dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX);
1905
1906         if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
1907                 qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX,
1908                     QLA8XXX_DEV_QUIESCENT);
1909                 ql_log(ql_log_info, vha, 0xb0cd,
1910                     "%s: HW State: QUIESCENT\n", __func__);
1911         }
1912 }
1913
1914 /*
1915  * qla8044_device_state_handler - Adapter state machine
1916  * @ha: pointer to host adapter structure.
1917  *
1918  * Note: IDC lock must be UNLOCKED upon entry
1919  **/
1920 int
1921 qla8044_device_state_handler(struct scsi_qla_host *vha)
1922 {
1923         uint32_t dev_state;
1924         int rval = QLA_SUCCESS;
1925         unsigned long dev_init_timeout;
1926         struct qla_hw_data *ha = vha->hw;
1927
1928         rval = qla8044_update_idc_reg(vha);
1929         if (rval == QLA_FUNCTION_FAILED)
1930                 goto exit_error;
1931
1932         dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX);
1933         ql_dbg(ql_dbg_p3p, vha, 0xb0ce,
1934             "Device state is 0x%x = %s\n",
1935             dev_state, dev_state < MAX_STATES ?
1936             qdev_state(dev_state) : "Unknown");
1937
1938         /* wait for 30 seconds for device to go ready */
1939         dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
1940
1941         qla8044_idc_lock(ha);
1942
1943         while (1) {
1944                 if (time_after_eq(jiffies, dev_init_timeout)) {
1945                         if (qla8044_check_drv_active(vha) == QLA_SUCCESS) {
1946                                 ql_log(ql_log_warn, vha, 0xb0cf,
1947                                     "%s: Device Init Failed 0x%x = %s\n",
1948                                     QLA2XXX_DRIVER_NAME, dev_state,
1949                                     dev_state < MAX_STATES ?
1950                                     qdev_state(dev_state) : "Unknown");
1951                                 qla8044_wr_direct(vha,
1952                                     QLA8044_CRB_DEV_STATE_INDEX,
1953                                     QLA8XXX_DEV_FAILED);
1954                         }
1955                 }
1956
1957                 dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX);
1958                 ql_log(ql_log_info, vha, 0xb0d0,
1959                     "Device state is 0x%x = %s\n",
1960                     dev_state, dev_state < MAX_STATES ?
1961                     qdev_state(dev_state) : "Unknown");
1962
1963                 /* NOTE: Make sure idc unlocked upon exit of switch statement */
1964                 switch (dev_state) {
1965                 case QLA8XXX_DEV_READY:
1966                         ha->flags.nic_core_reset_owner = 0;
1967                         goto exit;
1968                 case QLA8XXX_DEV_COLD:
1969                         rval = qla8044_device_bootstrap(vha);
1970                         break;
1971                 case QLA8XXX_DEV_INITIALIZING:
1972                         qla8044_idc_unlock(ha);
1973                         msleep(1000);
1974                         qla8044_idc_lock(ha);
1975                         break;
1976                 case QLA8XXX_DEV_NEED_RESET:
1977                         /* For ISP8044, if NEED_RESET is set by any driver,
1978                          * it should be honored, irrespective of IDC_CTRL
1979                          * DONTRESET_BIT0 */
1980                         qla8044_need_reset_handler(vha);
1981                         break;
1982                 case QLA8XXX_DEV_NEED_QUIESCENT:
1983                         /* idc locked/unlocked in handler */
1984                         qla8044_need_qsnt_handler(vha);
1985
1986                         /* Reset the init timeout after qsnt handler */
1987                         dev_init_timeout = jiffies +
1988                             (ha->fcoe_reset_timeout * HZ);
1989                         break;
1990                 case QLA8XXX_DEV_QUIESCENT:
1991                         ql_log(ql_log_info, vha, 0xb0d1,
1992                             "HW State: QUIESCENT\n");
1993
1994                         qla8044_idc_unlock(ha);
1995                         msleep(1000);
1996                         qla8044_idc_lock(ha);
1997
1998                         /* Reset the init timeout after qsnt handler */
1999                         dev_init_timeout = jiffies +
2000                             (ha->fcoe_reset_timeout * HZ);
2001                         break;
2002                 case QLA8XXX_DEV_FAILED:
2003                         ha->flags.nic_core_reset_owner = 0;
2004                         qla8044_idc_unlock(ha);
2005                         qla8xxx_dev_failed_handler(vha);
2006                         rval = QLA_FUNCTION_FAILED;
2007                         qla8044_idc_lock(ha);
2008                         goto exit;
2009                 default:
2010                         qla8044_idc_unlock(ha);
2011                         qla8xxx_dev_failed_handler(vha);
2012                         rval = QLA_FUNCTION_FAILED;
2013                         qla8044_idc_lock(ha);
2014                         goto exit;
2015                 }
2016         }
2017 exit:
2018         qla8044_idc_unlock(ha);
2019
2020 exit_error:
2021         return rval;
2022 }
2023
2024 /**
2025  * qla4_8xxx_check_temp - Check the ISP82XX temperature.
2026  * @ha: adapter block pointer.
2027  *
2028  * Note: The caller should not hold the idc lock.
2029  **/
2030 static int
2031 qla8044_check_temp(struct scsi_qla_host *vha)
2032 {
2033         uint32_t temp, temp_state, temp_val;
2034         int status = QLA_SUCCESS;
2035
2036         temp = qla8044_rd_direct(vha, QLA8044_CRB_TEMP_STATE_INDEX);
2037         temp_state = qla82xx_get_temp_state(temp);
2038         temp_val = qla82xx_get_temp_val(temp);
2039
2040         if (temp_state == QLA82XX_TEMP_PANIC) {
2041                 ql_log(ql_log_warn, vha, 0xb0d2,
2042                     "Device temperature %d degrees C"
2043                     " exceeds maximum allowed. Hardware has been shut"
2044                     " down\n", temp_val);
2045                 status = QLA_FUNCTION_FAILED;
2046                 return status;
2047         } else if (temp_state == QLA82XX_TEMP_WARN) {
2048                 ql_log(ql_log_warn, vha, 0xb0d3,
2049                     "Device temperature %d"
2050                     " degrees C exceeds operating range."
2051                     " Immediate action needed.\n", temp_val);
2052         }
2053         return 0;
2054 }
2055
2056 int qla8044_read_temperature(scsi_qla_host_t *vha)
2057 {
2058         uint32_t temp;
2059
2060         temp = qla8044_rd_direct(vha, QLA8044_CRB_TEMP_STATE_INDEX);
2061         return qla82xx_get_temp_val(temp);
2062 }
2063
2064 /**
2065  * qla8044_check_fw_alive  - Check firmware health
2066  * @ha: Pointer to host adapter structure.
2067  *
2068  * Context: Interrupt
2069  **/
2070 int
2071 qla8044_check_fw_alive(struct scsi_qla_host *vha)
2072 {
2073         uint32_t fw_heartbeat_counter;
2074         uint32_t halt_status1, halt_status2;
2075         int status = QLA_SUCCESS;
2076
2077         fw_heartbeat_counter = qla8044_rd_direct(vha,
2078             QLA8044_PEG_ALIVE_COUNTER_INDEX);
2079
2080         /* If PEG_ALIVE_COUNTER is 0xffffffff, AER/EEH is in progress, ignore */
2081         if (fw_heartbeat_counter == 0xffffffff) {
2082                 ql_dbg(ql_dbg_p3p, vha, 0xb0d4,
2083                     "scsi%ld: %s: Device in frozen "
2084                     "state, QLA82XX_PEG_ALIVE_COUNTER is 0xffffffff\n",
2085                     vha->host_no, __func__);
2086                 return status;
2087         }
2088
2089         if (vha->fw_heartbeat_counter == fw_heartbeat_counter) {
2090                 vha->seconds_since_last_heartbeat++;
2091                 /* FW not alive after 2 seconds */
2092                 if (vha->seconds_since_last_heartbeat == 2) {
2093                         vha->seconds_since_last_heartbeat = 0;
2094                         halt_status1 = qla8044_rd_direct(vha,
2095                             QLA8044_PEG_HALT_STATUS1_INDEX);
2096                         halt_status2 = qla8044_rd_direct(vha,
2097                             QLA8044_PEG_HALT_STATUS2_INDEX);
2098
2099                         ql_log(ql_log_info, vha, 0xb0d5,
2100                             "scsi(%ld): %s, ISP8044 "
2101                             "Dumping hw/fw registers:\n"
2102                             " PEG_HALT_STATUS1: 0x%x, "
2103                             "PEG_HALT_STATUS2: 0x%x,\n",
2104                             vha->host_no, __func__, halt_status1,
2105                             halt_status2);
2106                         status = QLA_FUNCTION_FAILED;
2107                 }
2108         } else
2109                 vha->seconds_since_last_heartbeat = 0;
2110
2111         vha->fw_heartbeat_counter = fw_heartbeat_counter;
2112         return status;
2113 }
2114
2115 void
2116 qla8044_watchdog(struct scsi_qla_host *vha)
2117 {
2118         uint32_t dev_state, halt_status;
2119         int halt_status_unrecoverable = 0;
2120         struct qla_hw_data *ha = vha->hw;
2121
2122         /* don't poll if reset is going on or FW hang in quiescent state */
2123         if (!(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) ||
2124             test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))) {
2125                 dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX);
2126
2127                 if (qla8044_check_fw_alive(vha)) {
2128                         ha->flags.isp82xx_fw_hung = 1;
2129                         ql_log(ql_log_warn, vha, 0xb10a,
2130                             "Firmware hung.\n");
2131                         qla82xx_clear_pending_mbx(vha);
2132                 }
2133
2134                 if (qla8044_check_temp(vha)) {
2135                         set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags);
2136                         ha->flags.isp82xx_fw_hung = 1;
2137                         qla2xxx_wake_dpc(vha);
2138                 } else if (dev_state == QLA8XXX_DEV_NEED_RESET &&
2139                            !test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) {
2140                         ql_log(ql_log_info, vha, 0xb0d6,
2141                             "%s: HW State: NEED RESET!\n",
2142                             __func__);
2143                         set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2144                         qla2xxx_wake_dpc(vha);
2145                 } else if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT &&
2146                     !test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) {
2147                         ql_log(ql_log_info, vha, 0xb0d7,
2148                             "%s: HW State: NEED QUIES detected!\n",
2149                             __func__);
2150                         set_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags);
2151                         qla2xxx_wake_dpc(vha);
2152                 } else  {
2153                         /* Check firmware health */
2154                         if (ha->flags.isp82xx_fw_hung) {
2155                                 halt_status = qla8044_rd_direct(vha,
2156                                         QLA8044_PEG_HALT_STATUS1_INDEX);
2157                                 if (halt_status &
2158                                     QLA8044_HALT_STATUS_FW_RESET) {
2159                                         ql_log(ql_log_fatal, vha,
2160                                             0xb0d8, "%s: Firmware "
2161                                             "error detected device "
2162                                             "is being reset\n",
2163                                             __func__);
2164                                 } else if (halt_status &
2165                                             QLA8044_HALT_STATUS_UNRECOVERABLE) {
2166                                                 halt_status_unrecoverable = 1;
2167                                 }
2168
2169                                 /* Since we cannot change dev_state in interrupt
2170                                  * context, set appropriate DPC flag then wakeup
2171                                  *  DPC */
2172                                 if (halt_status_unrecoverable) {
2173                                         set_bit(ISP_UNRECOVERABLE,
2174                                             &vha->dpc_flags);
2175                                 } else {
2176                                         if (dev_state ==
2177                                             QLA8XXX_DEV_QUIESCENT) {
2178                                                 set_bit(FCOE_CTX_RESET_NEEDED,
2179                                                     &vha->dpc_flags);
2180                                                 ql_log(ql_log_info, vha, 0xb0d9,
2181                                                     "%s: FW CONTEXT Reset "
2182                                                     "needed!\n", __func__);
2183                                         } else {
2184                                                 ql_log(ql_log_info, vha,
2185                                                     0xb0da, "%s: "
2186                                                     "detect abort needed\n",
2187                                                     __func__);
2188                                                 set_bit(ISP_ABORT_NEEDED,
2189                                                     &vha->dpc_flags);
2190                                         }
2191                                 }
2192                                 qla2xxx_wake_dpc(vha);
2193                         }
2194                 }
2195
2196         }
2197 }
2198
2199 static int
2200 qla8044_minidump_process_control(struct scsi_qla_host *vha,
2201                                  struct qla8044_minidump_entry_hdr *entry_hdr)
2202 {
2203         struct qla8044_minidump_entry_crb *crb_entry;
2204         uint32_t read_value, opcode, poll_time, addr, index;
2205         uint32_t crb_addr, rval = QLA_SUCCESS;
2206         unsigned long wtime;
2207         struct qla8044_minidump_template_hdr *tmplt_hdr;
2208         int i;
2209         struct qla_hw_data *ha = vha->hw;
2210
2211         ql_dbg(ql_dbg_p3p, vha, 0xb0dd, "Entering fn: %s\n", __func__);
2212         tmplt_hdr = (struct qla8044_minidump_template_hdr *)
2213                 ha->md_tmplt_hdr;
2214         crb_entry = (struct qla8044_minidump_entry_crb *)entry_hdr;
2215
2216         crb_addr = crb_entry->addr;
2217         for (i = 0; i < crb_entry->op_count; i++) {
2218                 opcode = crb_entry->crb_ctrl.opcode;
2219
2220                 if (opcode & QLA82XX_DBG_OPCODE_WR) {
2221                         qla8044_wr_reg_indirect(vha, crb_addr,
2222                             crb_entry->value_1);
2223                         opcode &= ~QLA82XX_DBG_OPCODE_WR;
2224                 }
2225
2226                 if (opcode & QLA82XX_DBG_OPCODE_RW) {
2227                         qla8044_rd_reg_indirect(vha, crb_addr, &read_value);
2228                         qla8044_wr_reg_indirect(vha, crb_addr, read_value);
2229                         opcode &= ~QLA82XX_DBG_OPCODE_RW;
2230                 }
2231
2232                 if (opcode & QLA82XX_DBG_OPCODE_AND) {
2233                         qla8044_rd_reg_indirect(vha, crb_addr, &read_value);
2234                         read_value &= crb_entry->value_2;
2235                         opcode &= ~QLA82XX_DBG_OPCODE_AND;
2236                         if (opcode & QLA82XX_DBG_OPCODE_OR) {
2237                                 read_value |= crb_entry->value_3;
2238                                 opcode &= ~QLA82XX_DBG_OPCODE_OR;
2239                         }
2240                         qla8044_wr_reg_indirect(vha, crb_addr, read_value);
2241                 }
2242                 if (opcode & QLA82XX_DBG_OPCODE_OR) {
2243                         qla8044_rd_reg_indirect(vha, crb_addr, &read_value);
2244                         read_value |= crb_entry->value_3;
2245                         qla8044_wr_reg_indirect(vha, crb_addr, read_value);
2246                         opcode &= ~QLA82XX_DBG_OPCODE_OR;
2247                 }
2248                 if (opcode & QLA82XX_DBG_OPCODE_POLL) {
2249                         poll_time = crb_entry->crb_strd.poll_timeout;
2250                         wtime = jiffies + poll_time;
2251                         qla8044_rd_reg_indirect(vha, crb_addr, &read_value);
2252
2253                         do {
2254                                 if ((read_value & crb_entry->value_2) ==
2255                                     crb_entry->value_1) {
2256                                         break;
2257                                 } else if (time_after_eq(jiffies, wtime)) {
2258                                         /* capturing dump failed */
2259                                         rval = QLA_FUNCTION_FAILED;
2260                                         break;
2261                                 } else {
2262                                         qla8044_rd_reg_indirect(vha,
2263                                             crb_addr, &read_value);
2264                                 }
2265                         } while (1);
2266                         opcode &= ~QLA82XX_DBG_OPCODE_POLL;
2267                 }
2268
2269                 if (opcode & QLA82XX_DBG_OPCODE_RDSTATE) {
2270                         if (crb_entry->crb_strd.state_index_a) {
2271                                 index = crb_entry->crb_strd.state_index_a;
2272                                 addr = tmplt_hdr->saved_state_array[index];
2273                         } else {
2274                                 addr = crb_addr;
2275                         }
2276
2277                         qla8044_rd_reg_indirect(vha, addr, &read_value);
2278                         index = crb_entry->crb_ctrl.state_index_v;
2279                         tmplt_hdr->saved_state_array[index] = read_value;
2280                         opcode &= ~QLA82XX_DBG_OPCODE_RDSTATE;
2281                 }
2282
2283                 if (opcode & QLA82XX_DBG_OPCODE_WRSTATE) {
2284                         if (crb_entry->crb_strd.state_index_a) {
2285                                 index = crb_entry->crb_strd.state_index_a;
2286                                 addr = tmplt_hdr->saved_state_array[index];
2287                         } else {
2288                                 addr = crb_addr;
2289                         }
2290
2291                         if (crb_entry->crb_ctrl.state_index_v) {
2292                                 index = crb_entry->crb_ctrl.state_index_v;
2293                                 read_value =
2294                                     tmplt_hdr->saved_state_array[index];
2295                         } else {
2296                                 read_value = crb_entry->value_1;
2297                         }
2298
2299                         qla8044_wr_reg_indirect(vha, addr, read_value);
2300                         opcode &= ~QLA82XX_DBG_OPCODE_WRSTATE;
2301                 }
2302
2303                 if (opcode & QLA82XX_DBG_OPCODE_MDSTATE) {
2304                         index = crb_entry->crb_ctrl.state_index_v;
2305                         read_value = tmplt_hdr->saved_state_array[index];
2306                         read_value <<= crb_entry->crb_ctrl.shl;
2307                         read_value >>= crb_entry->crb_ctrl.shr;
2308                         if (crb_entry->value_2)
2309                                 read_value &= crb_entry->value_2;
2310                         read_value |= crb_entry->value_3;
2311                         read_value += crb_entry->value_1;
2312                         tmplt_hdr->saved_state_array[index] = read_value;
2313                         opcode &= ~QLA82XX_DBG_OPCODE_MDSTATE;
2314                 }
2315                 crb_addr += crb_entry->crb_strd.addr_stride;
2316         }
2317         return rval;
2318 }
2319
2320 static void
2321 qla8044_minidump_process_rdcrb(struct scsi_qla_host *vha,
2322         struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
2323 {
2324         uint32_t r_addr, r_stride, loop_cnt, i, r_value;
2325         struct qla8044_minidump_entry_crb *crb_hdr;
2326         uint32_t *data_ptr = *d_ptr;
2327
2328         ql_dbg(ql_dbg_p3p, vha, 0xb0de, "Entering fn: %s\n", __func__);
2329         crb_hdr = (struct qla8044_minidump_entry_crb *)entry_hdr;
2330         r_addr = crb_hdr->addr;
2331         r_stride = crb_hdr->crb_strd.addr_stride;
2332         loop_cnt = crb_hdr->op_count;
2333
2334         for (i = 0; i < loop_cnt; i++) {
2335                 qla8044_rd_reg_indirect(vha, r_addr, &r_value);
2336                 *data_ptr++ = r_addr;
2337                 *data_ptr++ = r_value;
2338                 r_addr += r_stride;
2339         }
2340         *d_ptr = data_ptr;
2341 }
2342
2343 static int
2344 qla8044_minidump_process_rdmem(struct scsi_qla_host *vha,
2345         struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
2346 {
2347         uint32_t r_addr, r_value, r_data;
2348         uint32_t i, j, loop_cnt;
2349         struct qla8044_minidump_entry_rdmem *m_hdr;
2350         unsigned long flags;
2351         uint32_t *data_ptr = *d_ptr;
2352         struct qla_hw_data *ha = vha->hw;
2353
2354         ql_dbg(ql_dbg_p3p, vha, 0xb0df, "Entering fn: %s\n", __func__);
2355         m_hdr = (struct qla8044_minidump_entry_rdmem *)entry_hdr;
2356         r_addr = m_hdr->read_addr;
2357         loop_cnt = m_hdr->read_data_size/16;
2358
2359         ql_dbg(ql_dbg_p3p, vha, 0xb0f0,
2360             "[%s]: Read addr: 0x%x, read_data_size: 0x%x\n",
2361             __func__, r_addr, m_hdr->read_data_size);
2362
2363         if (r_addr & 0xf) {
2364                 ql_dbg(ql_dbg_p3p, vha, 0xb0f1,
2365                     "[%s]: Read addr 0x%x not 16 bytes aligned\n",
2366                     __func__, r_addr);
2367                 return QLA_FUNCTION_FAILED;
2368         }
2369
2370         if (m_hdr->read_data_size % 16) {
2371                 ql_dbg(ql_dbg_p3p, vha, 0xb0f2,
2372                     "[%s]: Read data[0x%x] not multiple of 16 bytes\n",
2373                     __func__, m_hdr->read_data_size);
2374                 return QLA_FUNCTION_FAILED;
2375         }
2376
2377         ql_dbg(ql_dbg_p3p, vha, 0xb0f3,
2378             "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n",
2379             __func__, r_addr, m_hdr->read_data_size, loop_cnt);
2380
2381         write_lock_irqsave(&ha->hw_lock, flags);
2382         for (i = 0; i < loop_cnt; i++) {
2383                 qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_ADDR_LO, r_addr);
2384                 r_value = 0;
2385                 qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_ADDR_HI, r_value);
2386                 r_value = MIU_TA_CTL_ENABLE;
2387                 qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_CTRL, r_value);
2388                 r_value = MIU_TA_CTL_START_ENABLE;
2389                 qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_CTRL, r_value);
2390
2391                 for (j = 0; j < MAX_CTL_CHECK; j++) {
2392                         qla8044_rd_reg_indirect(vha, MD_MIU_TEST_AGT_CTRL,
2393                             &r_value);
2394                         if ((r_value & MIU_TA_CTL_BUSY) == 0)
2395                                 break;
2396                 }
2397
2398                 if (j >= MAX_CTL_CHECK) {
2399                         write_unlock_irqrestore(&ha->hw_lock, flags);
2400                         return QLA_SUCCESS;
2401                 }
2402
2403                 for (j = 0; j < 4; j++) {
2404                         qla8044_rd_reg_indirect(vha, MD_MIU_TEST_AGT_RDDATA[j],
2405                             &r_data);
2406                         *data_ptr++ = r_data;
2407                 }
2408
2409                 r_addr += 16;
2410         }
2411         write_unlock_irqrestore(&ha->hw_lock, flags);
2412
2413         ql_dbg(ql_dbg_p3p, vha, 0xb0f4,
2414             "Leaving fn: %s datacount: 0x%x\n",
2415              __func__, (loop_cnt * 16));
2416
2417         *d_ptr = data_ptr;
2418         return QLA_SUCCESS;
2419 }
2420
2421 /* ISP83xx flash read for _RDROM _BOARD */
2422 static uint32_t
2423 qla8044_minidump_process_rdrom(struct scsi_qla_host *vha,
2424         struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
2425 {
2426         uint32_t fl_addr, u32_count, rval;
2427         struct qla8044_minidump_entry_rdrom *rom_hdr;
2428         uint32_t *data_ptr = *d_ptr;
2429
2430         rom_hdr = (struct qla8044_minidump_entry_rdrom *)entry_hdr;
2431         fl_addr = rom_hdr->read_addr;
2432         u32_count = (rom_hdr->read_data_size)/sizeof(uint32_t);
2433
2434         ql_dbg(ql_dbg_p3p, vha, 0xb0f5, "[%s]: fl_addr: 0x%x, count: 0x%x\n",
2435             __func__, fl_addr, u32_count);
2436
2437         rval = qla8044_lockless_flash_read_u32(vha, fl_addr,
2438             (u8 *)(data_ptr), u32_count);
2439
2440         if (rval != QLA_SUCCESS) {
2441                 ql_log(ql_log_fatal, vha, 0xb0f6,
2442                     "%s: Flash Read Error,Count=%d\n", __func__, u32_count);
2443                 return QLA_FUNCTION_FAILED;
2444         } else {
2445                 data_ptr += u32_count;
2446                 *d_ptr = data_ptr;
2447                 return QLA_SUCCESS;
2448         }
2449 }
2450
2451 static void
2452 qla8044_mark_entry_skipped(struct scsi_qla_host *vha,
2453         struct qla8044_minidump_entry_hdr *entry_hdr, int index)
2454 {
2455         entry_hdr->d_ctrl.driver_flags |= QLA82XX_DBG_SKIPPED_FLAG;
2456
2457         ql_log(ql_log_info, vha, 0xb0f7,
2458             "scsi(%ld): Skipping entry[%d]: ETYPE[0x%x]-ELEVEL[0x%x]\n",
2459             vha->host_no, index, entry_hdr->entry_type,
2460             entry_hdr->d_ctrl.entry_capture_mask);
2461 }
2462
2463 static int
2464 qla8044_minidump_process_l2tag(struct scsi_qla_host *vha,
2465         struct qla8044_minidump_entry_hdr *entry_hdr,
2466                                  uint32_t **d_ptr)
2467 {
2468         uint32_t addr, r_addr, c_addr, t_r_addr;
2469         uint32_t i, k, loop_count, t_value, r_cnt, r_value;
2470         unsigned long p_wait, w_time, p_mask;
2471         uint32_t c_value_w, c_value_r;
2472         struct qla8044_minidump_entry_cache *cache_hdr;
2473         int rval = QLA_FUNCTION_FAILED;
2474         uint32_t *data_ptr = *d_ptr;
2475
2476         ql_dbg(ql_dbg_p3p, vha, 0xb0f8, "Entering fn: %s\n", __func__);
2477         cache_hdr = (struct qla8044_minidump_entry_cache *)entry_hdr;
2478
2479         loop_count = cache_hdr->op_count;
2480         r_addr = cache_hdr->read_addr;
2481         c_addr = cache_hdr->control_addr;
2482         c_value_w = cache_hdr->cache_ctrl.write_value;
2483
2484         t_r_addr = cache_hdr->tag_reg_addr;
2485         t_value = cache_hdr->addr_ctrl.init_tag_value;
2486         r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
2487         p_wait = cache_hdr->cache_ctrl.poll_wait;
2488         p_mask = cache_hdr->cache_ctrl.poll_mask;
2489
2490         for (i = 0; i < loop_count; i++) {
2491                 qla8044_wr_reg_indirect(vha, t_r_addr, t_value);
2492                 if (c_value_w)
2493                         qla8044_wr_reg_indirect(vha, c_addr, c_value_w);
2494
2495                 if (p_mask) {
2496                         w_time = jiffies + p_wait;
2497                         do {
2498                                 qla8044_rd_reg_indirect(vha, c_addr,
2499                                     &c_value_r);
2500                                 if ((c_value_r & p_mask) == 0) {
2501                                         break;
2502                                 } else if (time_after_eq(jiffies, w_time)) {
2503                                         /* capturing dump failed */
2504                                         return rval;
2505                                 }
2506                         } while (1);
2507                 }
2508
2509                 addr = r_addr;
2510                 for (k = 0; k < r_cnt; k++) {
2511                         qla8044_rd_reg_indirect(vha, addr, &r_value);
2512                         *data_ptr++ = r_value;
2513                         addr += cache_hdr->read_ctrl.read_addr_stride;
2514                 }
2515                 t_value += cache_hdr->addr_ctrl.tag_value_stride;
2516         }
2517         *d_ptr = data_ptr;
2518         return QLA_SUCCESS;
2519 }
2520
2521 static void
2522 qla8044_minidump_process_l1cache(struct scsi_qla_host *vha,
2523         struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
2524 {
2525         uint32_t addr, r_addr, c_addr, t_r_addr;
2526         uint32_t i, k, loop_count, t_value, r_cnt, r_value;
2527         uint32_t c_value_w;
2528         struct qla8044_minidump_entry_cache *cache_hdr;
2529         uint32_t *data_ptr = *d_ptr;
2530
2531         cache_hdr = (struct qla8044_minidump_entry_cache *)entry_hdr;
2532         loop_count = cache_hdr->op_count;
2533         r_addr = cache_hdr->read_addr;
2534         c_addr = cache_hdr->control_addr;
2535         c_value_w = cache_hdr->cache_ctrl.write_value;
2536
2537         t_r_addr = cache_hdr->tag_reg_addr;
2538         t_value = cache_hdr->addr_ctrl.init_tag_value;
2539         r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
2540
2541         for (i = 0; i < loop_count; i++) {
2542                 qla8044_wr_reg_indirect(vha, t_r_addr, t_value);
2543                 qla8044_wr_reg_indirect(vha, c_addr, c_value_w);
2544                 addr = r_addr;
2545                 for (k = 0; k < r_cnt; k++) {
2546                         qla8044_rd_reg_indirect(vha, addr, &r_value);
2547                         *data_ptr++ = r_value;
2548                         addr += cache_hdr->read_ctrl.read_addr_stride;
2549                 }
2550                 t_value += cache_hdr->addr_ctrl.tag_value_stride;
2551         }
2552         *d_ptr = data_ptr;
2553 }
2554
2555 static void
2556 qla8044_minidump_process_rdocm(struct scsi_qla_host *vha,
2557         struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
2558 {
2559         uint32_t r_addr, r_stride, loop_cnt, i, r_value;
2560         struct qla8044_minidump_entry_rdocm *ocm_hdr;
2561         uint32_t *data_ptr = *d_ptr;
2562         struct qla_hw_data *ha = vha->hw;
2563
2564         ql_dbg(ql_dbg_p3p, vha, 0xb0f9, "Entering fn: %s\n", __func__);
2565
2566         ocm_hdr = (struct qla8044_minidump_entry_rdocm *)entry_hdr;
2567         r_addr = ocm_hdr->read_addr;
2568         r_stride = ocm_hdr->read_addr_stride;
2569         loop_cnt = ocm_hdr->op_count;
2570
2571         ql_dbg(ql_dbg_p3p, vha, 0xb0fa,
2572             "[%s]: r_addr: 0x%x, r_stride: 0x%x, loop_cnt: 0x%x\n",
2573             __func__, r_addr, r_stride, loop_cnt);
2574
2575         for (i = 0; i < loop_cnt; i++) {
2576                 r_value = readl((void __iomem *)(r_addr + ha->nx_pcibase));
2577                 *data_ptr++ = r_value;
2578                 r_addr += r_stride;
2579         }
2580         ql_dbg(ql_dbg_p3p, vha, 0xb0fb, "Leaving fn: %s datacount: 0x%lx\n",
2581             __func__, (long unsigned int) (loop_cnt * sizeof(uint32_t)));
2582
2583         *d_ptr = data_ptr;
2584 }
2585
2586 static void
2587 qla8044_minidump_process_rdmux(struct scsi_qla_host *vha,
2588         struct qla8044_minidump_entry_hdr *entry_hdr,
2589         uint32_t **d_ptr)
2590 {
2591         uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value;
2592         struct qla8044_minidump_entry_mux *mux_hdr;
2593         uint32_t *data_ptr = *d_ptr;
2594
2595         ql_dbg(ql_dbg_p3p, vha, 0xb0fc, "Entering fn: %s\n", __func__);
2596
2597         mux_hdr = (struct qla8044_minidump_entry_mux *)entry_hdr;
2598         r_addr = mux_hdr->read_addr;
2599         s_addr = mux_hdr->select_addr;
2600         s_stride = mux_hdr->select_value_stride;
2601         s_value = mux_hdr->select_value;
2602         loop_cnt = mux_hdr->op_count;
2603
2604         for (i = 0; i < loop_cnt; i++) {
2605                 qla8044_wr_reg_indirect(vha, s_addr, s_value);
2606                 qla8044_rd_reg_indirect(vha, r_addr, &r_value);
2607                 *data_ptr++ = s_value;
2608                 *data_ptr++ = r_value;
2609                 s_value += s_stride;
2610         }
2611         *d_ptr = data_ptr;
2612 }
2613
2614 static void
2615 qla8044_minidump_process_queue(struct scsi_qla_host *vha,
2616         struct qla8044_minidump_entry_hdr *entry_hdr,
2617         uint32_t **d_ptr)
2618 {
2619         uint32_t s_addr, r_addr;
2620         uint32_t r_stride, r_value, r_cnt, qid = 0;
2621         uint32_t i, k, loop_cnt;
2622         struct qla8044_minidump_entry_queue *q_hdr;
2623         uint32_t *data_ptr = *d_ptr;
2624
2625         ql_dbg(ql_dbg_p3p, vha, 0xb0fd, "Entering fn: %s\n", __func__);
2626         q_hdr = (struct qla8044_minidump_entry_queue *)entry_hdr;
2627         s_addr = q_hdr->select_addr;
2628         r_cnt = q_hdr->rd_strd.read_addr_cnt;
2629         r_stride = q_hdr->rd_strd.read_addr_stride;
2630         loop_cnt = q_hdr->op_count;
2631
2632         for (i = 0; i < loop_cnt; i++) {
2633                 qla8044_wr_reg_indirect(vha, s_addr, qid);
2634                 r_addr = q_hdr->read_addr;
2635                 for (k = 0; k < r_cnt; k++) {
2636                         qla8044_rd_reg_indirect(vha, r_addr, &r_value);
2637                         *data_ptr++ = r_value;
2638                         r_addr += r_stride;
2639                 }
2640                 qid += q_hdr->q_strd.queue_id_stride;
2641         }
2642         *d_ptr = data_ptr;
2643 }
2644
2645 /* ISP83xx functions to process new minidump entries... */
2646 static uint32_t
2647 qla8044_minidump_process_pollrd(struct scsi_qla_host *vha,
2648         struct qla8044_minidump_entry_hdr *entry_hdr,
2649         uint32_t **d_ptr)
2650 {
2651         uint32_t r_addr, s_addr, s_value, r_value, poll_wait, poll_mask;
2652         uint16_t s_stride, i;
2653         struct qla8044_minidump_entry_pollrd *pollrd_hdr;
2654         uint32_t *data_ptr = *d_ptr;
2655
2656         pollrd_hdr = (struct qla8044_minidump_entry_pollrd *) entry_hdr;
2657         s_addr = pollrd_hdr->select_addr;
2658         r_addr = pollrd_hdr->read_addr;
2659         s_value = pollrd_hdr->select_value;
2660         s_stride = pollrd_hdr->select_value_stride;
2661
2662         poll_wait = pollrd_hdr->poll_wait;
2663         poll_mask = pollrd_hdr->poll_mask;
2664
2665         for (i = 0; i < pollrd_hdr->op_count; i++) {
2666                 qla8044_wr_reg_indirect(vha, s_addr, s_value);
2667                 poll_wait = pollrd_hdr->poll_wait;
2668                 while (1) {
2669                         qla8044_rd_reg_indirect(vha, s_addr, &r_value);
2670                         if ((r_value & poll_mask) != 0) {
2671                                 break;
2672                         } else {
2673                                 usleep_range(1000, 1100);
2674                                 if (--poll_wait == 0) {
2675                                         ql_log(ql_log_fatal, vha, 0xb0fe,
2676                                             "%s: TIMEOUT\n", __func__);
2677                                         goto error;
2678                                 }
2679                         }
2680                 }
2681                 qla8044_rd_reg_indirect(vha, r_addr, &r_value);
2682                 *data_ptr++ = s_value;
2683                 *data_ptr++ = r_value;
2684
2685                 s_value += s_stride;
2686         }
2687         *d_ptr = data_ptr;
2688         return QLA_SUCCESS;
2689
2690 error:
2691         return QLA_FUNCTION_FAILED;
2692 }
2693
2694 static void
2695 qla8044_minidump_process_rdmux2(struct scsi_qla_host *vha,
2696         struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
2697 {
2698         uint32_t sel_val1, sel_val2, t_sel_val, data, i;
2699         uint32_t sel_addr1, sel_addr2, sel_val_mask, read_addr;
2700         struct qla8044_minidump_entry_rdmux2 *rdmux2_hdr;
2701         uint32_t *data_ptr = *d_ptr;
2702
2703         rdmux2_hdr = (struct qla8044_minidump_entry_rdmux2 *) entry_hdr;
2704         sel_val1 = rdmux2_hdr->select_value_1;
2705         sel_val2 = rdmux2_hdr->select_value_2;
2706         sel_addr1 = rdmux2_hdr->select_addr_1;
2707         sel_addr2 = rdmux2_hdr->select_addr_2;
2708         sel_val_mask = rdmux2_hdr->select_value_mask;
2709         read_addr = rdmux2_hdr->read_addr;
2710
2711         for (i = 0; i < rdmux2_hdr->op_count; i++) {
2712                 qla8044_wr_reg_indirect(vha, sel_addr1, sel_val1);
2713                 t_sel_val = sel_val1 & sel_val_mask;
2714                 *data_ptr++ = t_sel_val;
2715
2716                 qla8044_wr_reg_indirect(vha, sel_addr2, t_sel_val);
2717                 qla8044_rd_reg_indirect(vha, read_addr, &data);
2718
2719                 *data_ptr++ = data;
2720
2721                 qla8044_wr_reg_indirect(vha, sel_addr1, sel_val2);
2722                 t_sel_val = sel_val2 & sel_val_mask;
2723                 *data_ptr++ = t_sel_val;
2724
2725                 qla8044_wr_reg_indirect(vha, sel_addr2, t_sel_val);
2726                 qla8044_rd_reg_indirect(vha, read_addr, &data);
2727
2728                 *data_ptr++ = data;
2729
2730                 sel_val1 += rdmux2_hdr->select_value_stride;
2731                 sel_val2 += rdmux2_hdr->select_value_stride;
2732         }
2733
2734         *d_ptr = data_ptr;
2735 }
2736
2737 static uint32_t
2738 qla8044_minidump_process_pollrdmwr(struct scsi_qla_host *vha,
2739         struct qla8044_minidump_entry_hdr *entry_hdr,
2740         uint32_t **d_ptr)
2741 {
2742         uint32_t poll_wait, poll_mask, r_value, data;
2743         uint32_t addr_1, addr_2, value_1, value_2;
2744         struct qla8044_minidump_entry_pollrdmwr *poll_hdr;
2745         uint32_t *data_ptr = *d_ptr;
2746
2747         poll_hdr = (struct qla8044_minidump_entry_pollrdmwr *) entry_hdr;
2748         addr_1 = poll_hdr->addr_1;
2749         addr_2 = poll_hdr->addr_2;
2750         value_1 = poll_hdr->value_1;
2751         value_2 = poll_hdr->value_2;
2752         poll_mask = poll_hdr->poll_mask;
2753
2754         qla8044_wr_reg_indirect(vha, addr_1, value_1);
2755
2756         poll_wait = poll_hdr->poll_wait;
2757         while (1) {
2758                 qla8044_rd_reg_indirect(vha, addr_1, &r_value);
2759
2760                 if ((r_value & poll_mask) != 0) {
2761                         break;
2762                 } else {
2763                         usleep_range(1000, 1100);
2764                         if (--poll_wait == 0) {
2765                                 ql_log(ql_log_fatal, vha, 0xb0ff,
2766                                     "%s: TIMEOUT\n", __func__);
2767                                 goto error;
2768                         }
2769                 }
2770         }
2771
2772         qla8044_rd_reg_indirect(vha, addr_2, &data);
2773         data &= poll_hdr->modify_mask;
2774         qla8044_wr_reg_indirect(vha, addr_2, data);
2775         qla8044_wr_reg_indirect(vha, addr_1, value_2);
2776
2777         poll_wait = poll_hdr->poll_wait;
2778         while (1) {
2779                 qla8044_rd_reg_indirect(vha, addr_1, &r_value);
2780
2781                 if ((r_value & poll_mask) != 0) {
2782                         break;
2783                 } else {
2784                         usleep_range(1000, 1100);
2785                         if (--poll_wait == 0) {
2786                                 ql_log(ql_log_fatal, vha, 0xb100,
2787                                     "%s: TIMEOUT2\n", __func__);
2788                                 goto error;
2789                         }
2790                 }
2791         }
2792
2793         *data_ptr++ = addr_2;
2794         *data_ptr++ = data;
2795
2796         *d_ptr = data_ptr;
2797
2798         return QLA_SUCCESS;
2799
2800 error:
2801         return QLA_FUNCTION_FAILED;
2802 }
2803
2804 #define ISP8044_PEX_DMA_ENGINE_INDEX            8
2805 #define ISP8044_PEX_DMA_BASE_ADDRESS            0x77320000
2806 #define ISP8044_PEX_DMA_NUM_OFFSET              0x10000
2807 #define ISP8044_PEX_DMA_CMD_ADDR_LOW            0x0
2808 #define ISP8044_PEX_DMA_CMD_ADDR_HIGH           0x04
2809 #define ISP8044_PEX_DMA_CMD_STS_AND_CNTRL       0x08
2810
2811 #define ISP8044_PEX_DMA_READ_SIZE       (16 * 1024)
2812 #define ISP8044_PEX_DMA_MAX_WAIT        (100 * 100) /* Max wait of 100 msecs */
2813
2814 static int
2815 qla8044_check_dma_engine_state(struct scsi_qla_host *vha)
2816 {
2817         struct qla_hw_data *ha = vha->hw;
2818         int rval = QLA_SUCCESS;
2819         uint32_t dma_eng_num = 0, cmd_sts_and_cntrl = 0;
2820         uint64_t dma_base_addr = 0;
2821         struct qla8044_minidump_template_hdr *tmplt_hdr = NULL;
2822
2823         tmplt_hdr = ha->md_tmplt_hdr;
2824         dma_eng_num =
2825             tmplt_hdr->saved_state_array[ISP8044_PEX_DMA_ENGINE_INDEX];
2826         dma_base_addr = ISP8044_PEX_DMA_BASE_ADDRESS +
2827                 (dma_eng_num * ISP8044_PEX_DMA_NUM_OFFSET);
2828
2829         /* Read the pex-dma's command-status-and-control register. */
2830         rval = qla8044_rd_reg_indirect(vha,
2831             (dma_base_addr + ISP8044_PEX_DMA_CMD_STS_AND_CNTRL),
2832             &cmd_sts_and_cntrl);
2833         if (rval)
2834                 return QLA_FUNCTION_FAILED;
2835
2836         /* Check if requested pex-dma engine is available. */
2837         if (cmd_sts_and_cntrl & BIT_31)
2838                 return QLA_SUCCESS;
2839
2840         return QLA_FUNCTION_FAILED;
2841 }
2842
2843 static int
2844 qla8044_start_pex_dma(struct scsi_qla_host *vha,
2845         struct qla8044_minidump_entry_rdmem_pex_dma *m_hdr)
2846 {
2847         struct qla_hw_data *ha = vha->hw;
2848         int rval = QLA_SUCCESS, wait = 0;
2849         uint32_t dma_eng_num = 0, cmd_sts_and_cntrl = 0;
2850         uint64_t dma_base_addr = 0;
2851         struct qla8044_minidump_template_hdr *tmplt_hdr = NULL;
2852
2853         tmplt_hdr = ha->md_tmplt_hdr;
2854         dma_eng_num =
2855             tmplt_hdr->saved_state_array[ISP8044_PEX_DMA_ENGINE_INDEX];
2856         dma_base_addr = ISP8044_PEX_DMA_BASE_ADDRESS +
2857                 (dma_eng_num * ISP8044_PEX_DMA_NUM_OFFSET);
2858
2859         rval = qla8044_wr_reg_indirect(vha,
2860             dma_base_addr + ISP8044_PEX_DMA_CMD_ADDR_LOW,
2861             m_hdr->desc_card_addr);
2862         if (rval)
2863                 goto error_exit;
2864
2865         rval = qla8044_wr_reg_indirect(vha,
2866             dma_base_addr + ISP8044_PEX_DMA_CMD_ADDR_HIGH, 0);
2867         if (rval)
2868                 goto error_exit;
2869
2870         rval = qla8044_wr_reg_indirect(vha,
2871             dma_base_addr + ISP8044_PEX_DMA_CMD_STS_AND_CNTRL,
2872             m_hdr->start_dma_cmd);
2873         if (rval)
2874                 goto error_exit;
2875
2876         /* Wait for dma operation to complete. */
2877         for (wait = 0; wait < ISP8044_PEX_DMA_MAX_WAIT; wait++) {
2878                 rval = qla8044_rd_reg_indirect(vha,
2879                     (dma_base_addr + ISP8044_PEX_DMA_CMD_STS_AND_CNTRL),
2880                     &cmd_sts_and_cntrl);
2881                 if (rval)
2882                         goto error_exit;
2883
2884                 if ((cmd_sts_and_cntrl & BIT_1) == 0)
2885                         break;
2886
2887                 udelay(10);
2888         }
2889
2890         /* Wait a max of 100 ms, otherwise fallback to rdmem entry read */
2891         if (wait >= ISP8044_PEX_DMA_MAX_WAIT) {
2892                 rval = QLA_FUNCTION_FAILED;
2893                 goto error_exit;
2894         }
2895
2896 error_exit:
2897         return rval;
2898 }
2899
2900 static int
2901 qla8044_minidump_pex_dma_read(struct scsi_qla_host *vha,
2902         struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
2903 {
2904         struct qla_hw_data *ha = vha->hw;
2905         int rval = QLA_SUCCESS;
2906         struct qla8044_minidump_entry_rdmem_pex_dma *m_hdr = NULL;
2907         uint32_t chunk_size, read_size;
2908         uint8_t *data_ptr = (uint8_t *)*d_ptr;
2909         void *rdmem_buffer = NULL;
2910         dma_addr_t rdmem_dma;
2911         struct qla8044_pex_dma_descriptor dma_desc;
2912
2913         rval = qla8044_check_dma_engine_state(vha);
2914         if (rval != QLA_SUCCESS) {
2915                 ql_dbg(ql_dbg_p3p, vha, 0xb147,
2916                     "DMA engine not available. Fallback to rdmem-read.\n");
2917                 return QLA_FUNCTION_FAILED;
2918         }
2919
2920         m_hdr = (void *)entry_hdr;
2921
2922         rdmem_buffer = dma_alloc_coherent(&ha->pdev->dev,
2923             ISP8044_PEX_DMA_READ_SIZE, &rdmem_dma, GFP_KERNEL);
2924         if (!rdmem_buffer) {
2925                 ql_dbg(ql_dbg_p3p, vha, 0xb148,
2926                     "Unable to allocate rdmem dma buffer\n");
2927                 return QLA_FUNCTION_FAILED;
2928         }
2929
2930         /* Prepare pex-dma descriptor to be written to MS memory. */
2931         /* dma-desc-cmd layout:
2932          *              0-3: dma-desc-cmd 0-3
2933          *              4-7: pcid function number
2934          *              8-15: dma-desc-cmd 8-15
2935          * dma_bus_addr: dma buffer address
2936          * cmd.read_data_size: amount of data-chunk to be read.
2937          */
2938         dma_desc.cmd.dma_desc_cmd = (m_hdr->dma_desc_cmd & 0xff0f);
2939         dma_desc.cmd.dma_desc_cmd |=
2940             ((PCI_FUNC(ha->pdev->devfn) & 0xf) << 0x4);
2941
2942         dma_desc.dma_bus_addr = rdmem_dma;
2943         dma_desc.cmd.read_data_size = chunk_size = ISP8044_PEX_DMA_READ_SIZE;
2944         read_size = 0;
2945
2946         /*
2947          * Perform rdmem operation using pex-dma.
2948          * Prepare dma in chunks of ISP8044_PEX_DMA_READ_SIZE.
2949          */
2950         while (read_size < m_hdr->read_data_size) {
2951                 if (m_hdr->read_data_size - read_size <
2952                     ISP8044_PEX_DMA_READ_SIZE) {
2953                         chunk_size = (m_hdr->read_data_size - read_size);
2954                         dma_desc.cmd.read_data_size = chunk_size;
2955                 }
2956
2957                 dma_desc.src_addr = m_hdr->read_addr + read_size;
2958
2959                 /* Prepare: Write pex-dma descriptor to MS memory. */
2960                 rval = qla8044_ms_mem_write_128b(vha,
2961                     m_hdr->desc_card_addr, (void *)&dma_desc,
2962                     (sizeof(struct qla8044_pex_dma_descriptor)/16));
2963                 if (rval) {
2964                         ql_log(ql_log_warn, vha, 0xb14a,
2965                             "%s: Error writing rdmem-dma-init to MS !!!\n",
2966                             __func__);
2967                         goto error_exit;
2968                 }
2969                 ql_dbg(ql_dbg_p3p, vha, 0xb14b,
2970                     "%s: Dma-descriptor: Instruct for rdmem dma "
2971                     "(chunk_size 0x%x).\n", __func__, chunk_size);
2972
2973                 /* Execute: Start pex-dma operation. */
2974                 rval = qla8044_start_pex_dma(vha, m_hdr);
2975                 if (rval)
2976                         goto error_exit;
2977
2978                 memcpy(data_ptr, rdmem_buffer, chunk_size);
2979                 data_ptr += chunk_size;
2980                 read_size += chunk_size;
2981         }
2982
2983         *d_ptr = (void *)data_ptr;
2984
2985 error_exit:
2986         if (rdmem_buffer)
2987                 dma_free_coherent(&ha->pdev->dev, ISP8044_PEX_DMA_READ_SIZE,
2988                     rdmem_buffer, rdmem_dma);
2989
2990         return rval;
2991 }
2992
2993 static uint32_t
2994 qla8044_minidump_process_rddfe(struct scsi_qla_host *vha,
2995         struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
2996 {
2997         int loop_cnt;
2998         uint32_t addr1, addr2, value, data, temp, wrVal;
2999         uint8_t stride, stride2;
3000         uint16_t count;
3001         uint32_t poll, mask, data_size, modify_mask;
3002         uint32_t wait_count = 0;
3003
3004         uint32_t *data_ptr = *d_ptr;
3005
3006         struct qla8044_minidump_entry_rddfe *rddfe;
3007         rddfe = (struct qla8044_minidump_entry_rddfe *) entry_hdr;
3008
3009         addr1 = rddfe->addr_1;
3010         value = rddfe->value;
3011         stride = rddfe->stride;
3012         stride2 = rddfe->stride2;
3013         count = rddfe->count;
3014
3015         poll = rddfe->poll;
3016         mask = rddfe->mask;
3017         modify_mask = rddfe->modify_mask;
3018         data_size = rddfe->data_size;
3019
3020         addr2 = addr1 + stride;
3021
3022         for (loop_cnt = 0x0; loop_cnt < count; loop_cnt++) {
3023                 qla8044_wr_reg_indirect(vha, addr1, (0x40000000 | value));
3024
3025                 wait_count = 0;
3026                 while (wait_count < poll) {
3027                         qla8044_rd_reg_indirect(vha, addr1, &temp);
3028                         if ((temp & mask) != 0)
3029                                 break;
3030                         wait_count++;
3031                 }
3032
3033                 if (wait_count == poll) {
3034                         ql_log(ql_log_warn, vha, 0xb153,
3035                             "%s: TIMEOUT\n", __func__);
3036                         goto error;
3037                 } else {
3038                         qla8044_rd_reg_indirect(vha, addr2, &temp);
3039                         temp = temp & modify_mask;
3040                         temp = (temp | ((loop_cnt << 16) | loop_cnt));
3041                         wrVal = ((temp << 16) | temp);
3042
3043                         qla8044_wr_reg_indirect(vha, addr2, wrVal);
3044                         qla8044_wr_reg_indirect(vha, addr1, value);
3045
3046                         wait_count = 0;
3047                         while (wait_count < poll) {
3048                                 qla8044_rd_reg_indirect(vha, addr1, &temp);
3049                                 if ((temp & mask) != 0)
3050                                         break;
3051                                 wait_count++;
3052                         }
3053                         if (wait_count == poll) {
3054                                 ql_log(ql_log_warn, vha, 0xb154,
3055                                     "%s: TIMEOUT\n", __func__);
3056                                 goto error;
3057                         }
3058
3059                         qla8044_wr_reg_indirect(vha, addr1,
3060                             ((0x40000000 | value) + stride2));
3061                         wait_count = 0;
3062                         while (wait_count < poll) {
3063                                 qla8044_rd_reg_indirect(vha, addr1, &temp);
3064                                 if ((temp & mask) != 0)
3065                                         break;
3066                                 wait_count++;
3067                         }
3068
3069                         if (wait_count == poll) {
3070                                 ql_log(ql_log_warn, vha, 0xb155,
3071                                     "%s: TIMEOUT\n", __func__);
3072                                 goto error;
3073                         }
3074
3075                         qla8044_rd_reg_indirect(vha, addr2, &data);
3076
3077                         *data_ptr++ = wrVal;
3078                         *data_ptr++ = data;
3079                 }
3080
3081         }
3082
3083         *d_ptr = data_ptr;
3084         return QLA_SUCCESS;
3085
3086 error:
3087         return -1;
3088
3089 }
3090
3091 static uint32_t
3092 qla8044_minidump_process_rdmdio(struct scsi_qla_host *vha,
3093         struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
3094 {
3095         int ret = 0;
3096         uint32_t addr1, addr2, value1, value2, data, selVal;
3097         uint8_t stride1, stride2;
3098         uint32_t addr3, addr4, addr5, addr6, addr7;
3099         uint16_t count, loop_cnt;
3100         uint32_t poll, mask;
3101         uint32_t *data_ptr = *d_ptr;
3102
3103         struct qla8044_minidump_entry_rdmdio *rdmdio;
3104
3105         rdmdio = (struct qla8044_minidump_entry_rdmdio *) entry_hdr;
3106
3107         addr1 = rdmdio->addr_1;
3108         addr2 = rdmdio->addr_2;
3109         value1 = rdmdio->value_1;
3110         stride1 = rdmdio->stride_1;
3111         stride2 = rdmdio->stride_2;
3112         count = rdmdio->count;
3113
3114         poll = rdmdio->poll;
3115         mask = rdmdio->mask;
3116         value2 = rdmdio->value_2;
3117
3118         addr3 = addr1 + stride1;
3119
3120         for (loop_cnt = 0; loop_cnt < count; loop_cnt++) {
3121                 ret = qla8044_poll_wait_ipmdio_bus_idle(vha, addr1, addr2,
3122                     addr3, mask);
3123                 if (ret == -1)
3124                         goto error;
3125
3126                 addr4 = addr2 - stride1;
3127                 ret = qla8044_ipmdio_wr_reg(vha, addr1, addr3, mask, addr4,
3128                     value2);
3129                 if (ret == -1)
3130                         goto error;
3131
3132                 addr5 = addr2 - (2 * stride1);
3133                 ret = qla8044_ipmdio_wr_reg(vha, addr1, addr3, mask, addr5,
3134                     value1);
3135                 if (ret == -1)
3136                         goto error;
3137
3138                 addr6 = addr2 - (3 * stride1);
3139                 ret = qla8044_ipmdio_wr_reg(vha, addr1, addr3, mask,
3140                     addr6, 0x2);
3141                 if (ret == -1)
3142                         goto error;
3143
3144                 ret = qla8044_poll_wait_ipmdio_bus_idle(vha, addr1, addr2,
3145                     addr3, mask);
3146                 if (ret == -1)
3147                         goto error;
3148
3149                 addr7 = addr2 - (4 * stride1);
3150                         data = qla8044_ipmdio_rd_reg(vha, addr1, addr3,
3151                             mask, addr7);
3152                 if (data == -1)
3153                         goto error;
3154
3155                 selVal = (value2 << 18) | (value1 << 2) | 2;
3156
3157                 stride2 = rdmdio->stride_2;
3158                 *data_ptr++ = selVal;
3159                 *data_ptr++ = data;
3160
3161                 value1 = value1 + stride2;
3162                 *d_ptr = data_ptr;
3163         }
3164
3165         return 0;
3166
3167 error:
3168         return -1;
3169 }
3170
3171 static uint32_t qla8044_minidump_process_pollwr(struct scsi_qla_host *vha,
3172                 struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
3173 {
3174         uint32_t addr1, addr2, value1, value2, poll, mask, r_value;
3175         uint32_t wait_count = 0;
3176         struct qla8044_minidump_entry_pollwr *pollwr_hdr;
3177
3178         pollwr_hdr = (struct qla8044_minidump_entry_pollwr *)entry_hdr;
3179         addr1 = pollwr_hdr->addr_1;
3180         addr2 = pollwr_hdr->addr_2;
3181         value1 = pollwr_hdr->value_1;
3182         value2 = pollwr_hdr->value_2;
3183
3184         poll = pollwr_hdr->poll;
3185         mask = pollwr_hdr->mask;
3186
3187         while (wait_count < poll) {
3188                 qla8044_rd_reg_indirect(vha, addr1, &r_value);
3189
3190                 if ((r_value & poll) != 0)
3191                         break;
3192                 wait_count++;
3193         }
3194
3195         if (wait_count == poll) {
3196                 ql_log(ql_log_warn, vha, 0xb156, "%s: TIMEOUT\n", __func__);
3197                 goto error;
3198         }
3199
3200         qla8044_wr_reg_indirect(vha, addr2, value2);
3201         qla8044_wr_reg_indirect(vha, addr1, value1);
3202
3203         wait_count = 0;
3204         while (wait_count < poll) {
3205                 qla8044_rd_reg_indirect(vha, addr1, &r_value);
3206
3207                 if ((r_value & poll) != 0)
3208                         break;
3209                 wait_count++;
3210         }
3211
3212         return QLA_SUCCESS;
3213
3214 error:
3215         return -1;
3216 }
3217
3218 /*
3219  *
3220  * qla8044_collect_md_data - Retrieve firmware minidump data.
3221  * @ha: pointer to adapter structure
3222  **/
3223 int
3224 qla8044_collect_md_data(struct scsi_qla_host *vha)
3225 {
3226         int num_entry_hdr = 0;
3227         struct qla8044_minidump_entry_hdr *entry_hdr;
3228         struct qla8044_minidump_template_hdr *tmplt_hdr;
3229         uint32_t *data_ptr;
3230         uint32_t data_collected = 0, f_capture_mask;
3231         int i, rval = QLA_FUNCTION_FAILED;
3232         uint64_t now;
3233         uint32_t timestamp, idc_control;
3234         struct qla_hw_data *ha = vha->hw;
3235
3236         if (!ha->md_dump) {
3237                 ql_log(ql_log_info, vha, 0xb101,
3238                     "%s(%ld) No buffer to dump\n",
3239                     __func__, vha->host_no);
3240                 return rval;
3241         }
3242
3243         if (ha->fw_dumped) {
3244                 ql_log(ql_log_warn, vha, 0xb10d,
3245                     "Firmware has been previously dumped (%p) "
3246                     "-- ignoring request.\n", ha->fw_dump);
3247                 goto md_failed;
3248         }
3249
3250         ha->fw_dumped = 0;
3251
3252         if (!ha->md_tmplt_hdr || !ha->md_dump) {
3253                 ql_log(ql_log_warn, vha, 0xb10e,
3254                     "Memory not allocated for minidump capture\n");
3255                 goto md_failed;
3256         }
3257
3258         qla8044_idc_lock(ha);
3259         idc_control = qla8044_rd_reg(ha, QLA8044_IDC_DRV_CTRL);
3260         if (idc_control & GRACEFUL_RESET_BIT1) {
3261                 ql_log(ql_log_warn, vha, 0xb112,
3262                     "Forced reset from application, "
3263                     "ignore minidump capture\n");
3264                 qla8044_wr_reg(ha, QLA8044_IDC_DRV_CTRL,
3265                     (idc_control & ~GRACEFUL_RESET_BIT1));
3266                 qla8044_idc_unlock(ha);
3267
3268                 goto md_failed;
3269         }
3270         qla8044_idc_unlock(ha);
3271
3272         if (qla82xx_validate_template_chksum(vha)) {
3273                 ql_log(ql_log_info, vha, 0xb109,
3274                     "Template checksum validation error\n");
3275                 goto md_failed;
3276         }
3277
3278         tmplt_hdr = (struct qla8044_minidump_template_hdr *)
3279                 ha->md_tmplt_hdr;
3280         data_ptr = (uint32_t *)((uint8_t *)ha->md_dump);
3281         num_entry_hdr = tmplt_hdr->num_of_entries;
3282
3283         ql_dbg(ql_dbg_p3p, vha, 0xb11a,
3284             "Capture Mask obtained: 0x%x\n", tmplt_hdr->capture_debug_level);
3285
3286         f_capture_mask = tmplt_hdr->capture_debug_level & 0xFF;
3287
3288         /* Validate whether required debug level is set */
3289         if ((f_capture_mask & 0x3) != 0x3) {
3290                 ql_log(ql_log_warn, vha, 0xb10f,
3291                     "Minimum required capture mask[0x%x] level not set\n",
3292                     f_capture_mask);
3293
3294         }
3295         tmplt_hdr->driver_capture_mask = ql2xmdcapmask;
3296         ql_log(ql_log_info, vha, 0xb102,
3297             "[%s]: starting data ptr: %p\n",
3298            __func__, data_ptr);
3299         ql_log(ql_log_info, vha, 0xb10b,
3300            "[%s]: no of entry headers in Template: 0x%x\n",
3301            __func__, num_entry_hdr);
3302         ql_log(ql_log_info, vha, 0xb10c,
3303             "[%s]: Total_data_size 0x%x, %d obtained\n",
3304            __func__, ha->md_dump_size, ha->md_dump_size);
3305
3306         /* Update current timestamp before taking dump */
3307         now = get_jiffies_64();
3308         timestamp = (u32)(jiffies_to_msecs(now) / 1000);
3309         tmplt_hdr->driver_timestamp = timestamp;
3310
3311         entry_hdr = (struct qla8044_minidump_entry_hdr *)
3312                 (((uint8_t *)ha->md_tmplt_hdr) + tmplt_hdr->first_entry_offset);
3313         tmplt_hdr->saved_state_array[QLA8044_SS_OCM_WNDREG_INDEX] =
3314             tmplt_hdr->ocm_window_reg[ha->portnum];
3315
3316         /* Walk through the entry headers - validate/perform required action */
3317         for (i = 0; i < num_entry_hdr; i++) {
3318                 if (data_collected > ha->md_dump_size) {
3319                         ql_log(ql_log_info, vha, 0xb103,
3320                             "Data collected: [0x%x], "
3321                             "Total Dump size: [0x%x]\n",
3322                             data_collected, ha->md_dump_size);
3323                         return rval;
3324                 }
3325
3326                 if (!(entry_hdr->d_ctrl.entry_capture_mask &
3327                       ql2xmdcapmask)) {
3328                         entry_hdr->d_ctrl.driver_flags |=
3329                             QLA82XX_DBG_SKIPPED_FLAG;
3330                         goto skip_nxt_entry;
3331                 }
3332
3333                 ql_dbg(ql_dbg_p3p, vha, 0xb104,
3334                     "Data collected: [0x%x], Dump size left:[0x%x]\n",
3335                     data_collected,
3336                     (ha->md_dump_size - data_collected));
3337
3338                 /* Decode the entry type and take required action to capture
3339                  * debug data
3340                  */
3341                 switch (entry_hdr->entry_type) {
3342                 case QLA82XX_RDEND:
3343                         qla8044_mark_entry_skipped(vha, entry_hdr, i);
3344                         break;
3345                 case QLA82XX_CNTRL:
3346                         rval = qla8044_minidump_process_control(vha,
3347                             entry_hdr);
3348                         if (rval != QLA_SUCCESS) {
3349                                 qla8044_mark_entry_skipped(vha, entry_hdr, i);
3350                                 goto md_failed;
3351                         }
3352                         break;
3353                 case QLA82XX_RDCRB:
3354                         qla8044_minidump_process_rdcrb(vha,
3355                             entry_hdr, &data_ptr);
3356                         break;
3357                 case QLA82XX_RDMEM:
3358                         rval = qla8044_minidump_pex_dma_read(vha,
3359                             entry_hdr, &data_ptr);
3360                         if (rval != QLA_SUCCESS) {
3361                                 rval = qla8044_minidump_process_rdmem(vha,
3362                                     entry_hdr, &data_ptr);
3363                                 if (rval != QLA_SUCCESS) {
3364                                         qla8044_mark_entry_skipped(vha,
3365                                             entry_hdr, i);
3366                                         goto md_failed;
3367                                 }
3368                         }
3369                         break;
3370                 case QLA82XX_BOARD:
3371                 case QLA82XX_RDROM:
3372                         rval = qla8044_minidump_process_rdrom(vha,
3373                             entry_hdr, &data_ptr);
3374                         if (rval != QLA_SUCCESS) {
3375                                 qla8044_mark_entry_skipped(vha,
3376                                     entry_hdr, i);
3377                         }
3378                         break;
3379                 case QLA82XX_L2DTG:
3380                 case QLA82XX_L2ITG:
3381                 case QLA82XX_L2DAT:
3382                 case QLA82XX_L2INS:
3383                         rval = qla8044_minidump_process_l2tag(vha,
3384                             entry_hdr, &data_ptr);
3385                         if (rval != QLA_SUCCESS) {
3386                                 qla8044_mark_entry_skipped(vha, entry_hdr, i);
3387                                 goto md_failed;
3388                         }
3389                         break;
3390                 case QLA8044_L1DTG:
3391                 case QLA8044_L1ITG:
3392                 case QLA82XX_L1DAT:
3393                 case QLA82XX_L1INS:
3394                         qla8044_minidump_process_l1cache(vha,
3395                             entry_hdr, &data_ptr);
3396                         break;
3397                 case QLA82XX_RDOCM:
3398                         qla8044_minidump_process_rdocm(vha,
3399                             entry_hdr, &data_ptr);
3400                         break;
3401                 case QLA82XX_RDMUX:
3402                         qla8044_minidump_process_rdmux(vha,
3403                             entry_hdr, &data_ptr);
3404                         break;
3405                 case QLA82XX_QUEUE:
3406                         qla8044_minidump_process_queue(vha,
3407                             entry_hdr, &data_ptr);
3408                         break;
3409                 case QLA8044_POLLRD:
3410                         rval = qla8044_minidump_process_pollrd(vha,
3411                             entry_hdr, &data_ptr);
3412                         if (rval != QLA_SUCCESS)
3413                                 qla8044_mark_entry_skipped(vha, entry_hdr, i);
3414                         break;
3415                 case QLA8044_RDMUX2:
3416                         qla8044_minidump_process_rdmux2(vha,
3417                             entry_hdr, &data_ptr);
3418                         break;
3419                 case QLA8044_POLLRDMWR:
3420                         rval = qla8044_minidump_process_pollrdmwr(vha,
3421                             entry_hdr, &data_ptr);
3422                         if (rval != QLA_SUCCESS)
3423                                 qla8044_mark_entry_skipped(vha, entry_hdr, i);
3424                         break;
3425                 case QLA8044_RDDFE:
3426                         rval = qla8044_minidump_process_rddfe(vha, entry_hdr,
3427                             &data_ptr);
3428                         if (rval != QLA_SUCCESS)
3429                                 qla8044_mark_entry_skipped(vha, entry_hdr, i);
3430                         break;
3431                 case QLA8044_RDMDIO:
3432                         rval = qla8044_minidump_process_rdmdio(vha, entry_hdr,
3433                             &data_ptr);
3434                         if (rval != QLA_SUCCESS)
3435                                 qla8044_mark_entry_skipped(vha, entry_hdr, i);
3436                         break;
3437                 case QLA8044_POLLWR:
3438                         rval = qla8044_minidump_process_pollwr(vha, entry_hdr,
3439                             &data_ptr);
3440                         if (rval != QLA_SUCCESS)
3441                                 qla8044_mark_entry_skipped(vha, entry_hdr, i);
3442                         break;
3443                 case QLA82XX_RDNOP:
3444                 default:
3445                         qla8044_mark_entry_skipped(vha, entry_hdr, i);
3446                         break;
3447                 }
3448
3449                 data_collected = (uint8_t *)data_ptr -
3450                     (uint8_t *)((uint8_t *)ha->md_dump);
3451 skip_nxt_entry:
3452                 /*
3453                  * next entry in the template
3454                  */
3455                 entry_hdr = (struct qla8044_minidump_entry_hdr *)
3456                     (((uint8_t *)entry_hdr) + entry_hdr->entry_size);
3457         }
3458
3459         if (data_collected != ha->md_dump_size) {
3460                 ql_log(ql_log_info, vha, 0xb105,
3461                     "Dump data mismatch: Data collected: "
3462                     "[0x%x], total_data_size:[0x%x]\n",
3463                     data_collected, ha->md_dump_size);
3464                 rval = QLA_FUNCTION_FAILED;
3465                 goto md_failed;
3466         }
3467
3468         ql_log(ql_log_info, vha, 0xb110,
3469             "Firmware dump saved to temp buffer (%ld/%p %ld/%p).\n",
3470             vha->host_no, ha->md_tmplt_hdr, vha->host_no, ha->md_dump);
3471         ha->fw_dumped = 1;
3472         qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP);
3473
3474
3475         ql_log(ql_log_info, vha, 0xb106,
3476             "Leaving fn: %s Last entry: 0x%x\n",
3477             __func__, i);
3478 md_failed:
3479         return rval;
3480 }
3481
3482 void
3483 qla8044_get_minidump(struct scsi_qla_host *vha)
3484 {
3485         struct qla_hw_data *ha = vha->hw;
3486
3487         if (!qla8044_collect_md_data(vha)) {
3488                 ha->fw_dumped = 1;
3489                 ha->prev_minidump_failed = 0;
3490         } else {
3491                 ql_log(ql_log_fatal, vha, 0xb0db,
3492                     "%s: Unable to collect minidump\n",
3493                     __func__);
3494                 ha->prev_minidump_failed = 1;
3495         }
3496 }
3497
3498 static int
3499 qla8044_poll_flash_status_reg(struct scsi_qla_host *vha)
3500 {
3501         uint32_t flash_status;
3502         int retries = QLA8044_FLASH_READ_RETRY_COUNT;
3503         int ret_val = QLA_SUCCESS;
3504
3505         while (retries--) {
3506                 ret_val = qla8044_rd_reg_indirect(vha, QLA8044_FLASH_STATUS,
3507                     &flash_status);
3508                 if (ret_val) {
3509                         ql_log(ql_log_warn, vha, 0xb13c,
3510                             "%s: Failed to read FLASH_STATUS reg.\n",
3511                             __func__);
3512                         break;
3513                 }
3514                 if ((flash_status & QLA8044_FLASH_STATUS_READY) ==
3515                     QLA8044_FLASH_STATUS_READY)
3516                         break;
3517                 msleep(QLA8044_FLASH_STATUS_REG_POLL_DELAY);
3518         }
3519
3520         if (!retries)
3521                 ret_val = QLA_FUNCTION_FAILED;
3522
3523         return ret_val;
3524 }
3525
3526 static int
3527 qla8044_write_flash_status_reg(struct scsi_qla_host *vha,
3528                                uint32_t data)
3529 {
3530         int ret_val = QLA_SUCCESS;
3531         uint32_t cmd;
3532
3533         cmd = vha->hw->fdt_wrt_sts_reg_cmd;
3534
3535         ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR,
3536             QLA8044_FLASH_STATUS_WRITE_DEF_SIG | cmd);
3537         if (ret_val) {
3538                 ql_log(ql_log_warn, vha, 0xb125,
3539                     "%s: Failed to write to FLASH_ADDR.\n", __func__);
3540                 goto exit_func;
3541         }
3542
3543         ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_WRDATA, data);
3544         if (ret_val) {
3545                 ql_log(ql_log_warn, vha, 0xb126,
3546                     "%s: Failed to write to FLASH_WRDATA.\n", __func__);
3547                 goto exit_func;
3548         }
3549
3550         ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL,
3551             QLA8044_FLASH_SECOND_ERASE_MS_VAL);
3552         if (ret_val) {
3553                 ql_log(ql_log_warn, vha, 0xb127,
3554                     "%s: Failed to write to FLASH_CONTROL.\n", __func__);
3555                 goto exit_func;
3556         }
3557
3558         ret_val = qla8044_poll_flash_status_reg(vha);
3559         if (ret_val)
3560                 ql_log(ql_log_warn, vha, 0xb128,
3561                     "%s: Error polling flash status reg.\n", __func__);
3562
3563 exit_func:
3564         return ret_val;
3565 }
3566
3567 /*
3568  * This function assumes that the flash lock is held.
3569  */
3570 static int
3571 qla8044_unprotect_flash(scsi_qla_host_t *vha)
3572 {
3573         int ret_val;
3574         struct qla_hw_data *ha = vha->hw;
3575
3576         ret_val = qla8044_write_flash_status_reg(vha, ha->fdt_wrt_enable);
3577         if (ret_val)
3578                 ql_log(ql_log_warn, vha, 0xb139,
3579                     "%s: Write flash status failed.\n", __func__);
3580
3581         return ret_val;
3582 }
3583
3584 /*
3585  * This function assumes that the flash lock is held.
3586  */
3587 static int
3588 qla8044_protect_flash(scsi_qla_host_t *vha)
3589 {
3590         int ret_val;
3591         struct qla_hw_data *ha = vha->hw;
3592
3593         ret_val = qla8044_write_flash_status_reg(vha, ha->fdt_wrt_disable);
3594         if (ret_val)
3595                 ql_log(ql_log_warn, vha, 0xb13b,
3596                     "%s: Write flash status failed.\n", __func__);
3597
3598         return ret_val;
3599 }
3600
3601
3602 static int
3603 qla8044_erase_flash_sector(struct scsi_qla_host *vha,
3604                            uint32_t sector_start_addr)
3605 {
3606         uint32_t reversed_addr;
3607         int ret_val = QLA_SUCCESS;
3608
3609         ret_val = qla8044_poll_flash_status_reg(vha);
3610         if (ret_val) {
3611                 ql_log(ql_log_warn, vha, 0xb12e,
3612                     "%s: Poll flash status after erase failed..\n", __func__);
3613         }
3614
3615         reversed_addr = (((sector_start_addr & 0xFF) << 16) |
3616             (sector_start_addr & 0xFF00) |
3617             ((sector_start_addr & 0xFF0000) >> 16));
3618
3619         ret_val = qla8044_wr_reg_indirect(vha,
3620             QLA8044_FLASH_WRDATA, reversed_addr);
3621         if (ret_val) {
3622                 ql_log(ql_log_warn, vha, 0xb12f,
3623                     "%s: Failed to write to FLASH_WRDATA.\n", __func__);
3624         }
3625         ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR,
3626            QLA8044_FLASH_ERASE_SIG | vha->hw->fdt_erase_cmd);
3627         if (ret_val) {
3628                 ql_log(ql_log_warn, vha, 0xb130,
3629                     "%s: Failed to write to FLASH_ADDR.\n", __func__);
3630         }
3631         ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL,
3632             QLA8044_FLASH_LAST_ERASE_MS_VAL);
3633         if (ret_val) {
3634                 ql_log(ql_log_warn, vha, 0xb131,
3635                     "%s: Failed write to FLASH_CONTROL.\n", __func__);
3636         }
3637         ret_val = qla8044_poll_flash_status_reg(vha);
3638         if (ret_val) {
3639                 ql_log(ql_log_warn, vha, 0xb132,
3640                     "%s: Poll flash status failed.\n", __func__);
3641         }
3642
3643
3644         return ret_val;
3645 }
3646
3647 /*
3648  * qla8044_flash_write_u32 - Write data to flash
3649  *
3650  * @ha : Pointer to adapter structure
3651  * addr : Flash address to write to
3652  * p_data : Data to be written
3653  *
3654  * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED
3655  *
3656  * NOTE: Lock should be held on entry
3657  */
3658 static int
3659 qla8044_flash_write_u32(struct scsi_qla_host *vha, uint32_t addr,
3660                         uint32_t *p_data)
3661 {
3662         int ret_val = QLA_SUCCESS;
3663
3664         ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR,
3665             0x00800000 | (addr >> 2));
3666         if (ret_val) {
3667                 ql_log(ql_log_warn, vha, 0xb134,
3668                     "%s: Failed write to FLASH_ADDR.\n", __func__);
3669                 goto exit_func;
3670         }
3671         ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_WRDATA, *p_data);
3672         if (ret_val) {
3673                 ql_log(ql_log_warn, vha, 0xb135,
3674                     "%s: Failed write to FLASH_WRDATA.\n", __func__);
3675                 goto exit_func;
3676         }
3677         ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL, 0x3D);
3678         if (ret_val) {
3679                 ql_log(ql_log_warn, vha, 0xb136,
3680                     "%s: Failed write to FLASH_CONTROL.\n", __func__);
3681                 goto exit_func;
3682         }
3683         ret_val = qla8044_poll_flash_status_reg(vha);
3684         if (ret_val) {
3685                 ql_log(ql_log_warn, vha, 0xb137,
3686                     "%s: Poll flash status failed.\n", __func__);
3687         }
3688
3689 exit_func:
3690         return ret_val;
3691 }
3692
3693 static int
3694 qla8044_write_flash_buffer_mode(scsi_qla_host_t *vha, uint32_t *dwptr,
3695                                 uint32_t faddr, uint32_t dwords)
3696 {
3697         int ret = QLA_FUNCTION_FAILED;
3698         uint32_t spi_val;
3699
3700         if (dwords < QLA8044_MIN_OPTROM_BURST_DWORDS ||
3701             dwords > QLA8044_MAX_OPTROM_BURST_DWORDS) {
3702                 ql_dbg(ql_dbg_user, vha, 0xb123,
3703                     "Got unsupported dwords = 0x%x.\n",
3704                     dwords);
3705                 return QLA_FUNCTION_FAILED;
3706         }
3707
3708         qla8044_rd_reg_indirect(vha, QLA8044_FLASH_SPI_CONTROL, &spi_val);
3709         qla8044_wr_reg_indirect(vha, QLA8044_FLASH_SPI_CONTROL,
3710             spi_val | QLA8044_FLASH_SPI_CTL);
3711         qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR,
3712             QLA8044_FLASH_FIRST_TEMP_VAL);
3713
3714         /* First DWORD write to FLASH_WRDATA */
3715         ret = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_WRDATA,
3716             *dwptr++);
3717         qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL,
3718             QLA8044_FLASH_FIRST_MS_PATTERN);
3719
3720         ret = qla8044_poll_flash_status_reg(vha);
3721         if (ret) {
3722                 ql_log(ql_log_warn, vha, 0xb124,
3723                     "%s: Failed.\n", __func__);
3724                 goto exit_func;
3725         }
3726
3727         dwords--;
3728
3729         qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR,
3730             QLA8044_FLASH_SECOND_TEMP_VAL);
3731
3732
3733         /* Second to N-1 DWORDS writes */
3734         while (dwords != 1) {
3735                 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_WRDATA, *dwptr++);
3736                 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL,
3737                     QLA8044_FLASH_SECOND_MS_PATTERN);
3738                 ret = qla8044_poll_flash_status_reg(vha);
3739                 if (ret) {
3740                         ql_log(ql_log_warn, vha, 0xb129,
3741                             "%s: Failed.\n", __func__);
3742                         goto exit_func;
3743                 }
3744                 dwords--;
3745         }
3746
3747         qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR,
3748             QLA8044_FLASH_FIRST_TEMP_VAL | (faddr >> 2));
3749
3750         /* Last DWORD write */
3751         qla8044_wr_reg_indirect(vha, QLA8044_FLASH_WRDATA, *dwptr++);
3752         qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL,
3753             QLA8044_FLASH_LAST_MS_PATTERN);
3754         ret = qla8044_poll_flash_status_reg(vha);
3755         if (ret) {
3756                 ql_log(ql_log_warn, vha, 0xb12a,
3757                     "%s: Failed.\n", __func__);
3758                 goto exit_func;
3759         }
3760         qla8044_rd_reg_indirect(vha, QLA8044_FLASH_SPI_STATUS, &spi_val);
3761
3762         if ((spi_val & QLA8044_FLASH_SPI_CTL) == QLA8044_FLASH_SPI_CTL) {
3763                 ql_log(ql_log_warn, vha, 0xb12b,
3764                     "%s: Failed.\n", __func__);
3765                 spi_val = 0;
3766                 /* Operation failed, clear error bit. */
3767                 qla8044_rd_reg_indirect(vha, QLA8044_FLASH_SPI_CONTROL,
3768                     &spi_val);
3769                 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_SPI_CONTROL,
3770                     spi_val | QLA8044_FLASH_SPI_CTL);
3771         }
3772 exit_func:
3773         return ret;
3774 }
3775
3776 static int
3777 qla8044_write_flash_dword_mode(scsi_qla_host_t *vha, uint32_t *dwptr,
3778                                uint32_t faddr, uint32_t dwords)
3779 {
3780         int ret = QLA_FUNCTION_FAILED;
3781         uint32_t liter;
3782
3783         for (liter = 0; liter < dwords; liter++, faddr += 4, dwptr++) {
3784                 ret = qla8044_flash_write_u32(vha, faddr, dwptr);
3785                 if (ret) {
3786                         ql_dbg(ql_dbg_p3p, vha, 0xb141,
3787                             "%s: flash address=%x data=%x.\n", __func__,
3788                              faddr, *dwptr);
3789                         break;
3790                 }
3791         }
3792
3793         return ret;
3794 }
3795
3796 int
3797 qla8044_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
3798                           uint32_t offset, uint32_t length)
3799 {
3800         int rval = QLA_FUNCTION_FAILED, i, burst_iter_count;
3801         int dword_count, erase_sec_count;
3802         uint32_t erase_offset;
3803         uint8_t *p_cache, *p_src;
3804
3805         erase_offset = offset;
3806
3807         p_cache = kcalloc(length, sizeof(uint8_t), GFP_KERNEL);
3808         if (!p_cache)
3809                 return QLA_FUNCTION_FAILED;
3810
3811         memcpy(p_cache, buf, length);
3812         p_src = p_cache;
3813         dword_count = length / sizeof(uint32_t);
3814         /* Since the offset and legth are sector aligned, it will be always
3815          * multiple of burst_iter_count (64)
3816          */
3817         burst_iter_count = dword_count / QLA8044_MAX_OPTROM_BURST_DWORDS;
3818         erase_sec_count = length / QLA8044_SECTOR_SIZE;
3819
3820         /* Suspend HBA. */
3821         scsi_block_requests(vha->host);
3822         /* Lock and enable write for whole operation. */
3823         qla8044_flash_lock(vha);
3824         qla8044_unprotect_flash(vha);
3825
3826         /* Erasing the sectors */
3827         for (i = 0; i < erase_sec_count; i++) {
3828                 rval = qla8044_erase_flash_sector(vha, erase_offset);
3829                 ql_dbg(ql_dbg_user, vha, 0xb138,
3830                     "Done erase of sector=0x%x.\n",
3831                     erase_offset);
3832                 if (rval) {
3833                         ql_log(ql_log_warn, vha, 0xb121,
3834                             "Failed to erase the sector having address: "
3835                             "0x%x.\n", erase_offset);
3836                         goto out;
3837                 }
3838                 erase_offset += QLA8044_SECTOR_SIZE;
3839         }
3840         ql_dbg(ql_dbg_user, vha, 0xb13f,
3841             "Got write for addr = 0x%x length=0x%x.\n",
3842             offset, length);
3843
3844         for (i = 0; i < burst_iter_count; i++) {
3845
3846                 /* Go with write. */
3847                 rval = qla8044_write_flash_buffer_mode(vha, (uint32_t *)p_src,
3848                     offset, QLA8044_MAX_OPTROM_BURST_DWORDS);
3849                 if (rval) {
3850                         /* Buffer Mode failed skip to dword mode */
3851                         ql_log(ql_log_warn, vha, 0xb122,
3852                             "Failed to write flash in buffer mode, "
3853                             "Reverting to slow-write.\n");
3854                         rval = qla8044_write_flash_dword_mode(vha,
3855                             (uint32_t *)p_src, offset,
3856                             QLA8044_MAX_OPTROM_BURST_DWORDS);
3857                 }
3858                 p_src +=  sizeof(uint32_t) * QLA8044_MAX_OPTROM_BURST_DWORDS;
3859                 offset += sizeof(uint32_t) * QLA8044_MAX_OPTROM_BURST_DWORDS;
3860         }
3861         ql_dbg(ql_dbg_user, vha, 0xb133,
3862             "Done writing.\n");
3863
3864 out:
3865         qla8044_protect_flash(vha);
3866         qla8044_flash_unlock(vha);
3867         scsi_unblock_requests(vha->host);
3868         kfree(p_cache);
3869
3870         return rval;
3871 }
3872
3873 #define LEG_INT_PTR_B31         (1 << 31)
3874 #define LEG_INT_PTR_B30         (1 << 30)
3875 #define PF_BITS_MASK            (0xF << 16)
3876 /**
3877  * qla8044_intr_handler() - Process interrupts for the ISP8044
3878  * @irq:
3879  * @dev_id: SCSI driver HA context
3880  *
3881  * Called by system whenever the host adapter generates an interrupt.
3882  *
3883  * Returns handled flag.
3884  */
3885 irqreturn_t
3886 qla8044_intr_handler(int irq, void *dev_id)
3887 {
3888         scsi_qla_host_t *vha;
3889         struct qla_hw_data *ha;
3890         struct rsp_que *rsp;
3891         struct device_reg_82xx __iomem *reg;
3892         int             status = 0;
3893         unsigned long   flags;
3894         unsigned long   iter;
3895         uint32_t        stat;
3896         uint16_t        mb[4];
3897         uint32_t leg_int_ptr = 0, pf_bit;
3898
3899         rsp = (struct rsp_que *) dev_id;
3900         if (!rsp) {
3901                 ql_log(ql_log_info, NULL, 0xb143,
3902                     "%s(): NULL response queue pointer\n", __func__);
3903                 return IRQ_NONE;
3904         }
3905         ha = rsp->hw;
3906         vha = pci_get_drvdata(ha->pdev);
3907
3908         if (unlikely(pci_channel_offline(ha->pdev)))
3909                 return IRQ_HANDLED;
3910
3911         leg_int_ptr = qla8044_rd_reg(ha, LEG_INTR_PTR_OFFSET);
3912
3913         /* Legacy interrupt is valid if bit31 of leg_int_ptr is set */
3914         if (!(leg_int_ptr & (LEG_INT_PTR_B31))) {
3915                 ql_dbg(ql_dbg_p3p, vha, 0xb144,
3916                     "%s: Legacy Interrupt Bit 31 not set, "
3917                     "spurious interrupt!\n", __func__);
3918                 return IRQ_NONE;
3919         }
3920
3921         pf_bit = ha->portnum << 16;
3922         /* Validate the PCIE function ID set in leg_int_ptr bits [19..16] */
3923         if ((leg_int_ptr & (PF_BITS_MASK)) != pf_bit) {
3924                 ql_dbg(ql_dbg_p3p, vha, 0xb145,
3925                     "%s: Incorrect function ID 0x%x in "
3926                     "legacy interrupt register, "
3927                     "ha->pf_bit = 0x%x\n", __func__,
3928                     (leg_int_ptr & (PF_BITS_MASK)), pf_bit);
3929                 return IRQ_NONE;
3930         }
3931
3932         /* To de-assert legacy interrupt, write 0 to Legacy Interrupt Trigger
3933          * Control register and poll till Legacy Interrupt Pointer register
3934          * bit32 is 0.
3935          */
3936         qla8044_wr_reg(ha, LEG_INTR_TRIG_OFFSET, 0);
3937         do {
3938                 leg_int_ptr = qla8044_rd_reg(ha, LEG_INTR_PTR_OFFSET);
3939                 if ((leg_int_ptr & (PF_BITS_MASK)) != pf_bit)
3940                         break;
3941         } while (leg_int_ptr & (LEG_INT_PTR_B30));
3942
3943         reg = &ha->iobase->isp82;
3944         spin_lock_irqsave(&ha->hardware_lock, flags);
3945         for (iter = 1; iter--; ) {
3946
3947                 if (RD_REG_DWORD(&reg->host_int)) {
3948                         stat = RD_REG_DWORD(&reg->host_status);
3949                         if ((stat & HSRX_RISC_INT) == 0)
3950                                 break;
3951
3952                         switch (stat & 0xff) {
3953                         case 0x1:
3954                         case 0x2:
3955                         case 0x10:
3956                         case 0x11:
3957                                 qla82xx_mbx_completion(vha, MSW(stat));
3958                                 status |= MBX_INTERRUPT;
3959                                 break;
3960                         case 0x12:
3961                                 mb[0] = MSW(stat);
3962                                 mb[1] = RD_REG_WORD(&reg->mailbox_out[1]);
3963                                 mb[2] = RD_REG_WORD(&reg->mailbox_out[2]);
3964                                 mb[3] = RD_REG_WORD(&reg->mailbox_out[3]);
3965                                 qla2x00_async_event(vha, rsp, mb);
3966                                 break;
3967                         case 0x13:
3968                                 qla24xx_process_response_queue(vha, rsp);
3969                                 break;
3970                         default:
3971                                 ql_dbg(ql_dbg_p3p, vha, 0xb146,
3972                                     "Unrecognized interrupt type "
3973                                     "(%d).\n", stat & 0xff);
3974                                 break;
3975                         }
3976                 }
3977                 WRT_REG_DWORD(&reg->host_int, 0);
3978         }
3979
3980         qla2x00_handle_mbx_completion(ha, status);
3981         spin_unlock_irqrestore(&ha->hardware_lock, flags);
3982
3983         return IRQ_HANDLED;
3984 }
3985
3986 static int
3987 qla8044_idc_dontreset(struct qla_hw_data *ha)
3988 {
3989         uint32_t idc_ctrl;
3990
3991         idc_ctrl = qla8044_rd_reg(ha, QLA8044_IDC_DRV_CTRL);
3992         return idc_ctrl & DONTRESET_BIT0;
3993 }
3994
3995 static void
3996 qla8044_clear_rst_ready(scsi_qla_host_t *vha)
3997 {
3998         uint32_t drv_state;
3999
4000         drv_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX);
4001
4002         /*
4003          * For ISP8044, drv_active register has 1 bit per function,
4004          * shift 1 by func_num to set a bit for the function.
4005          * For ISP82xx, drv_active has 4 bits per function
4006          */
4007         drv_state &= ~(1 << vha->hw->portnum);
4008
4009         ql_dbg(ql_dbg_p3p, vha, 0xb13d,
4010             "drv_state: 0x%08x\n", drv_state);
4011         qla8044_wr_direct(vha, QLA8044_CRB_DRV_STATE_INDEX, drv_state);
4012 }
4013
4014 int
4015 qla8044_abort_isp(scsi_qla_host_t *vha)
4016 {
4017         int rval;
4018         uint32_t dev_state;
4019         struct qla_hw_data *ha = vha->hw;
4020
4021         qla8044_idc_lock(ha);
4022         dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX);
4023
4024         if (ql2xdontresethba)
4025                 qla8044_set_idc_dontreset(vha);
4026
4027         /* If device_state is NEED_RESET, go ahead with
4028          * Reset,irrespective of ql2xdontresethba. This is to allow a
4029          * non-reset-owner to force a reset. Non-reset-owner sets
4030          * the IDC_CTRL BIT0 to prevent Reset-owner from doing a Reset
4031          * and then forces a Reset by setting device_state to
4032          * NEED_RESET. */
4033         if (dev_state == QLA8XXX_DEV_READY) {
4034                 /* If IDC_CTRL DONTRESETHBA_BIT0 is set don't do reset
4035                  * recovery */
4036                 if (qla8044_idc_dontreset(ha) == DONTRESET_BIT0) {
4037                         ql_dbg(ql_dbg_p3p, vha, 0xb13e,
4038                             "Reset recovery disabled\n");
4039                         rval = QLA_FUNCTION_FAILED;
4040                         goto exit_isp_reset;
4041                 }
4042
4043                 ql_dbg(ql_dbg_p3p, vha, 0xb140,
4044                     "HW State: NEED RESET\n");
4045                 qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX,
4046                     QLA8XXX_DEV_NEED_RESET);
4047         }
4048
4049         /* For ISP8044, Reset owner is NIC, iSCSI or FCOE based on priority
4050          * and which drivers are present. Unlike ISP82XX, the function setting
4051          * NEED_RESET, may not be the Reset owner. */
4052         qla83xx_reset_ownership(vha);
4053
4054         qla8044_idc_unlock(ha);
4055         rval = qla8044_device_state_handler(vha);
4056         qla8044_idc_lock(ha);
4057         qla8044_clear_rst_ready(vha);
4058
4059 exit_isp_reset:
4060         qla8044_idc_unlock(ha);
4061         if (rval == QLA_SUCCESS) {
4062                 ha->flags.isp82xx_fw_hung = 0;
4063                 ha->flags.nic_core_reset_hdlr_active = 0;
4064                 rval = qla82xx_restart_isp(vha);
4065         }
4066
4067         return rval;
4068 }
4069
4070 void
4071 qla8044_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
4072 {
4073         struct qla_hw_data *ha = vha->hw;
4074
4075         if (!ha->allow_cna_fw_dump)
4076                 return;
4077
4078         scsi_block_requests(vha->host);
4079         ha->flags.isp82xx_no_md_cap = 1;
4080         qla8044_idc_lock(ha);
4081         qla82xx_set_reset_owner(vha);
4082         qla8044_idc_unlock(ha);
4083         qla2x00_wait_for_chip_reset(vha);
4084         scsi_unblock_requests(vha->host);
4085 }