drivers/scsi/qla4xxx/ql4_nx.c

   1 /*
   2  * QLogic iSCSI HBA Driver
   3  * Copyright (c)  2003-2013 QLogic Corporation
   4  *
   5  * See LICENSE.qla4xxx for copyright and licensing details.
   6  */
   7 #include <linux/delay.h>
   8 #include <linux/io.h>
   9 #include <linux/pci.h>
  10 #include <linux/ratelimit.h>
  11 #include "ql4_def.h"
  12 #include "ql4_glbl.h"
  13 #include "ql4_inline.h"
  14
  15 #include <asm-generic/io-64-nonatomic-lo-hi.h>
  16
  17 #define TIMEOUT_100_MS  100
  18 #define MASK(n)         DMA_BIT_MASK(n)
  19 #define MN_WIN(addr)    (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
  20 #define OCM_WIN(addr)   (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
  21 #define MS_WIN(addr)    (addr & 0x0ffc0000)
  22 #define QLA82XX_PCI_MN_2M       (0)
  23 #define QLA82XX_PCI_MS_2M       (0x80000)
  24 #define QLA82XX_PCI_OCM0_2M     (0xc0000)
  25 #define VALID_OCM_ADDR(addr)    (((addr) & 0x3f800) != 0x3f800)
  26 #define GET_MEM_OFFS_2M(addr)   (addr & MASK(18))
  27
  28 /* CRB window related */
  29 #define CRB_BLK(off)    ((off >> 20) & 0x3f)
  30 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
  31 #define CRB_WINDOW_2M   (0x130060)
  32 #define CRB_HI(off)     ((qla4_82xx_crb_hub_agt[CRB_BLK(off)] << 20) | \
  33                         ((off) & 0xf0000))
  34 #define QLA82XX_PCI_CAMQM_2M_END        (0x04800800UL)
  35 #define QLA82XX_PCI_CAMQM_2M_BASE       (0x000ff800UL)
  36 #define CRB_INDIRECT_2M                 (0x1e0000UL)
  37
  38 static inline void __iomem *
  39 qla4_8xxx_pci_base_offsetfset(struct scsi_qla_host *ha, unsigned long off)
  40 {
  41         if ((off < ha->first_page_group_end) &&
  42             (off >= ha->first_page_group_start))
  43                 return (void __iomem *)(ha->nx_pcibase + off);
  44
  45         return NULL;
  46 }
  47
  48 #define MAX_CRB_XFORM 60
  49 static unsigned long crb_addr_xform[MAX_CRB_XFORM];
  50 static int qla4_8xxx_crb_table_initialized;
  51
  52 #define qla4_8xxx_crb_addr_transform(name) \
  53         (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \
  54          QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20)
  55 static void
  56 qla4_82xx_crb_addr_transform_setup(void)
  57 {
  58         qla4_8xxx_crb_addr_transform(XDMA);
  59         qla4_8xxx_crb_addr_transform(TIMR);
  60         qla4_8xxx_crb_addr_transform(SRE);
  61         qla4_8xxx_crb_addr_transform(SQN3);
  62         qla4_8xxx_crb_addr_transform(SQN2);
  63         qla4_8xxx_crb_addr_transform(SQN1);
  64         qla4_8xxx_crb_addr_transform(SQN0);
  65         qla4_8xxx_crb_addr_transform(SQS3);
  66         qla4_8xxx_crb_addr_transform(SQS2);
  67         qla4_8xxx_crb_addr_transform(SQS1);
  68         qla4_8xxx_crb_addr_transform(SQS0);
  69         qla4_8xxx_crb_addr_transform(RPMX7);
  70         qla4_8xxx_crb_addr_transform(RPMX6);
  71         qla4_8xxx_crb_addr_transform(RPMX5);
  72         qla4_8xxx_crb_addr_transform(RPMX4);
  73         qla4_8xxx_crb_addr_transform(RPMX3);
  74         qla4_8xxx_crb_addr_transform(RPMX2);
  75         qla4_8xxx_crb_addr_transform(RPMX1);
  76         qla4_8xxx_crb_addr_transform(RPMX0);
  77         qla4_8xxx_crb_addr_transform(ROMUSB);
  78         qla4_8xxx_crb_addr_transform(SN);
  79         qla4_8xxx_crb_addr_transform(QMN);
  80         qla4_8xxx_crb_addr_transform(QMS);
  81         qla4_8xxx_crb_addr_transform(PGNI);
  82         qla4_8xxx_crb_addr_transform(PGND);
  83         qla4_8xxx_crb_addr_transform(PGN3);
  84         qla4_8xxx_crb_addr_transform(PGN2);
  85         qla4_8xxx_crb_addr_transform(PGN1);
  86         qla4_8xxx_crb_addr_transform(PGN0);
  87         qla4_8xxx_crb_addr_transform(PGSI);
  88         qla4_8xxx_crb_addr_transform(PGSD);
  89         qla4_8xxx_crb_addr_transform(PGS3);
  90         qla4_8xxx_crb_addr_transform(PGS2);
  91         qla4_8xxx_crb_addr_transform(PGS1);
  92         qla4_8xxx_crb_addr_transform(PGS0);
  93         qla4_8xxx_crb_addr_transform(PS);
  94         qla4_8xxx_crb_addr_transform(PH);
  95         qla4_8xxx_crb_addr_transform(NIU);
  96         qla4_8xxx_crb_addr_transform(I2Q);
  97         qla4_8xxx_crb_addr_transform(EG);
  98         qla4_8xxx_crb_addr_transform(MN);
  99         qla4_8xxx_crb_addr_transform(MS);
 100         qla4_8xxx_crb_addr_transform(CAS2);
 101         qla4_8xxx_crb_addr_transform(CAS1);
 102         qla4_8xxx_crb_addr_transform(CAS0);
 103         qla4_8xxx_crb_addr_transform(CAM);
 104         qla4_8xxx_crb_addr_transform(C2C1);
 105         qla4_8xxx_crb_addr_transform(C2C0);
 106         qla4_8xxx_crb_addr_transform(SMB);
 107         qla4_8xxx_crb_addr_transform(OCM0);
 108         qla4_8xxx_crb_addr_transform(I2C0);
 109
 110         qla4_8xxx_crb_table_initialized = 1;
 111 }
 112
 113 static struct crb_128M_2M_block_map crb_128M_2M_map[64] = {
 114         {{{0, 0,         0,         0} } },             /* 0: PCI */
 115         {{{1, 0x0100000, 0x0102000, 0x120000},  /* 1: PCIE */
 116                 {1, 0x0110000, 0x0120000, 0x130000},
 117                 {1, 0x0120000, 0x0122000, 0x124000},
 118                 {1, 0x0130000, 0x0132000, 0x126000},
 119                 {1, 0x0140000, 0x0142000, 0x128000},
 120                 {1, 0x0150000, 0x0152000, 0x12a000},
 121                 {1, 0x0160000, 0x0170000, 0x110000},
 122                 {1, 0x0170000, 0x0172000, 0x12e000},
 123                 {0, 0x0000000, 0x0000000, 0x000000},
 124                 {0, 0x0000000, 0x0000000, 0x000000},
 125                 {0, 0x0000000, 0x0000000, 0x000000},
 126                 {0, 0x0000000, 0x0000000, 0x000000},
 127                 {0, 0x0000000, 0x0000000, 0x000000},
 128                 {0, 0x0000000, 0x0000000, 0x000000},
 129                 {1, 0x01e0000, 0x01e0800, 0x122000},
 130                 {0, 0x0000000, 0x0000000, 0x000000} } },
 131         {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
 132         {{{0, 0,         0,         0} } },         /* 3: */
 133         {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
 134         {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE   */
 135         {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU   */
 136         {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM    */
 137         {{{1, 0x0800000, 0x0802000, 0x170000},  /* 8: SQM0  */
 138                 {0, 0x0000000, 0x0000000, 0x000000},
 139                 {0, 0x0000000, 0x0000000, 0x000000},
 140                 {0, 0x0000000, 0x0000000, 0x000000},
 141                 {0, 0x0000000, 0x0000000, 0x000000},
 142                 {0, 0x0000000, 0x0000000, 0x000000},
 143                 {0, 0x0000000, 0x0000000, 0x000000},
 144                 {0, 0x0000000, 0x0000000, 0x000000},
 145                 {0, 0x0000000, 0x0000000, 0x000000},
 146                 {0, 0x0000000, 0x0000000, 0x000000},
 147                 {0, 0x0000000, 0x0000000, 0x000000},
 148                 {0, 0x0000000, 0x0000000, 0x000000},
 149                 {0, 0x0000000, 0x0000000, 0x000000},
 150                 {0, 0x0000000, 0x0000000, 0x000000},
 151                 {0, 0x0000000, 0x0000000, 0x000000},
 152                 {1, 0x08f0000, 0x08f2000, 0x172000} } },
 153         {{{1, 0x0900000, 0x0902000, 0x174000},  /* 9: SQM1*/
 154                 {0, 0x0000000, 0x0000000, 0x000000},
 155                 {0, 0x0000000, 0x0000000, 0x000000},
 156                 {0, 0x0000000, 0x0000000, 0x000000},
 157                 {0, 0x0000000, 0x0000000, 0x000000},
 158                 {0, 0x0000000, 0x0000000, 0x000000},
 159                 {0, 0x0000000, 0x0000000, 0x000000},
 160                 {0, 0x0000000, 0x0000000, 0x000000},
 161                 {0, 0x0000000, 0x0000000, 0x000000},
 162                 {0, 0x0000000, 0x0000000, 0x000000},
 163                 {0, 0x0000000, 0x0000000, 0x000000},
 164                 {0, 0x0000000, 0x0000000, 0x000000},
 165                 {0, 0x0000000, 0x0000000, 0x000000},
 166                 {0, 0x0000000, 0x0000000, 0x000000},
 167                 {0, 0x0000000, 0x0000000, 0x000000},
 168                 {1, 0x09f0000, 0x09f2000, 0x176000} } },
 169         {{{0, 0x0a00000, 0x0a02000, 0x178000},  /* 10: SQM2*/
 170                 {0, 0x0000000, 0x0000000, 0x000000},
 171                 {0, 0x0000000, 0x0000000, 0x000000},
 172                 {0, 0x0000000, 0x0000000, 0x000000},
 173                 {0, 0x0000000, 0x0000000, 0x000000},
 174                 {0, 0x0000000, 0x0000000, 0x000000},
 175                 {0, 0x0000000, 0x0000000, 0x000000},
 176                 {0, 0x0000000, 0x0000000, 0x000000},
 177                 {0, 0x0000000, 0x0000000, 0x000000},
 178                 {0, 0x0000000, 0x0000000, 0x000000},
 179                 {0, 0x0000000, 0x0000000, 0x000000},
 180                 {0, 0x0000000, 0x0000000, 0x000000},
 181                 {0, 0x0000000, 0x0000000, 0x000000},
 182                 {0, 0x0000000, 0x0000000, 0x000000},
 183                 {0, 0x0000000, 0x0000000, 0x000000},
 184                 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
 185         {{{0, 0x0b00000, 0x0b02000, 0x17c000},  /* 11: SQM3*/
 186                 {0, 0x0000000, 0x0000000, 0x000000},
 187                 {0, 0x0000000, 0x0000000, 0x000000},
 188                 {0, 0x0000000, 0x0000000, 0x000000},
 189                 {0, 0x0000000, 0x0000000, 0x000000},
 190                 {0, 0x0000000, 0x0000000, 0x000000},
 191                 {0, 0x0000000, 0x0000000, 0x000000},
 192                 {0, 0x0000000, 0x0000000, 0x000000},
 193                 {0, 0x0000000, 0x0000000, 0x000000},
 194                 {0, 0x0000000, 0x0000000, 0x000000},
 195                 {0, 0x0000000, 0x0000000, 0x000000},
 196                 {0, 0x0000000, 0x0000000, 0x000000},
 197                 {0, 0x0000000, 0x0000000, 0x000000},
 198                 {0, 0x0000000, 0x0000000, 0x000000},
 199                 {0, 0x0000000, 0x0000000, 0x000000},
 200                 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
 201         {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
 202         {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
 203         {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
 204         {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
 205         {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
 206         {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
 207         {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
 208         {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
 209         {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
 210         {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
 211         {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
 212         {{{0, 0,         0,         0} } },     /* 23: */
 213         {{{0, 0,         0,         0} } },     /* 24: */
 214         {{{0, 0,         0,         0} } },     /* 25: */
 215         {{{0, 0,         0,         0} } },     /* 26: */
 216         {{{0, 0,         0,         0} } },     /* 27: */
 217         {{{0, 0,         0,         0} } },     /* 28: */
 218         {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
 219         {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
 220         {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
 221         {{{0} } },                              /* 32: PCI */
 222         {{{1, 0x2100000, 0x2102000, 0x120000},  /* 33: PCIE */
 223                 {1, 0x2110000, 0x2120000, 0x130000},
 224                 {1, 0x2120000, 0x2122000, 0x124000},
 225                 {1, 0x2130000, 0x2132000, 0x126000},
 226                 {1, 0x2140000, 0x2142000, 0x128000},
 227                 {1, 0x2150000, 0x2152000, 0x12a000},
 228                 {1, 0x2160000, 0x2170000, 0x110000},
 229                 {1, 0x2170000, 0x2172000, 0x12e000},
 230                 {0, 0x0000000, 0x0000000, 0x000000},
 231                 {0, 0x0000000, 0x0000000, 0x000000},
 232                 {0, 0x0000000, 0x0000000, 0x000000},
 233                 {0, 0x0000000, 0x0000000, 0x000000},
 234                 {0, 0x0000000, 0x0000000, 0x000000},
 235                 {0, 0x0000000, 0x0000000, 0x000000},
 236                 {0, 0x0000000, 0x0000000, 0x000000},
 237                 {0, 0x0000000, 0x0000000, 0x000000} } },
 238         {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
 239         {{{0} } },                              /* 35: */
 240         {{{0} } },                              /* 36: */
 241         {{{0} } },                              /* 37: */
 242         {{{0} } },                              /* 38: */
 243         {{{0} } },                              /* 39: */
 244         {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
 245         {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
 246         {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
 247         {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
 248         {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
 249         {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
 250         {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
 251         {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
 252         {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
 253         {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
 254         {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
 255         {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
 256         {{{0} } },                              /* 52: */
 257         {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
 258         {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
 259         {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
 260         {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
 261         {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
 262         {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
 263         {{{0} } },                              /* 59: I2C0 */
 264         {{{0} } },                              /* 60: I2C1 */
 265         {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } },/* 61: LPC */
 266         {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
 267         {{{1, 0x3f00000, 0x3f01000, 0x168000} } }       /* 63: P2NR0 */
 268 };
 269
 270 /*
 271  * top 12 bits of crb internal address (hub, agent)
 272  */
 273 static unsigned qla4_82xx_crb_hub_agt[64] = {
 274         0,
 275         QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
 276         QLA82XX_HW_CRB_HUB_AGT_ADR_MN,
 277         QLA82XX_HW_CRB_HUB_AGT_ADR_MS,
 278         0,
 279         QLA82XX_HW_CRB_HUB_AGT_ADR_SRE,
 280         QLA82XX_HW_CRB_HUB_AGT_ADR_NIU,
 281         QLA82XX_HW_CRB_HUB_AGT_ADR_QMN,
 282         QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0,
 283         QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1,
 284         QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2,
 285         QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3,
 286         QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
 287         QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
 288         QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
 289         QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4,
 290         QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
 291         QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0,
 292         QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1,
 293         QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2,
 294         QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3,
 295         QLA82XX_HW_CRB_HUB_AGT_ADR_PGND,
 296         QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI,
 297         QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0,
 298         QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1,
 299         QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2,
 300         QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3,
 301         0,
 302         QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI,
 303         QLA82XX_HW_CRB_HUB_AGT_ADR_SN,
 304         0,
 305         QLA82XX_HW_CRB_HUB_AGT_ADR_EG,
 306         0,
 307         QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
 308         QLA82XX_HW_CRB_HUB_AGT_ADR_CAM,
 309         0,
 310         0,
 311         0,
 312         0,
 313         0,
 314         QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
 315         0,
 316         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1,
 317         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2,
 318         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3,
 319         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4,
 320         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5,
 321         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6,
 322         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7,
 323         QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
 324         QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
 325         QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
 326         0,
 327         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0,
 328         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8,
 329         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9,
 330         QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0,
 331         0,
 332         QLA82XX_HW_CRB_HUB_AGT_ADR_SMB,
 333         QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0,
 334         QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1,
 335         0,
 336         QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC,
 337         0,
 338 };
 339
 340 /* Device states */
 341 static char *qdev_state[] = {
 342         "Unknown",
 343         "Cold",
 344         "Initializing",
 345         "Ready",
 346         "Need Reset",
 347         "Need Quiescent",
 348         "Failed",
 349         "Quiescent",
 350 };
 351
 352 /*
 353  * In: 'off' is offset from CRB space in 128M pci map
 354  * Out: 'off' is 2M pci map addr
 355  * side effect: lock crb window
 356  */
 357 static void
 358 qla4_82xx_pci_set_crbwindow_2M(struct scsi_qla_host *ha, ulong *off)
 359 {
 360         u32 win_read;
 361
 362         ha->crb_win = CRB_HI(*off);
 363         writel(ha->crb_win,
 364                 (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
 365
 366         /* Read back value to make sure write has gone through before trying
 367         * to use it. */
 368         win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
 369         if (win_read != ha->crb_win) {
 370                 DEBUG2(ql4_printk(KERN_INFO, ha,
 371                     "%s: Written crbwin (0x%x) != Read crbwin (0x%x),"
 372                     " off=0x%lx\n", __func__, ha->crb_win, win_read, *off));
 373         }
 374         *off = (*off & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase;
 375 }
 376
 377 void
 378 qla4_82xx_wr_32(struct scsi_qla_host *ha, ulong off, u32 data)
 379 {
 380         unsigned long flags = 0;
 381         int rv;
 382
 383         rv = qla4_82xx_pci_get_crb_addr_2M(ha, &off);
 384
 385         BUG_ON(rv == -1);
 386
 387         if (rv == 1) {
 388                 write_lock_irqsave(&ha->hw_lock, flags);
 389                 qla4_82xx_crb_win_lock(ha);
 390                 qla4_82xx_pci_set_crbwindow_2M(ha, &off);
 391         }
 392
 393         writel(data, (void __iomem *)off);
 394
 395         if (rv == 1) {
 396                 qla4_82xx_crb_win_unlock(ha);
 397                 write_unlock_irqrestore(&ha->hw_lock, flags);
 398         }
 399 }
 400
 401 uint32_t qla4_82xx_rd_32(struct scsi_qla_host *ha, ulong off)
 402 {
 403         unsigned long flags = 0;
 404         int rv;
 405         u32 data;
 406
 407         rv = qla4_82xx_pci_get_crb_addr_2M(ha, &off);
 408
 409         BUG_ON(rv == -1);
 410
 411         if (rv == 1) {
 412                 write_lock_irqsave(&ha->hw_lock, flags);
 413                 qla4_82xx_crb_win_lock(ha);
 414                 qla4_82xx_pci_set_crbwindow_2M(ha, &off);
 415         }
 416         data = readl((void __iomem *)off);
 417
 418         if (rv == 1) {
 419                 qla4_82xx_crb_win_unlock(ha);
 420                 write_unlock_irqrestore(&ha->hw_lock, flags);
 421         }
 422         return data;
 423 }
 424
 425 /* Minidump related functions */
 426 int qla4_82xx_md_rd_32(struct scsi_qla_host *ha, uint32_t off, uint32_t *data)
 427 {
 428         uint32_t win_read, off_value;
 429         int rval = QLA_SUCCESS;
 430
 431         off_value  = off & 0xFFFF0000;
 432         writel(off_value, (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
 433
 434         /*
 435          * Read back value to make sure write has gone through before trying
 436          * to use it.
 437          */
 438         win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
 439         if (win_read != off_value) {
 440                 DEBUG2(ql4_printk(KERN_INFO, ha,
 441                                   "%s: Written (0x%x) != Read (0x%x), off=0x%x\n",
 442                                   __func__, off_value, win_read, off));
 443                 rval = QLA_ERROR;
 444         } else {
 445                 off_value  = off & 0x0000FFFF;
 446                 *data = readl((void __iomem *)(off_value + CRB_INDIRECT_2M +
 447                                                ha->nx_pcibase));
 448         }
 449         return rval;
 450 }
 451
 452 int qla4_82xx_md_wr_32(struct scsi_qla_host *ha, uint32_t off, uint32_t data)
 453 {
 454         uint32_t win_read, off_value;
 455         int rval = QLA_SUCCESS;
 456
 457         off_value  = off & 0xFFFF0000;
 458         writel(off_value, (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
 459
 460         /* Read back value to make sure write has gone through before trying
 461          * to use it.
 462          */
 463         win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
 464         if (win_read != off_value) {
 465                 DEBUG2(ql4_printk(KERN_INFO, ha,
 466                                   "%s: Written (0x%x) != Read (0x%x), off=0x%x\n",
 467                                   __func__, off_value, win_read, off));
 468                 rval = QLA_ERROR;
 469         } else {
 470                 off_value  = off & 0x0000FFFF;
 471                 writel(data, (void __iomem *)(off_value + CRB_INDIRECT_2M +
 472                                               ha->nx_pcibase));
 473         }
 474         return rval;
 475 }
 476
 477 #define CRB_WIN_LOCK_TIMEOUT 100000000
 478
 479 int qla4_82xx_crb_win_lock(struct scsi_qla_host *ha)
 480 {
 481         int i;
 482         int done = 0, timeout = 0;
 483
 484         while (!done) {
 485                 /* acquire semaphore3 from PCI HW block */
 486                 done = qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK));
 487                 if (done == 1)
 488                         break;
 489                 if (timeout >= CRB_WIN_LOCK_TIMEOUT)
 490                         return -1;
 491
 492                 timeout++;
 493
 494                 /* Yield CPU */
 495                 if (!in_interrupt())
 496                         schedule();
 497                 else {
 498                         for (i = 0; i < 20; i++)
 499                                 cpu_relax();    /*This a nop instr on i386*/
 500                 }
 501         }
 502         qla4_82xx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->func_num);
 503         return 0;
 504 }
 505
 506 void qla4_82xx_crb_win_unlock(struct scsi_qla_host *ha)
 507 {
 508         qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK));
 509 }
 510
 511 #define IDC_LOCK_TIMEOUT 100000000
 512
 513 /**
 514  * qla4_82xx_idc_lock - hw_lock
 515  * @ha: pointer to adapter structure
 516  *
 517  * General purpose lock used to synchronize access to
 518  * CRB_DEV_STATE, CRB_DEV_REF_COUNT, etc.
 519  **/
 520 int qla4_82xx_idc_lock(struct scsi_qla_host *ha)
 521 {
 522         int i;
 523         int done = 0, timeout = 0;
 524
 525         while (!done) {
 526                 /* acquire semaphore5 from PCI HW block */
 527                 done = qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK));
 528                 if (done == 1)
 529                         break;
 530                 if (timeout >= IDC_LOCK_TIMEOUT)
 531                         return -1;
 532
 533                 timeout++;
 534
 535                 /* Yield CPU */
 536                 if (!in_interrupt())
 537                         schedule();
 538                 else {
 539                         for (i = 0; i < 20; i++)
 540                                 cpu_relax();    /*This a nop instr on i386*/
 541                 }
 542         }
 543         return 0;
 544 }
 545
 546 void qla4_82xx_idc_unlock(struct scsi_qla_host *ha)
 547 {
 548         qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK));
 549 }
 550
 551 int
 552 qla4_82xx_pci_get_crb_addr_2M(struct scsi_qla_host *ha, ulong *off)
 553 {
 554         struct crb_128M_2M_sub_block_map *m;
 555
 556         if (*off >= QLA82XX_CRB_MAX)
 557                 return -1;
 558
 559         if (*off >= QLA82XX_PCI_CAMQM && (*off < QLA82XX_PCI_CAMQM_2M_END)) {
 560                 *off = (*off - QLA82XX_PCI_CAMQM) +
 561                     QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase;
 562                 return 0;
 563         }
 564
 565         if (*off < QLA82XX_PCI_CRBSPACE)
 566                 return -1;
 567
 568         *off -= QLA82XX_PCI_CRBSPACE;
 569         /*
 570          * Try direct map
 571          */
 572
 573         m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)];
 574
 575         if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) {
 576                 *off = *off + m->start_2M - m->start_128M + ha->nx_pcibase;
 577                 return 0;
 578         }
 579
 580         /*
 581          * Not in direct map, use crb window
 582          */
 583         return 1;
 584 }
 585
 586 /*
 587 * check memory access boundary.
 588 * used by test agent. support ddr access only for now
 589 */
 590 static unsigned long
 591 qla4_82xx_pci_mem_bound_check(struct scsi_qla_host *ha,
 592                 unsigned long long addr, int size)
 593 {
 594         if (!QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_DDR_NET,
 595             QLA8XXX_ADDR_DDR_NET_MAX) ||
 596             !QLA8XXX_ADDR_IN_RANGE(addr + size - 1,
 597             QLA8XXX_ADDR_DDR_NET, QLA8XXX_ADDR_DDR_NET_MAX) ||
 598             ((size != 1) && (size != 2) && (size != 4) && (size != 8))) {
 599                 return 0;
 600         }
 601         return 1;
 602 }
 603
 604 static int qla4_82xx_pci_set_window_warning_count;
 605
 606 static unsigned long
 607 qla4_82xx_pci_set_window(struct scsi_qla_host *ha, unsigned long long addr)
 608 {
 609         int window;
 610         u32 win_read;
 611
 612         if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_DDR_NET,
 613             QLA8XXX_ADDR_DDR_NET_MAX)) {
 614                 /* DDR network side */
 615                 window = MN_WIN(addr);
 616                 ha->ddr_mn_window = window;
 617                 qla4_82xx_wr_32(ha, ha->mn_win_crb |
 618                     QLA82XX_PCI_CRBSPACE, window);
 619                 win_read = qla4_82xx_rd_32(ha, ha->mn_win_crb |
 620                     QLA82XX_PCI_CRBSPACE);
 621                 if ((win_read << 17) != window) {
 622                         ql4_printk(KERN_WARNING, ha,
 623                         "%s: Written MNwin (0x%x) != Read MNwin (0x%x)\n",
 624                         __func__, window, win_read);
 625                 }
 626                 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET;
 627         } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_OCM0,
 628                                 QLA8XXX_ADDR_OCM0_MAX)) {
 629                 unsigned int temp1;
 630                 /* if bits 19:18&17:11 are on */
 631                 if ((addr & 0x00ff800) == 0xff800) {
 632                         printk("%s: QM access not handled.\n", __func__);
 633                         addr = -1UL;
 634                 }
 635
 636                 window = OCM_WIN(addr);
 637                 ha->ddr_mn_window = window;
 638                 qla4_82xx_wr_32(ha, ha->mn_win_crb |
 639                     QLA82XX_PCI_CRBSPACE, window);
 640                 win_read = qla4_82xx_rd_32(ha, ha->mn_win_crb |
 641                     QLA82XX_PCI_CRBSPACE);
 642                 temp1 = ((window & 0x1FF) << 7) |
 643                     ((window & 0x0FFFE0000) >> 17);
 644                 if (win_read != temp1) {
 645                         printk("%s: Written OCMwin (0x%x) != Read"
 646                             " OCMwin (0x%x)\n", __func__, temp1, win_read);
 647                 }
 648                 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M;
 649
 650         } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_QDR_NET,
 651                                 QLA82XX_P3_ADDR_QDR_NET_MAX)) {
 652                 /* QDR network side */
 653                 window = MS_WIN(addr);
 654                 ha->qdr_sn_window = window;
 655                 qla4_82xx_wr_32(ha, ha->ms_win_crb |
 656                     QLA82XX_PCI_CRBSPACE, window);
 657                 win_read = qla4_82xx_rd_32(ha,
 658                      ha->ms_win_crb | QLA82XX_PCI_CRBSPACE);
 659                 if (win_read != window) {
 660                         printk("%s: Written MSwin (0x%x) != Read "
 661                             "MSwin (0x%x)\n", __func__, window, win_read);
 662                 }
 663                 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET;
 664
 665         } else {
 666                 /*
 667                  * peg gdb frequently accesses memory that doesn't exist,
 668                  * this limits the chit chat so debugging isn't slowed down.
 669                  */
 670                 if ((qla4_82xx_pci_set_window_warning_count++ < 8) ||
 671                     (qla4_82xx_pci_set_window_warning_count%64 == 0)) {
 672                         printk("%s: Warning:%s Unknown address range!\n",
 673                             __func__, DRIVER_NAME);
 674                 }
 675                 addr = -1UL;
 676         }
 677         return addr;
 678 }
 679
 680 /* check if address is in the same windows as the previous access */
 681 static int qla4_82xx_pci_is_same_window(struct scsi_qla_host *ha,
 682                 unsigned long long addr)
 683 {
 684         int window;
 685         unsigned long long qdr_max;
 686
 687         qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX;
 688
 689         if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_DDR_NET,
 690             QLA8XXX_ADDR_DDR_NET_MAX)) {
 691                 /* DDR network side */
 692                 BUG();  /* MN access can not come here */
 693         } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_OCM0,
 694              QLA8XXX_ADDR_OCM0_MAX)) {
 695                 return 1;
 696         } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_OCM1,
 697              QLA8XXX_ADDR_OCM1_MAX)) {
 698                 return 1;
 699         } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_QDR_NET,
 700             qdr_max)) {
 701                 /* QDR network side */
 702                 window = ((addr - QLA8XXX_ADDR_QDR_NET) >> 22) & 0x3f;
 703                 if (ha->qdr_sn_window == window)
 704                         return 1;
 705         }
 706
 707         return 0;
 708 }
 709
 710 static int qla4_82xx_pci_mem_read_direct(struct scsi_qla_host *ha,
 711                 u64 off, void *data, int size)
 712 {
 713         unsigned long flags;
 714         void __iomem *addr;
 715         int ret = 0;
 716         u64 start;
 717         void __iomem *mem_ptr = NULL;
 718         unsigned long mem_base;
 719         unsigned long mem_page;
 720
 721         write_lock_irqsave(&ha->hw_lock, flags);
 722
 723         /*
 724          * If attempting to access unknown address or straddle hw windows,
 725          * do not access.
 726          */
 727         start = qla4_82xx_pci_set_window(ha, off);
 728         if ((start == -1UL) ||
 729             (qla4_82xx_pci_is_same_window(ha, off + size - 1) == 0)) {
 730                 write_unlock_irqrestore(&ha->hw_lock, flags);
 731                 printk(KERN_ERR"%s out of bound pci memory access. "
 732                                 "offset is 0x%llx\n", DRIVER_NAME, off);
 733                 return -1;
 734         }
 735
 736         addr = qla4_8xxx_pci_base_offsetfset(ha, start);
 737         if (!addr) {
 738                 write_unlock_irqrestore(&ha->hw_lock, flags);
 739                 mem_base = pci_resource_start(ha->pdev, 0);
 740                 mem_page = start & PAGE_MASK;
 741                 /* Map two pages whenever user tries to access addresses in two
 742                    consecutive pages.
 743                  */
 744                 if (mem_page != ((start + size - 1) & PAGE_MASK))
 745                         mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2);
 746                 else
 747                         mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
 748
 749                 if (mem_ptr == NULL) {
 750                         *(u8 *)data = 0;
 751                         return -1;
 752                 }
 753                 addr = mem_ptr;
 754                 addr += start & (PAGE_SIZE - 1);
 755                 write_lock_irqsave(&ha->hw_lock, flags);
 756         }
 757
 758         switch (size) {
 759         case 1:
 760                 *(u8  *)data = readb(addr);
 761                 break;
 762         case 2:
 763                 *(u16 *)data = readw(addr);
 764                 break;
 765         case 4:
 766                 *(u32 *)data = readl(addr);
 767                 break;
 768         case 8:
 769                 *(u64 *)data = readq(addr);
 770                 break;
 771         default:
 772                 ret = -1;
 773                 break;
 774         }
 775         write_unlock_irqrestore(&ha->hw_lock, flags);
 776
 777         if (mem_ptr)
 778                 iounmap(mem_ptr);
 779         return ret;
 780 }
 781
 782 static int
 783 qla4_82xx_pci_mem_write_direct(struct scsi_qla_host *ha, u64 off,
 784                 void *data, int size)
 785 {
 786         unsigned long flags;
 787         void __iomem *addr;
 788         int ret = 0;
 789         u64 start;
 790         void __iomem *mem_ptr = NULL;
 791         unsigned long mem_base;
 792         unsigned long mem_page;
 793
 794         write_lock_irqsave(&ha->hw_lock, flags);
 795
 796         /*
 797          * If attempting to access unknown address or straddle hw windows,
 798          * do not access.
 799          */
 800         start = qla4_82xx_pci_set_window(ha, off);
 801         if ((start == -1UL) ||
 802             (qla4_82xx_pci_is_same_window(ha, off + size - 1) == 0)) {
 803                 write_unlock_irqrestore(&ha->hw_lock, flags);
 804                 printk(KERN_ERR"%s out of bound pci memory access. "
 805                                 "offset is 0x%llx\n", DRIVER_NAME, off);
 806                 return -1;
 807         }
 808
 809         addr = qla4_8xxx_pci_base_offsetfset(ha, start);
 810         if (!addr) {
 811                 write_unlock_irqrestore(&ha->hw_lock, flags);
 812                 mem_base = pci_resource_start(ha->pdev, 0);
 813                 mem_page = start & PAGE_MASK;
 814                 /* Map two pages whenever user tries to access addresses in two
 815                    consecutive pages.
 816                  */
 817                 if (mem_page != ((start + size - 1) & PAGE_MASK))
 818                         mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2);
 819                 else
 820                         mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
 821                 if (mem_ptr == NULL)
 822                         return -1;
 823
 824                 addr = mem_ptr;
 825                 addr += start & (PAGE_SIZE - 1);
 826                 write_lock_irqsave(&ha->hw_lock, flags);
 827         }
 828
 829         switch (size) {
 830         case 1:
 831                 writeb(*(u8 *)data, addr);
 832                 break;
 833         case 2:
 834                 writew(*(u16 *)data, addr);
 835                 break;
 836         case 4:
 837                 writel(*(u32 *)data, addr);
 838                 break;
 839         case 8:
 840                 writeq(*(u64 *)data, addr);
 841                 break;
 842         default:
 843                 ret = -1;
 844                 break;
 845         }
 846         write_unlock_irqrestore(&ha->hw_lock, flags);
 847         if (mem_ptr)
 848                 iounmap(mem_ptr);
 849         return ret;
 850 }
 851
 852 #define MTU_FUDGE_FACTOR 100
 853
 854 static unsigned long
 855 qla4_82xx_decode_crb_addr(unsigned long addr)
 856 {
 857         int i;
 858         unsigned long base_addr, offset, pci_base;
 859
 860         if (!qla4_8xxx_crb_table_initialized)
 861                 qla4_82xx_crb_addr_transform_setup();
 862
 863         pci_base = ADDR_ERROR;
 864         base_addr = addr & 0xfff00000;
 865         offset = addr & 0x000fffff;
 866
 867         for (i = 0; i < MAX_CRB_XFORM; i++) {
 868                 if (crb_addr_xform[i] == base_addr) {
 869                         pci_base = i << 20;
 870                         break;
 871                 }
 872         }
 873         if (pci_base == ADDR_ERROR)
 874                 return pci_base;
 875         else
 876                 return pci_base + offset;
 877 }
 878
 879 static long rom_max_timeout = 100;
 880 static long qla4_82xx_rom_lock_timeout = 100;
 881
 882 static int
 883 qla4_82xx_rom_lock(struct scsi_qla_host *ha)
 884 {
 885         int i;
 886         int done = 0, timeout = 0;
 887
 888         while (!done) {
 889                 /* acquire semaphore2 from PCI HW block */
 890
 891                 done = qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK));
 892                 if (done == 1)
 893                         break;
 894                 if (timeout >= qla4_82xx_rom_lock_timeout)
 895                         return -1;
 896
 897                 timeout++;
 898
 899                 /* Yield CPU */
 900                 if (!in_interrupt())
 901                         schedule();
 902                 else {
 903                         for (i = 0; i < 20; i++)
 904                                 cpu_relax();    /*This a nop instr on i386*/
 905                 }
 906         }
 907         qla4_82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ROM_LOCK_DRIVER);
 908         return 0;
 909 }
 910
 911 static void
 912 qla4_82xx_rom_unlock(struct scsi_qla_host *ha)
 913 {
 914         qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK));
 915 }
 916
 917 static int
 918 qla4_82xx_wait_rom_done(struct scsi_qla_host *ha)
 919 {
 920         long timeout = 0;
 921         long done = 0 ;
 922
 923         while (done == 0) {
 924                 done = qla4_82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS);
 925                 done &= 2;
 926                 timeout++;
 927                 if (timeout >= rom_max_timeout) {
 928                         printk("%s: Timeout reached  waiting for rom done",
 929                                         DRIVER_NAME);
 930                         return -1;
 931                 }
 932         }
 933         return 0;
 934 }
 935
 936 static int
 937 qla4_82xx_do_rom_fast_read(struct scsi_qla_host *ha, int addr, int *valp)
 938 {
 939         qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr);
 940         qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
 941         qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3);
 942         qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0xb);
 943         if (qla4_82xx_wait_rom_done(ha)) {
 944                 printk("%s: Error waiting for rom done\n", DRIVER_NAME);
 945                 return -1;
 946         }
 947         /* reset abyte_cnt and dummy_byte_cnt */
 948         qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
 949         udelay(10);
 950         qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0);
 951
 952         *valp = qla4_82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA);
 953         return 0;
 954 }
 955
 956 static int
 957 qla4_82xx_rom_fast_read(struct scsi_qla_host *ha, int addr, int *valp)
 958 {
 959         int ret, loops = 0;
 960
 961         while ((qla4_82xx_rom_lock(ha) != 0) && (loops < 50000)) {
 962                 udelay(100);
 963                 loops++;
 964         }
 965         if (loops >= 50000) {
 966                 ql4_printk(KERN_WARNING, ha, "%s: qla4_82xx_rom_lock failed\n",
 967                            DRIVER_NAME);
 968                 return -1;
 969         }
 970         ret = qla4_82xx_do_rom_fast_read(ha, addr, valp);
 971         qla4_82xx_rom_unlock(ha);
 972         return ret;
 973 }
 974
 975 /**
 976  * This routine does CRB initialize sequence
 977  * to put the ISP into operational state
 978  **/
 979 static int
 980 qla4_82xx_pinit_from_rom(struct scsi_qla_host *ha, int verbose)
 981 {
 982         int addr, val;
 983         int i ;
 984         struct crb_addr_pair *buf;
 985         unsigned long off;
 986         unsigned offset, n;
 987
 988         struct crb_addr_pair {
 989                 long addr;
 990                 long data;
 991         };
 992
 993         /* Halt all the indiviual PEGs and other blocks of the ISP */
 994         qla4_82xx_rom_lock(ha);
 995
 996         /* disable all I2Q */
 997         qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0);
 998         qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0);
 999         qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0);
1000         qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0);
1001         qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0);
1002         qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0);
1003
1004         /* disable all niu interrupts */
1005         qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff);
1006         /* disable xge rx/tx */
1007         qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00);
1008         /* disable xg1 rx/tx */
1009         qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00);
1010         /* disable sideband mac */
1011         qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00);
1012         /* disable ap0 mac */
1013         qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00);
1014         /* disable ap1 mac */
1015         qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00);
1016
1017         /* halt sre */
1018         val = qla4_82xx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000);
1019         qla4_82xx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1)));
1020
1021         /* halt epg */
1022         qla4_82xx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1);
1023
1024         /* halt timers */
1025         qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0);
1026         qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0);
1027         qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0);
1028         qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0);
1029         qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0);
1030         qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0);
1031
1032         /* halt pegs */
1033         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1);
1034         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1);
1035         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1);
1036         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1);
1037         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1);
1038         msleep(5);
1039
1040         /* big hammer */
1041         if (test_bit(DPC_RESET_HA, &ha->dpc_flags))
1042                 /* don't reset CAM block on reset */
1043                 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff);
1044         else
1045                 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff);
1046
1047         qla4_82xx_rom_unlock(ha);
1048
1049         /* Read the signature value from the flash.
1050          * Offset 0: Contain signature (0xcafecafe)
1051          * Offset 4: Offset and number of addr/value pairs
1052          * that present in CRB initialize sequence
1053          */
1054         if (qla4_82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL ||
1055             qla4_82xx_rom_fast_read(ha, 4, &n) != 0) {
1056                 ql4_printk(KERN_WARNING, ha,
1057                         "[ERROR] Reading crb_init area: n: %08x\n", n);
1058                 return -1;
1059         }
1060
1061         /* Offset in flash = lower 16 bits
1062          * Number of enteries = upper 16 bits
1063          */
1064         offset = n & 0xffffU;
1065         n = (n >> 16) & 0xffffU;
1066
1067         /* number of addr/value pair should not exceed 1024 enteries */
1068         if (n  >= 1024) {
1069                 ql4_printk(KERN_WARNING, ha,
1070                     "%s: %s:n=0x%x [ERROR] Card flash not initialized.\n",
1071                     DRIVER_NAME, __func__, n);
1072                 return -1;
1073         }
1074
1075         ql4_printk(KERN_INFO, ha,
1076                 "%s: %d CRB init values found in ROM.\n", DRIVER_NAME, n);
1077
1078         buf = kmalloc(n * sizeof(struct crb_addr_pair), GFP_KERNEL);
1079         if (buf == NULL) {
1080                 ql4_printk(KERN_WARNING, ha,
1081                     "%s: [ERROR] Unable to malloc memory.\n", DRIVER_NAME);
1082                 return -1;
1083         }
1084
1085         for (i = 0; i < n; i++) {
1086                 if (qla4_82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 ||
1087                     qla4_82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) !=
1088                     0) {
1089                         kfree(buf);
1090                         return -1;
1091                 }
1092
1093                 buf[i].addr = addr;
1094                 buf[i].data = val;
1095         }
1096
1097         for (i = 0; i < n; i++) {
1098                 /* Translate internal CRB initialization
1099                  * address to PCI bus address
1100                  */
1101                 off = qla4_82xx_decode_crb_addr((unsigned long)buf[i].addr) +
1102                     QLA82XX_PCI_CRBSPACE;
1103                 /* Not all CRB  addr/value pair to be written,
1104                  * some of them are skipped
1105                  */
1106
1107                 /* skip if LS bit is set*/
1108                 if (off & 0x1) {
1109                         DEBUG2(ql4_printk(KERN_WARNING, ha,
1110                             "Skip CRB init replay for offset = 0x%lx\n", off));
1111                         continue;
1112                 }
1113
1114                 /* skipping cold reboot MAGIC */
1115                 if (off == QLA82XX_CAM_RAM(0x1fc))
1116                         continue;
1117
1118                 /* do not reset PCI */
1119                 if (off == (ROMUSB_GLB + 0xbc))
1120                         continue;
1121
1122                 /* skip core clock, so that firmware can increase the clock */
1123                 if (off == (ROMUSB_GLB + 0xc8))
1124                         continue;
1125
1126                 /* skip the function enable register */
1127                 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION))
1128                         continue;
1129
1130                 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2))
1131                         continue;
1132
1133                 if ((off & 0x0ff00000) == QLA82XX_CRB_SMB)
1134                         continue;
1135
1136                 if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET)
1137                         continue;
1138
1139                 if (off == ADDR_ERROR) {
1140                         ql4_printk(KERN_WARNING, ha,
1141                             "%s: [ERROR] Unknown addr: 0x%08lx\n",
1142                             DRIVER_NAME, buf[i].addr);
1143                         continue;
1144                 }
1145
1146                 qla4_82xx_wr_32(ha, off, buf[i].data);
1147
1148                 /* ISP requires much bigger delay to settle down,
1149                  * else crb_window returns 0xffffffff
1150                  */
1151                 if (off == QLA82XX_ROMUSB_GLB_SW_RESET)
1152                         msleep(1000);
1153
1154                 /* ISP requires millisec delay between
1155                  * successive CRB register updation
1156                  */
1157                 msleep(1);
1158         }
1159
1160         kfree(buf);
1161
1162         /* Resetting the data and instruction cache */
1163         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e);
1164         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8);
1165         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8);
1166
1167         /* Clear all protocol processing engines */
1168         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0);
1169         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0);
1170         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0);
1171         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0);
1172         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0);
1173         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0);
1174         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0);
1175         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0);
1176
1177         return 0;
1178 }
1179
1180 static int
1181 qla4_82xx_load_from_flash(struct scsi_qla_host *ha, uint32_t image_start)
1182 {
1183         int  i, rval = 0;
1184         long size = 0;
1185         long flashaddr, memaddr;
1186         u64 data;
1187         u32 high, low;
1188
1189         flashaddr = memaddr = ha->hw.flt_region_bootload;
1190         size = (image_start - flashaddr) / 8;
1191
1192         DEBUG2(printk("scsi%ld: %s: bootldr=0x%lx, fw_image=0x%x\n",
1193             ha->host_no, __func__, flashaddr, image_start));
1194
1195         for (i = 0; i < size; i++) {
1196                 if ((qla4_82xx_rom_fast_read(ha, flashaddr, (int *)&low)) ||
1197                     (qla4_82xx_rom_fast_read(ha, flashaddr + 4,
1198                     (int *)&high))) {
1199                         rval = -1;
1200                         goto exit_load_from_flash;
1201                 }
1202                 data = ((u64)high << 32) | low ;
1203                 rval = qla4_82xx_pci_mem_write_2M(ha, memaddr, &data, 8);
1204                 if (rval)
1205                         goto exit_load_from_flash;
1206
1207                 flashaddr += 8;
1208                 memaddr   += 8;
1209
1210                 if (i % 0x1000 == 0)
1211                         msleep(1);
1212
1213         }
1214
1215         udelay(100);
1216
1217         read_lock(&ha->hw_lock);
1218         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020);
1219         qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e);
1220         read_unlock(&ha->hw_lock);
1221
1222 exit_load_from_flash:
1223         return rval;
1224 }
1225
1226 static int qla4_82xx_load_fw(struct scsi_qla_host *ha, uint32_t image_start)
1227 {
1228         u32 rst;
1229
1230         qla4_82xx_wr_32(ha, CRB_CMDPEG_STATE, 0);
1231         if (qla4_82xx_pinit_from_rom(ha, 0) != QLA_SUCCESS) {
1232                 printk(KERN_WARNING "%s: Error during CRB Initialization\n",
1233                     __func__);
1234                 return QLA_ERROR;
1235         }
1236
1237         udelay(500);
1238
1239         /* at this point, QM is in reset. This could be a problem if there are
1240          * incoming d* transition queue messages. QM/PCIE could wedge.
1241          * To get around this, QM is brought out of reset.
1242          */
1243
1244         rst = qla4_82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET);
1245         /* unreset qm */
1246         rst &= ~(1 << 28);
1247         qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst);
1248
1249         if (qla4_82xx_load_from_flash(ha, image_start)) {
1250                 printk("%s: Error trying to load fw from flash!\n", __func__);
1251                 return QLA_ERROR;
1252         }
1253
1254         return QLA_SUCCESS;
1255 }
1256
1257 int
1258 qla4_82xx_pci_mem_read_2M(struct scsi_qla_host *ha,
1259                 u64 off, void *data, int size)
1260 {
1261         int i, j = 0, k, start, end, loop, sz[2], off0[2];
1262         int shift_amount;
1263         uint32_t temp;
1264         uint64_t off8, val, mem_crb, word[2] = {0, 0};
1265
1266         /*
1267          * If not MN, go check for MS or invalid.
1268          */
1269
1270         if (off >= QLA8XXX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
1271                 mem_crb = QLA82XX_CRB_QDR_NET;
1272         else {
1273                 mem_crb = QLA82XX_CRB_DDR_NET;
1274                 if (qla4_82xx_pci_mem_bound_check(ha, off, size) == 0)
1275                         return qla4_82xx_pci_mem_read_direct(ha,
1276                                         off, data, size);
1277         }
1278
1279
1280         off8 = off & 0xfffffff0;
1281         off0[0] = off & 0xf;
1282         sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]);
1283         shift_amount = 4;
1284
1285         loop = ((off0[0] + size - 1) >> shift_amount) + 1;
1286         off0[1] = 0;
1287         sz[1] = size - sz[0];
1288
1289         for (i = 0; i < loop; i++) {
1290                 temp = off8 + (i << shift_amount);
1291                 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp);
1292                 temp = 0;
1293                 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp);
1294                 temp = MIU_TA_CTL_ENABLE;
1295                 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1296                 temp = MIU_TA_CTL_START_ENABLE;
1297                 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1298
1299                 for (j = 0; j < MAX_CTL_CHECK; j++) {
1300                         temp = qla4_82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
1301                         if ((temp & MIU_TA_CTL_BUSY) == 0)
1302                                 break;
1303                 }
1304
1305                 if (j >= MAX_CTL_CHECK) {
1306                         printk_ratelimited(KERN_ERR
1307                                            "%s: failed to read through agent\n",
1308                                            __func__);
1309                         break;
1310                 }
1311
1312                 start = off0[i] >> 2;
1313                 end   = (off0[i] + sz[i] - 1) >> 2;
1314                 for (k = start; k <= end; k++) {
1315                         temp = qla4_82xx_rd_32(ha,
1316                                 mem_crb + MIU_TEST_AGT_RDDATA(k));
1317                         word[i] |= ((uint64_t)temp << (32 * (k & 1)));
1318                 }
1319         }
1320
1321         if (j >= MAX_CTL_CHECK)
1322                 return -1;
1323
1324         if ((off0[0] & 7) == 0) {
1325                 val = word[0];
1326         } else {
1327                 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1328                 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1329         }
1330
1331         switch (size) {
1332         case 1:
1333                 *(uint8_t  *)data = val;
1334                 break;
1335         case 2:
1336                 *(uint16_t *)data = val;
1337                 break;
1338         case 4:
1339                 *(uint32_t *)data = val;
1340                 break;
1341         case 8:
1342                 *(uint64_t *)data = val;
1343                 break;
1344         }
1345         return 0;
1346 }
1347
1348 int
1349 qla4_82xx_pci_mem_write_2M(struct scsi_qla_host *ha,
1350                 u64 off, void *data, int size)
1351 {
1352         int i, j, ret = 0, loop, sz[2], off0;
1353         int scale, shift_amount, startword;
1354         uint32_t temp;
1355         uint64_t off8, mem_crb, tmpw, word[2] = {0, 0};
1356
1357         /*
1358          * If not MN, go check for MS or invalid.
1359          */
1360         if (off >= QLA8XXX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
1361                 mem_crb = QLA82XX_CRB_QDR_NET;
1362         else {
1363                 mem_crb = QLA82XX_CRB_DDR_NET;
1364                 if (qla4_82xx_pci_mem_bound_check(ha, off, size) == 0)
1365                         return qla4_82xx_pci_mem_write_direct(ha,
1366                                         off, data, size);
1367         }
1368
1369         off0 = off & 0x7;
1370         sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1371         sz[1] = size - sz[0];
1372
1373         off8 = off & 0xfffffff0;
1374         loop = (((off & 0xf) + size - 1) >> 4) + 1;
1375         shift_amount = 4;
1376         scale = 2;
1377         startword = (off & 0xf)/8;
1378
1379         for (i = 0; i < loop; i++) {
1380                 if (qla4_82xx_pci_mem_read_2M(ha, off8 +
1381                     (i << shift_amount), &word[i * scale], 8))
1382                         return -1;
1383         }
1384
1385         switch (size) {
1386         case 1:
1387                 tmpw = *((uint8_t *)data);
1388                 break;
1389         case 2:
1390                 tmpw = *((uint16_t *)data);
1391                 break;
1392         case 4:
1393                 tmpw = *((uint32_t *)data);
1394                 break;
1395         case 8:
1396         default:
1397                 tmpw = *((uint64_t *)data);
1398                 break;
1399         }
1400
1401         if (sz[0] == 8)
1402                 word[startword] = tmpw;
1403         else {
1404                 word[startword] &=
1405                     ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1406                 word[startword] |= tmpw << (off0 * 8);
1407         }
1408
1409         if (sz[1] != 0) {
1410                 word[startword+1] &= ~(~0ULL << (sz[1] * 8));
1411                 word[startword+1] |= tmpw >> (sz[0] * 8);
1412         }
1413
1414         for (i = 0; i < loop; i++) {
1415                 temp = off8 + (i << shift_amount);
1416                 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp);
1417                 temp = 0;
1418                 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp);
1419                 temp = word[i * scale] & 0xffffffff;
1420                 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp);
1421                 temp = (word[i * scale] >> 32) & 0xffffffff;
1422                 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp);
1423                 temp = word[i*scale + 1] & 0xffffffff;
1424                 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_LO,
1425                     temp);
1426                 temp = (word[i*scale + 1] >> 32) & 0xffffffff;
1427                 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_HI,
1428                     temp);
1429
1430                 temp = MIU_TA_CTL_WRITE_ENABLE;
1431                 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp);
1432                 temp = MIU_TA_CTL_WRITE_START;
1433                 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp);
1434
1435                 for (j = 0; j < MAX_CTL_CHECK; j++) {
1436                         temp = qla4_82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
1437                         if ((temp & MIU_TA_CTL_BUSY) == 0)
1438                                 break;
1439                 }
1440
1441                 if (j >= MAX_CTL_CHECK) {
1442                         if (printk_ratelimit())
1443                                 ql4_printk(KERN_ERR, ha,
1444                                            "%s: failed to read through agent\n",
1445                                            __func__);
1446                         ret = -1;
1447                         break;
1448                 }
1449         }
1450
1451         return ret;
1452 }
1453
1454 static int qla4_82xx_cmdpeg_ready(struct scsi_qla_host *ha, int pegtune_val)
1455 {
1456         u32 val = 0;
1457         int retries = 60;
1458
1459         if (!pegtune_val) {
1460                 do {
1461                         val = qla4_82xx_rd_32(ha, CRB_CMDPEG_STATE);
1462                         if ((val == PHAN_INITIALIZE_COMPLETE) ||
1463                             (val == PHAN_INITIALIZE_ACK))
1464                                 return 0;
1465                         set_current_state(TASK_UNINTERRUPTIBLE);
1466                         schedule_timeout(500);
1467
1468                 } while (--retries);
1469
1470                 if (!retries) {
1471                         pegtune_val = qla4_82xx_rd_32(ha,
1472                                 QLA82XX_ROMUSB_GLB_PEGTUNE_DONE);
1473                         printk(KERN_WARNING "%s: init failed, "
1474                                 "pegtune_val = %x\n", __func__, pegtune_val);
1475                         return -1;
1476                 }
1477         }
1478         return 0;
1479 }
1480
1481 static int qla4_82xx_rcvpeg_ready(struct scsi_qla_host *ha)
1482 {
1483         uint32_t state = 0;
1484         int loops = 0;
1485
1486         /* Window 1 call */
1487         read_lock(&ha->hw_lock);
1488         state = qla4_82xx_rd_32(ha, CRB_RCVPEG_STATE);
1489         read_unlock(&ha->hw_lock);
1490
1491         while ((state != PHAN_PEG_RCV_INITIALIZED) && (loops < 30000)) {
1492                 udelay(100);
1493                 /* Window 1 call */
1494                 read_lock(&ha->hw_lock);
1495                 state = qla4_82xx_rd_32(ha, CRB_RCVPEG_STATE);
1496                 read_unlock(&ha->hw_lock);
1497
1498                 loops++;
1499         }
1500
1501         if (loops >= 30000) {
1502                 DEBUG2(ql4_printk(KERN_INFO, ha,
1503                     "Receive Peg initialization not complete: 0x%x.\n", state));
1504                 return QLA_ERROR;
1505         }
1506
1507         return QLA_SUCCESS;
1508 }
1509
1510 void
1511 qla4_8xxx_set_drv_active(struct scsi_qla_host *ha)
1512 {
1513         uint32_t drv_active;
1514
1515         drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
1516
1517         /*
1518          * For ISP8324 and ISP8042, drv_active register has 1 bit per function,
1519          * shift 1 by func_num to set a bit for the function.
1520          * For ISP8022, drv_active has 4 bits per function
1521          */
1522         if (is_qla8032(ha) || is_qla8042(ha))
1523                 drv_active |= (1 << ha->func_num);
1524         else
1525                 drv_active |= (1 << (ha->func_num * 4));
1526
1527         ql4_printk(KERN_INFO, ha, "%s(%ld): drv_active: 0x%08x\n",
1528                    __func__, ha->host_no, drv_active);
1529         qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_ACTIVE, drv_active);
1530 }
1531
1532 void
1533 qla4_8xxx_clear_drv_active(struct scsi_qla_host *ha)
1534 {
1535         uint32_t drv_active;
1536
1537         drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
1538
1539         /*
1540          * For ISP8324 and ISP8042, drv_active register has 1 bit per function,
1541          * shift 1 by func_num to set a bit for the function.
1542          * For ISP8022, drv_active has 4 bits per function
1543          */
1544         if (is_qla8032(ha) || is_qla8042(ha))
1545                 drv_active &= ~(1 << (ha->func_num));
1546         else
1547                 drv_active &= ~(1 << (ha->func_num * 4));
1548
1549         ql4_printk(KERN_INFO, ha, "%s(%ld): drv_active: 0x%08x\n",
1550                    __func__, ha->host_no, drv_active);
1551         qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_ACTIVE, drv_active);
1552 }
1553
1554 inline int qla4_8xxx_need_reset(struct scsi_qla_host *ha)
1555 {
1556         uint32_t drv_state, drv_active;
1557         int rval;
1558
1559         drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
1560         drv_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE);
1561
1562         /*
1563          * For ISP8324 and ISP8042, drv_active register has 1 bit per function,
1564          * shift 1 by func_num to set a bit for the function.
1565          * For ISP8022, drv_active has 4 bits per function
1566          */
1567         if (is_qla8032(ha) || is_qla8042(ha))
1568                 rval = drv_state & (1 << ha->func_num);
1569         else
1570                 rval = drv_state & (1 << (ha->func_num * 4));
1571
1572         if ((test_bit(AF_EEH_BUSY, &ha->flags)) && drv_active)
1573                 rval = 1;
1574
1575         return rval;
1576 }
1577
1578 void qla4_8xxx_set_rst_ready(struct scsi_qla_host *ha)
1579 {
1580         uint32_t drv_state;
1581
1582         drv_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE);
1583
1584         /*
1585          * For ISP8324 and ISP8042, drv_active register has 1 bit per function,
1586          * shift 1 by func_num to set a bit for the function.
1587          * For ISP8022, drv_active has 4 bits per function
1588          */
1589         if (is_qla8032(ha) || is_qla8042(ha))
1590                 drv_state |= (1 << ha->func_num);
1591         else
1592                 drv_state |= (1 << (ha->func_num * 4));
1593
1594         ql4_printk(KERN_INFO, ha, "%s(%ld): drv_state: 0x%08x\n",
1595                    __func__, ha->host_no, drv_state);
1596         qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_STATE, drv_state);
1597 }
1598
1599 void qla4_8xxx_clear_rst_ready(struct scsi_qla_host *ha)
1600 {
1601         uint32_t drv_state;
1602
1603         drv_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE);
1604
1605         /*
1606          * For ISP8324 and ISP8042, drv_active register has 1 bit per function,
1607          * shift 1 by func_num to set a bit for the function.
1608          * For ISP8022, drv_active has 4 bits per function
1609          */
1610         if (is_qla8032(ha) || is_qla8042(ha))
1611                 drv_state &= ~(1 << ha->func_num);
1612         else
1613                 drv_state &= ~(1 << (ha->func_num * 4));
1614
1615         ql4_printk(KERN_INFO, ha, "%s(%ld): drv_state: 0x%08x\n",
1616                    __func__, ha->host_no, drv_state);
1617         qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_STATE, drv_state);
1618 }
1619
1620 static inline void
1621 qla4_8xxx_set_qsnt_ready(struct scsi_qla_host *ha)
1622 {
1623         uint32_t qsnt_state;
1624
1625         qsnt_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE);
1626
1627         /*
1628          * For ISP8324 and ISP8042, drv_active register has 1 bit per function,
1629          * shift 1 by func_num to set a bit for the function.
1630          * For ISP8022, drv_active has 4 bits per function.
1631          */
1632         if (is_qla8032(ha) || is_qla8042(ha))
1633                 qsnt_state |= (1 << ha->func_num);
1634         else
1635                 qsnt_state |= (2 << (ha->func_num * 4));
1636
1637         qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_STATE, qsnt_state);
1638 }
1639
1640
1641 static int
1642 qla4_82xx_start_firmware(struct scsi_qla_host *ha, uint32_t image_start)
1643 {
1644         uint16_t lnk;
1645
1646         /* scrub dma mask expansion register */
1647         qla4_82xx_wr_32(ha, CRB_DMA_SHIFT, 0x55555555);
1648
1649         /* Overwrite stale initialization register values */
1650         qla4_82xx_wr_32(ha, CRB_CMDPEG_STATE, 0);
1651         qla4_82xx_wr_32(ha, CRB_RCVPEG_STATE, 0);
1652         qla4_82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0);
1653         qla4_82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0);
1654
1655         if (qla4_82xx_load_fw(ha, image_start) != QLA_SUCCESS) {
1656                 printk("%s: Error trying to start fw!\n", __func__);
1657                 return QLA_ERROR;
1658         }
1659
1660         /* Handshake with the card before we register the devices. */
1661         if (qla4_82xx_cmdpeg_ready(ha, 0) != QLA_SUCCESS) {
1662                 printk("%s: Error during card handshake!\n", __func__);
1663                 return QLA_ERROR;
1664         }
1665
1666         /* Negotiated Link width */
1667         pcie_capability_read_word(ha->pdev, PCI_EXP_LNKSTA, &lnk);
1668         ha->link_width = (lnk >> 4) & 0x3f;
1669
1670         /* Synchronize with Receive peg */
1671         return qla4_82xx_rcvpeg_ready(ha);
1672 }
1673
1674 int qla4_82xx_try_start_fw(struct scsi_qla_host *ha)
1675 {
1676         int rval = QLA_ERROR;
1677
1678         /*
1679          * FW Load priority:
1680          * 1) Operational firmware residing in flash.
1681          * 2) Fail
1682          */
1683
1684         ql4_printk(KERN_INFO, ha,
1685             "FW: Retrieving flash offsets from FLT/FDT ...\n");
1686         rval = qla4_8xxx_get_flash_info(ha);
1687         if (rval != QLA_SUCCESS)
1688                 return rval;
1689
1690         ql4_printk(KERN_INFO, ha,
1691             "FW: Attempting to load firmware from flash...\n");
1692         rval = qla4_82xx_start_firmware(ha, ha->hw.flt_region_fw);
1693
1694         if (rval != QLA_SUCCESS) {
1695                 ql4_printk(KERN_ERR, ha, "FW: Load firmware from flash"
1696                     " FAILED...\n");
1697                 return rval;
1698         }
1699
1700         return rval;
1701 }
1702
1703 void qla4_82xx_rom_lock_recovery(struct scsi_qla_host *ha)
1704 {
1705         if (qla4_82xx_rom_lock(ha)) {
1706                 /* Someone else is holding the lock. */
1707                 dev_info(&ha->pdev->dev, "Resetting rom_lock\n");
1708         }
1709
1710         /*
1711          * Either we got the lock, or someone
1712          * else died while holding it.
1713          * In either case, unlock.
1714          */
1715         qla4_82xx_rom_unlock(ha);
1716 }
1717
1718 static uint32_t ql4_84xx_poll_wait_for_ready(struct scsi_qla_host *ha,
1719                                              uint32_t addr1, uint32_t mask)
1720 {
1721         unsigned long timeout;
1722         uint32_t rval = QLA_SUCCESS;
1723         uint32_t temp;
1724
1725         timeout = jiffies + msecs_to_jiffies(TIMEOUT_100_MS);
1726         do {
1727                 ha->isp_ops->rd_reg_indirect(ha, addr1, &temp);
1728                 if ((temp & mask) != 0)
1729                         break;
1730
1731                 if (time_after_eq(jiffies, timeout)) {
1732                         ql4_printk(KERN_INFO, ha, "Error in processing rdmdio entry\n");
1733                         return QLA_ERROR;
1734                 }
1735         } while (1);
1736
1737         return rval;
1738 }
1739
1740 uint32_t ql4_84xx_ipmdio_rd_reg(struct scsi_qla_host *ha, uint32_t addr1,
1741                                 uint32_t addr3, uint32_t mask, uint32_t addr,
1742                                 uint32_t *data_ptr)
1743 {
1744         int rval = QLA_SUCCESS;
1745         uint32_t temp;
1746         uint32_t data;
1747
1748         rval = ql4_84xx_poll_wait_for_ready(ha, addr1, mask);
1749         if (rval)
1750                 goto exit_ipmdio_rd_reg;
1751
1752         temp = (0x40000000 | addr);
1753         ha->isp_ops->wr_reg_indirect(ha, addr1, temp);
1754
1755         rval = ql4_84xx_poll_wait_for_ready(ha, addr1, mask);
1756         if (rval)
1757                 goto exit_ipmdio_rd_reg;
1758
1759         ha->isp_ops->rd_reg_indirect(ha, addr3, &data);
1760         *data_ptr = data;
1761
1762 exit_ipmdio_rd_reg:
1763         return rval;
1764 }
1765
1766
1767 static uint32_t ql4_84xx_poll_wait_ipmdio_bus_idle(struct scsi_qla_host *ha,
1768                                                     uint32_t addr1,
1769                                                     uint32_t addr2,
1770                                                     uint32_t addr3,
1771                                                     uint32_t mask)
1772 {
1773         unsigned long timeout;
1774         uint32_t temp;
1775         uint32_t rval = QLA_SUCCESS;
1776
1777         timeout = jiffies + msecs_to_jiffies(TIMEOUT_100_MS);
1778         do {
1779                 ql4_84xx_ipmdio_rd_reg(ha, addr1, addr3, mask, addr2, &temp);
1780                 if ((temp & 0x1) != 1)
1781                         break;
1782                 if (time_after_eq(jiffies, timeout)) {
1783                         ql4_printk(KERN_INFO, ha, "Error in processing mdiobus idle\n");
1784                         return QLA_ERROR;
1785                 }
1786         } while (1);
1787
1788         return rval;
1789 }
1790
1791 static int ql4_84xx_ipmdio_wr_reg(struct scsi_qla_host *ha,
1792                                   uint32_t addr1, uint32_t addr3,
1793                                   uint32_t mask, uint32_t addr,
1794                                   uint32_t value)
1795 {
1796         int rval = QLA_SUCCESS;
1797
1798         rval = ql4_84xx_poll_wait_for_ready(ha, addr1, mask);
1799         if (rval)
1800                 goto exit_ipmdio_wr_reg;
1801
1802         ha->isp_ops->wr_reg_indirect(ha, addr3, value);
1803         ha->isp_ops->wr_reg_indirect(ha, addr1, addr);
1804
1805         rval = ql4_84xx_poll_wait_for_ready(ha, addr1, mask);
1806         if (rval)
1807                 goto exit_ipmdio_wr_reg;
1808
1809 exit_ipmdio_wr_reg:
1810         return rval;
1811 }
1812
1813 static void qla4_8xxx_minidump_process_rdcrb(struct scsi_qla_host *ha,
1814                                 struct qla8xxx_minidump_entry_hdr *entry_hdr,
1815                                 uint32_t **d_ptr)
1816 {
1817         uint32_t r_addr, r_stride, loop_cnt, i, r_value;
1818         struct qla8xxx_minidump_entry_crb *crb_hdr;
1819         uint32_t *data_ptr = *d_ptr;
1820
1821         DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
1822         crb_hdr = (struct qla8xxx_minidump_entry_crb *)entry_hdr;
1823         r_addr = crb_hdr->addr;
1824         r_stride = crb_hdr->crb_strd.addr_stride;
1825         loop_cnt = crb_hdr->op_count;
1826
1827         for (i = 0; i < loop_cnt; i++) {
1828                 ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value);
1829                 *data_ptr++ = cpu_to_le32(r_addr);
1830                 *data_ptr++ = cpu_to_le32(r_value);
1831                 r_addr += r_stride;
1832         }
1833         *d_ptr = data_ptr;
1834 }
1835
1836 static int qla4_83xx_check_dma_engine_state(struct scsi_qla_host *ha)
1837 {
1838         int rval = QLA_SUCCESS;
1839         uint32_t dma_eng_num = 0, cmd_sts_and_cntrl = 0;
1840         uint64_t dma_base_addr = 0;
1841         struct qla4_8xxx_minidump_template_hdr *tmplt_hdr = NULL;
1842
1843         tmplt_hdr = (struct qla4_8xxx_minidump_template_hdr *)
1844                                                         ha->fw_dump_tmplt_hdr;
1845         dma_eng_num =
1846                 tmplt_hdr->saved_state_array[QLA83XX_PEX_DMA_ENGINE_INDEX];
1847         dma_base_addr = QLA83XX_PEX_DMA_BASE_ADDRESS +
1848                                 (dma_eng_num * QLA83XX_PEX_DMA_NUM_OFFSET);
1849
1850         /* Read the pex-dma's command-status-and-control register. */
1851         rval = ha->isp_ops->rd_reg_indirect(ha,
1852                         (dma_base_addr + QLA83XX_PEX_DMA_CMD_STS_AND_CNTRL),
1853                         &cmd_sts_and_cntrl);
1854
1855         if (rval)
1856                 return QLA_ERROR;
1857
1858         /* Check if requested pex-dma engine is available. */
1859         if (cmd_sts_and_cntrl & BIT_31)
1860                 return QLA_SUCCESS;
1861         else
1862                 return QLA_ERROR;
1863 }
1864
1865 static int qla4_83xx_start_pex_dma(struct scsi_qla_host *ha,
1866                            struct qla4_83xx_minidump_entry_rdmem_pex_dma *m_hdr)
1867 {
1868         int rval = QLA_SUCCESS, wait = 0;
1869         uint32_t dma_eng_num = 0, cmd_sts_and_cntrl = 0;
1870         uint64_t dma_base_addr = 0;
1871         struct qla4_8xxx_minidump_template_hdr *tmplt_hdr = NULL;
1872
1873         tmplt_hdr = (struct qla4_8xxx_minidump_template_hdr *)
1874                                                         ha->fw_dump_tmplt_hdr;
1875         dma_eng_num =
1876                 tmplt_hdr->saved_state_array[QLA83XX_PEX_DMA_ENGINE_INDEX];
1877         dma_base_addr = QLA83XX_PEX_DMA_BASE_ADDRESS +
1878                                 (dma_eng_num * QLA83XX_PEX_DMA_NUM_OFFSET);
1879
1880         rval = ha->isp_ops->wr_reg_indirect(ha,
1881                                 dma_base_addr + QLA83XX_PEX_DMA_CMD_ADDR_LOW,
1882                                 m_hdr->desc_card_addr);
1883         if (rval)
1884                 goto error_exit;
1885
1886         rval = ha->isp_ops->wr_reg_indirect(ha,
1887                               dma_base_addr + QLA83XX_PEX_DMA_CMD_ADDR_HIGH, 0);
1888         if (rval)
1889                 goto error_exit;
1890
1891         rval = ha->isp_ops->wr_reg_indirect(ha,
1892                               dma_base_addr + QLA83XX_PEX_DMA_CMD_STS_AND_CNTRL,
1893                               m_hdr->start_dma_cmd);
1894         if (rval)
1895                 goto error_exit;
1896
1897         /* Wait for dma operation to complete. */
1898         for (wait = 0; wait < QLA83XX_PEX_DMA_MAX_WAIT; wait++) {
1899                 rval = ha->isp_ops->rd_reg_indirect(ha,
1900                             (dma_base_addr + QLA83XX_PEX_DMA_CMD_STS_AND_CNTRL),
1901                             &cmd_sts_and_cntrl);
1902                 if (rval)
1903                         goto error_exit;
1904
1905                 if ((cmd_sts_and_cntrl & BIT_1) == 0)
1906                         break;
1907                 else
1908                         udelay(10);
1909         }
1910
1911         /* Wait a max of 100 ms, otherwise fallback to rdmem entry read */
1912         if (wait >= QLA83XX_PEX_DMA_MAX_WAIT) {
1913                 rval = QLA_ERROR;
1914                 goto error_exit;
1915         }
1916
1917 error_exit:
1918         return rval;
1919 }
1920
1921 static int qla4_8xxx_minidump_pex_dma_read(struct scsi_qla_host *ha,
1922                                 struct qla8xxx_minidump_entry_hdr *entry_hdr,
1923                                 uint32_t **d_ptr)
1924 {
1925         int rval = QLA_SUCCESS;
1926         struct qla4_83xx_minidump_entry_rdmem_pex_dma *m_hdr = NULL;
1927         uint32_t size, read_size;
1928         uint8_t *data_ptr = (uint8_t *)*d_ptr;
1929         void *rdmem_buffer = NULL;
1930         dma_addr_t rdmem_dma;
1931         struct qla4_83xx_pex_dma_descriptor dma_desc;
1932
1933         DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
1934
1935         rval = qla4_83xx_check_dma_engine_state(ha);
1936         if (rval != QLA_SUCCESS) {
1937                 DEBUG2(ql4_printk(KERN_INFO, ha,
1938                                   "%s: DMA engine not available. Fallback to rdmem-read.\n",
1939                                   __func__));
1940                 return QLA_ERROR;
1941         }
1942
1943         m_hdr = (struct qla4_83xx_minidump_entry_rdmem_pex_dma *)entry_hdr;
1944         rdmem_buffer = dma_alloc_coherent(&ha->pdev->dev,
1945                                           QLA83XX_PEX_DMA_READ_SIZE,
1946                                           &rdmem_dma, GFP_KERNEL);
1947         if (!rdmem_buffer) {
1948                 DEBUG2(ql4_printk(KERN_INFO, ha,
1949                                   "%s: Unable to allocate rdmem dma buffer\n",
1950                                   __func__));
1951                 return QLA_ERROR;
1952         }
1953
1954         /* Prepare pex-dma descriptor to be written to MS memory. */
1955         /* dma-desc-cmd layout:
1956          *              0-3: dma-desc-cmd 0-3
1957          *              4-7: pcid function number
1958          *              8-15: dma-desc-cmd 8-15
1959          */
1960         dma_desc.cmd.dma_desc_cmd = (m_hdr->dma_desc_cmd & 0xff0f);
1961         dma_desc.cmd.dma_desc_cmd |= ((PCI_FUNC(ha->pdev->devfn) & 0xf) << 0x4);
1962         dma_desc.dma_bus_addr = rdmem_dma;
1963
1964         size = 0;
1965         read_size = 0;
1966         /*
1967          * Perform rdmem operation using pex-dma.
1968          * Prepare dma in chunks of QLA83XX_PEX_DMA_READ_SIZE.
1969          */
1970         while (read_size < m_hdr->read_data_size) {
1971                 if (m_hdr->read_data_size - read_size >=
1972                     QLA83XX_PEX_DMA_READ_SIZE)
1973                         size = QLA83XX_PEX_DMA_READ_SIZE;
1974                 else {
1975                         size = (m_hdr->read_data_size - read_size);
1976
1977                         if (rdmem_buffer)
1978                                 dma_free_coherent(&ha->pdev->dev,
1979                                                   QLA83XX_PEX_DMA_READ_SIZE,
1980                                                   rdmem_buffer, rdmem_dma);
1981
1982                         rdmem_buffer = dma_alloc_coherent(&ha->pdev->dev, size,
1983                                                           &rdmem_dma,
1984                                                           GFP_KERNEL);
1985                         if (!rdmem_buffer) {
1986                                 DEBUG2(ql4_printk(KERN_INFO, ha,
1987                                                   "%s: Unable to allocate rdmem dma buffer\n",
1988                                                   __func__));
1989                                 return QLA_ERROR;
1990                         }
1991                         dma_desc.dma_bus_addr = rdmem_dma;
1992                 }
1993
1994                 dma_desc.src_addr = m_hdr->read_addr + read_size;
1995                 dma_desc.cmd.read_data_size = size;
1996
1997                 /* Prepare: Write pex-dma descriptor to MS memory. */
1998                 rval = qla4_8xxx_ms_mem_write_128b(ha,
1999                               (uint64_t)m_hdr->desc_card_addr,
2000                               (uint32_t *)&dma_desc,
2001                               (sizeof(struct qla4_83xx_pex_dma_descriptor)/16));
2002                 if (rval == -1) {
2003                         ql4_printk(KERN_INFO, ha,
2004                                    "%s: Error writing rdmem-dma-init to MS !!!\n",
2005                                    __func__);
2006                         goto error_exit;
2007                 }
2008
2009                 DEBUG2(ql4_printk(KERN_INFO, ha,
2010                                   "%s: Dma-desc: Instruct for rdmem dma (size 0x%x).\n",
2011                                   __func__, size));
2012                 /* Execute: Start pex-dma operation. */
2013                 rval = qla4_83xx_start_pex_dma(ha, m_hdr);
2014                 if (rval != QLA_SUCCESS) {
2015                         DEBUG2(ql4_printk(KERN_INFO, ha,
2016                                           "scsi(%ld): start-pex-dma failed rval=0x%x\n",
2017                                           ha->host_no, rval));
2018                         goto error_exit;
2019                 }
2020
2021                 memcpy(data_ptr, rdmem_buffer, size);
2022                 data_ptr += size;
2023                 read_size += size;
2024         }
2025
2026         DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s\n", __func__));
2027
2028         *d_ptr = (uint32_t *)data_ptr;
2029
2030 error_exit:
2031         if (rdmem_buffer)
2032                 dma_free_coherent(&ha->pdev->dev, size, rdmem_buffer,
2033                                   rdmem_dma);
2034
2035         return rval;
2036 }
2037
2038 static int qla4_8xxx_minidump_process_l2tag(struct scsi_qla_host *ha,
2039                                  struct qla8xxx_minidump_entry_hdr *entry_hdr,
2040                                  uint32_t **d_ptr)
2041 {
2042         uint32_t addr, r_addr, c_addr, t_r_addr;
2043         uint32_t i, k, loop_count, t_value, r_cnt, r_value;
2044         unsigned long p_wait, w_time, p_mask;
2045         uint32_t c_value_w, c_value_r;
2046         struct qla8xxx_minidump_entry_cache *cache_hdr;
2047         int rval = QLA_ERROR;
2048         uint32_t *data_ptr = *d_ptr;
2049
2050         DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
2051         cache_hdr = (struct qla8xxx_minidump_entry_cache *)entry_hdr;
2052
2053         loop_count = cache_hdr->op_count;
2054         r_addr = cache_hdr->read_addr;
2055         c_addr = cache_hdr->control_addr;
2056         c_value_w = cache_hdr->cache_ctrl.write_value;
2057
2058         t_r_addr = cache_hdr->tag_reg_addr;
2059         t_value = cache_hdr->addr_ctrl.init_tag_value;
2060         r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
2061         p_wait = cache_hdr->cache_ctrl.poll_wait;
2062         p_mask = cache_hdr->cache_ctrl.poll_mask;
2063
2064         for (i = 0; i < loop_count; i++) {
2065                 ha->isp_ops->wr_reg_indirect(ha, t_r_addr, t_value);
2066
2067                 if (c_value_w)
2068                         ha->isp_ops->wr_reg_indirect(ha, c_addr, c_value_w);
2069
2070                 if (p_mask) {
2071                         w_time = jiffies + p_wait;
2072                         do {
2073                                 ha->isp_ops->rd_reg_indirect(ha, c_addr,
2074                                                              &c_value_r);
2075                                 if ((c_value_r & p_mask) == 0) {
2076                                         break;
2077                                 } else if (time_after_eq(jiffies, w_time)) {
2078                                         /* capturing dump failed */
2079                                         return rval;
2080                                 }
2081                         } while (1);
2082                 }
2083
2084                 addr = r_addr;
2085                 for (k = 0; k < r_cnt; k++) {
2086                         ha->isp_ops->rd_reg_indirect(ha, addr, &r_value);
2087                         *data_ptr++ = cpu_to_le32(r_value);
2088                         addr += cache_hdr->read_ctrl.read_addr_stride;
2089                 }
2090
2091                 t_value += cache_hdr->addr_ctrl.tag_value_stride;
2092         }
2093         *d_ptr = data_ptr;
2094         return QLA_SUCCESS;
2095 }
2096
2097 static int qla4_8xxx_minidump_process_control(struct scsi_qla_host *ha,
2098                                 struct qla8xxx_minidump_entry_hdr *entry_hdr)
2099 {
2100         struct qla8xxx_minidump_entry_crb *crb_entry;
2101         uint32_t read_value, opcode, poll_time, addr, index, rval = QLA_SUCCESS;
2102         uint32_t crb_addr;
2103         unsigned long wtime;
2104         struct qla4_8xxx_minidump_template_hdr *tmplt_hdr;
2105         int i;
2106
2107         DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
2108         tmplt_hdr = (struct qla4_8xxx_minidump_template_hdr *)
2109                                                 ha->fw_dump_tmplt_hdr;
2110         crb_entry = (struct qla8xxx_minidump_entry_crb *)entry_hdr;
2111
2112         crb_addr = crb_entry->addr;
2113         for (i = 0; i < crb_entry->op_count; i++) {
2114                 opcode = crb_entry->crb_ctrl.opcode;
2115                 if (opcode & QLA8XXX_DBG_OPCODE_WR) {
2116                         ha->isp_ops->wr_reg_indirect(ha, crb_addr,
2117                                                      crb_entry->value_1);
2118                         opcode &= ~QLA8XXX_DBG_OPCODE_WR;
2119                 }
2120                 if (opcode & QLA8XXX_DBG_OPCODE_RW) {
2121                         ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value);
2122                         ha->isp_ops->wr_reg_indirect(ha, crb_addr, read_value);
2123                         opcode &= ~QLA8XXX_DBG_OPCODE_RW;
2124                 }
2125                 if (opcode & QLA8XXX_DBG_OPCODE_AND) {
2126                         ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value);
2127                         read_value &= crb_entry->value_2;
2128                         opcode &= ~QLA8XXX_DBG_OPCODE_AND;
2129                         if (opcode & QLA8XXX_DBG_OPCODE_OR) {
2130                                 read_value |= crb_entry->value_3;
2131                                 opcode &= ~QLA8XXX_DBG_OPCODE_OR;
2132                         }
2133                         ha->isp_ops->wr_reg_indirect(ha, crb_addr, read_value);
2134                 }
2135                 if (opcode & QLA8XXX_DBG_OPCODE_OR) {
2136                         ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value);
2137                         read_value |= crb_entry->value_3;
2138                         ha->isp_ops->wr_reg_indirect(ha, crb_addr, read_value);
2139                         opcode &= ~QLA8XXX_DBG_OPCODE_OR;
2140                 }
2141                 if (opcode & QLA8XXX_DBG_OPCODE_POLL) {
2142                         poll_time = crb_entry->crb_strd.poll_timeout;
2143                         wtime = jiffies + poll_time;
2144                         ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value);
2145
2146                         do {
2147                                 if ((read_value & crb_entry->value_2) ==
2148                                     crb_entry->value_1) {
2149                                         break;
2150                                 } else if (time_after_eq(jiffies, wtime)) {
2151                                         /* capturing dump failed */
2152                                         rval = QLA_ERROR;
2153                                         break;
2154                                 } else {
2155                                         ha->isp_ops->rd_reg_indirect(ha,
2156                                                         crb_addr, &read_value);
2157                                 }
2158                         } while (1);
2159                         opcode &= ~QLA8XXX_DBG_OPCODE_POLL;
2160                 }
2161
2162                 if (opcode & QLA8XXX_DBG_OPCODE_RDSTATE) {
2163                         if (crb_entry->crb_strd.state_index_a) {
2164                                 index = crb_entry->crb_strd.state_index_a;
2165                                 addr = tmplt_hdr->saved_state_array[index];
2166                         } else {
2167                                 addr = crb_addr;
2168                         }
2169
2170                         ha->isp_ops->rd_reg_indirect(ha, addr, &read_value);
2171                         index = crb_entry->crb_ctrl.state_index_v;
2172                         tmplt_hdr->saved_state_array[index] = read_value;
2173                         opcode &= ~QLA8XXX_DBG_OPCODE_RDSTATE;
2174                 }
2175
2176                 if (opcode & QLA8XXX_DBG_OPCODE_WRSTATE) {
2177                         if (crb_entry->crb_strd.state_index_a) {
2178                                 index = crb_entry->crb_strd.state_index_a;
2179                                 addr = tmplt_hdr->saved_state_array[index];
2180                         } else {
2181                                 addr = crb_addr;
2182                         }
2183
2184                         if (crb_entry->crb_ctrl.state_index_v) {
2185                                 index = crb_entry->crb_ctrl.state_index_v;
2186                                 read_value =
2187                                         tmplt_hdr->saved_state_array[index];
2188                         } else {
2189                                 read_value = crb_entry->value_1;
2190                         }
2191
2192                         ha->isp_ops->wr_reg_indirect(ha, addr, read_value);
2193                         opcode &= ~QLA8XXX_DBG_OPCODE_WRSTATE;
2194                 }
2195
2196                 if (opcode & QLA8XXX_DBG_OPCODE_MDSTATE) {
2197                         index = crb_entry->crb_ctrl.state_index_v;
2198                         read_value = tmplt_hdr->saved_state_array[index];
2199                         read_value <<= crb_entry->crb_ctrl.shl;
2200                         read_value >>= crb_entry->crb_ctrl.shr;
2201                         if (crb_entry->value_2)
2202                                 read_value &= crb_entry->value_2;
2203                         read_value |= crb_entry->value_3;
2204                         read_value += crb_entry->value_1;
2205                         tmplt_hdr->saved_state_array[index] = read_value;
2206                         opcode &= ~QLA8XXX_DBG_OPCODE_MDSTATE;
2207                 }
2208                 crb_addr += crb_entry->crb_strd.addr_stride;
2209         }
2210         DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s\n", __func__));
2211         return rval;
2212 }
2213
2214 static void qla4_8xxx_minidump_process_rdocm(struct scsi_qla_host *ha,
2215                                 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2216                                 uint32_t **d_ptr)
2217 {
2218         uint32_t r_addr, r_stride, loop_cnt, i, r_value;
2219         struct qla8xxx_minidump_entry_rdocm *ocm_hdr;
2220         uint32_t *data_ptr = *d_ptr;
2221
2222         DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
2223         ocm_hdr = (struct qla8xxx_minidump_entry_rdocm *)entry_hdr;
2224         r_addr = ocm_hdr->read_addr;
2225         r_stride = ocm_hdr->read_addr_stride;
2226         loop_cnt = ocm_hdr->op_count;
2227
2228         DEBUG2(ql4_printk(KERN_INFO, ha,
2229                           "[%s]: r_addr: 0x%x, r_stride: 0x%x, loop_cnt: 0x%x\n",
2230                           __func__, r_addr, r_stride, loop_cnt));
2231
2232         for (i = 0; i < loop_cnt; i++) {
2233                 r_value = readl((void __iomem *)(r_addr + ha->nx_pcibase));
2234                 *data_ptr++ = cpu_to_le32(r_value);
2235                 r_addr += r_stride;
2236         }
2237         DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s datacount: 0x%lx\n",
2238                 __func__, (long unsigned int) (loop_cnt * sizeof(uint32_t))));
2239         *d_ptr = data_ptr;
2240 }
2241
2242 static void qla4_8xxx_minidump_process_rdmux(struct scsi_qla_host *ha,
2243                                 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2244                                 uint32_t **d_ptr)
2245 {
2246         uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value;
2247         struct qla8xxx_minidump_entry_mux *mux_hdr;
2248         uint32_t *data_ptr = *d_ptr;
2249
2250         DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
2251         mux_hdr = (struct qla8xxx_minidump_entry_mux *)entry_hdr;
2252         r_addr = mux_hdr->read_addr;
2253         s_addr = mux_hdr->select_addr;
2254         s_stride = mux_hdr->select_value_stride;
2255         s_value = mux_hdr->select_value;
2256         loop_cnt = mux_hdr->op_count;
2257
2258         for (i = 0; i < loop_cnt; i++) {
2259                 ha->isp_ops->wr_reg_indirect(ha, s_addr, s_value);
2260                 ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value);
2261                 *data_ptr++ = cpu_to_le32(s_value);
2262                 *data_ptr++ = cpu_to_le32(r_value);
2263                 s_value += s_stride;
2264         }
2265         *d_ptr = data_ptr;
2266 }
2267
2268 static void qla4_8xxx_minidump_process_l1cache(struct scsi_qla_host *ha,
2269                                 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2270                                 uint32_t **d_ptr)
2271 {
2272         uint32_t addr, r_addr, c_addr, t_r_addr;
2273         uint32_t i, k, loop_count, t_value, r_cnt, r_value;
2274         uint32_t c_value_w;
2275         struct qla8xxx_minidump_entry_cache *cache_hdr;
2276         uint32_t *data_ptr = *d_ptr;
2277
2278         cache_hdr = (struct qla8xxx_minidump_entry_cache *)entry_hdr;
2279         loop_count = cache_hdr->op_count;
2280         r_addr = cache_hdr->read_addr;
2281         c_addr = cache_hdr->control_addr;
2282         c_value_w = cache_hdr->cache_ctrl.write_value;
2283
2284         t_r_addr = cache_hdr->tag_reg_addr;
2285         t_value = cache_hdr->addr_ctrl.init_tag_value;
2286         r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
2287
2288         for (i = 0; i < loop_count; i++) {
2289                 ha->isp_ops->wr_reg_indirect(ha, t_r_addr, t_value);
2290                 ha->isp_ops->wr_reg_indirect(ha, c_addr, c_value_w);
2291                 addr = r_addr;
2292                 for (k = 0; k < r_cnt; k++) {
2293                         ha->isp_ops->rd_reg_indirect(ha, addr, &r_value);
2294                         *data_ptr++ = cpu_to_le32(r_value);
2295                         addr += cache_hdr->read_ctrl.read_addr_stride;
2296                 }
2297                 t_value += cache_hdr->addr_ctrl.tag_value_stride;
2298         }
2299         *d_ptr = data_ptr;
2300 }
2301
2302 static void qla4_8xxx_minidump_process_queue(struct scsi_qla_host *ha,
2303                                 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2304                                 uint32_t **d_ptr)
2305 {
2306         uint32_t s_addr, r_addr;
2307         uint32_t r_stride, r_value, r_cnt, qid = 0;
2308         uint32_t i, k, loop_cnt;
2309         struct qla8xxx_minidump_entry_queue *q_hdr;
2310         uint32_t *data_ptr = *d_ptr;
2311
2312         DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
2313         q_hdr = (struct qla8xxx_minidump_entry_queue *)entry_hdr;
2314         s_addr = q_hdr->select_addr;
2315         r_cnt = q_hdr->rd_strd.read_addr_cnt;
2316         r_stride = q_hdr->rd_strd.read_addr_stride;
2317         loop_cnt = q_hdr->op_count;
2318
2319         for (i = 0; i < loop_cnt; i++) {
2320                 ha->isp_ops->wr_reg_indirect(ha, s_addr, qid);
2321                 r_addr = q_hdr->read_addr;
2322                 for (k = 0; k < r_cnt; k++) {
2323                         ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value);
2324                         *data_ptr++ = cpu_to_le32(r_value);
2325                         r_addr += r_stride;
2326                 }
2327                 qid += q_hdr->q_strd.queue_id_stride;
2328         }
2329         *d_ptr = data_ptr;
2330 }
2331
2332 #define MD_DIRECT_ROM_WINDOW            0x42110030
2333 #define MD_DIRECT_ROM_READ_BASE         0x42150000
2334
2335 static void qla4_82xx_minidump_process_rdrom(struct scsi_qla_host *ha,
2336                                 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2337                                 uint32_t **d_ptr)
2338 {
2339         uint32_t r_addr, r_value;
2340         uint32_t i, loop_cnt;
2341         struct qla8xxx_minidump_entry_rdrom *rom_hdr;
2342         uint32_t *data_ptr = *d_ptr;
2343
2344         DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
2345         rom_hdr = (struct qla8xxx_minidump_entry_rdrom *)entry_hdr;
2346         r_addr = rom_hdr->read_addr;
2347         loop_cnt = rom_hdr->read_data_size/sizeof(uint32_t);
2348
2349         DEBUG2(ql4_printk(KERN_INFO, ha,
2350                           "[%s]: flash_addr: 0x%x, read_data_size: 0x%x\n",
2351                            __func__, r_addr, loop_cnt));
2352
2353         for (i = 0; i < loop_cnt; i++) {
2354                 ha->isp_ops->wr_reg_indirect(ha, MD_DIRECT_ROM_WINDOW,
2355                                              (r_addr & 0xFFFF0000));
2356                 ha->isp_ops->rd_reg_indirect(ha,
2357                                 MD_DIRECT_ROM_READ_BASE + (r_addr & 0x0000FFFF),
2358                                 &r_value);
2359                 *data_ptr++ = cpu_to_le32(r_value);
2360                 r_addr += sizeof(uint32_t);
2361         }
2362         *d_ptr = data_ptr;
2363 }
2364
2365 #define MD_MIU_TEST_AGT_CTRL            0x41000090
2366 #define MD_MIU_TEST_AGT_ADDR_LO         0x41000094
2367 #define MD_MIU_TEST_AGT_ADDR_HI         0x41000098
2368
2369 static int __qla4_8xxx_minidump_process_rdmem(struct scsi_qla_host *ha,
2370                                 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2371                                 uint32_t **d_ptr)
2372 {
2373         uint32_t r_addr, r_value, r_data;
2374         uint32_t i, j, loop_cnt;
2375         struct qla8xxx_minidump_entry_rdmem *m_hdr;
2376         unsigned long flags;
2377         uint32_t *data_ptr = *d_ptr;
2378
2379         DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
2380         m_hdr = (struct qla8xxx_minidump_entry_rdmem *)entry_hdr;
2381         r_addr = m_hdr->read_addr;
2382         loop_cnt = m_hdr->read_data_size/16;
2383
2384         DEBUG2(ql4_printk(KERN_INFO, ha,
2385                           "[%s]: Read addr: 0x%x, read_data_size: 0x%x\n",
2386                           __func__, r_addr, m_hdr->read_data_size));
2387
2388         if (r_addr & 0xf) {
2389                 DEBUG2(ql4_printk(KERN_INFO, ha,
2390                                   "[%s]: Read addr 0x%x not 16 bytes aligned\n",
2391                                   __func__, r_addr));
2392                 return QLA_ERROR;
2393         }
2394
2395         if (m_hdr->read_data_size % 16) {
2396                 DEBUG2(ql4_printk(KERN_INFO, ha,
2397                                   "[%s]: Read data[0x%x] not multiple of 16 bytes\n",
2398                                   __func__, m_hdr->read_data_size));
2399                 return QLA_ERROR;
2400         }
2401
2402         DEBUG2(ql4_printk(KERN_INFO, ha,
2403                           "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n",
2404                           __func__, r_addr, m_hdr->read_data_size, loop_cnt));
2405
2406         write_lock_irqsave(&ha->hw_lock, flags);
2407         for (i = 0; i < loop_cnt; i++) {
2408                 ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_ADDR_LO,
2409                                              r_addr);
2410                 r_value = 0;
2411                 ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_ADDR_HI,
2412                                              r_value);
2413                 r_value = MIU_TA_CTL_ENABLE;
2414                 ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL, r_value);
2415                 r_value = MIU_TA_CTL_START_ENABLE;
2416                 ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL, r_value);
2417
2418                 for (j = 0; j < MAX_CTL_CHECK; j++) {
2419                         ha->isp_ops->rd_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL,
2420                                                      &r_value);
2421                         if ((r_value & MIU_TA_CTL_BUSY) == 0)
2422                                 break;
2423                 }
2424
2425                 if (j >= MAX_CTL_CHECK) {
2426                         printk_ratelimited(KERN_ERR
2427                                            "%s: failed to read through agent\n",
2428                                             __func__);
2429                         write_unlock_irqrestore(&ha->hw_lock, flags);
2430                         return QLA_SUCCESS;
2431                 }
2432
2433                 for (j = 0; j < 4; j++) {
2434                         ha->isp_ops->rd_reg_indirect(ha,
2435                                                      MD_MIU_TEST_AGT_RDDATA[j],
2436                                                      &r_data);
2437                         *data_ptr++ = cpu_to_le32(r_data);
2438                 }
2439
2440                 r_addr += 16;
2441         }
2442         write_unlock_irqrestore(&ha->hw_lock, flags);
2443
2444         DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s datacount: 0x%x\n",
2445                           __func__, (loop_cnt * 16)));
2446
2447         *d_ptr = data_ptr;
2448         return QLA_SUCCESS;
2449 }
2450
2451 static int qla4_8xxx_minidump_process_rdmem(struct scsi_qla_host *ha,
2452                                 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2453                                 uint32_t **d_ptr)
2454 {
2455         uint32_t *data_ptr = *d_ptr;
2456         int rval = QLA_SUCCESS;
2457
2458         rval = qla4_8xxx_minidump_pex_dma_read(ha, entry_hdr, &data_ptr);
2459         if (rval != QLA_SUCCESS)
2460                 rval = __qla4_8xxx_minidump_process_rdmem(ha, entry_hdr,
2461                                                           &data_ptr);
2462         *d_ptr = data_ptr;
2463         return rval;
2464 }
2465
2466 static void qla4_8xxx_mark_entry_skipped(struct scsi_qla_host *ha,
2467                                 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2468                                 int index)
2469 {
2470         entry_hdr->d_ctrl.driver_flags |= QLA8XXX_DBG_SKIPPED_FLAG;
2471         DEBUG2(ql4_printk(KERN_INFO, ha,
2472                           "scsi(%ld): Skipping entry[%d]: ETYPE[0x%x]-ELEVEL[0x%x]\n",
2473                           ha->host_no, index, entry_hdr->entry_type,
2474                           entry_hdr->d_ctrl.entry_capture_mask));
2475         /* If driver encounters a new entry type that it cannot process,
2476          * it should just skip the entry and adjust the total buffer size by
2477          * from subtracting the skipped bytes from it
2478          */
2479         ha->fw_dump_skip_size += entry_hdr->entry_capture_size;
2480 }
2481
2482 /* ISP83xx functions to process new minidump entries... */
2483 static uint32_t qla83xx_minidump_process_pollrd(struct scsi_qla_host *ha,
2484                                 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2485                                 uint32_t **d_ptr)
2486 {
2487         uint32_t r_addr, s_addr, s_value, r_value, poll_wait, poll_mask;
2488         uint16_t s_stride, i;
2489         uint32_t *data_ptr = *d_ptr;
2490         uint32_t rval = QLA_SUCCESS;
2491         struct qla83xx_minidump_entry_pollrd *pollrd_hdr;
2492
2493         pollrd_hdr = (struct qla83xx_minidump_entry_pollrd *)entry_hdr;
2494         s_addr = le32_to_cpu(pollrd_hdr->select_addr);
2495         r_addr = le32_to_cpu(pollrd_hdr->read_addr);
2496         s_value = le32_to_cpu(pollrd_hdr->select_value);
2497         s_stride = le32_to_cpu(pollrd_hdr->select_value_stride);
2498
2499         poll_wait = le32_to_cpu(pollrd_hdr->poll_wait);
2500         poll_mask = le32_to_cpu(pollrd_hdr->poll_mask);
2501
2502         for (i = 0; i < le32_to_cpu(pollrd_hdr->op_count); i++) {
2503                 ha->isp_ops->wr_reg_indirect(ha, s_addr, s_value);
2504                 poll_wait = le32_to_cpu(pollrd_hdr->poll_wait);
2505                 while (1) {
2506                         ha->isp_ops->rd_reg_indirect(ha, s_addr, &r_value);
2507
2508                         if ((r_value & poll_mask) != 0) {
2509                                 break;
2510                         } else {
2511                                 msleep(1);
2512                                 if (--poll_wait == 0) {
2513                                         ql4_printk(KERN_ERR, ha, "%s: TIMEOUT\n",
2514                                                    __func__);
2515                                         rval = QLA_ERROR;
2516                                         goto exit_process_pollrd;
2517                                 }
2518                         }
2519                 }
2520                 ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value);
2521                 *data_ptr++ = cpu_to_le32(s_value);
2522                 *data_ptr++ = cpu_to_le32(r_value);
2523                 s_value += s_stride;
2524         }
2525
2526         *d_ptr = data_ptr;
2527
2528 exit_process_pollrd:
2529         return rval;
2530 }
2531
2532 static uint32_t qla4_84xx_minidump_process_rddfe(struct scsi_qla_host *ha,
2533                                 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2534                                 uint32_t **d_ptr)
2535 {
2536         int loop_cnt;
2537         uint32_t addr1, addr2, value, data, temp, wrval;
2538         uint8_t stride, stride2;
2539         uint16_t count;
2540         uint32_t poll, mask, data_size, modify_mask;
2541         uint32_t wait_count = 0;
2542         uint32_t *data_ptr = *d_ptr;
2543         struct qla8044_minidump_entry_rddfe *rddfe;
2544         uint32_t rval = QLA_SUCCESS;
2545
2546         rddfe = (struct qla8044_minidump_entry_rddfe *)entry_hdr;
2547         addr1 = le32_to_cpu(rddfe->addr_1);
2548         value = le32_to_cpu(rddfe->value);
2549         stride = le32_to_cpu(rddfe->stride);
2550         stride2 = le32_to_cpu(rddfe->stride2);
2551         count = le32_to_cpu(rddfe->count);
2552
2553         poll = le32_to_cpu(rddfe->poll);
2554         mask = le32_to_cpu(rddfe->mask);
2555         modify_mask = le32_to_cpu(rddfe->modify_mask);
2556         data_size = le32_to_cpu(rddfe->data_size);
2557
2558         addr2 = addr1 + stride;
2559
2560         for (loop_cnt = 0x0; loop_cnt < count; loop_cnt++) {
2561                 ha->isp_ops->wr_reg_indirect(ha, addr1, (0x40000000 | value));
2562
2563                 wait_count = 0;
2564                 while (wait_count < poll) {
2565                         ha->isp_ops->rd_reg_indirect(ha, addr1, &temp);
2566                         if ((temp & mask) != 0)
2567                                 break;
2568                         wait_count++;
2569                 }
2570
2571                 if (wait_count == poll) {
2572                         ql4_printk(KERN_ERR, ha, "%s: TIMEOUT\n", __func__);
2573                         rval = QLA_ERROR;
2574                         goto exit_process_rddfe;
2575                 } else {
2576                         ha->isp_ops->rd_reg_indirect(ha, addr2, &temp);
2577                         temp = temp & modify_mask;
2578                         temp = (temp | ((loop_cnt << 16) | loop_cnt));
2579                         wrval = ((temp << 16) | temp);
2580
2581                         ha->isp_ops->wr_reg_indirect(ha, addr2, wrval);
2582                         ha->isp_ops->wr_reg_indirect(ha, addr1, value);
2583
2584                         wait_count = 0;
2585                         while (wait_count < poll) {
2586                                 ha->isp_ops->rd_reg_indirect(ha, addr1, &temp);
2587                                 if ((temp & mask) != 0)
2588                                         break;
2589                                 wait_count++;
2590                         }
2591                         if (wait_count == poll) {
2592                                 ql4_printk(KERN_ERR, ha, "%s: TIMEOUT\n",
2593                                            __func__);
2594                                 rval = QLA_ERROR;
2595                                 goto exit_process_rddfe;
2596                         }
2597
2598                         ha->isp_ops->wr_reg_indirect(ha, addr1,
2599                                                      ((0x40000000 | value) +
2600                                                      stride2));
2601                         wait_count = 0;
2602                         while (wait_count < poll) {
2603                                 ha->isp_ops->rd_reg_indirect(ha, addr1, &temp);
2604                                 if ((temp & mask) != 0)
2605                                         break;
2606                                 wait_count++;
2607                         }
2608
2609                         if (wait_count == poll) {
2610                                 ql4_printk(KERN_ERR, ha, "%s: TIMEOUT\n",
2611                                            __func__);
2612                                 rval = QLA_ERROR;
2613                                 goto exit_process_rddfe;
2614                         }
2615
2616                         ha->isp_ops->rd_reg_indirect(ha, addr2, &data);
2617
2618                         *data_ptr++ = cpu_to_le32(wrval);
2619                         *data_ptr++ = cpu_to_le32(data);
2620                 }
2621         }
2622
2623         *d_ptr = data_ptr;
2624 exit_process_rddfe:
2625         return rval;
2626 }
2627
2628 static uint32_t qla4_84xx_minidump_process_rdmdio(struct scsi_qla_host *ha,
2629                                 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2630                                 uint32_t **d_ptr)
2631 {
2632         int rval = QLA_SUCCESS;
2633         uint32_t addr1, addr2, value1, value2, data, selval;
2634         uint8_t stride1, stride2;
2635         uint32_t addr3, addr4, addr5, addr6, addr7;
2636         uint16_t count, loop_cnt;
2637         uint32_t poll, mask;
2638         uint32_t *data_ptr = *d_ptr;
2639         struct qla8044_minidump_entry_rdmdio *rdmdio;
2640
2641         rdmdio = (struct qla8044_minidump_entry_rdmdio *)entry_hdr;
2642         addr1 = le32_to_cpu(rdmdio->addr_1);
2643         addr2 = le32_to_cpu(rdmdio->addr_2);
2644         value1 = le32_to_cpu(rdmdio->value_1);
2645         stride1 = le32_to_cpu(rdmdio->stride_1);
2646         stride2 = le32_to_cpu(rdmdio->stride_2);
2647         count = le32_to_cpu(rdmdio->count);
2648
2649         poll = le32_to_cpu(rdmdio->poll);
2650         mask = le32_to_cpu(rdmdio->mask);
2651         value2 = le32_to_cpu(rdmdio->value_2);
2652
2653         addr3 = addr1 + stride1;
2654
2655         for (loop_cnt = 0; loop_cnt < count; loop_cnt++) {
2656                 rval = ql4_84xx_poll_wait_ipmdio_bus_idle(ha, addr1, addr2,
2657                                                          addr3, mask);
2658                 if (rval)
2659                         goto exit_process_rdmdio;
2660
2661                 addr4 = addr2 - stride1;
2662                 rval = ql4_84xx_ipmdio_wr_reg(ha, addr1, addr3, mask, addr4,
2663                                              value2);
2664                 if (rval)
2665                         goto exit_process_rdmdio;
2666
2667                 addr5 = addr2 - (2 * stride1);
2668                 rval = ql4_84xx_ipmdio_wr_reg(ha, addr1, addr3, mask, addr5,
2669                                              value1);
2670                 if (rval)
2671                         goto exit_process_rdmdio;
2672
2673                 addr6 = addr2 - (3 * stride1);
2674                 rval = ql4_84xx_ipmdio_wr_reg(ha, addr1, addr3, mask,
2675                                              addr6, 0x2);
2676                 if (rval)
2677                         goto exit_process_rdmdio;
2678
2679                 rval = ql4_84xx_poll_wait_ipmdio_bus_idle(ha, addr1, addr2,
2680                                                          addr3, mask);
2681                 if (rval)
2682                         goto exit_process_rdmdio;
2683
2684                 addr7 = addr2 - (4 * stride1);
2685                 rval = ql4_84xx_ipmdio_rd_reg(ha, addr1, addr3,
2686                                                       mask, addr7, &data);
2687                 if (rval)
2688                         goto exit_process_rdmdio;
2689
2690                 selval = (value2 << 18) | (value1 << 2) | 2;
2691
2692                 stride2 = le32_to_cpu(rdmdio->stride_2);
2693                 *data_ptr++ = cpu_to_le32(selval);
2694                 *data_ptr++ = cpu_to_le32(data);
2695
2696                 value1 = value1 + stride2;
2697                 *d_ptr = data_ptr;
2698         }
2699
2700 exit_process_rdmdio:
2701         return rval;
2702 }
2703
2704 static uint32_t qla4_84xx_minidump_process_pollwr(struct scsi_qla_host *ha,
2705                                 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2706                                 uint32_t **d_ptr)
2707 {
2708         uint32_t addr1, addr2, value1, value2, poll, mask, r_value;
2709         struct qla8044_minidump_entry_pollwr *pollwr_hdr;
2710         uint32_t wait_count = 0;
2711         uint32_t rval = QLA_SUCCESS;
2712
2713         pollwr_hdr = (struct qla8044_minidump_entry_pollwr *)entry_hdr;
2714         addr1 = le32_to_cpu(pollwr_hdr->addr_1);
2715         addr2 = le32_to_cpu(pollwr_hdr->addr_2);
2716         value1 = le32_to_cpu(pollwr_hdr->value_1);
2717         value2 = le32_to_cpu(pollwr_hdr->value_2);
2718
2719         poll = le32_to_cpu(pollwr_hdr->poll);
2720         mask = le32_to_cpu(pollwr_hdr->mask);
2721
2722         while (wait_count < poll) {
2723                 ha->isp_ops->rd_reg_indirect(ha, addr1, &r_value);
2724
2725                 if ((r_value & poll) != 0)
2726                         break;
2727
2728                 wait_count++;
2729         }
2730
2731         if (wait_count == poll) {
2732                 ql4_printk(KERN_ERR, ha, "%s: TIMEOUT\n", __func__);
2733                 rval = QLA_ERROR;
2734                 goto exit_process_pollwr;
2735         }
2736
2737         ha->isp_ops->wr_reg_indirect(ha, addr2, value2);
2738         ha->isp_ops->wr_reg_indirect(ha, addr1, value1);
2739
2740         wait_count = 0;
2741         while (wait_count < poll) {
2742                 ha->isp_ops->rd_reg_indirect(ha, addr1, &r_value);
2743
2744                 if ((r_value & poll) != 0)
2745                         break;
2746                 wait_count++;
2747         }
2748
2749 exit_process_pollwr:
2750         return rval;
2751 }
2752
2753 static void qla83xx_minidump_process_rdmux2(struct scsi_qla_host *ha,
2754                                 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2755                                 uint32_t **d_ptr)
2756 {
2757         uint32_t sel_val1, sel_val2, t_sel_val, data, i;
2758         uint32_t sel_addr1, sel_addr2, sel_val_mask, read_addr;
2759         struct qla83xx_minidump_entry_rdmux2 *rdmux2_hdr;
2760         uint32_t *data_ptr = *d_ptr;
2761
2762         rdmux2_hdr = (struct qla83xx_minidump_entry_rdmux2 *)entry_hdr;
2763         sel_val1 = le32_to_cpu(rdmux2_hdr->select_value_1);
2764         sel_val2 = le32_to_cpu(rdmux2_hdr->select_value_2);
2765         sel_addr1 = le32_to_cpu(rdmux2_hdr->select_addr_1);
2766         sel_addr2 = le32_to_cpu(rdmux2_hdr->select_addr_2);
2767         sel_val_mask = le32_to_cpu(rdmux2_hdr->select_value_mask);
2768         read_addr = le32_to_cpu(rdmux2_hdr->read_addr);
2769
2770         for (i = 0; i < rdmux2_hdr->op_count; i++) {
2771                 ha->isp_ops->wr_reg_indirect(ha, sel_addr1, sel_val1);
2772                 t_sel_val = sel_val1 & sel_val_mask;
2773                 *data_ptr++ = cpu_to_le32(t_sel_val);
2774
2775                 ha->isp_ops->wr_reg_indirect(ha, sel_addr2, t_sel_val);
2776                 ha->isp_ops->rd_reg_indirect(ha, read_addr, &data);
2777
2778                 *data_ptr++ = cpu_to_le32(data);
2779
2780                 ha->isp_ops->wr_reg_indirect(ha, sel_addr1, sel_val2);
2781                 t_sel_val = sel_val2 & sel_val_mask;
2782                 *data_ptr++ = cpu_to_le32(t_sel_val);
2783
2784                 ha->isp_ops->wr_reg_indirect(ha, sel_addr2, t_sel_val);
2785                 ha->isp_ops->rd_reg_indirect(ha, read_addr, &data);
2786
2787                 *data_ptr++ = cpu_to_le32(data);
2788
2789                 sel_val1 += rdmux2_hdr->select_value_stride;
2790                 sel_val2 += rdmux2_hdr->select_value_stride;
2791         }
2792
2793         *d_ptr = data_ptr;
2794 }
2795
2796 static uint32_t qla83xx_minidump_process_pollrdmwr(struct scsi_qla_host *ha,
2797                                 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2798                                 uint32_t **d_ptr)
2799 {
2800         uint32_t poll_wait, poll_mask, r_value, data;
2801         uint32_t addr_1, addr_2, value_1, value_2;
2802         uint32_t *data_ptr = *d_ptr;
2803         uint32_t rval = QLA_SUCCESS;
2804         struct qla83xx_minidump_entry_pollrdmwr *poll_hdr;
2805
2806         poll_hdr = (struct qla83xx_minidump_entry_pollrdmwr *)entry_hdr;
2807         addr_1 = le32_to_cpu(poll_hdr->addr_1);
2808         addr_2 = le32_to_cpu(poll_hdr->addr_2);
2809         value_1 = le32_to_cpu(poll_hdr->value_1);
2810         value_2 = le32_to_cpu(poll_hdr->value_2);
2811         poll_mask = le32_to_cpu(poll_hdr->poll_mask);
2812
2813         ha->isp_ops->wr_reg_indirect(ha, addr_1, value_1);
2814
2815         poll_wait = le32_to_cpu(poll_hdr->poll_wait);
2816         while (1) {
2817                 ha->isp_ops->rd_reg_indirect(ha, addr_1, &r_value);
2818
2819                 if ((r_value & poll_mask) != 0) {
2820                         break;
2821                 } else {
2822                         msleep(1);
2823                         if (--poll_wait == 0) {
2824                                 ql4_printk(KERN_ERR, ha, "%s: TIMEOUT_1\n",
2825                                            __func__);
2826                                 rval = QLA_ERROR;
2827                                 goto exit_process_pollrdmwr;
2828                         }
2829                 }
2830         }
2831
2832         ha->isp_ops->rd_reg_indirect(ha, addr_2, &data);
2833         data &= le32_to_cpu(poll_hdr->modify_mask);
2834         ha->isp_ops->wr_reg_indirect(ha, addr_2, data);
2835         ha->isp_ops->wr_reg_indirect(ha, addr_1, value_2);
2836
2837         poll_wait = le32_to_cpu(poll_hdr->poll_wait);
2838         while (1) {
2839                 ha->isp_ops->rd_reg_indirect(ha, addr_1, &r_value);
2840
2841                 if ((r_value & poll_mask) != 0) {
2842                         break;
2843                 } else {
2844                         msleep(1);
2845                         if (--poll_wait == 0) {
2846                                 ql4_printk(KERN_ERR, ha, "%s: TIMEOUT_2\n",
2847                                            __func__);
2848                                 rval = QLA_ERROR;
2849                                 goto exit_process_pollrdmwr;
2850                         }
2851                 }
2852         }
2853
2854         *data_ptr++ = cpu_to_le32(addr_2);
2855         *data_ptr++ = cpu_to_le32(data);
2856         *d_ptr = data_ptr;
2857
2858 exit_process_pollrdmwr:
2859         return rval;
2860 }
2861
2862 static uint32_t qla4_83xx_minidump_process_rdrom(struct scsi_qla_host *ha,
2863                                 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2864                                 uint32_t **d_ptr)
2865 {
2866         uint32_t fl_addr, u32_count, rval;
2867         struct qla8xxx_minidump_entry_rdrom *rom_hdr;
2868         uint32_t *data_ptr = *d_ptr;
2869
2870         rom_hdr = (struct qla8xxx_minidump_entry_rdrom *)entry_hdr;
2871         fl_addr = le32_to_cpu(rom_hdr->read_addr);
2872         u32_count = le32_to_cpu(rom_hdr->read_data_size)/sizeof(uint32_t);
2873
2874         DEBUG2(ql4_printk(KERN_INFO, ha, "[%s]: fl_addr: 0x%x, count: 0x%x\n",
2875                           __func__, fl_addr, u32_count));
2876
2877         rval = qla4_83xx_lockless_flash_read_u32(ha, fl_addr,
2878                                                  (u8 *)(data_ptr), u32_count);
2879
2880         if (rval == QLA_ERROR) {
2881                 ql4_printk(KERN_ERR, ha, "%s: Flash Read Error,Count=%d\n",
2882                            __func__, u32_count);
2883                 goto exit_process_rdrom;
2884         }
2885
2886         data_ptr += u32_count;
2887         *d_ptr = data_ptr;
2888
2889 exit_process_rdrom:
2890         return rval;
2891 }
2892
2893 /**
2894  * qla4_8xxx_collect_md_data - Retrieve firmware minidump data.
2895  * @ha: pointer to adapter structure
2896  **/
2897 static int qla4_8xxx_collect_md_data(struct scsi_qla_host *ha)
2898 {
2899         int num_entry_hdr = 0;
2900         struct qla8xxx_minidump_entry_hdr *entry_hdr;
2901         struct qla4_8xxx_minidump_template_hdr *tmplt_hdr;
2902         uint32_t *data_ptr;
2903         uint32_t data_collected = 0;
2904         int i, rval = QLA_ERROR;
2905         uint64_t now;
2906         uint32_t timestamp;
2907
2908         ha->fw_dump_skip_size = 0;
2909         if (!ha->fw_dump) {
2910                 ql4_printk(KERN_INFO, ha, "%s(%ld) No buffer to dump\n",
2911                            __func__, ha->host_no);
2912                 return rval;
2913         }
2914
2915         tmplt_hdr = (struct qla4_8xxx_minidump_template_hdr *)
2916                                                 ha->fw_dump_tmplt_hdr;
2917         data_ptr = (uint32_t *)((uint8_t *)ha->fw_dump +
2918                                                 ha->fw_dump_tmplt_size);
2919         data_collected += ha->fw_dump_tmplt_size;
2920
2921         num_entry_hdr = tmplt_hdr->num_of_entries;
2922         ql4_printk(KERN_INFO, ha, "[%s]: starting data ptr: %p\n",
2923                    __func__, data_ptr);
2924         ql4_printk(KERN_INFO, ha,
2925                    "[%s]: no of entry headers in Template: 0x%x\n",
2926                    __func__, num_entry_hdr);
2927         ql4_printk(KERN_INFO, ha, "[%s]: Capture Mask obtained: 0x%x\n",
2928                    __func__, ha->fw_dump_capture_mask);
2929         ql4_printk(KERN_INFO, ha, "[%s]: Total_data_size 0x%x, %d obtained\n",
2930                    __func__, ha->fw_dump_size, ha->fw_dump_size);
2931
2932         /* Update current timestamp before taking dump */
2933         now = get_jiffies_64();
2934         timestamp = (u32)(jiffies_to_msecs(now) / 1000);
2935         tmplt_hdr->driver_timestamp = timestamp;
2936
2937         entry_hdr = (struct qla8xxx_minidump_entry_hdr *)
2938                                         (((uint8_t *)ha->fw_dump_tmplt_hdr) +
2939                                          tmplt_hdr->first_entry_offset);
2940
2941         if (is_qla8032(ha) || is_qla8042(ha))
2942                 tmplt_hdr->saved_state_array[QLA83XX_SS_OCM_WNDREG_INDEX] =
2943                                         tmplt_hdr->ocm_window_reg[ha->func_num];
2944
2945         /* Walk through the entry headers - validate/perform required action */
2946         for (i = 0; i < num_entry_hdr; i++) {
2947                 if (data_collected > ha->fw_dump_size) {
2948                         ql4_printk(KERN_INFO, ha,
2949                                    "Data collected: [0x%x], Total Dump size: [0x%x]\n",
2950                                    data_collected, ha->fw_dump_size);
2951                         return rval;
2952                 }
2953
2954                 if (!(entry_hdr->d_ctrl.entry_capture_mask &
2955                       ha->fw_dump_capture_mask)) {
2956                         entry_hdr->d_ctrl.driver_flags |=
2957                                                 QLA8XXX_DBG_SKIPPED_FLAG;
2958                         goto skip_nxt_entry;
2959                 }
2960
2961                 DEBUG2(ql4_printk(KERN_INFO, ha,
2962                                   "Data collected: [0x%x], Dump size left:[0x%x]\n",
2963                                   data_collected,
2964                                   (ha->fw_dump_size - data_collected)));
2965
2966                 /* Decode the entry type and take required action to capture
2967                  * debug data
2968                  */
2969                 switch (entry_hdr->entry_type) {
2970                 case QLA8XXX_RDEND:
2971                         qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
2972                         break;
2973                 case QLA8XXX_CNTRL:
2974                         rval = qla4_8xxx_minidump_process_control(ha,
2975                                                                   entry_hdr);
2976                         if (rval != QLA_SUCCESS) {
2977                                 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
2978                                 goto md_failed;
2979                         }
2980                         break;
2981                 case QLA8XXX_RDCRB:
2982                         qla4_8xxx_minidump_process_rdcrb(ha, entry_hdr,
2983                                                          &data_ptr);
2984                         break;
2985                 case QLA8XXX_RDMEM:
2986                         rval = qla4_8xxx_minidump_process_rdmem(ha, entry_hdr,
2987                                                                 &data_ptr);
2988                         if (rval != QLA_SUCCESS) {
2989                                 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
2990                                 goto md_failed;
2991                         }
2992                         break;
2993                 case QLA8XXX_BOARD:
2994                 case QLA8XXX_RDROM:
2995                         if (is_qla8022(ha)) {
2996                                 qla4_82xx_minidump_process_rdrom(ha, entry_hdr,
2997                                                                  &data_ptr);
2998                         } else if (is_qla8032(ha) || is_qla8042(ha)) {
2999                                 rval = qla4_83xx_minidump_process_rdrom(ha,
3000                                                                     entry_hdr,
3001                                                                     &data_ptr);
3002                                 if (rval != QLA_SUCCESS)
3003                                         qla4_8xxx_mark_entry_skipped(ha,
3004                                                                      entry_hdr,
3005                                                                      i);
3006                         }
3007                         break;
3008                 case QLA8XXX_L2DTG:
3009                 case QLA8XXX_L2ITG:
3010                 case QLA8XXX_L2DAT:
3011                 case QLA8XXX_L2INS:
3012                         rval = qla4_8xxx_minidump_process_l2tag(ha, entry_hdr,
3013                                                                 &data_ptr);
3014                         if (rval != QLA_SUCCESS) {
3015                                 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
3016                                 goto md_failed;
3017                         }
3018                         break;
3019                 case QLA8XXX_L1DTG:
3020                 case QLA8XXX_L1ITG:
3021                 case QLA8XXX_L1DAT:
3022                 case QLA8XXX_L1INS:
3023                         qla4_8xxx_minidump_process_l1cache(ha, entry_hdr,
3024                                                            &data_ptr);
3025                         break;
3026                 case QLA8XXX_RDOCM:
3027                         qla4_8xxx_minidump_process_rdocm(ha, entry_hdr,
3028                                                          &data_ptr);
3029                         break;
3030                 case QLA8XXX_RDMUX:
3031                         qla4_8xxx_minidump_process_rdmux(ha, entry_hdr,
3032                                                          &data_ptr);
3033                         break;
3034                 case QLA8XXX_QUEUE:
3035                         qla4_8xxx_minidump_process_queue(ha, entry_hdr,
3036                                                          &data_ptr);
3037                         break;
3038                 case QLA83XX_POLLRD:
3039                         if (is_qla8022(ha)) {
3040                                 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
3041                                 break;
3042                         }
3043                         rval = qla83xx_minidump_process_pollrd(ha, entry_hdr,
3044                                                                &data_ptr);
3045                         if (rval != QLA_SUCCESS)
3046                                 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
3047                         break;
3048                 case QLA83XX_RDMUX2:
3049                         if (is_qla8022(ha)) {
3050                                 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
3051                                 break;
3052                         }
3053                         qla83xx_minidump_process_rdmux2(ha, entry_hdr,
3054                                                         &data_ptr);
3055                         break;
3056                 case QLA83XX_POLLRDMWR:
3057                         if (is_qla8022(ha)) {
3058                                 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
3059                                 break;
3060                         }
3061                         rval = qla83xx_minidump_process_pollrdmwr(ha, entry_hdr,
3062                                                                   &data_ptr);
3063                         if (rval != QLA_SUCCESS)
3064                                 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
3065                         break;
3066                 case QLA8044_RDDFE:
3067                         rval = qla4_84xx_minidump_process_rddfe(ha, entry_hdr,
3068                                                                 &data_ptr);
3069                         if (rval != QLA_SUCCESS)
3070                                 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
3071                         break;
3072                 case QLA8044_RDMDIO:
3073                         rval = qla4_84xx_minidump_process_rdmdio(ha, entry_hdr,
3074                                                                  &data_ptr);
3075                         if (rval != QLA_SUCCESS)
3076                                 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
3077                         break;
3078                 case QLA8044_POLLWR:
3079                         rval = qla4_84xx_minidump_process_pollwr(ha, entry_hdr,
3080                                                                  &data_ptr);
3081                         if (rval != QLA_SUCCESS)
3082                                 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
3083                         break;
3084                 case QLA8XXX_RDNOP:
3085                 default:
3086                         qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
3087                         break;
3088                 }
3089
3090                 data_collected = (uint8_t *)data_ptr - (uint8_t *)ha->fw_dump;
3091 skip_nxt_entry:
3092                 /*  next entry in the template */
3093                 entry_hdr = (struct qla8xxx_minidump_entry_hdr *)
3094                                 (((uint8_t *)entry_hdr) +
3095                                  entry_hdr->entry_size);
3096         }
3097
3098         if ((data_collected + ha->fw_dump_skip_size) != ha->fw_dump_size) {
3099                 ql4_printk(KERN_INFO, ha,
3100                            "Dump data mismatch: Data collected: [0x%x], total_data_size:[0x%x]\n",
3101                            data_collected, ha->fw_dump_size);
3102                 rval = QLA_ERROR;
3103                 goto md_failed;
3104         }
3105
3106         DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s Last entry: 0x%x\n",
3107                           __func__, i));
3108 md_failed:
3109         return rval;
3110 }
3111
3112 /**
3113  * qla4_8xxx_uevent_emit - Send uevent when the firmware dump is ready.
3114  * @ha: pointer to adapter structure
3115  **/
3116 static void qla4_8xxx_uevent_emit(struct scsi_qla_host *ha, u32 code)
3117 {
3118         char event_string[40];
3119         char *envp[] = { event_string, NULL };
3120
3121         switch (code) {
3122         case QL4_UEVENT_CODE_FW_DUMP:
3123                 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
3124                          ha->host_no);
3125                 break;
3126         default:
3127                 /*do nothing*/
3128                 break;
3129         }
3130
3131         kobject_uevent_env(&(&ha->pdev->dev)->kobj, KOBJ_CHANGE, envp);
3132 }
3133
3134 void qla4_8xxx_get_minidump(struct scsi_qla_host *ha)
3135 {
3136         if (ql4xenablemd && test_bit(AF_FW_RECOVERY, &ha->flags) &&
3137             !test_bit(AF_82XX_FW_DUMPED, &ha->flags)) {
3138                 if (!qla4_8xxx_collect_md_data(ha)) {
3139                         qla4_8xxx_uevent_emit(ha, QL4_UEVENT_CODE_FW_DUMP);
3140                         set_bit(AF_82XX_FW_DUMPED, &ha->flags);
3141                 } else {
3142                         ql4_printk(KERN_INFO, ha, "%s: Unable to collect minidump\n",
3143                                    __func__);
3144                 }
3145         }
3146 }
3147
3148 /**
3149  * qla4_8xxx_device_bootstrap - Initialize device, set DEV_READY, start fw
3150  * @ha: pointer to adapter structure
3151  *
3152  * Note: IDC lock must be held upon entry
3153  **/
3154 int qla4_8xxx_device_bootstrap(struct scsi_qla_host *ha)
3155 {
3156         int rval = QLA_ERROR;
3157         int i;
3158         uint32_t old_count, count;
3159         int need_reset = 0;
3160
3161         need_reset = ha->isp_ops->need_reset(ha);
3162
3163         if (need_reset) {
3164                 /* We are trying to perform a recovery here. */
3165                 if (test_bit(AF_FW_RECOVERY, &ha->flags))
3166                         ha->isp_ops->rom_lock_recovery(ha);
3167         } else  {
3168                 old_count = qla4_8xxx_rd_direct(ha, QLA8XXX_PEG_ALIVE_COUNTER);
3169                 for (i = 0; i < 10; i++) {
3170                         msleep(200);
3171                         count = qla4_8xxx_rd_direct(ha,
3172                                                     QLA8XXX_PEG_ALIVE_COUNTER);
3173                         if (count != old_count) {
3174                                 rval = QLA_SUCCESS;
3175                                 goto dev_ready;
3176                         }
3177                 }
3178                 ha->isp_ops->rom_lock_recovery(ha);
3179         }
3180
3181         /* set to DEV_INITIALIZING */
3182         ql4_printk(KERN_INFO, ha, "HW State: INITIALIZING\n");
3183         qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE,
3184                             QLA8XXX_DEV_INITIALIZING);
3185
3186         ha->isp_ops->idc_unlock(ha);
3187
3188         if (is_qla8022(ha))
3189                 qla4_8xxx_get_minidump(ha);
3190
3191         rval = ha->isp_ops->restart_firmware(ha);
3192         ha->isp_ops->idc_lock(ha);
3193
3194         if (rval != QLA_SUCCESS) {
3195                 ql4_printk(KERN_INFO, ha, "HW State: FAILED\n");
3196                 qla4_8xxx_clear_drv_active(ha);
3197                 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE,
3198                                     QLA8XXX_DEV_FAILED);
3199                 return rval;
3200         }
3201
3202 dev_ready:
3203         ql4_printk(KERN_INFO, ha, "HW State: READY\n");
3204         qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE, QLA8XXX_DEV_READY);
3205
3206         return rval;
3207 }
3208
3209 /**
3210  * qla4_82xx_need_reset_handler - Code to start reset sequence
3211  * @ha: pointer to adapter structure
3212  *
3213  * Note: IDC lock must be held upon entry
3214  **/
3215 static void
3216 qla4_82xx_need_reset_handler(struct scsi_qla_host *ha)
3217 {
3218         uint32_t dev_state, drv_state, drv_active;
3219         uint32_t active_mask = 0xFFFFFFFF;
3220         unsigned long reset_timeout;
3221
3222         ql4_printk(KERN_INFO, ha,
3223                 "Performing ISP error recovery\n");
3224
3225         if (test_and_clear_bit(AF_ONLINE, &ha->flags)) {
3226                 qla4_82xx_idc_unlock(ha);
3227                 ha->isp_ops->disable_intrs(ha);
3228                 qla4_82xx_idc_lock(ha);
3229         }
3230
3231         if (!test_bit(AF_8XXX_RST_OWNER, &ha->flags)) {
3232                 DEBUG2(ql4_printk(KERN_INFO, ha,
3233                                   "%s(%ld): reset acknowledged\n",
3234                                   __func__, ha->host_no));
3235                 qla4_8xxx_set_rst_ready(ha);
3236         } else {
3237                 active_mask = (~(1 << (ha->func_num * 4)));
3238         }
3239
3240         /* wait for 10 seconds for reset ack from all functions */
3241         reset_timeout = jiffies + (ha->nx_reset_timeout * HZ);
3242
3243         drv_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
3244         drv_active = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
3245
3246         ql4_printk(KERN_INFO, ha,
3247                 "%s(%ld): drv_state = 0x%x, drv_active = 0x%x\n",
3248                 __func__, ha->host_no, drv_state, drv_active);
3249
3250         while (drv_state != (drv_active & active_mask)) {
3251                 if (time_after_eq(jiffies, reset_timeout)) {
3252                         ql4_printk(KERN_INFO, ha,
3253                                    "%s: RESET TIMEOUT! drv_state: 0x%08x, drv_active: 0x%08x\n",
3254                                    DRIVER_NAME, drv_state, drv_active);
3255                         break;
3256                 }
3257
3258                 /*
3259                  * When reset_owner times out, check which functions
3260                  * acked/did not ack
3261                  */
3262                 if (test_bit(AF_8XXX_RST_OWNER, &ha->flags)) {
3263                         ql4_printk(KERN_INFO, ha,
3264                                    "%s(%ld): drv_state = 0x%x, drv_active = 0x%x\n",
3265                                    __func__, ha->host_no, drv_state,
3266                                    drv_active);
3267                 }
3268                 qla4_82xx_idc_unlock(ha);
3269                 msleep(1000);
3270                 qla4_82xx_idc_lock(ha);
3271
3272                 drv_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
3273                 drv_active = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
3274         }
3275
3276         /* Clear RESET OWNER as we are not going to use it any further */
3277         clear_bit(AF_8XXX_RST_OWNER, &ha->flags);
3278
3279         dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3280         ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n", dev_state,
3281                    dev_state < MAX_STATES ? qdev_state[dev_state] : "Unknown");
3282
3283         /* Force to DEV_COLD unless someone else is starting a reset */
3284         if (dev_state != QLA8XXX_DEV_INITIALIZING) {
3285                 ql4_printk(KERN_INFO, ha, "HW State: COLD/RE-INIT\n");
3286                 qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_COLD);
3287                 qla4_8xxx_set_rst_ready(ha);
3288         }
3289 }
3290
3291 /**
3292  * qla4_8xxx_need_qsnt_handler - Code to start qsnt
3293  * @ha: pointer to adapter structure
3294  **/
3295 void
3296 qla4_8xxx_need_qsnt_handler(struct scsi_qla_host *ha)
3297 {
3298         ha->isp_ops->idc_lock(ha);
3299         qla4_8xxx_set_qsnt_ready(ha);
3300         ha->isp_ops->idc_unlock(ha);
3301 }
3302
3303 static void qla4_82xx_set_idc_ver(struct scsi_qla_host *ha)
3304 {
3305         int idc_ver;
3306         uint32_t drv_active;
3307
3308         drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
3309         if (drv_active == (1 << (ha->func_num * 4))) {
3310                 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION,
3311                                     QLA82XX_IDC_VERSION);
3312                 ql4_printk(KERN_INFO, ha,
3313                            "%s: IDC version updated to %d\n", __func__,
3314                            QLA82XX_IDC_VERSION);
3315         } else {
3316                 idc_ver = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION);
3317                 if (QLA82XX_IDC_VERSION != idc_ver) {
3318                         ql4_printk(KERN_INFO, ha,
3319                                    "%s: qla4xxx driver IDC version %d is not compatible with IDC version %d of other drivers!\n",
3320                                    __func__, QLA82XX_IDC_VERSION, idc_ver);
3321                 }
3322         }
3323 }
3324
3325 static int qla4_83xx_set_idc_ver(struct scsi_qla_host *ha)
3326 {
3327         int idc_ver;
3328         uint32_t drv_active;
3329         int rval = QLA_SUCCESS;
3330
3331         drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
3332         if (drv_active == (1 << ha->func_num)) {
3333                 idc_ver = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION);
3334                 idc_ver &= (~0xFF);
3335                 idc_ver |= QLA83XX_IDC_VER_MAJ_VALUE;
3336                 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION, idc_ver);
3337                 ql4_printk(KERN_INFO, ha,
3338                            "%s: IDC version updated to %d\n", __func__,
3339                            idc_ver);
3340         } else {
3341                 idc_ver = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION);
3342                 idc_ver &= 0xFF;
3343                 if (QLA83XX_IDC_VER_MAJ_VALUE != idc_ver) {
3344                         ql4_printk(KERN_INFO, ha,
3345                                    "%s: qla4xxx driver IDC version %d is not compatible with IDC version %d of other drivers!\n",
3346                                    __func__, QLA83XX_IDC_VER_MAJ_VALUE,
3347                                    idc_ver);
3348                         rval = QLA_ERROR;
3349                         goto exit_set_idc_ver;
3350                 }
3351         }
3352
3353         /* Update IDC_MINOR_VERSION */
3354         idc_ver = qla4_83xx_rd_reg(ha, QLA83XX_CRB_IDC_VER_MINOR);
3355         idc_ver &= ~(0x03 << (ha->func_num * 2));
3356         idc_ver |= (QLA83XX_IDC_VER_MIN_VALUE << (ha->func_num * 2));
3357         qla4_83xx_wr_reg(ha, QLA83XX_CRB_IDC_VER_MINOR, idc_ver);
3358
3359 exit_set_idc_ver:
3360         return rval;
3361 }
3362
3363 int qla4_8xxx_update_idc_reg(struct scsi_qla_host *ha)
3364 {
3365         uint32_t drv_active;
3366         int rval = QLA_SUCCESS;
3367
3368         if (test_bit(AF_INIT_DONE, &ha->flags))
3369                 goto exit_update_idc_reg;
3370
3371         ha->isp_ops->idc_lock(ha);
3372         qla4_8xxx_set_drv_active(ha);
3373
3374         /*
3375          * If we are the first driver to load and
3376          * ql4xdontresethba is not set, clear IDC_CTRL BIT0.
3377          */
3378         if (is_qla8032(ha) || is_qla8042(ha)) {
3379                 drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
3380                 if ((drv_active == (1 << ha->func_num)) && !ql4xdontresethba)
3381                         qla4_83xx_clear_idc_dontreset(ha);
3382         }
3383
3384         if (is_qla8022(ha)) {
3385                 qla4_82xx_set_idc_ver(ha);
3386         } else if (is_qla8032(ha) || is_qla8042(ha)) {
3387                 rval = qla4_83xx_set_idc_ver(ha);
3388                 if (rval == QLA_ERROR)
3389                         qla4_8xxx_clear_drv_active(ha);
3390         }
3391
3392         ha->isp_ops->idc_unlock(ha);
3393
3394 exit_update_idc_reg:
3395         return rval;
3396 }
3397
3398 /**
3399  * qla4_8xxx_device_state_handler - Adapter state machine
3400  * @ha: pointer to host adapter structure.
3401  *
3402  * Note: IDC lock must be UNLOCKED upon entry
3403  **/
3404 int qla4_8xxx_device_state_handler(struct scsi_qla_host *ha)
3405 {
3406         uint32_t dev_state;
3407         int rval = QLA_SUCCESS;
3408         unsigned long dev_init_timeout;
3409
3410         rval = qla4_8xxx_update_idc_reg(ha);
3411         if (rval == QLA_ERROR)
3412                 goto exit_state_handler;
3413
3414         dev_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DEV_STATE);
3415         DEBUG2(ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n",
3416                           dev_state, dev_state < MAX_STATES ?
3417                           qdev_state[dev_state] : "Unknown"));
3418
3419         /* wait for 30 seconds for device to go ready */
3420         dev_init_timeout = jiffies + (ha->nx_dev_init_timeout * HZ);
3421
3422         ha->isp_ops->idc_lock(ha);
3423         while (1) {
3424
3425                 if (time_after_eq(jiffies, dev_init_timeout)) {
3426                         ql4_printk(KERN_WARNING, ha,
3427                                    "%s: Device Init Failed 0x%x = %s\n",
3428                                    DRIVER_NAME,
3429                                    dev_state, dev_state < MAX_STATES ?
3430                                    qdev_state[dev_state] : "Unknown");
3431                         qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE,
3432                                             QLA8XXX_DEV_FAILED);
3433                 }
3434
3435                 dev_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DEV_STATE);
3436                 ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n",
3437                            dev_state, dev_state < MAX_STATES ?
3438                            qdev_state[dev_state] : "Unknown");
3439
3440                 /* NOTE: Make sure idc unlocked upon exit of switch statement */
3441                 switch (dev_state) {
3442                 case QLA8XXX_DEV_READY:
3443                         goto exit;
3444                 case QLA8XXX_DEV_COLD:
3445                         rval = qla4_8xxx_device_bootstrap(ha);
3446                         goto exit;
3447                 case QLA8XXX_DEV_INITIALIZING:
3448                         ha->isp_ops->idc_unlock(ha);
3449                         msleep(1000);
3450                         ha->isp_ops->idc_lock(ha);
3451                         break;
3452                 case QLA8XXX_DEV_NEED_RESET:
3453                         /*
3454                          * For ISP8324 and ISP8042, if NEED_RESET is set by any
3455                          * driver, it should be honored, irrespective of
3456                          * IDC_CTRL DONTRESET_BIT0
3457                          */
3458                         if (is_qla8032(ha) || is_qla8042(ha)) {
3459                                 qla4_83xx_need_reset_handler(ha);
3460                         } else if (is_qla8022(ha)) {
3461                                 if (!ql4xdontresethba) {
3462                                         qla4_82xx_need_reset_handler(ha);
3463                                         /* Update timeout value after need
3464                                          * reset handler */
3465                                         dev_init_timeout = jiffies +
3466                                                 (ha->nx_dev_init_timeout * HZ);
3467                                 } else {
3468                                         ha->isp_ops->idc_unlock(ha);
3469                                         msleep(1000);
3470                                         ha->isp_ops->idc_lock(ha);
3471                                 }
3472                         }
3473                         break;
3474                 case QLA8XXX_DEV_NEED_QUIESCENT:
3475                         /* idc locked/unlocked in handler */
3476                         qla4_8xxx_need_qsnt_handler(ha);
3477                         break;
3478                 case QLA8XXX_DEV_QUIESCENT:
3479                         ha->isp_ops->idc_unlock(ha);
3480                         msleep(1000);
3481                         ha->isp_ops->idc_lock(ha);
3482                         break;
3483                 case QLA8XXX_DEV_FAILED:
3484                         ha->isp_ops->idc_unlock(ha);
3485                         qla4xxx_dead_adapter_cleanup(ha);
3486                         rval = QLA_ERROR;
3487                         ha->isp_ops->idc_lock(ha);
3488                         goto exit;
3489                 default:
3490                         ha->isp_ops->idc_unlock(ha);
3491                         qla4xxx_dead_adapter_cleanup(ha);
3492                         rval = QLA_ERROR;
3493                         ha->isp_ops->idc_lock(ha);
3494                         goto exit;
3495                 }
3496         }
3497 exit:
3498         ha->isp_ops->idc_unlock(ha);
3499 exit_state_handler:
3500         return rval;
3501 }
3502
3503 int qla4_8xxx_load_risc(struct scsi_qla_host *ha)
3504 {
3505         int retval;
3506
3507         /* clear the interrupt */
3508         if (is_qla8032(ha) || is_qla8042(ha)) {
3509                 writel(0, &ha->qla4_83xx_reg->risc_intr);
3510                 readl(&ha->qla4_83xx_reg->risc_intr);
3511         } else if (is_qla8022(ha)) {
3512                 writel(0, &ha->qla4_82xx_reg->host_int);
3513                 readl(&ha->qla4_82xx_reg->host_int);
3514         }
3515
3516         retval = qla4_8xxx_device_state_handler(ha);
3517
3518         /* Initialize request and response queues. */
3519         if (retval == QLA_SUCCESS)
3520                 qla4xxx_init_rings(ha);
3521
3522         if (retval == QLA_SUCCESS && !test_bit(AF_IRQ_ATTACHED, &ha->flags))
3523                 retval = qla4xxx_request_irqs(ha);
3524
3525         return retval;
3526 }
3527
3528 /*****************************************************************************/
3529 /* Flash Manipulation Routines                                               */
3530 /*****************************************************************************/
3531
3532 #define OPTROM_BURST_SIZE       0x1000
3533 #define OPTROM_BURST_DWORDS     (OPTROM_BURST_SIZE / 4)
3534
3535 #define FARX_DATA_FLAG  BIT_31
3536 #define FARX_ACCESS_FLASH_CONF  0x7FFD0000
3537 #define FARX_ACCESS_FLASH_DATA  0x7FF00000
3538
3539 static inline uint32_t
3540 flash_conf_addr(struct ql82xx_hw_data *hw, uint32_t faddr)
3541 {
3542         return hw->flash_conf_off | faddr;
3543 }
3544
3545 static inline uint32_t
3546 flash_data_addr(struct ql82xx_hw_data *hw, uint32_t faddr)
3547 {
3548         return hw->flash_data_off | faddr;
3549 }
3550
3551 static uint32_t *
3552 qla4_82xx_read_flash_data(struct scsi_qla_host *ha, uint32_t *dwptr,
3553     uint32_t faddr, uint32_t length)
3554 {
3555         uint32_t i;
3556         uint32_t val;
3557         int loops = 0;
3558         while ((qla4_82xx_rom_lock(ha) != 0) && (loops < 50000)) {
3559                 udelay(100);
3560                 cond_resched();
3561                 loops++;
3562         }
3563         if (loops >= 50000) {
3564                 ql4_printk(KERN_WARNING, ha, "ROM lock failed\n");
3565                 return dwptr;
3566         }
3567
3568         /* Dword reads to flash. */
3569         for (i = 0; i < length/4; i++, faddr += 4) {
3570                 if (qla4_82xx_do_rom_fast_read(ha, faddr, &val)) {
3571                         ql4_printk(KERN_WARNING, ha,
3572                             "Do ROM fast read failed\n");
3573                         goto done_read;
3574                 }
3575                 dwptr[i] = __constant_cpu_to_le32(val);
3576         }
3577
3578 done_read:
3579         qla4_82xx_rom_unlock(ha);
3580         return dwptr;
3581 }
3582
3583 /**
3584  * Address and length are byte address
3585  **/
3586 static uint8_t *
3587 qla4_82xx_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
3588                 uint32_t offset, uint32_t length)
3589 {
3590         qla4_82xx_read_flash_data(ha, (uint32_t *)buf, offset, length);
3591         return buf;
3592 }
3593
3594 static int
3595 qla4_8xxx_find_flt_start(struct scsi_qla_host *ha, uint32_t *start)
3596 {
3597         const char *loc, *locations[] = { "DEF", "PCI" };
3598
3599         /*
3600          * FLT-location structure resides after the last PCI region.
3601          */
3602
3603         /* Begin with sane defaults. */
3604         loc = locations[0];
3605         *start = FA_FLASH_LAYOUT_ADDR_82;
3606
3607         DEBUG2(ql4_printk(KERN_INFO, ha, "FLTL[%s] = 0x%x.\n", loc, *start));
3608         return QLA_SUCCESS;
3609 }
3610
3611 static void
3612 qla4_8xxx_get_flt_info(struct scsi_qla_host *ha, uint32_t flt_addr)
3613 {
3614         const char *loc, *locations[] = { "DEF", "FLT" };
3615         uint16_t *wptr;
3616         uint16_t cnt, chksum;
3617         uint32_t start, status;
3618         struct qla_flt_header *flt;
3619         struct qla_flt_region *region;
3620         struct ql82xx_hw_data *hw = &ha->hw;
3621
3622         hw->flt_region_flt = flt_addr;
3623         wptr = (uint16_t *)ha->request_ring;
3624         flt = (struct qla_flt_header *)ha->request_ring;
3625         region = (struct qla_flt_region *)&flt[1];
3626
3627         if (is_qla8022(ha)) {
3628                 qla4_82xx_read_optrom_data(ha, (uint8_t *)ha->request_ring,
3629                                            flt_addr << 2, OPTROM_BURST_SIZE);
3630         } else if (is_qla8032(ha) || is_qla8042(ha)) {
3631                 status = qla4_83xx_flash_read_u32(ha, flt_addr << 2,
3632                                                   (uint8_t *)ha->request_ring,
3633                                                   0x400);
3634                 if (status != QLA_SUCCESS)
3635                         goto no_flash_data;
3636         }
3637
3638         if (*wptr == __constant_cpu_to_le16(0xffff))
3639                 goto no_flash_data;
3640         if (flt->version != __constant_cpu_to_le16(1)) {
3641                 DEBUG2(ql4_printk(KERN_INFO, ha, "Unsupported FLT detected: "
3642                         "version=0x%x length=0x%x checksum=0x%x.\n",
3643                         le16_to_cpu(flt->version), le16_to_cpu(flt->length),
3644                         le16_to_cpu(flt->checksum)));
3645                 goto no_flash_data;
3646         }
3647
3648         cnt = (sizeof(struct qla_flt_header) + le16_to_cpu(flt->length)) >> 1;
3649         for (chksum = 0; cnt; cnt--)
3650                 chksum += le16_to_cpu(*wptr++);
3651         if (chksum) {
3652                 DEBUG2(ql4_printk(KERN_INFO, ha, "Inconsistent FLT detected: "
3653                         "version=0x%x length=0x%x checksum=0x%x.\n",
3654                         le16_to_cpu(flt->version), le16_to_cpu(flt->length),
3655                         chksum));
3656                 goto no_flash_data;
3657         }
3658
3659         loc = locations[1];
3660         cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region);
3661         for ( ; cnt; cnt--, region++) {
3662                 /* Store addresses as DWORD offsets. */
3663                 start = le32_to_cpu(region->start) >> 2;
3664
3665                 DEBUG3(ql4_printk(KERN_DEBUG, ha, "FLT[%02x]: start=0x%x "
3666                     "end=0x%x size=0x%x.\n", le32_to_cpu(region->code), start,
3667                     le32_to_cpu(region->end) >> 2, le32_to_cpu(region->size)));
3668
3669                 switch (le32_to_cpu(region->code) & 0xff) {
3670                 case FLT_REG_FDT:
3671                         hw->flt_region_fdt = start;
3672                         break;
3673                 case FLT_REG_BOOT_CODE_82:
3674                         hw->flt_region_boot = start;
3675                         break;
3676                 case FLT_REG_FW_82:
3677                 case FLT_REG_FW_82_1:
3678                         hw->flt_region_fw = start;
3679                         break;
3680                 case FLT_REG_BOOTLOAD_82:
3681                         hw->flt_region_bootload = start;
3682                         break;
3683                 case FLT_REG_ISCSI_PARAM:
3684                         hw->flt_iscsi_param =  start;
3685                         break;
3686                 case FLT_REG_ISCSI_CHAP:
3687                         hw->flt_region_chap =  start;
3688                         hw->flt_chap_size =  le32_to_cpu(region->size);
3689                         break;
3690                 case FLT_REG_ISCSI_DDB:
3691                         hw->flt_region_ddb =  start;
3692                         hw->flt_ddb_size =  le32_to_cpu(region->size);
3693                         break;
3694                 }
3695         }
3696         goto done;
3697
3698 no_flash_data:
3699         /* Use hardcoded defaults. */
3700         loc = locations[0];
3701
3702         hw->flt_region_fdt      = FA_FLASH_DESCR_ADDR_82;
3703         hw->flt_region_boot     = FA_BOOT_CODE_ADDR_82;
3704         hw->flt_region_bootload = FA_BOOT_LOAD_ADDR_82;
3705         hw->flt_region_fw       = FA_RISC_CODE_ADDR_82;
3706         hw->flt_region_chap     = FA_FLASH_ISCSI_CHAP >> 2;
3707         hw->flt_chap_size       = FA_FLASH_CHAP_SIZE;
3708         hw->flt_region_ddb      = FA_FLASH_ISCSI_DDB >> 2;
3709         hw->flt_ddb_size        = FA_FLASH_DDB_SIZE;
3710
3711 done:
3712         DEBUG2(ql4_printk(KERN_INFO, ha,
3713                           "FLT[%s]: flt=0x%x fdt=0x%x boot=0x%x bootload=0x%x fw=0x%x chap=0x%x chap_size=0x%x ddb=0x%x  ddb_size=0x%x\n",
3714                           loc, hw->flt_region_flt, hw->flt_region_fdt,
3715                           hw->flt_region_boot, hw->flt_region_bootload,
3716                           hw->flt_region_fw, hw->flt_region_chap,
3717                           hw->flt_chap_size, hw->flt_region_ddb,
3718                           hw->flt_ddb_size));
3719 }
3720
3721 static void
3722 qla4_82xx_get_fdt_info(struct scsi_qla_host *ha)
3723 {
3724 #define FLASH_BLK_SIZE_4K       0x1000
3725 #define FLASH_BLK_SIZE_32K      0x8000
3726 #define FLASH_BLK_SIZE_64K      0x10000
3727         const char *loc, *locations[] = { "MID", "FDT" };
3728         uint16_t cnt, chksum;
3729         uint16_t *wptr;
3730         struct qla_fdt_layout *fdt;
3731         uint16_t mid = 0;
3732         uint16_t fid = 0;
3733         struct ql82xx_hw_data *hw = &ha->hw;
3734
3735         hw->flash_conf_off = FARX_ACCESS_FLASH_CONF;
3736         hw->flash_data_off = FARX_ACCESS_FLASH_DATA;
3737
3738         wptr = (uint16_t *)ha->request_ring;
3739         fdt = (struct qla_fdt_layout *)ha->request_ring;
3740         qla4_82xx_read_optrom_data(ha, (uint8_t *)ha->request_ring,
3741             hw->flt_region_fdt << 2, OPTROM_BURST_SIZE);
3742
3743         if (*wptr == __constant_cpu_to_le16(0xffff))
3744                 goto no_flash_data;
3745
3746         if (fdt->sig[0] != 'Q' || fdt->sig[1] != 'L' || fdt->sig[2] != 'I' ||
3747             fdt->sig[3] != 'D')
3748                 goto no_flash_data;
3749
3750         for (cnt = 0, chksum = 0; cnt < sizeof(struct qla_fdt_layout) >> 1;
3751             cnt++)
3752                 chksum += le16_to_cpu(*wptr++);
3753
3754         if (chksum) {
3755                 DEBUG2(ql4_printk(KERN_INFO, ha, "Inconsistent FDT detected: "
3756                     "checksum=0x%x id=%c version=0x%x.\n", chksum, fdt->sig[0],
3757                     le16_to_cpu(fdt->version)));
3758                 goto no_flash_data;
3759         }
3760
3761         loc = locations[1];
3762         mid = le16_to_cpu(fdt->man_id);
3763         fid = le16_to_cpu(fdt->id);
3764         hw->fdt_wrt_disable = fdt->wrt_disable_bits;
3765         hw->fdt_erase_cmd = flash_conf_addr(hw, 0x0300 | fdt->erase_cmd);
3766         hw->fdt_block_size = le32_to_cpu(fdt->block_size);
3767
3768         if (fdt->unprotect_sec_cmd) {
3769                 hw->fdt_unprotect_sec_cmd = flash_conf_addr(hw, 0x0300 |
3770                     fdt->unprotect_sec_cmd);
3771                 hw->fdt_protect_sec_cmd = fdt->protect_sec_cmd ?
3772                     flash_conf_addr(hw, 0x0300 | fdt->protect_sec_cmd) :
3773                     flash_conf_addr(hw, 0x0336);
3774         }
3775         goto done;
3776
3777 no_flash_data:
3778         loc = locations[0];
3779         hw->fdt_block_size = FLASH_BLK_SIZE_64K;
3780 done:
3781         DEBUG2(ql4_printk(KERN_INFO, ha, "FDT[%s]: (0x%x/0x%x) erase=0x%x "
3782                 "pro=%x upro=%x wrtd=0x%x blk=0x%x.\n", loc, mid, fid,
3783                 hw->fdt_erase_cmd, hw->fdt_protect_sec_cmd,
3784                 hw->fdt_unprotect_sec_cmd, hw->fdt_wrt_disable,
3785                 hw->fdt_block_size));
3786 }
3787
3788 static void
3789 qla4_82xx_get_idc_param(struct scsi_qla_host *ha)
3790 {
3791 #define QLA82XX_IDC_PARAM_ADDR      0x003e885c
3792         uint32_t *wptr;
3793
3794         if (!is_qla8022(ha))
3795                 return;
3796         wptr = (uint32_t *)ha->request_ring;
3797         qla4_82xx_read_optrom_data(ha, (uint8_t *)ha->request_ring,
3798                         QLA82XX_IDC_PARAM_ADDR , 8);
3799
3800         if (*wptr == __constant_cpu_to_le32(0xffffffff)) {
3801                 ha->nx_dev_init_timeout = ROM_DEV_INIT_TIMEOUT;
3802                 ha->nx_reset_timeout = ROM_DRV_RESET_ACK_TIMEOUT;
3803         } else {
3804                 ha->nx_dev_init_timeout = le32_to_cpu(*wptr++);
3805                 ha->nx_reset_timeout = le32_to_cpu(*wptr);
3806         }
3807
3808         DEBUG2(ql4_printk(KERN_DEBUG, ha,
3809                 "ha->nx_dev_init_timeout = %d\n", ha->nx_dev_init_timeout));
3810         DEBUG2(ql4_printk(KERN_DEBUG, ha,
3811                 "ha->nx_reset_timeout = %d\n", ha->nx_reset_timeout));
3812         return;
3813 }
3814
3815 void qla4_82xx_queue_mbox_cmd(struct scsi_qla_host *ha, uint32_t *mbx_cmd,
3816                               int in_count)
3817 {
3818         int i;
3819
3820         /* Load all mailbox registers, except mailbox 0. */
3821         for (i = 1; i < in_count; i++)
3822                 writel(mbx_cmd[i], &ha->qla4_82xx_reg->mailbox_in[i]);
3823
3824         /* Wakeup firmware  */
3825         writel(mbx_cmd[0], &ha->qla4_82xx_reg->mailbox_in[0]);
3826         readl(&ha->qla4_82xx_reg->mailbox_in[0]);
3827         writel(HINT_MBX_INT_PENDING, &ha->qla4_82xx_reg->hint);
3828         readl(&ha->qla4_82xx_reg->hint);
3829 }
3830
3831 void qla4_82xx_process_mbox_intr(struct scsi_qla_host *ha, int out_count)
3832 {
3833         int intr_status;
3834
3835         intr_status = readl(&ha->qla4_82xx_reg->host_int);
3836         if (intr_status & ISRX_82XX_RISC_INT) {
3837                 ha->mbox_status_count = out_count;
3838                 intr_status = readl(&ha->qla4_82xx_reg->host_status);
3839                 ha->isp_ops->interrupt_service_routine(ha, intr_status);
3840
3841                 if (test_bit(AF_INTERRUPTS_ON, &ha->flags) &&
3842                     test_bit(AF_INTx_ENABLED, &ha->flags))
3843                         qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg,
3844                                         0xfbff);
3845         }
3846 }
3847
3848 int
3849 qla4_8xxx_get_flash_info(struct scsi_qla_host *ha)
3850 {
3851         int ret;
3852         uint32_t flt_addr;
3853
3854         ret = qla4_8xxx_find_flt_start(ha, &flt_addr);
3855         if (ret != QLA_SUCCESS)
3856                 return ret;
3857
3858         qla4_8xxx_get_flt_info(ha, flt_addr);
3859         if (is_qla8022(ha)) {
3860                 qla4_82xx_get_fdt_info(ha);
3861                 qla4_82xx_get_idc_param(ha);
3862         } else if (is_qla8032(ha) || is_qla8042(ha)) {
3863                 qla4_83xx_get_idc_param(ha);
3864         }
3865
3866         return QLA_SUCCESS;
3867 }
3868
3869 /**
3870  * qla4_8xxx_stop_firmware - stops firmware on specified adapter instance
3871  * @ha: pointer to host adapter structure.
3872  *
3873  * Remarks:
3874  * For iSCSI, throws away all I/O and AENs into bit bucket, so they will
3875  * not be available after successful return.  Driver must cleanup potential
3876  * outstanding I/O's after calling this funcion.
3877  **/
3878 int
3879 qla4_8xxx_stop_firmware(struct scsi_qla_host *ha)
3880 {
3881         int status;
3882         uint32_t mbox_cmd[MBOX_REG_COUNT];
3883         uint32_t mbox_sts[MBOX_REG_COUNT];
3884
3885         memset(&mbox_cmd, 0, sizeof(mbox_cmd));
3886         memset(&mbox_sts, 0, sizeof(mbox_sts));
3887
3888         mbox_cmd[0] = MBOX_CMD_STOP_FW;
3889         status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1,
3890             &mbox_cmd[0], &mbox_sts[0]);
3891
3892         DEBUG2(printk("scsi%ld: %s: status = %d\n", ha->host_no,
3893             __func__, status));
3894         return status;
3895 }
3896
3897 /**
3898  * qla4_82xx_isp_reset - Resets ISP and aborts all outstanding commands.
3899  * @ha: pointer to host adapter structure.
3900  **/
3901 int
3902 qla4_82xx_isp_reset(struct scsi_qla_host *ha)
3903 {
3904         int rval;
3905         uint32_t dev_state;
3906
3907         qla4_82xx_idc_lock(ha);
3908         dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3909
3910         if (dev_state == QLA8XXX_DEV_READY) {
3911                 ql4_printk(KERN_INFO, ha, "HW State: NEED RESET\n");
3912                 qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
3913                     QLA8XXX_DEV_NEED_RESET);
3914                 set_bit(AF_8XXX_RST_OWNER, &ha->flags);
3915         } else
3916                 ql4_printk(KERN_INFO, ha, "HW State: DEVICE INITIALIZING\n");
3917
3918         qla4_82xx_idc_unlock(ha);
3919
3920         rval = qla4_8xxx_device_state_handler(ha);
3921
3922         qla4_82xx_idc_lock(ha);
3923         qla4_8xxx_clear_rst_ready(ha);
3924         qla4_82xx_idc_unlock(ha);
3925
3926         if (rval == QLA_SUCCESS) {
3927                 ql4_printk(KERN_INFO, ha, "Clearing AF_RECOVERY in qla4_82xx_isp_reset\n");
3928                 clear_bit(AF_FW_RECOVERY, &ha->flags);
3929         }
3930
3931         return rval;
3932 }
3933
3934 /**
3935  * qla4_8xxx_get_sys_info - get adapter MAC address(es) and serial number
3936  * @ha: pointer to host adapter structure.
3937  *
3938  **/
3939 int qla4_8xxx_get_sys_info(struct scsi_qla_host *ha)
3940 {
3941         uint32_t mbox_cmd[MBOX_REG_COUNT];
3942         uint32_t mbox_sts[MBOX_REG_COUNT];
3943         struct mbx_sys_info *sys_info;
3944         dma_addr_t sys_info_dma;
3945         int status = QLA_ERROR;
3946
3947         sys_info = dma_alloc_coherent(&ha->pdev->dev, sizeof(*sys_info),
3948                                       &sys_info_dma, GFP_KERNEL);
3949         if (sys_info == NULL) {
3950                 DEBUG2(printk("scsi%ld: %s: Unable to allocate dma buffer.\n",
3951                     ha->host_no, __func__));
3952                 return status;
3953         }
3954
3955         memset(sys_info, 0, sizeof(*sys_info));
3956         memset(&mbox_cmd, 0, sizeof(mbox_cmd));
3957         memset(&mbox_sts, 0, sizeof(mbox_sts));
3958
3959         mbox_cmd[0] = MBOX_CMD_GET_SYS_INFO;
3960         mbox_cmd[1] = LSDW(sys_info_dma);
3961         mbox_cmd[2] = MSDW(sys_info_dma);
3962         mbox_cmd[4] = sizeof(*sys_info);
3963
3964         if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 6, &mbox_cmd[0],
3965             &mbox_sts[0]) != QLA_SUCCESS) {
3966                 DEBUG2(printk("scsi%ld: %s: GET_SYS_INFO failed\n",
3967                     ha->host_no, __func__));
3968                 goto exit_validate_mac82;
3969         }
3970
3971         /* Make sure we receive the minimum required data to cache internally */
3972         if (((is_qla8032(ha) || is_qla8042(ha)) ? mbox_sts[3] : mbox_sts[4]) <
3973             offsetof(struct mbx_sys_info, reserved)) {
3974                 DEBUG2(printk("scsi%ld: %s: GET_SYS_INFO data receive"
3975                     " error (%x)\n", ha->host_no, __func__, mbox_sts[4]));
3976                 goto exit_validate_mac82;
3977         }
3978
3979         /* Save M.A.C. address & serial_number */
3980         ha->port_num = sys_info->port_num;
3981         memcpy(ha->my_mac, &sys_info->mac_addr[0],
3982             min(sizeof(ha->my_mac), sizeof(sys_info->mac_addr)));
3983         memcpy(ha->serial_number, &sys_info->serial_number,
3984             min(sizeof(ha->serial_number), sizeof(sys_info->serial_number)));
3985         memcpy(ha->model_name, &sys_info->board_id_str,
3986                min(sizeof(ha->model_name), sizeof(sys_info->board_id_str)));
3987         ha->phy_port_cnt = sys_info->phys_port_cnt;
3988         ha->phy_port_num = sys_info->port_num;
3989         ha->iscsi_pci_func_cnt = sys_info->iscsi_pci_func_cnt;
3990
3991         DEBUG2(printk("scsi%ld: %s: "
3992             "mac %02x:%02x:%02x:%02x:%02x:%02x "
3993             "serial %s\n", ha->host_no, __func__,
3994             ha->my_mac[0], ha->my_mac[1], ha->my_mac[2],
3995             ha->my_mac[3], ha->my_mac[4], ha->my_mac[5],
3996             ha->serial_number));
3997
3998         status = QLA_SUCCESS;
3999
4000 exit_validate_mac82:
4001         dma_free_coherent(&ha->pdev->dev, sizeof(*sys_info), sys_info,
4002                           sys_info_dma);
4003         return status;
4004 }
4005
4006 /* Interrupt handling helpers. */
4007
4008 int qla4_8xxx_intr_enable(struct scsi_qla_host *ha)
4009 {
4010         uint32_t mbox_cmd[MBOX_REG_COUNT];
4011         uint32_t mbox_sts[MBOX_REG_COUNT];
4012
4013         DEBUG2(ql4_printk(KERN_INFO, ha, "%s\n", __func__));
4014
4015         memset(&mbox_cmd, 0, sizeof(mbox_cmd));
4016         memset(&mbox_sts, 0, sizeof(mbox_sts));
4017         mbox_cmd[0] = MBOX_CMD_ENABLE_INTRS;
4018         mbox_cmd[1] = INTR_ENABLE;
4019         if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
4020                 &mbox_sts[0]) != QLA_SUCCESS) {
4021                 DEBUG2(ql4_printk(KERN_INFO, ha,
4022                     "%s: MBOX_CMD_ENABLE_INTRS failed (0x%04x)\n",
4023                     __func__, mbox_sts[0]));
4024                 return QLA_ERROR;
4025         }
4026         return QLA_SUCCESS;
4027 }
4028
4029 int qla4_8xxx_intr_disable(struct scsi_qla_host *ha)
4030 {
4031         uint32_t mbox_cmd[MBOX_REG_COUNT];
4032         uint32_t mbox_sts[MBOX_REG_COUNT];
4033
4034         DEBUG2(ql4_printk(KERN_INFO, ha, "%s\n", __func__));
4035
4036         memset(&mbox_cmd, 0, sizeof(mbox_cmd));
4037         memset(&mbox_sts, 0, sizeof(mbox_sts));
4038         mbox_cmd[0] = MBOX_CMD_ENABLE_INTRS;
4039         mbox_cmd[1] = INTR_DISABLE;
4040         if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
4041             &mbox_sts[0]) != QLA_SUCCESS) {
4042                 DEBUG2(ql4_printk(KERN_INFO, ha,
4043                         "%s: MBOX_CMD_ENABLE_INTRS failed (0x%04x)\n",
4044                         __func__, mbox_sts[0]));
4045                 return QLA_ERROR;
4046         }
4047
4048         return QLA_SUCCESS;
4049 }
4050
4051 void
4052 qla4_82xx_enable_intrs(struct scsi_qla_host *ha)
4053 {
4054         qla4_8xxx_intr_enable(ha);
4055
4056         spin_lock_irq(&ha->hardware_lock);
4057         /* BIT 10 - reset */
4058         qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff);
4059         spin_unlock_irq(&ha->hardware_lock);
4060         set_bit(AF_INTERRUPTS_ON, &ha->flags);
4061 }
4062
4063 void
4064 qla4_82xx_disable_intrs(struct scsi_qla_host *ha)
4065 {
4066         if (test_and_clear_bit(AF_INTERRUPTS_ON, &ha->flags))
4067                 qla4_8xxx_intr_disable(ha);
4068
4069         spin_lock_irq(&ha->hardware_lock);
4070         /* BIT 10 - set */
4071         qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400);
4072         spin_unlock_irq(&ha->hardware_lock);
4073 }
4074
4075 struct ql4_init_msix_entry {
4076         uint16_t entry;
4077         uint16_t index;
4078         const char *name;
4079         irq_handler_t handler;
4080 };
4081
4082 static struct ql4_init_msix_entry qla4_8xxx_msix_entries[QLA_MSIX_ENTRIES] = {
4083         { QLA_MSIX_DEFAULT, QLA_MIDX_DEFAULT,
4084             "qla4xxx (default)",
4085             (irq_handler_t)qla4_8xxx_default_intr_handler },
4086         { QLA_MSIX_RSP_Q, QLA_MIDX_RSP_Q,
4087             "qla4xxx (rsp_q)", (irq_handler_t)qla4_8xxx_msix_rsp_q },
4088 };
4089
4090 void
4091 qla4_8xxx_disable_msix(struct scsi_qla_host *ha)
4092 {
4093         int i;
4094         struct ql4_msix_entry *qentry;
4095
4096         for (i = 0; i < QLA_MSIX_ENTRIES; i++) {
4097                 qentry = &ha->msix_entries[qla4_8xxx_msix_entries[i].index];
4098                 if (qentry->have_irq) {
4099                         free_irq(qentry->msix_vector, ha);
4100                         DEBUG2(ql4_printk(KERN_INFO, ha, "%s: %s\n",
4101                                 __func__, qla4_8xxx_msix_entries[i].name));
4102                 }
4103         }
4104         pci_disable_msix(ha->pdev);
4105         clear_bit(AF_MSIX_ENABLED, &ha->flags);
4106 }
4107
4108 int
4109 qla4_8xxx_enable_msix(struct scsi_qla_host *ha)
4110 {
4111         int i, ret;
4112         struct msix_entry entries[QLA_MSIX_ENTRIES];
4113         struct ql4_msix_entry *qentry;
4114
4115         for (i = 0; i < QLA_MSIX_ENTRIES; i++)
4116                 entries[i].entry = qla4_8xxx_msix_entries[i].entry;
4117
4118         ret = pci_enable_msix(ha->pdev, entries, ARRAY_SIZE(entries));
4119         if (ret) {
4120                 ql4_printk(KERN_WARNING, ha,
4121                     "MSI-X: Failed to enable support -- %d/%d\n",
4122                     QLA_MSIX_ENTRIES, ret);
4123                 goto msix_out;
4124         }
4125         set_bit(AF_MSIX_ENABLED, &ha->flags);
4126
4127         for (i = 0; i < QLA_MSIX_ENTRIES; i++) {
4128                 qentry = &ha->msix_entries[qla4_8xxx_msix_entries[i].index];
4129                 qentry->msix_vector = entries[i].vector;
4130                 qentry->msix_entry = entries[i].entry;
4131                 qentry->have_irq = 0;
4132                 ret = request_irq(qentry->msix_vector,
4133                     qla4_8xxx_msix_entries[i].handler, 0,
4134                     qla4_8xxx_msix_entries[i].name, ha);
4135                 if (ret) {
4136                         ql4_printk(KERN_WARNING, ha,
4137                             "MSI-X: Unable to register handler -- %x/%d.\n",
4138                             qla4_8xxx_msix_entries[i].index, ret);
4139                         qla4_8xxx_disable_msix(ha);
4140                         goto msix_out;
4141                 }
4142                 qentry->have_irq = 1;
4143                 DEBUG2(ql4_printk(KERN_INFO, ha, "%s: %s\n",
4144                         __func__, qla4_8xxx_msix_entries[i].name));
4145         }
4146 msix_out:
4147         return ret;
4148 }
4149
4150 int qla4_8xxx_check_init_adapter_retry(struct scsi_qla_host *ha)
4151 {
4152         int status = QLA_SUCCESS;
4153
4154         /* Dont retry adapter initialization if IRQ allocation failed */
4155         if (!test_bit(AF_IRQ_ATTACHED, &ha->flags)) {
4156                 ql4_printk(KERN_WARNING, ha, "%s: Skipping retry of adapter initialization as IRQs are not attached\n",
4157                            __func__);
4158                 status = QLA_ERROR;
4159                 goto exit_init_adapter_failure;
4160         }
4161
4162         /* Since interrupts are registered in start_firmware for
4163          * 8xxx, release them here if initialize_adapter fails
4164          * and retry adapter initialization */
4165         qla4xxx_free_irqs(ha);
4166
4167 exit_init_adapter_failure:
4168         return status;
4169 }