2 * linux/drivers/char/8250_pci.c
4 * Probe module for 8250/16550-type PCI serial ports.
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
8 * Copyright (C) 2001 Russell King, All Rights Reserved.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
14 * $Id: 8250_pci.c,v 1.28 2002/11/02 11:14:18 rmk Exp $
16 #include <linux/module.h>
17 #include <linux/init.h>
18 #include <linux/pci.h>
19 #include <linux/sched.h>
20 #include <linux/string.h>
21 #include <linux/kernel.h>
22 #include <linux/slab.h>
23 #include <linux/delay.h>
24 #include <linux/tty.h>
25 #include <linux/serial_core.h>
26 #include <linux/8250_pci.h>
27 #include <linux/bitops.h>
29 #include <asm/byteorder.h>
34 #undef SERIAL_DEBUG_PCI
37 * init function returns:
38 * > 0 - number of ports
39 * = 0 - use board->num_ports
42 struct pci_serial_quirk {
47 int (*init)(struct pci_dev *dev);
48 int (*setup)(struct serial_private *, struct pciserial_board *,
49 struct uart_port *, int);
50 void (*exit)(struct pci_dev *dev);
53 #define PCI_NUM_BAR_RESOURCES 6
55 struct serial_private {
58 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
59 struct pci_serial_quirk *quirk;
63 static void moan_device(const char *str, struct pci_dev *dev)
65 printk(KERN_WARNING "%s: %s\n"
66 KERN_WARNING "Please send the output of lspci -vv, this\n"
67 KERN_WARNING "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
68 KERN_WARNING "manufacturer and name of serial board or\n"
69 KERN_WARNING "modem board to rmk+serial@arm.linux.org.uk.\n",
70 pci_name(dev), str, dev->vendor, dev->device,
71 dev->subsystem_vendor, dev->subsystem_device);
75 setup_port(struct serial_private *priv, struct uart_port *port,
76 int bar, int offset, int regshift)
78 struct pci_dev *dev = priv->dev;
79 unsigned long base, len;
81 if (bar >= PCI_NUM_BAR_RESOURCES)
84 base = pci_resource_start(dev, bar);
86 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
87 len = pci_resource_len(dev, bar);
89 if (!priv->remapped_bar[bar])
90 priv->remapped_bar[bar] = ioremap(base, len);
91 if (!priv->remapped_bar[bar])
94 port->iotype = UPIO_MEM;
96 port->mapbase = base + offset;
97 port->membase = priv->remapped_bar[bar] + offset;
98 port->regshift = regshift;
100 port->iotype = UPIO_PORT;
101 port->iobase = base + offset;
103 port->membase = NULL;
110 * AFAVLAB uses a different mixture of BARs and offsets
111 * Not that ugly ;) -- HW
114 afavlab_setup(struct serial_private *priv, struct pciserial_board *board,
115 struct uart_port *port, int idx)
117 unsigned int bar, offset = board->first_offset;
119 bar = FL_GET_BASE(board->flags);
124 offset += (idx - 4) * board->uart_offset;
127 return setup_port(priv, port, bar, offset, board->reg_shift);
131 * HP's Remote Management Console. The Diva chip came in several
132 * different versions. N-class, L2000 and A500 have two Diva chips, each
133 * with 3 UARTs (the third UART on the second chip is unused). Superdome
134 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
135 * one Diva chip, but it has been expanded to 5 UARTs.
137 static int __devinit pci_hp_diva_init(struct pci_dev *dev)
141 switch (dev->subsystem_device) {
142 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
143 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
144 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
145 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
148 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
151 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
154 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
163 * HP's Diva chip puts the 4th/5th serial port further out, and
164 * some serial ports are supposed to be hidden on certain models.
167 pci_hp_diva_setup(struct serial_private *priv, struct pciserial_board *board,
168 struct uart_port *port, int idx)
170 unsigned int offset = board->first_offset;
171 unsigned int bar = FL_GET_BASE(board->flags);
173 switch (priv->dev->subsystem_device) {
174 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
178 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
188 offset += idx * board->uart_offset;
190 return setup_port(priv, port, bar, offset, board->reg_shift);
194 * Added for EKF Intel i960 serial boards
196 static int __devinit pci_inteli960ni_init(struct pci_dev *dev)
198 unsigned long oldval;
200 if (!(dev->subsystem_device & 0x1000))
203 /* is firmware started? */
204 pci_read_config_dword(dev, 0x44, (void*) &oldval);
205 if (oldval == 0x00001000L) { /* RESET value */
206 printk(KERN_DEBUG "Local i960 firmware missing");
213 * Some PCI serial cards using the PLX 9050 PCI interface chip require
214 * that the card interrupt be explicitly enabled or disabled. This
215 * seems to be mainly needed on card using the PLX which also use I/O
218 static int __devinit pci_plx9050_init(struct pci_dev *dev)
223 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
224 moan_device("no memory in bar 0", dev);
229 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
230 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS) {
233 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
234 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) {
236 * As the megawolf cards have the int pins active
237 * high, and have 2 UART chips, both ints must be
238 * enabled on the 9050. Also, the UARTS are set in
239 * 16450 mode by default, so we have to enable the
240 * 16C950 'enhanced' mode so that we can use the
247 * enable/disable interrupts
249 p = ioremap(pci_resource_start(dev, 0), 0x80);
252 writel(irq_config, p + 0x4c);
255 * Read the register back to ensure that it took effect.
263 static void __devexit pci_plx9050_exit(struct pci_dev *dev)
267 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
273 p = ioremap(pci_resource_start(dev, 0), 0x80);
278 * Read the register back to ensure that it took effect.
285 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
287 sbs_setup(struct serial_private *priv, struct pciserial_board *board,
288 struct uart_port *port, int idx)
290 unsigned int bar, offset = board->first_offset;
295 /* first four channels map to 0, 0x100, 0x200, 0x300 */
296 offset += idx * board->uart_offset;
297 } else if (idx < 8) {
298 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
299 offset += idx * board->uart_offset + 0xC00;
300 } else /* we have only 8 ports on PMC-OCTALPRO */
303 return setup_port(priv, port, bar, offset, board->reg_shift);
307 * This does initialization for PMC OCTALPRO cards:
308 * maps the device memory, resets the UARTs (needed, bc
309 * if the module is removed and inserted again, the card
310 * is in the sleep mode) and enables global interrupt.
313 /* global control register offset for SBS PMC-OctalPro */
314 #define OCT_REG_CR_OFF 0x500
316 static int __devinit sbs_init(struct pci_dev *dev)
320 p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
324 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
325 writeb(0x10,p + OCT_REG_CR_OFF);
327 writeb(0x0,p + OCT_REG_CR_OFF);
329 /* Set bit-2 (INTENABLE) of Control Register */
330 writeb(0x4, p + OCT_REG_CR_OFF);
337 * Disables the global interrupt of PMC-OctalPro
340 static void __devexit sbs_exit(struct pci_dev *dev)
344 p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
346 writeb(0, p + OCT_REG_CR_OFF);
352 * SIIG serial cards have an PCI interface chip which also controls
353 * the UART clocking frequency. Each UART can be clocked independently
354 * (except cards equiped with 4 UARTs) and initial clocking settings
355 * are stored in the EEPROM chip. It can cause problems because this
356 * version of serial driver doesn't support differently clocked UART's
357 * on single PCI card. To prevent this, initialization functions set
358 * high frequency clocking for all UART's on given card. It is safe (I
359 * hope) because it doesn't touch EEPROM settings to prevent conflicts
360 * with other OSes (like M$ DOS).
362 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
364 * There is two family of SIIG serial cards with different PCI
365 * interface chip and different configuration methods:
366 * - 10x cards have control registers in IO and/or memory space;
367 * - 20x cards have control registers in standard PCI configuration space.
369 * Note: all 10x cards have PCI device ids 0x10..
370 * all 20x cards have PCI device ids 0x20..
372 * There are also Quartet Serial cards which use Oxford Semiconductor
373 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
375 * Note: some SIIG cards are probed by the parport_serial object.
378 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
379 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
381 static int pci_siig10x_init(struct pci_dev *dev)
386 switch (dev->device & 0xfff8) {
387 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
390 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
393 default: /* 1S1P, 4S */
398 p = ioremap(pci_resource_start(dev, 0), 0x80);
402 writew(readw(p + 0x28) & data, p + 0x28);
408 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
409 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
411 static int pci_siig20x_init(struct pci_dev *dev)
415 /* Change clock frequency for the first UART. */
416 pci_read_config_byte(dev, 0x6f, &data);
417 pci_write_config_byte(dev, 0x6f, data & 0xef);
419 /* If this card has 2 UART, we have to do the same with second UART. */
420 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
421 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
422 pci_read_config_byte(dev, 0x73, &data);
423 pci_write_config_byte(dev, 0x73, data & 0xef);
428 static int pci_siig_init(struct pci_dev *dev)
430 unsigned int type = dev->device & 0xff00;
433 return pci_siig10x_init(dev);
434 else if (type == 0x2000)
435 return pci_siig20x_init(dev);
437 moan_device("Unknown SIIG card", dev);
442 * Timedia has an explosion of boards, and to avoid the PCI table from
443 * growing *huge*, we use this function to collapse some 70 entries
444 * in the PCI table into one, for sanity's and compactness's sake.
446 static unsigned short timedia_single_port[] = {
447 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
450 static unsigned short timedia_dual_port[] = {
451 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
452 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
453 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
454 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
458 static unsigned short timedia_quad_port[] = {
459 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
460 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
461 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
465 static unsigned short timedia_eight_port[] = {
466 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
467 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
470 static struct timedia_struct {
474 { 1, timedia_single_port },
475 { 2, timedia_dual_port },
476 { 4, timedia_quad_port },
477 { 8, timedia_eight_port },
481 static int __devinit pci_timedia_init(struct pci_dev *dev)
486 for (i = 0; timedia_data[i].num; i++) {
487 ids = timedia_data[i].ids;
488 for (j = 0; ids[j]; j++)
489 if (dev->subsystem_device == ids[j])
490 return timedia_data[i].num;
496 * Timedia/SUNIX uses a mixture of BARs and offsets
497 * Ugh, this is ugly as all hell --- TYT
500 pci_timedia_setup(struct serial_private *priv, struct pciserial_board *board,
501 struct uart_port *port, int idx)
503 unsigned int bar = 0, offset = board->first_offset;
510 offset = board->uart_offset;
517 offset = board->uart_offset;
526 return setup_port(priv, port, bar, offset, board->reg_shift);
530 * Some Titan cards are also a little weird
533 titan_400l_800l_setup(struct serial_private *priv,
534 struct pciserial_board *board,
535 struct uart_port *port, int idx)
537 unsigned int bar, offset = board->first_offset;
548 offset = (idx - 2) * board->uart_offset;
551 return setup_port(priv, port, bar, offset, board->reg_shift);
554 static int __devinit pci_xircom_init(struct pci_dev *dev)
560 static int __devinit pci_netmos_init(struct pci_dev *dev)
562 /* subdevice 0x00PS means <P> parallel, <S> serial */
563 unsigned int num_serial = dev->subsystem_device & 0xf;
571 pci_default_setup(struct serial_private *priv, struct pciserial_board *board,
572 struct uart_port *port, int idx)
574 unsigned int bar, offset = board->first_offset, maxnr;
576 bar = FL_GET_BASE(board->flags);
577 if (board->flags & FL_BASE_BARS)
580 offset += idx * board->uart_offset;
582 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) /
583 (8 << board->reg_shift);
585 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
588 return setup_port(priv, port, bar, offset, board->reg_shift);
591 /* This should be in linux/pci_ids.h */
592 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
593 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
594 #define PCI_DEVICE_ID_OCTPRO 0x0001
595 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
596 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
597 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
598 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
601 * Master list of serial port init/setup/exit quirks.
602 * This does not describe the general nature of the port.
603 * (ie, baud base, number and location of ports, etc)
605 * This list is ordered alphabetically by vendor then device.
606 * Specific entries must come before more generic entries.
608 static struct pci_serial_quirk pci_serial_quirks[] = {
611 * It is not clear whether this applies to all products.
614 .vendor = PCI_VENDOR_ID_AFAVLAB,
615 .device = PCI_ANY_ID,
616 .subvendor = PCI_ANY_ID,
617 .subdevice = PCI_ANY_ID,
618 .setup = afavlab_setup,
624 .vendor = PCI_VENDOR_ID_HP,
625 .device = PCI_DEVICE_ID_HP_DIVA,
626 .subvendor = PCI_ANY_ID,
627 .subdevice = PCI_ANY_ID,
628 .init = pci_hp_diva_init,
629 .setup = pci_hp_diva_setup,
635 .vendor = PCI_VENDOR_ID_INTEL,
636 .device = PCI_DEVICE_ID_INTEL_80960_RP,
638 .subdevice = PCI_ANY_ID,
639 .init = pci_inteli960ni_init,
640 .setup = pci_default_setup,
646 .vendor = PCI_VENDOR_ID_PANACOM,
647 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
648 .subvendor = PCI_ANY_ID,
649 .subdevice = PCI_ANY_ID,
650 .init = pci_plx9050_init,
651 .setup = pci_default_setup,
652 .exit = __devexit_p(pci_plx9050_exit),
655 .vendor = PCI_VENDOR_ID_PANACOM,
656 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
657 .subvendor = PCI_ANY_ID,
658 .subdevice = PCI_ANY_ID,
659 .init = pci_plx9050_init,
660 .setup = pci_default_setup,
661 .exit = __devexit_p(pci_plx9050_exit),
667 .vendor = PCI_VENDOR_ID_PLX,
668 .device = PCI_DEVICE_ID_PLX_9050,
669 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
670 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
671 .init = pci_plx9050_init,
672 .setup = pci_default_setup,
673 .exit = __devexit_p(pci_plx9050_exit),
676 .vendor = PCI_VENDOR_ID_PLX,
677 .device = PCI_DEVICE_ID_PLX_9050,
678 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
679 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
680 .init = pci_plx9050_init,
681 .setup = pci_default_setup,
682 .exit = __devexit_p(pci_plx9050_exit),
685 .vendor = PCI_VENDOR_ID_PLX,
686 .device = PCI_DEVICE_ID_PLX_ROMULUS,
687 .subvendor = PCI_VENDOR_ID_PLX,
688 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
689 .init = pci_plx9050_init,
690 .setup = pci_default_setup,
691 .exit = __devexit_p(pci_plx9050_exit),
694 * SBS Technologies, Inc., PMC-OCTALPRO 232
697 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
698 .device = PCI_DEVICE_ID_OCTPRO,
699 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
700 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
703 .exit = __devexit_p(sbs_exit),
706 * SBS Technologies, Inc., PMC-OCTALPRO 422
709 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
710 .device = PCI_DEVICE_ID_OCTPRO,
711 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
712 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
715 .exit = __devexit_p(sbs_exit),
718 * SBS Technologies, Inc., P-Octal 232
721 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
722 .device = PCI_DEVICE_ID_OCTPRO,
723 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
724 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
727 .exit = __devexit_p(sbs_exit),
730 * SBS Technologies, Inc., P-Octal 422
733 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
734 .device = PCI_DEVICE_ID_OCTPRO,
735 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
736 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
739 .exit = __devexit_p(sbs_exit),
745 .vendor = PCI_VENDOR_ID_SIIG,
746 .device = PCI_ANY_ID,
747 .subvendor = PCI_ANY_ID,
748 .subdevice = PCI_ANY_ID,
749 .init = pci_siig_init,
750 .setup = pci_default_setup,
756 .vendor = PCI_VENDOR_ID_TITAN,
757 .device = PCI_DEVICE_ID_TITAN_400L,
758 .subvendor = PCI_ANY_ID,
759 .subdevice = PCI_ANY_ID,
760 .setup = titan_400l_800l_setup,
763 .vendor = PCI_VENDOR_ID_TITAN,
764 .device = PCI_DEVICE_ID_TITAN_800L,
765 .subvendor = PCI_ANY_ID,
766 .subdevice = PCI_ANY_ID,
767 .setup = titan_400l_800l_setup,
773 .vendor = PCI_VENDOR_ID_TIMEDIA,
774 .device = PCI_DEVICE_ID_TIMEDIA_1889,
775 .subvendor = PCI_VENDOR_ID_TIMEDIA,
776 .subdevice = PCI_ANY_ID,
777 .init = pci_timedia_init,
778 .setup = pci_timedia_setup,
781 .vendor = PCI_VENDOR_ID_TIMEDIA,
782 .device = PCI_ANY_ID,
783 .subvendor = PCI_ANY_ID,
784 .subdevice = PCI_ANY_ID,
785 .setup = pci_timedia_setup,
791 .vendor = PCI_VENDOR_ID_XIRCOM,
792 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
793 .subvendor = PCI_ANY_ID,
794 .subdevice = PCI_ANY_ID,
795 .init = pci_xircom_init,
796 .setup = pci_default_setup,
802 .vendor = PCI_VENDOR_ID_NETMOS,
803 .device = PCI_ANY_ID,
804 .subvendor = PCI_ANY_ID,
805 .subdevice = PCI_ANY_ID,
806 .init = pci_netmos_init,
807 .setup = pci_default_setup,
810 * Default "match everything" terminator entry
813 .vendor = PCI_ANY_ID,
814 .device = PCI_ANY_ID,
815 .subvendor = PCI_ANY_ID,
816 .subdevice = PCI_ANY_ID,
817 .setup = pci_default_setup,
821 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
823 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
826 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
828 struct pci_serial_quirk *quirk;
830 for (quirk = pci_serial_quirks; ; quirk++)
831 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
832 quirk_id_matches(quirk->device, dev->device) &&
833 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
834 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
840 get_pci_irq(struct pci_dev *dev, struct pciserial_board *board)
842 if (board->flags & FL_NOIRQ)
849 * This is the configuration table for all of the PCI serial boards
850 * which we support. It is directly indexed by the pci_board_num_t enum
851 * value, which is encoded in the pci_device_id PCI probe table's
852 * driver_data member.
854 * The makeup of these names are:
857 * bn = PCI BAR number
858 * bt = Index using PCI BARs
859 * n = number of serial ports
862 * This table is sorted by (in order): baud, bt, bn, n.
864 * Please note: in theory if n = 1, _bt infix should make no difference.
865 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
867 enum pci_board_num_t {
936 * Board-specific versions.
957 * uart_offset - the space between channels
958 * reg_shift - describes how the UART registers are mapped
959 * to PCI memory by the card.
960 * For example IER register on SBS, Inc. PMC-OctPro is located at
961 * offset 0x10 from the UART base, while UART_IER is defined as 1
962 * in include/linux/serial_reg.h,
963 * see first lines of serial_in() and serial_out() in 8250.c
966 static struct pciserial_board pci_boards[] __devinitdata = {
973 [pbn_b0_1_115200] = {
979 [pbn_b0_2_115200] = {
985 [pbn_b0_4_115200] = {
991 [pbn_b0_5_115200] = {
998 [pbn_b0_1_921600] = {
1001 .base_baud = 921600,
1004 [pbn_b0_2_921600] = {
1007 .base_baud = 921600,
1010 [pbn_b0_4_921600] = {
1013 .base_baud = 921600,
1017 [pbn_b0_2_1130000] = {
1020 .base_baud = 1130000,
1024 [pbn_b0_4_1152000] = {
1027 .base_baud = 1152000,
1031 [pbn_b0_bt_1_115200] = {
1032 .flags = FL_BASE0|FL_BASE_BARS,
1034 .base_baud = 115200,
1037 [pbn_b0_bt_2_115200] = {
1038 .flags = FL_BASE0|FL_BASE_BARS,
1040 .base_baud = 115200,
1043 [pbn_b0_bt_8_115200] = {
1044 .flags = FL_BASE0|FL_BASE_BARS,
1046 .base_baud = 115200,
1050 [pbn_b0_bt_1_460800] = {
1051 .flags = FL_BASE0|FL_BASE_BARS,
1053 .base_baud = 460800,
1056 [pbn_b0_bt_2_460800] = {
1057 .flags = FL_BASE0|FL_BASE_BARS,
1059 .base_baud = 460800,
1062 [pbn_b0_bt_4_460800] = {
1063 .flags = FL_BASE0|FL_BASE_BARS,
1065 .base_baud = 460800,
1069 [pbn_b0_bt_1_921600] = {
1070 .flags = FL_BASE0|FL_BASE_BARS,
1072 .base_baud = 921600,
1075 [pbn_b0_bt_2_921600] = {
1076 .flags = FL_BASE0|FL_BASE_BARS,
1078 .base_baud = 921600,
1081 [pbn_b0_bt_4_921600] = {
1082 .flags = FL_BASE0|FL_BASE_BARS,
1084 .base_baud = 921600,
1087 [pbn_b0_bt_8_921600] = {
1088 .flags = FL_BASE0|FL_BASE_BARS,
1090 .base_baud = 921600,
1094 [pbn_b1_1_115200] = {
1097 .base_baud = 115200,
1100 [pbn_b1_2_115200] = {
1103 .base_baud = 115200,
1106 [pbn_b1_4_115200] = {
1109 .base_baud = 115200,
1112 [pbn_b1_8_115200] = {
1115 .base_baud = 115200,
1119 [pbn_b1_1_921600] = {
1122 .base_baud = 921600,
1125 [pbn_b1_2_921600] = {
1128 .base_baud = 921600,
1131 [pbn_b1_4_921600] = {
1134 .base_baud = 921600,
1137 [pbn_b1_8_921600] = {
1140 .base_baud = 921600,
1144 [pbn_b1_bt_2_921600] = {
1145 .flags = FL_BASE1|FL_BASE_BARS,
1147 .base_baud = 921600,
1151 [pbn_b1_1_1382400] = {
1154 .base_baud = 1382400,
1157 [pbn_b1_2_1382400] = {
1160 .base_baud = 1382400,
1163 [pbn_b1_4_1382400] = {
1166 .base_baud = 1382400,
1169 [pbn_b1_8_1382400] = {
1172 .base_baud = 1382400,
1176 [pbn_b2_1_115200] = {
1179 .base_baud = 115200,
1182 [pbn_b2_8_115200] = {
1185 .base_baud = 115200,
1189 [pbn_b2_1_460800] = {
1192 .base_baud = 460800,
1195 [pbn_b2_4_460800] = {
1198 .base_baud = 460800,
1201 [pbn_b2_8_460800] = {
1204 .base_baud = 460800,
1207 [pbn_b2_16_460800] = {
1210 .base_baud = 460800,
1214 [pbn_b2_1_921600] = {
1217 .base_baud = 921600,
1220 [pbn_b2_4_921600] = {
1223 .base_baud = 921600,
1226 [pbn_b2_8_921600] = {
1229 .base_baud = 921600,
1233 [pbn_b2_bt_1_115200] = {
1234 .flags = FL_BASE2|FL_BASE_BARS,
1236 .base_baud = 115200,
1239 [pbn_b2_bt_2_115200] = {
1240 .flags = FL_BASE2|FL_BASE_BARS,
1242 .base_baud = 115200,
1245 [pbn_b2_bt_4_115200] = {
1246 .flags = FL_BASE2|FL_BASE_BARS,
1248 .base_baud = 115200,
1252 [pbn_b2_bt_2_921600] = {
1253 .flags = FL_BASE2|FL_BASE_BARS,
1255 .base_baud = 921600,
1258 [pbn_b2_bt_4_921600] = {
1259 .flags = FL_BASE2|FL_BASE_BARS,
1261 .base_baud = 921600,
1265 [pbn_b3_4_115200] = {
1268 .base_baud = 115200,
1271 [pbn_b3_8_115200] = {
1274 .base_baud = 115200,
1279 * Entries following this are board-specific.
1288 .base_baud = 921600,
1289 .uart_offset = 0x400,
1293 .flags = FL_BASE2|FL_BASE_BARS,
1295 .base_baud = 921600,
1296 .uart_offset = 0x400,
1300 .flags = FL_BASE2|FL_BASE_BARS,
1302 .base_baud = 921600,
1303 .uart_offset = 0x400,
1307 [pbn_exsys_4055] = {
1310 .base_baud = 115200,
1314 /* I think this entry is broken - the first_offset looks wrong --rmk */
1315 [pbn_plx_romulus] = {
1318 .base_baud = 921600,
1319 .uart_offset = 8 << 2,
1321 .first_offset = 0x03,
1325 * This board uses the size of PCI Base region 0 to
1326 * signal now many ports are available
1329 .flags = FL_BASE0|FL_REGION_SZ_CAP,
1331 .base_baud = 115200,
1336 * EKF addition for i960 Boards form EKF with serial port.
1339 [pbn_intel_i960] = {
1342 .base_baud = 921600,
1343 .uart_offset = 8 << 2,
1345 .first_offset = 0x10000,
1348 .flags = FL_BASE0|FL_NOIRQ,
1350 .base_baud = 458333,
1353 .first_offset = 0x20178,
1357 * NEC Vrc-5074 (Nile 4) builtin UART.
1362 .base_baud = 520833,
1363 .uart_offset = 8 << 3,
1365 .first_offset = 0x300,
1369 * Computone - uses IOMEM.
1371 [pbn_computone_4] = {
1374 .base_baud = 921600,
1375 .uart_offset = 0x40,
1377 .first_offset = 0x200,
1379 [pbn_computone_6] = {
1382 .base_baud = 921600,
1383 .uart_offset = 0x40,
1385 .first_offset = 0x200,
1387 [pbn_computone_8] = {
1390 .base_baud = 921600,
1391 .uart_offset = 0x40,
1393 .first_offset = 0x200,
1398 .base_baud = 460800,
1403 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
1404 * Only basic 16550A support.
1405 * XR17C15[24] are not tested, but they should work.
1407 [pbn_exar_XR17C152] = {
1410 .base_baud = 921600,
1411 .uart_offset = 0x200,
1413 [pbn_exar_XR17C154] = {
1416 .base_baud = 921600,
1417 .uart_offset = 0x200,
1419 [pbn_exar_XR17C158] = {
1422 .base_baud = 921600,
1423 .uart_offset = 0x200,
1428 * Given a complete unknown PCI device, try to use some heuristics to
1429 * guess what the configuration might be, based on the pitiful PCI
1430 * serial specs. Returns 0 on success, 1 on failure.
1432 static int __devinit
1433 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
1435 int num_iomem, num_port, first_port = -1, i;
1438 * If it is not a communications device or the programming
1439 * interface is greater than 6, give up.
1441 * (Should we try to make guesses for multiport serial devices
1444 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
1445 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
1446 (dev->class & 0xff) > 6)
1449 num_iomem = num_port = 0;
1450 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1451 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
1453 if (first_port == -1)
1456 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
1461 * If there is 1 or 0 iomem regions, and exactly one port,
1462 * use it. We guess the number of ports based on the IO
1465 if (num_iomem <= 1 && num_port == 1) {
1466 board->flags = first_port;
1467 board->num_ports = pci_resource_len(dev, first_port) / 8;
1472 * Now guess if we've got a board which indexes by BARs.
1473 * Each IO BAR should be 8 bytes, and they should follow
1478 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1479 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
1480 pci_resource_len(dev, i) == 8 &&
1481 (first_port == -1 || (first_port + num_port) == i)) {
1483 if (first_port == -1)
1489 board->flags = first_port | FL_BASE_BARS;
1490 board->num_ports = num_port;
1498 serial_pci_matches(struct pciserial_board *board,
1499 struct pciserial_board *guessed)
1502 board->num_ports == guessed->num_ports &&
1503 board->base_baud == guessed->base_baud &&
1504 board->uart_offset == guessed->uart_offset &&
1505 board->reg_shift == guessed->reg_shift &&
1506 board->first_offset == guessed->first_offset;
1509 struct serial_private *
1510 pciserial_init_ports(struct pci_dev *dev, struct pciserial_board *board)
1512 struct uart_port serial_port;
1513 struct serial_private *priv;
1514 struct pci_serial_quirk *quirk;
1515 int rc, nr_ports, i;
1517 nr_ports = board->num_ports;
1520 * Find an init and setup quirks.
1522 quirk = find_quirk(dev);
1525 * Run the new-style initialization function.
1526 * The initialization function returns:
1528 * 0 - use board->num_ports
1529 * >0 - number of ports
1532 rc = quirk->init(dev);
1541 priv = kmalloc(sizeof(struct serial_private) +
1542 sizeof(unsigned int) * nr_ports,
1545 priv = ERR_PTR(-ENOMEM);
1549 memset(priv, 0, sizeof(struct serial_private) +
1550 sizeof(unsigned int) * nr_ports);
1553 priv->quirk = quirk;
1555 memset(&serial_port, 0, sizeof(struct uart_port));
1556 serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
1557 serial_port.uartclk = board->base_baud * 16;
1558 serial_port.irq = get_pci_irq(dev, board);
1559 serial_port.dev = &dev->dev;
1561 for (i = 0; i < nr_ports; i++) {
1562 if (quirk->setup(priv, board, &serial_port, i))
1565 #ifdef SERIAL_DEBUG_PCI
1566 printk("Setup PCI port: port %x, irq %d, type %d\n",
1567 serial_port.iobase, serial_port.irq, serial_port.iotype);
1570 priv->line[i] = serial8250_register_port(&serial_port);
1571 if (priv->line[i] < 0) {
1572 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
1587 EXPORT_SYMBOL_GPL(pciserial_init_ports);
1589 void pciserial_remove_ports(struct serial_private *priv)
1591 struct pci_serial_quirk *quirk;
1594 for (i = 0; i < priv->nr; i++)
1595 serial8250_unregister_port(priv->line[i]);
1597 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1598 if (priv->remapped_bar[i])
1599 iounmap(priv->remapped_bar[i]);
1600 priv->remapped_bar[i] = NULL;
1604 * Find the exit quirks.
1606 quirk = find_quirk(priv->dev);
1608 quirk->exit(priv->dev);
1612 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
1614 void pciserial_suspend_ports(struct serial_private *priv)
1618 for (i = 0; i < priv->nr; i++)
1619 if (priv->line[i] >= 0)
1620 serial8250_suspend_port(priv->line[i]);
1622 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
1624 void pciserial_resume_ports(struct serial_private *priv)
1629 * Ensure that the board is correctly configured.
1631 if (priv->quirk->init)
1632 priv->quirk->init(priv->dev);
1634 for (i = 0; i < priv->nr; i++)
1635 if (priv->line[i] >= 0)
1636 serial8250_resume_port(priv->line[i]);
1638 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
1641 * Probe one serial board. Unfortunately, there is no rhyme nor reason
1642 * to the arrangement of serial ports on a PCI card.
1644 static int __devinit
1645 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
1647 struct serial_private *priv;
1648 struct pciserial_board *board, tmp;
1651 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
1652 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
1657 board = &pci_boards[ent->driver_data];
1659 rc = pci_enable_device(dev);
1663 if (ent->driver_data == pbn_default) {
1665 * Use a copy of the pci_board entry for this;
1666 * avoid changing entries in the table.
1668 memcpy(&tmp, board, sizeof(struct pciserial_board));
1672 * We matched one of our class entries. Try to
1673 * determine the parameters of this board.
1675 rc = serial_pci_guess_board(dev, board);
1680 * We matched an explicit entry. If we are able to
1681 * detect this boards settings with our heuristic,
1682 * then we no longer need this entry.
1684 memcpy(&tmp, &pci_boards[pbn_default],
1685 sizeof(struct pciserial_board));
1686 rc = serial_pci_guess_board(dev, &tmp);
1687 if (rc == 0 && serial_pci_matches(board, &tmp))
1688 moan_device("Redundant entry in serial pci_table.",
1692 priv = pciserial_init_ports(dev, board);
1693 if (!IS_ERR(priv)) {
1694 pci_set_drvdata(dev, priv);
1701 pci_disable_device(dev);
1705 static void __devexit pciserial_remove_one(struct pci_dev *dev)
1707 struct serial_private *priv = pci_get_drvdata(dev);
1709 pci_set_drvdata(dev, NULL);
1711 pciserial_remove_ports(priv);
1713 pci_disable_device(dev);
1716 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
1718 struct serial_private *priv = pci_get_drvdata(dev);
1721 pciserial_suspend_ports(priv);
1723 pci_save_state(dev);
1724 pci_set_power_state(dev, pci_choose_state(dev, state));
1728 static int pciserial_resume_one(struct pci_dev *dev)
1730 struct serial_private *priv = pci_get_drvdata(dev);
1732 pci_set_power_state(dev, PCI_D0);
1733 pci_restore_state(dev);
1737 * The device may have been disabled. Re-enable it.
1739 pci_enable_device(dev);
1741 pciserial_resume_ports(priv);
1746 static struct pci_device_id serial_pci_tbl[] = {
1747 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1748 PCI_SUBVENDOR_ID_CONNECT_TECH,
1749 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
1751 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1752 PCI_SUBVENDOR_ID_CONNECT_TECH,
1753 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
1755 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1756 PCI_SUBVENDOR_ID_CONNECT_TECH,
1757 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
1759 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1760 PCI_SUBVENDOR_ID_CONNECT_TECH,
1761 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
1763 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1764 PCI_SUBVENDOR_ID_CONNECT_TECH,
1765 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
1767 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1768 PCI_SUBVENDOR_ID_CONNECT_TECH,
1769 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
1771 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1772 PCI_SUBVENDOR_ID_CONNECT_TECH,
1773 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
1775 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1776 PCI_SUBVENDOR_ID_CONNECT_TECH,
1777 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
1779 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1780 PCI_SUBVENDOR_ID_CONNECT_TECH,
1781 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
1783 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1784 PCI_SUBVENDOR_ID_CONNECT_TECH,
1785 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
1787 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1788 PCI_SUBVENDOR_ID_CONNECT_TECH,
1789 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
1791 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1792 PCI_SUBVENDOR_ID_CONNECT_TECH,
1793 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
1795 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1796 PCI_SUBVENDOR_ID_CONNECT_TECH,
1797 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
1799 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1800 PCI_SUBVENDOR_ID_CONNECT_TECH,
1801 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
1804 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
1805 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1806 pbn_b2_bt_1_115200 },
1807 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
1808 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1809 pbn_b2_bt_2_115200 },
1810 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
1811 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1812 pbn_b2_bt_4_115200 },
1813 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
1814 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1815 pbn_b2_bt_2_115200 },
1816 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
1817 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1818 pbn_b2_bt_4_115200 },
1819 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
1820 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1822 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
1823 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1826 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
1827 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1828 pbn_b2_bt_2_115200 },
1829 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
1830 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1831 pbn_b2_bt_2_921600 },
1833 * VScom SPCOM800, from sl@s.pl
1835 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
1836 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1838 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
1839 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1841 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1842 PCI_SUBVENDOR_ID_KEYSPAN,
1843 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
1845 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
1846 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1848 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
1849 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1851 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1852 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1853 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
1855 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1856 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1857 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
1859 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1860 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1861 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
1863 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1864 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1865 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
1867 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1868 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
1869 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
1871 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1872 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
1873 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
1875 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1876 PCI_SUBVENDOR_ID_EXSYS,
1877 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
1880 * Megawolf Romulus PCI Serial Card, from Mike Hudson
1883 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
1884 0x10b5, 0x106a, 0, 0,
1886 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
1887 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1889 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
1890 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1892 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
1893 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1895 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
1896 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1898 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
1899 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, 0, 0,
1901 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
1902 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL, 0, 0,
1906 * The below card is a little controversial since it is the
1907 * subject of a PCI vendor/device ID clash. (See
1908 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
1909 * For now just used the hex ID 0x950a.
1911 { PCI_VENDOR_ID_OXSEMI, 0x950a,
1912 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1914 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
1915 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1917 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
1918 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1919 pbn_b0_bt_2_921600 },
1922 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
1923 * from skokodyn@yahoo.com
1925 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
1926 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
1928 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
1929 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
1931 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
1932 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
1934 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
1935 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
1939 * Digitan DS560-558, from jimd@esoft.com
1941 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
1942 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1946 * Titan Electronic cards
1947 * The 400L and 800L have a custom setup quirk.
1949 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
1950 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1952 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
1953 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1955 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
1956 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1958 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
1959 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1961 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
1962 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1964 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
1965 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1966 pbn_b1_bt_2_921600 },
1967 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
1968 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1969 pbn_b0_bt_4_921600 },
1970 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
1971 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1972 pbn_b0_bt_8_921600 },
1974 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
1975 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1977 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
1978 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1980 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
1981 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1983 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
1984 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1985 pbn_b2_bt_2_921600 },
1986 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
1987 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1988 pbn_b2_bt_2_921600 },
1989 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
1990 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1991 pbn_b2_bt_2_921600 },
1992 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
1993 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1994 pbn_b2_bt_4_921600 },
1995 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
1996 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1997 pbn_b2_bt_4_921600 },
1998 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
1999 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2000 pbn_b2_bt_4_921600 },
2001 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
2002 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2004 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
2005 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2007 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
2008 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2010 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
2011 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2012 pbn_b0_bt_2_921600 },
2013 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
2014 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2015 pbn_b0_bt_2_921600 },
2016 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
2017 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2018 pbn_b0_bt_2_921600 },
2019 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
2020 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2021 pbn_b0_bt_4_921600 },
2022 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
2023 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2024 pbn_b0_bt_4_921600 },
2025 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
2026 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2027 pbn_b0_bt_4_921600 },
2030 * Computone devices submitted by Doug McNash dmcnash@computone.com
2032 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2033 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
2034 0, 0, pbn_computone_4 },
2035 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2036 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
2037 0, 0, pbn_computone_8 },
2038 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2039 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
2040 0, 0, pbn_computone_6 },
2042 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
2043 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2045 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
2046 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
2047 pbn_b0_bt_1_921600 },
2050 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
2052 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
2053 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2054 pbn_b0_bt_8_115200 },
2055 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
2056 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2057 pbn_b0_bt_8_115200 },
2059 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
2060 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2061 pbn_b0_bt_2_115200 },
2062 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
2063 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2064 pbn_b0_bt_2_115200 },
2065 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
2066 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2067 pbn_b0_bt_2_115200 },
2068 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
2069 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2070 pbn_b0_bt_4_460800 },
2071 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
2072 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2073 pbn_b0_bt_4_460800 },
2074 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
2075 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2076 pbn_b0_bt_2_460800 },
2077 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
2078 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2079 pbn_b0_bt_2_460800 },
2080 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
2081 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2082 pbn_b0_bt_2_460800 },
2083 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
2084 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2085 pbn_b0_bt_1_115200 },
2086 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
2087 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2088 pbn_b0_bt_1_460800 },
2091 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
2093 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
2094 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2098 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
2100 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
2101 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2105 * RAStel 2 port modem, gerg@moreton.com.au
2107 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
2108 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2109 pbn_b2_bt_2_115200 },
2112 * EKF addition for i960 Boards form EKF with serial port
2114 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
2115 0xE4BF, PCI_ANY_ID, 0, 0,
2119 * Xircom Cardbus/Ethernet combos
2121 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2122 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2125 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
2127 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
2128 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2132 * Untested PCI modems, sent in from various folks...
2136 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
2138 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
2139 0x1048, 0x1500, 0, 0,
2142 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
2149 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2150 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
2152 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2153 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2155 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
2156 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2160 * NEC Vrc-5074 (Nile 4) builtin UART.
2162 { PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_NILE4,
2163 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2166 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
2167 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2169 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
2170 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2174 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2176 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2177 PCI_ANY_ID, PCI_ANY_ID,
2179 0, pbn_exar_XR17C152 },
2180 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2181 PCI_ANY_ID, PCI_ANY_ID,
2183 0, pbn_exar_XR17C154 },
2184 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2185 PCI_ANY_ID, PCI_ANY_ID,
2187 0, pbn_exar_XR17C158 },
2190 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
2192 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
2193 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2197 * These entries match devices with class COMMUNICATION_SERIAL,
2198 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
2200 { PCI_ANY_ID, PCI_ANY_ID,
2201 PCI_ANY_ID, PCI_ANY_ID,
2202 PCI_CLASS_COMMUNICATION_SERIAL << 8,
2203 0xffff00, pbn_default },
2204 { PCI_ANY_ID, PCI_ANY_ID,
2205 PCI_ANY_ID, PCI_ANY_ID,
2206 PCI_CLASS_COMMUNICATION_MODEM << 8,
2207 0xffff00, pbn_default },
2208 { PCI_ANY_ID, PCI_ANY_ID,
2209 PCI_ANY_ID, PCI_ANY_ID,
2210 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
2211 0xffff00, pbn_default },
2215 static struct pci_driver serial_pci_driver = {
2217 .probe = pciserial_init_one,
2218 .remove = __devexit_p(pciserial_remove_one),
2219 .suspend = pciserial_suspend_one,
2220 .resume = pciserial_resume_one,
2221 .id_table = serial_pci_tbl,
2224 static int __init serial8250_pci_init(void)
2226 return pci_register_driver(&serial_pci_driver);
2229 static void __exit serial8250_pci_exit(void)
2231 pci_unregister_driver(&serial_pci_driver);
2234 module_init(serial8250_pci_init);
2235 module_exit(serial8250_pci_exit);
2237 MODULE_LICENSE("GPL");
2238 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
2239 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);