2 * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/errno.h>
27 #include <linux/types.h>
33 extern s32 spi_get_cfg(struct imx_spi_dev_t *dev);
35 static inline struct imx_spi_dev_t *to_imx_spi_slave(struct spi_slave *slave)
37 return container_of(slave, struct imx_spi_dev_t, slave);
40 static s32 spi_reset(struct spi_slave *slave)
42 u32 clk_src = mxc_get_clock(MXC_CSPI_CLK);
43 s32 div = 0, i, reg_ctrl;
44 struct imx_spi_dev_t *dev = to_imx_spi_slave(slave);
45 struct spi_reg_t *reg = &(dev->reg);
47 unsigned int baud_rate_div[] = { 4, 8, 16, 32, 64, 128, 256, 512 };
50 printf("Error: desired clock is 0\n");
54 reg_ctrl = readl(dev->base + SPI_CON_REG);
56 writel(0, dev->base + SPI_CON_REG);
57 writel((reg_ctrl | SPI_CTRL_EN), dev->base + SPI_CON_REG);
59 lim = sizeof(baud_rate_div) / sizeof(unsigned int);
60 if (clk_src > dev->freq) {
61 div = clk_src / dev->freq;
63 for (i = 0; i < lim; i++) {
64 if (div <= baud_rate_div[i])
68 debug("div = %d\n", baud_rate_div[i]);
71 (reg_ctrl & ~SPI_CTRL_SS_MASK) | (dev->ss << SPI_CTRL_SS_OFF);
72 reg_ctrl = (reg_ctrl & ~SPI_CTRL_DATA_MASK) | (i << SPI_CTRL_DATA_OFF);
73 reg_ctrl |= SPI_CTRL_MODE; /* always set to master mode !!!! */
74 reg_ctrl &= ~SPI_CTRL_EN; /* disable spi */
76 /* configuration register setup */
78 (reg_ctrl & ~SPI_CTRL_SSPOL) | (dev->ss_pol << SPI_CTRL_SSPOL_OFF);
80 (reg_ctrl & ~SPI_CTRL_SSCTL) | (dev->ssctl << SPI_CTRL_SSCTL_OFF);
82 (reg_ctrl & ~SPI_CTRL_SCLK_POL) | (dev->
84 SPI_CTRL_SCLK_POL_OFF);
86 (reg_ctrl & ~SPI_CTRL_SCLK_PHA) | (dev->
88 SPI_CTRL_SCLK_PHA_OFF);
90 debug("reg_ctrl = 0x%x\n", reg_ctrl);
91 writel(reg_ctrl, dev->base + SPI_CON_REG);
92 /* save control register */
93 reg->ctrl_reg = reg_ctrl;
95 /* clear interrupt reg */
96 writel(0, dev->base + SPI_INT_REG);
97 writel(SPI_INT_STAT_TC, dev->base + SPI_STAT_REG);
106 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
107 unsigned int max_hz, unsigned int mode)
109 struct imx_spi_dev_t *imx_spi_slave = NULL;
111 if (!spi_cs_is_valid(bus, cs))
115 (struct imx_spi_dev_t *)malloc(sizeof(struct imx_spi_dev_t));
119 imx_spi_slave->slave.bus = bus;
120 imx_spi_slave->slave.cs = cs;
122 spi_get_cfg(imx_spi_slave);
124 spi_io_init(imx_spi_slave);
126 spi_reset(&(imx_spi_slave->slave));
128 return &(imx_spi_slave->slave);
131 void spi_free_slave(struct spi_slave *slave)
133 struct imx_spi_dev_t *imx_spi_slave;
136 imx_spi_slave = to_imx_spi_slave(slave);
141 int spi_claim_bus(struct spi_slave *slave)
146 void spi_release_bus(struct spi_slave *slave)
154 * See include/spi.h and http://www.altera.com/literature/ds/ds_nios_spi.pdf
155 * for more informations.
157 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
158 void *din, unsigned long flags)
160 s32 val = SPI_RETRY_TIMES;
163 s32 len = 0, ret_val = 0;
164 s32 burst_bytes = bitlen >> 3;
165 struct imx_spi_dev_t *dev = to_imx_spi_slave(slave);
166 struct spi_reg_t *spi_reg = &(dev->reg);
171 if ((bitlen % 8) != 0)
174 if (burst_bytes > (dev->fifo_sz)) {
175 printf("Error: maximum burst size is 0x%x bytes, asking 0x%x\n",
176 dev->fifo_sz, burst_bytes);
180 if (flags & SPI_XFER_BEGIN) {
181 spi_cs_activate(slave);
183 if (spi_reg->ctrl_reg == 0) {
185 ("Error: spi(base=0x%x) has not been initialized\n",
190 spi_reg->ctrl_reg = (spi_reg->ctrl_reg & ~SPI_CTRL_BURST_MASK) |
191 ((bitlen - 1) << SPI_CTRL_BURST_OFF);
192 writel(spi_reg->ctrl_reg | SPI_CTRL_EN,
193 dev->base + SPI_CON_REG);
194 debug("ctrl_reg=0x%x\n", readl(dev->base + SPI_CON_REG));
196 /* move data to the tx fifo */
198 for (p_buf = (u32 *) dout, len = burst_bytes; len > 0;
200 writel(*p_buf, dev->base + SPI_TX_DATA);
203 reg = readl(dev->base + SPI_CON_REG);
204 reg |= SPI_CTRL_REG_XCH_BIT; /* set xch bit */
205 debug("control reg = 0x%08x\n", reg);
206 writel(reg, dev->base + SPI_CON_REG);
208 /* poll on the TC bit (transfer complete) */
209 while ((val-- > 0) &&
211 readl(dev->base + SPI_STAT_REG)) & SPI_INT_STAT_TC) ==
214 /* clear the TC bit */
215 writel(reg | SPI_INT_STAT_TC, dev->base + SPI_STAT_REG);
218 ("Error: re-tried %d times without response. Give up\n",
225 /* move data in the rx buf */
226 if (flags & SPI_XFER_END) {
228 for (p_buf = (u32 *) din, len = burst_bytes; len > 0;
230 *p_buf = readl(dev->base + SPI_RX_DATA);
234 spi_cs_deactivate(slave);
238 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
243 void spi_cs_activate(struct spi_slave *slave)
245 struct imx_spi_dev_t *dev = to_imx_spi_slave(slave);
250 void spi_cs_deactivate(struct spi_slave *slave)
252 struct imx_spi_dev_t *dev = to_imx_spi_slave(slave);
254 writel(0, dev->base + SPI_CON_REG);