drivers/spi/spi-atmel.c

   1 /*
   2  * Driver for Atmel AT32 and AT91 SPI Controllers
   3  *
   4  * Copyright (C) 2006 Atmel Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/clk.h>
  14 #include <linux/module.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/delay.h>
  17 #include <linux/dma-mapping.h>
  18 #include <linux/dmaengine.h>
  19 #include <linux/err.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/spi/spi.h>
  22 #include <linux/slab.h>
  23 #include <linux/platform_data/atmel.h>
  24 #include <linux/platform_data/dma-atmel.h>
  25 #include <linux/of.h>
  26
  27 #include <linux/io.h>
  28 #include <linux/gpio.h>
  29 #include <linux/pinctrl/consumer.h>
  30
  31 /* SPI register offsets */
  32 #define SPI_CR                                  0x0000
  33 #define SPI_MR                                  0x0004
  34 #define SPI_RDR                                 0x0008
  35 #define SPI_TDR                                 0x000c
  36 #define SPI_SR                                  0x0010
  37 #define SPI_IER                                 0x0014
  38 #define SPI_IDR                                 0x0018
  39 #define SPI_IMR                                 0x001c
  40 #define SPI_CSR0                                0x0030
  41 #define SPI_CSR1                                0x0034
  42 #define SPI_CSR2                                0x0038
  43 #define SPI_CSR3                                0x003c
  44 #define SPI_VERSION                             0x00fc
  45 #define SPI_RPR                                 0x0100
  46 #define SPI_RCR                                 0x0104
  47 #define SPI_TPR                                 0x0108
  48 #define SPI_TCR                                 0x010c
  49 #define SPI_RNPR                                0x0110
  50 #define SPI_RNCR                                0x0114
  51 #define SPI_TNPR                                0x0118
  52 #define SPI_TNCR                                0x011c
  53 #define SPI_PTCR                                0x0120
  54 #define SPI_PTSR                                0x0124
  55
  56 /* Bitfields in CR */
  57 #define SPI_SPIEN_OFFSET                        0
  58 #define SPI_SPIEN_SIZE                          1
  59 #define SPI_SPIDIS_OFFSET                       1
  60 #define SPI_SPIDIS_SIZE                         1
  61 #define SPI_SWRST_OFFSET                        7
  62 #define SPI_SWRST_SIZE                          1
  63 #define SPI_LASTXFER_OFFSET                     24
  64 #define SPI_LASTXFER_SIZE                       1
  65
  66 /* Bitfields in MR */
  67 #define SPI_MSTR_OFFSET                         0
  68 #define SPI_MSTR_SIZE                           1
  69 #define SPI_PS_OFFSET                           1
  70 #define SPI_PS_SIZE                             1
  71 #define SPI_PCSDEC_OFFSET                       2
  72 #define SPI_PCSDEC_SIZE                         1
  73 #define SPI_FDIV_OFFSET                         3
  74 #define SPI_FDIV_SIZE                           1
  75 #define SPI_MODFDIS_OFFSET                      4
  76 #define SPI_MODFDIS_SIZE                        1
  77 #define SPI_WDRBT_OFFSET                        5
  78 #define SPI_WDRBT_SIZE                          1
  79 #define SPI_LLB_OFFSET                          7
  80 #define SPI_LLB_SIZE                            1
  81 #define SPI_PCS_OFFSET                          16
  82 #define SPI_PCS_SIZE                            4
  83 #define SPI_DLYBCS_OFFSET                       24
  84 #define SPI_DLYBCS_SIZE                         8
  85
  86 /* Bitfields in RDR */
  87 #define SPI_RD_OFFSET                           0
  88 #define SPI_RD_SIZE                             16
  89
  90 /* Bitfields in TDR */
  91 #define SPI_TD_OFFSET                           0
  92 #define SPI_TD_SIZE                             16
  93
  94 /* Bitfields in SR */
  95 #define SPI_RDRF_OFFSET                         0
  96 #define SPI_RDRF_SIZE                           1
  97 #define SPI_TDRE_OFFSET                         1
  98 #define SPI_TDRE_SIZE                           1
  99 #define SPI_MODF_OFFSET                         2
 100 #define SPI_MODF_SIZE                           1
 101 #define SPI_OVRES_OFFSET                        3
 102 #define SPI_OVRES_SIZE                          1
 103 #define SPI_ENDRX_OFFSET                        4
 104 #define SPI_ENDRX_SIZE                          1
 105 #define SPI_ENDTX_OFFSET                        5
 106 #define SPI_ENDTX_SIZE                          1
 107 #define SPI_RXBUFF_OFFSET                       6
 108 #define SPI_RXBUFF_SIZE                         1
 109 #define SPI_TXBUFE_OFFSET                       7
 110 #define SPI_TXBUFE_SIZE                         1
 111 #define SPI_NSSR_OFFSET                         8
 112 #define SPI_NSSR_SIZE                           1
 113 #define SPI_TXEMPTY_OFFSET                      9
 114 #define SPI_TXEMPTY_SIZE                        1
 115 #define SPI_SPIENS_OFFSET                       16
 116 #define SPI_SPIENS_SIZE                         1
 117
 118 /* Bitfields in CSR0 */
 119 #define SPI_CPOL_OFFSET                         0
 120 #define SPI_CPOL_SIZE                           1
 121 #define SPI_NCPHA_OFFSET                        1
 122 #define SPI_NCPHA_SIZE                          1
 123 #define SPI_CSAAT_OFFSET                        3
 124 #define SPI_CSAAT_SIZE                          1
 125 #define SPI_BITS_OFFSET                         4
 126 #define SPI_BITS_SIZE                           4
 127 #define SPI_SCBR_OFFSET                         8
 128 #define SPI_SCBR_SIZE                           8
 129 #define SPI_DLYBS_OFFSET                        16
 130 #define SPI_DLYBS_SIZE                          8
 131 #define SPI_DLYBCT_OFFSET                       24
 132 #define SPI_DLYBCT_SIZE                         8
 133
 134 /* Bitfields in RCR */
 135 #define SPI_RXCTR_OFFSET                        0
 136 #define SPI_RXCTR_SIZE                          16
 137
 138 /* Bitfields in TCR */
 139 #define SPI_TXCTR_OFFSET                        0
 140 #define SPI_TXCTR_SIZE                          16
 141
 142 /* Bitfields in RNCR */
 143 #define SPI_RXNCR_OFFSET                        0
 144 #define SPI_RXNCR_SIZE                          16
 145
 146 /* Bitfields in TNCR */
 147 #define SPI_TXNCR_OFFSET                        0
 148 #define SPI_TXNCR_SIZE                          16
 149
 150 /* Bitfields in PTCR */
 151 #define SPI_RXTEN_OFFSET                        0
 152 #define SPI_RXTEN_SIZE                          1
 153 #define SPI_RXTDIS_OFFSET                       1
 154 #define SPI_RXTDIS_SIZE                         1
 155 #define SPI_TXTEN_OFFSET                        8
 156 #define SPI_TXTEN_SIZE                          1
 157 #define SPI_TXTDIS_OFFSET                       9
 158 #define SPI_TXTDIS_SIZE                         1
 159
 160 /* Constants for BITS */
 161 #define SPI_BITS_8_BPT                          0
 162 #define SPI_BITS_9_BPT                          1
 163 #define SPI_BITS_10_BPT                         2
 164 #define SPI_BITS_11_BPT                         3
 165 #define SPI_BITS_12_BPT                         4
 166 #define SPI_BITS_13_BPT                         5
 167 #define SPI_BITS_14_BPT                         6
 168 #define SPI_BITS_15_BPT                         7
 169 #define SPI_BITS_16_BPT                         8
 170
 171 /* Bit manipulation macros */
 172 #define SPI_BIT(name) \
 173         (1 << SPI_##name##_OFFSET)
 174 #define SPI_BF(name, value) \
 175         (((value) & ((1 << SPI_##name##_SIZE) - 1)) << SPI_##name##_OFFSET)
 176 #define SPI_BFEXT(name, value) \
 177         (((value) >> SPI_##name##_OFFSET) & ((1 << SPI_##name##_SIZE) - 1))
 178 #define SPI_BFINS(name, value, old) \
 179         (((old) & ~(((1 << SPI_##name##_SIZE) - 1) << SPI_##name##_OFFSET)) \
 180           | SPI_BF(name, value))
 181
 182 /* Register access macros */
 183 #define spi_readl(port, reg) \
 184         __raw_readl((port)->regs + SPI_##reg)
 185 #define spi_writel(port, reg, value) \
 186         __raw_writel((value), (port)->regs + SPI_##reg)
 187
 188 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
 189  * cache operations; better heuristics consider wordsize and bitrate.
 190  */
 191 #define DMA_MIN_BYTES   16
 192
 193 #define SPI_DMA_TIMEOUT         (msecs_to_jiffies(1000))
 194
 195 struct atmel_spi_dma {
 196         struct dma_chan                 *chan_rx;
 197         struct dma_chan                 *chan_tx;
 198         struct scatterlist              sgrx;
 199         struct scatterlist              sgtx;
 200         struct dma_async_tx_descriptor  *data_desc_rx;
 201         struct dma_async_tx_descriptor  *data_desc_tx;
 202
 203         struct at_dma_slave     dma_slave;
 204 };
 205
 206 struct atmel_spi_caps {
 207         bool    is_spi2;
 208         bool    has_wdrbt;
 209         bool    has_dma_support;
 210 };
 211
 212 /*
 213  * The core SPI transfer engine just talks to a register bank to set up
 214  * DMA transfers; transfer queue progress is driven by IRQs.  The clock
 215  * framework provides the base clock, subdivided for each spi_device.
 216  */
 217 struct atmel_spi {
 218         spinlock_t              lock;
 219         unsigned long           flags;
 220
 221         phys_addr_t             phybase;
 222         void __iomem            *regs;
 223         int                     irq;
 224         struct clk              *clk;
 225         struct platform_device  *pdev;
 226
 227         struct spi_transfer     *current_transfer;
 228         unsigned long           current_remaining_bytes;
 229         int                     done_status;
 230
 231         struct completion       xfer_completion;
 232
 233         /* scratch buffer */
 234         void                    *buffer;
 235         dma_addr_t              buffer_dma;
 236
 237         struct atmel_spi_caps   caps;
 238
 239         bool                    use_dma;
 240         bool                    use_pdc;
 241         /* dmaengine data */
 242         struct atmel_spi_dma    dma;
 243
 244         bool                    keep_cs;
 245         bool                    cs_active;
 246 };
 247
 248 /* Controller-specific per-slave state */
 249 struct atmel_spi_device {
 250         unsigned int            npcs_pin;
 251         u32                     csr;
 252 };
 253
 254 #define BUFFER_SIZE             PAGE_SIZE
 255 #define INVALID_DMA_ADDRESS     0xffffffff
 256
 257 /*
 258  * Version 2 of the SPI controller has
 259  *  - CR.LASTXFER
 260  *  - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero)
 261  *  - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs)
 262  *  - SPI_CSRx.CSAAT
 263  *  - SPI_CSRx.SBCR allows faster clocking
 264  */
 265 static bool atmel_spi_is_v2(struct atmel_spi *as)
 266 {
 267         return as->caps.is_spi2;
 268 }
 269
 270 /*
 271  * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby
 272  * they assume that spi slave device state will not change on deselect, so
 273  * that automagic deselection is OK.  ("NPCSx rises if no data is to be
 274  * transmitted")  Not so!  Workaround uses nCSx pins as GPIOs; or newer
 275  * controllers have CSAAT and friends.
 276  *
 277  * Since the CSAAT functionality is a bit weird on newer controllers as
 278  * well, we use GPIO to control nCSx pins on all controllers, updating
 279  * MR.PCS to avoid confusing the controller.  Using GPIOs also lets us
 280  * support active-high chipselects despite the controller's belief that
 281  * only active-low devices/systems exists.
 282  *
 283  * However, at91rm9200 has a second erratum whereby nCS0 doesn't work
 284  * right when driven with GPIO.  ("Mode Fault does not allow more than one
 285  * Master on Chip Select 0.")  No workaround exists for that ... so for
 286  * nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH,
 287  * and (c) will trigger that first erratum in some cases.
 288  */
 289
 290 static void cs_activate(struct atmel_spi *as, struct spi_device *spi)
 291 {
 292         struct atmel_spi_device *asd = spi->controller_state;
 293         unsigned active = spi->mode & SPI_CS_HIGH;
 294         u32 mr;
 295
 296         if (atmel_spi_is_v2(as)) {
 297                 spi_writel(as, CSR0 + 4 * spi->chip_select, asd->csr);
 298                 /* For the low SPI version, there is a issue that PDC transfer
 299                  * on CS1,2,3 needs SPI_CSR0.BITS config as SPI_CSR1,2,3.BITS
 300                  */
 301                 spi_writel(as, CSR0, asd->csr);
 302                 if (as->caps.has_wdrbt) {
 303                         spi_writel(as, MR,
 304                                         SPI_BF(PCS, ~(0x01 << spi->chip_select))
 305                                         | SPI_BIT(WDRBT)
 306                                         | SPI_BIT(MODFDIS)
 307                                         | SPI_BIT(MSTR));
 308                 } else {
 309                         spi_writel(as, MR,
 310                                         SPI_BF(PCS, ~(0x01 << spi->chip_select))
 311                                         | SPI_BIT(MODFDIS)
 312                                         | SPI_BIT(MSTR));
 313                 }
 314
 315                 mr = spi_readl(as, MR);
 316                 gpio_set_value(asd->npcs_pin, active);
 317         } else {
 318                 u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0;
 319                 int i;
 320                 u32 csr;
 321
 322                 /* Make sure clock polarity is correct */
 323                 for (i = 0; i < spi->master->num_chipselect; i++) {
 324                         csr = spi_readl(as, CSR0 + 4 * i);
 325                         if ((csr ^ cpol) & SPI_BIT(CPOL))
 326                                 spi_writel(as, CSR0 + 4 * i,
 327                                                 csr ^ SPI_BIT(CPOL));
 328                 }
 329
 330                 mr = spi_readl(as, MR);
 331                 mr = SPI_BFINS(PCS, ~(1 << spi->chip_select), mr);
 332                 if (spi->chip_select != 0)
 333                         gpio_set_value(asd->npcs_pin, active);
 334                 spi_writel(as, MR, mr);
 335         }
 336
 337         dev_dbg(&spi->dev, "activate %u%s, mr %08x\n",
 338                         asd->npcs_pin, active ? " (high)" : "",
 339                         mr);
 340 }
 341
 342 static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi)
 343 {
 344         struct atmel_spi_device *asd = spi->controller_state;
 345         unsigned active = spi->mode & SPI_CS_HIGH;
 346         u32 mr;
 347
 348         /* only deactivate *this* device; sometimes transfers to
 349          * another device may be active when this routine is called.
 350          */
 351         mr = spi_readl(as, MR);
 352         if (~SPI_BFEXT(PCS, mr) & (1 << spi->chip_select)) {
 353                 mr = SPI_BFINS(PCS, 0xf, mr);
 354                 spi_writel(as, MR, mr);
 355         }
 356
 357         dev_dbg(&spi->dev, "DEactivate %u%s, mr %08x\n",
 358                         asd->npcs_pin, active ? " (low)" : "",
 359                         mr);
 360
 361         if (atmel_spi_is_v2(as) || spi->chip_select != 0)
 362                 gpio_set_value(asd->npcs_pin, !active);
 363 }
 364
 365 static void atmel_spi_lock(struct atmel_spi *as) __acquires(&as->lock)
 366 {
 367         spin_lock_irqsave(&as->lock, as->flags);
 368 }
 369
 370 static void atmel_spi_unlock(struct atmel_spi *as) __releases(&as->lock)
 371 {
 372         spin_unlock_irqrestore(&as->lock, as->flags);
 373 }
 374
 375 static inline bool atmel_spi_use_dma(struct atmel_spi *as,
 376                                 struct spi_transfer *xfer)
 377 {
 378         return as->use_dma && xfer->len >= DMA_MIN_BYTES;
 379 }
 380
 381 static int atmel_spi_dma_slave_config(struct atmel_spi *as,
 382                                 struct dma_slave_config *slave_config,
 383                                 u8 bits_per_word)
 384 {
 385         int err = 0;
 386
 387         if (bits_per_word > 8) {
 388                 slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 389                 slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 390         } else {
 391                 slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 392                 slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 393         }
 394
 395         slave_config->dst_addr = (dma_addr_t)as->phybase + SPI_TDR;
 396         slave_config->src_addr = (dma_addr_t)as->phybase + SPI_RDR;
 397         slave_config->src_maxburst = 1;
 398         slave_config->dst_maxburst = 1;
 399         slave_config->device_fc = false;
 400
 401         slave_config->direction = DMA_MEM_TO_DEV;
 402         if (dmaengine_slave_config(as->dma.chan_tx, slave_config)) {
 403                 dev_err(&as->pdev->dev,
 404                         "failed to configure tx dma channel\n");
 405                 err = -EINVAL;
 406         }
 407
 408         slave_config->direction = DMA_DEV_TO_MEM;
 409         if (dmaengine_slave_config(as->dma.chan_rx, slave_config)) {
 410                 dev_err(&as->pdev->dev,
 411                         "failed to configure rx dma channel\n");
 412                 err = -EINVAL;
 413         }
 414
 415         return err;
 416 }
 417
 418 static bool filter(struct dma_chan *chan, void *pdata)
 419 {
 420         struct atmel_spi_dma *sl_pdata = pdata;
 421         struct at_dma_slave *sl;
 422
 423         if (!sl_pdata)
 424                 return false;
 425
 426         sl = &sl_pdata->dma_slave;
 427         if (sl->dma_dev == chan->device->dev) {
 428                 chan->private = sl;
 429                 return true;
 430         } else {
 431                 return false;
 432         }
 433 }
 434
 435 static int atmel_spi_configure_dma(struct atmel_spi *as)
 436 {
 437         struct dma_slave_config slave_config;
 438         struct device *dev = &as->pdev->dev;
 439         int err;
 440
 441         dma_cap_mask_t mask;
 442         dma_cap_zero(mask);
 443         dma_cap_set(DMA_SLAVE, mask);
 444
 445         as->dma.chan_tx = dma_request_slave_channel_compat(mask, filter,
 446                                                            &as->dma,
 447                                                            dev, "tx");
 448         if (!as->dma.chan_tx) {
 449                 dev_err(dev,
 450                         "DMA TX channel not available, SPI unable to use DMA\n");
 451                 err = -EBUSY;
 452                 goto error;
 453         }
 454
 455         as->dma.chan_rx = dma_request_slave_channel_compat(mask, filter,
 456                                                            &as->dma,
 457                                                            dev, "rx");
 458
 459         if (!as->dma.chan_rx) {
 460                 dev_err(dev,
 461                         "DMA RX channel not available, SPI unable to use DMA\n");
 462                 err = -EBUSY;
 463                 goto error;
 464         }
 465
 466         err = atmel_spi_dma_slave_config(as, &slave_config, 8);
 467         if (err)
 468                 goto error;
 469
 470         dev_info(&as->pdev->dev,
 471                         "Using %s (tx) and %s (rx) for DMA transfers\n",
 472                         dma_chan_name(as->dma.chan_tx),
 473                         dma_chan_name(as->dma.chan_rx));
 474         return 0;
 475 error:
 476         if (as->dma.chan_rx)
 477                 dma_release_channel(as->dma.chan_rx);
 478         if (as->dma.chan_tx)
 479                 dma_release_channel(as->dma.chan_tx);
 480         return err;
 481 }
 482
 483 static void atmel_spi_stop_dma(struct atmel_spi *as)
 484 {
 485         if (as->dma.chan_rx)
 486                 as->dma.chan_rx->device->device_control(as->dma.chan_rx,
 487                                                         DMA_TERMINATE_ALL, 0);
 488         if (as->dma.chan_tx)
 489                 as->dma.chan_tx->device->device_control(as->dma.chan_tx,
 490                                                         DMA_TERMINATE_ALL, 0);
 491 }
 492
 493 static void atmel_spi_release_dma(struct atmel_spi *as)
 494 {
 495         if (as->dma.chan_rx)
 496                 dma_release_channel(as->dma.chan_rx);
 497         if (as->dma.chan_tx)
 498                 dma_release_channel(as->dma.chan_tx);
 499 }
 500
 501 /* This function is called by the DMA driver from tasklet context */
 502 static void dma_callback(void *data)
 503 {
 504         struct spi_master       *master = data;
 505         struct atmel_spi        *as = spi_master_get_devdata(master);
 506
 507         complete(&as->xfer_completion);
 508 }
 509
 510 /*
 511  * Next transfer using PIO.
 512  */
 513 static void atmel_spi_next_xfer_pio(struct spi_master *master,
 514                                 struct spi_transfer *xfer)
 515 {
 516         struct atmel_spi        *as = spi_master_get_devdata(master);
 517         unsigned long xfer_pos = xfer->len - as->current_remaining_bytes;
 518
 519         dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_pio\n");
 520
 521         /* Make sure data is not remaining in RDR */
 522         spi_readl(as, RDR);
 523         while (spi_readl(as, SR) & SPI_BIT(RDRF)) {
 524                 spi_readl(as, RDR);
 525                 cpu_relax();
 526         }
 527
 528         if (xfer->tx_buf) {
 529                 if (xfer->bits_per_word > 8)
 530                         spi_writel(as, TDR, *(u16 *)(xfer->tx_buf + xfer_pos));
 531                 else
 532                         spi_writel(as, TDR, *(u8 *)(xfer->tx_buf + xfer_pos));
 533         } else {
 534                 spi_writel(as, TDR, 0);
 535         }
 536
 537         dev_dbg(master->dev.parent,
 538                 "  start pio xfer %p: len %u tx %p rx %p bitpw %d\n",
 539                 xfer, xfer->len, xfer->tx_buf, xfer->rx_buf,
 540                 xfer->bits_per_word);
 541
 542         /* Enable relevant interrupts */
 543         spi_writel(as, IER, SPI_BIT(RDRF) | SPI_BIT(OVRES));
 544 }
 545
 546 /*
 547  * Submit next transfer for DMA.
 548  */
 549 static int atmel_spi_next_xfer_dma_submit(struct spi_master *master,
 550                                 struct spi_transfer *xfer,
 551                                 u32 *plen)
 552 {
 553         struct atmel_spi        *as = spi_master_get_devdata(master);
 554         struct dma_chan         *rxchan = as->dma.chan_rx;
 555         struct dma_chan         *txchan = as->dma.chan_tx;
 556         struct dma_async_tx_descriptor *rxdesc;
 557         struct dma_async_tx_descriptor *txdesc;
 558         struct dma_slave_config slave_config;
 559         dma_cookie_t            cookie;
 560         u32     len = *plen;
 561
 562         dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_dma_submit\n");
 563
 564         /* Check that the channels are available */
 565         if (!rxchan || !txchan)
 566                 return -ENODEV;
 567
 568         /* release lock for DMA operations */
 569         atmel_spi_unlock(as);
 570
 571         /* prepare the RX dma transfer */
 572         sg_init_table(&as->dma.sgrx, 1);
 573         if (xfer->rx_buf) {
 574                 as->dma.sgrx.dma_address = xfer->rx_dma + xfer->len - *plen;
 575         } else {
 576                 as->dma.sgrx.dma_address = as->buffer_dma;
 577                 if (len > BUFFER_SIZE)
 578                         len = BUFFER_SIZE;
 579         }
 580
 581         /* prepare the TX dma transfer */
 582         sg_init_table(&as->dma.sgtx, 1);
 583         if (xfer->tx_buf) {
 584                 as->dma.sgtx.dma_address = xfer->tx_dma + xfer->len - *plen;
 585         } else {
 586                 as->dma.sgtx.dma_address = as->buffer_dma;
 587                 if (len > BUFFER_SIZE)
 588                         len = BUFFER_SIZE;
 589                 memset(as->buffer, 0, len);
 590         }
 591
 592         sg_dma_len(&as->dma.sgtx) = len;
 593         sg_dma_len(&as->dma.sgrx) = len;
 594
 595         *plen = len;
 596
 597         if (atmel_spi_dma_slave_config(as, &slave_config, 8))
 598                 goto err_exit;
 599
 600         /* Send both scatterlists */
 601         rxdesc = rxchan->device->device_prep_slave_sg(rxchan,
 602                                         &as->dma.sgrx,
 603                                         1,
 604                                         DMA_FROM_DEVICE,
 605                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK,
 606                                         NULL);
 607         if (!rxdesc)
 608                 goto err_dma;
 609
 610         txdesc = txchan->device->device_prep_slave_sg(txchan,
 611                                         &as->dma.sgtx,
 612                                         1,
 613                                         DMA_TO_DEVICE,
 614                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK,
 615                                         NULL);
 616         if (!txdesc)
 617                 goto err_dma;
 618
 619         dev_dbg(master->dev.parent,
 620                 "  start dma xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
 621                 xfer, xfer->len, xfer->tx_buf, (unsigned long long)xfer->tx_dma,
 622                 xfer->rx_buf, (unsigned long long)xfer->rx_dma);
 623
 624         /* Enable relevant interrupts */
 625         spi_writel(as, IER, SPI_BIT(OVRES));
 626
 627         /* Put the callback on the RX transfer only, that should finish last */
 628         rxdesc->callback = dma_callback;
 629         rxdesc->callback_param = master;
 630
 631         /* Submit and fire RX and TX with TX last so we're ready to read! */
 632         cookie = rxdesc->tx_submit(rxdesc);
 633         if (dma_submit_error(cookie))
 634                 goto err_dma;
 635         cookie = txdesc->tx_submit(txdesc);
 636         if (dma_submit_error(cookie))
 637                 goto err_dma;
 638         rxchan->device->device_issue_pending(rxchan);
 639         txchan->device->device_issue_pending(txchan);
 640
 641         /* take back lock */
 642         atmel_spi_lock(as);
 643         return 0;
 644
 645 err_dma:
 646         spi_writel(as, IDR, SPI_BIT(OVRES));
 647         atmel_spi_stop_dma(as);
 648 err_exit:
 649         atmel_spi_lock(as);
 650         return -ENOMEM;
 651 }
 652
 653 static void atmel_spi_next_xfer_data(struct spi_master *master,
 654                                 struct spi_transfer *xfer,
 655                                 dma_addr_t *tx_dma,
 656                                 dma_addr_t *rx_dma,
 657                                 u32 *plen)
 658 {
 659         struct atmel_spi        *as = spi_master_get_devdata(master);
 660         u32                     len = *plen;
 661
 662         /* use scratch buffer only when rx or tx data is unspecified */
 663         if (xfer->rx_buf)
 664                 *rx_dma = xfer->rx_dma + xfer->len - *plen;
 665         else {
 666                 *rx_dma = as->buffer_dma;
 667                 if (len > BUFFER_SIZE)
 668                         len = BUFFER_SIZE;
 669         }
 670
 671         if (xfer->tx_buf)
 672                 *tx_dma = xfer->tx_dma + xfer->len - *plen;
 673         else {
 674                 *tx_dma = as->buffer_dma;
 675                 if (len > BUFFER_SIZE)
 676                         len = BUFFER_SIZE;
 677                 memset(as->buffer, 0, len);
 678                 dma_sync_single_for_device(&as->pdev->dev,
 679                                 as->buffer_dma, len, DMA_TO_DEVICE);
 680         }
 681
 682         *plen = len;
 683 }
 684
 685 static int atmel_spi_set_xfer_speed(struct atmel_spi *as,
 686                                     struct spi_device *spi,
 687                                     struct spi_transfer *xfer)
 688 {
 689         u32                     scbr, csr;
 690         unsigned long           bus_hz;
 691
 692         /* v1 chips start out at half the peripheral bus speed. */
 693         bus_hz = clk_get_rate(as->clk);
 694         if (!atmel_spi_is_v2(as))
 695                 bus_hz /= 2;
 696
 697         /*
 698          * Calculate the lowest divider that satisfies the
 699          * constraint, assuming div32/fdiv/mbz == 0.
 700          */
 701         if (xfer->speed_hz)
 702                 scbr = DIV_ROUND_UP(bus_hz, xfer->speed_hz);
 703         else
 704                 /*
 705                  * This can happend if max_speed is null.
 706                  * In this case, we set the lowest possible speed
 707                  */
 708                 scbr = 0xff;
 709
 710         /*
 711          * If the resulting divider doesn't fit into the
 712          * register bitfield, we can't satisfy the constraint.
 713          */
 714         if (scbr >= (1 << SPI_SCBR_SIZE)) {
 715                 dev_err(&spi->dev,
 716                         "setup: %d Hz too slow, scbr %u; min %ld Hz\n",
 717                         xfer->speed_hz, scbr, bus_hz/255);
 718                 return -EINVAL;
 719         }
 720         if (scbr == 0) {
 721                 dev_err(&spi->dev,
 722                         "setup: %d Hz too high, scbr %u; max %ld Hz\n",
 723                         xfer->speed_hz, scbr, bus_hz);
 724                 return -EINVAL;
 725         }
 726         csr = spi_readl(as, CSR0 + 4 * spi->chip_select);
 727         csr = SPI_BFINS(SCBR, scbr, csr);
 728         spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
 729
 730         return 0;
 731 }
 732
 733 /*
 734  * Submit next transfer for PDC.
 735  * lock is held, spi irq is blocked
 736  */
 737 static void atmel_spi_pdc_next_xfer(struct spi_master *master,
 738                                         struct spi_message *msg,
 739                                         struct spi_transfer *xfer)
 740 {
 741         struct atmel_spi        *as = spi_master_get_devdata(master);
 742         u32                     len;
 743         dma_addr_t              tx_dma, rx_dma;
 744
 745         spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
 746
 747         len = as->current_remaining_bytes;
 748         atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
 749         as->current_remaining_bytes -= len;
 750
 751         spi_writel(as, RPR, rx_dma);
 752         spi_writel(as, TPR, tx_dma);
 753
 754         if (msg->spi->bits_per_word > 8)
 755                 len >>= 1;
 756         spi_writel(as, RCR, len);
 757         spi_writel(as, TCR, len);
 758
 759         dev_dbg(&msg->spi->dev,
 760                 "  start xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
 761                 xfer, xfer->len, xfer->tx_buf,
 762                 (unsigned long long)xfer->tx_dma, xfer->rx_buf,
 763                 (unsigned long long)xfer->rx_dma);
 764
 765         if (as->current_remaining_bytes) {
 766                 len = as->current_remaining_bytes;
 767                 atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
 768                 as->current_remaining_bytes -= len;
 769
 770                 spi_writel(as, RNPR, rx_dma);
 771                 spi_writel(as, TNPR, tx_dma);
 772
 773                 if (msg->spi->bits_per_word > 8)
 774                         len >>= 1;
 775                 spi_writel(as, RNCR, len);
 776                 spi_writel(as, TNCR, len);
 777
 778                 dev_dbg(&msg->spi->dev,
 779                         "  next xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
 780                         xfer, xfer->len, xfer->tx_buf,
 781                         (unsigned long long)xfer->tx_dma, xfer->rx_buf,
 782                         (unsigned long long)xfer->rx_dma);
 783         }
 784
 785         /* REVISIT: We're waiting for ENDRX before we start the next
 786          * transfer because we need to handle some difficult timing
 787          * issues otherwise. If we wait for ENDTX in one transfer and
 788          * then starts waiting for ENDRX in the next, it's difficult
 789          * to tell the difference between the ENDRX interrupt we're
 790          * actually waiting for and the ENDRX interrupt of the
 791          * previous transfer.
 792          *
 793          * It should be doable, though. Just not now...
 794          */
 795         spi_writel(as, IER, SPI_BIT(ENDRX) | SPI_BIT(OVRES));
 796         spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN));
 797 }
 798
 799 /*
 800  * For DMA, tx_buf/tx_dma have the same relationship as rx_buf/rx_dma:
 801  *  - The buffer is either valid for CPU access, else NULL
 802  *  - If the buffer is valid, so is its DMA address
 803  *
 804  * This driver manages the dma address unless message->is_dma_mapped.
 805  */
 806 static int
 807 atmel_spi_dma_map_xfer(struct atmel_spi *as, struct spi_transfer *xfer)
 808 {
 809         struct device   *dev = &as->pdev->dev;
 810
 811         xfer->tx_dma = xfer->rx_dma = INVALID_DMA_ADDRESS;
 812         if (xfer->tx_buf) {
 813                 /* tx_buf is a const void* where we need a void * for the dma
 814                  * mapping */
 815                 void *nonconst_tx = (void *)xfer->tx_buf;
 816
 817                 xfer->tx_dma = dma_map_single(dev,
 818                                 nonconst_tx, xfer->len,
 819                                 DMA_TO_DEVICE);
 820                 if (dma_mapping_error(dev, xfer->tx_dma))
 821                         return -ENOMEM;
 822         }
 823         if (xfer->rx_buf) {
 824                 xfer->rx_dma = dma_map_single(dev,
 825                                 xfer->rx_buf, xfer->len,
 826                                 DMA_FROM_DEVICE);
 827                 if (dma_mapping_error(dev, xfer->rx_dma)) {
 828                         if (xfer->tx_buf)
 829                                 dma_unmap_single(dev,
 830                                                 xfer->tx_dma, xfer->len,
 831                                                 DMA_TO_DEVICE);
 832                         return -ENOMEM;
 833                 }
 834         }
 835         return 0;
 836 }
 837
 838 static void atmel_spi_dma_unmap_xfer(struct spi_master *master,
 839                                      struct spi_transfer *xfer)
 840 {
 841         if (xfer->tx_dma != INVALID_DMA_ADDRESS)
 842                 dma_unmap_single(master->dev.parent, xfer->tx_dma,
 843                                  xfer->len, DMA_TO_DEVICE);
 844         if (xfer->rx_dma != INVALID_DMA_ADDRESS)
 845                 dma_unmap_single(master->dev.parent, xfer->rx_dma,
 846                                  xfer->len, DMA_FROM_DEVICE);
 847 }
 848
 849 static void atmel_spi_disable_pdc_transfer(struct atmel_spi *as)
 850 {
 851         spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
 852 }
 853
 854 /* Called from IRQ
 855  *
 856  * Must update "current_remaining_bytes" to keep track of data
 857  * to transfer.
 858  */
 859 static void
 860 atmel_spi_pump_pio_data(struct atmel_spi *as, struct spi_transfer *xfer)
 861 {
 862         u8              *rxp;
 863         u16             *rxp16;
 864         unsigned long   xfer_pos = xfer->len - as->current_remaining_bytes;
 865
 866         if (xfer->rx_buf) {
 867                 if (xfer->bits_per_word > 8) {
 868                         rxp16 = (u16 *)(((u8 *)xfer->rx_buf) + xfer_pos);
 869                         *rxp16 = spi_readl(as, RDR);
 870                 } else {
 871                         rxp = ((u8 *)xfer->rx_buf) + xfer_pos;
 872                         *rxp = spi_readl(as, RDR);
 873                 }
 874         } else {
 875                 spi_readl(as, RDR);
 876         }
 877         if (xfer->bits_per_word > 8) {
 878                 as->current_remaining_bytes -= 2;
 879                 if (as->current_remaining_bytes < 0)
 880                         as->current_remaining_bytes = 0;
 881         } else {
 882                 as->current_remaining_bytes--;
 883         }
 884 }
 885
 886 /* Interrupt
 887  *
 888  * No need for locking in this Interrupt handler: done_status is the
 889  * only information modified.
 890  */
 891 static irqreturn_t
 892 atmel_spi_pio_interrupt(int irq, void *dev_id)
 893 {
 894         struct spi_master       *master = dev_id;
 895         struct atmel_spi        *as = spi_master_get_devdata(master);
 896         u32                     status, pending, imr;
 897         struct spi_transfer     *xfer;
 898         int                     ret = IRQ_NONE;
 899
 900         imr = spi_readl(as, IMR);
 901         status = spi_readl(as, SR);
 902         pending = status & imr;
 903
 904         if (pending & SPI_BIT(OVRES)) {
 905                 ret = IRQ_HANDLED;
 906                 spi_writel(as, IDR, SPI_BIT(OVRES));
 907                 dev_warn(master->dev.parent, "overrun\n");
 908
 909                 /*
 910                  * When we get an overrun, we disregard the current
 911                  * transfer. Data will not be copied back from any
 912                  * bounce buffer and msg->actual_len will not be
 913                  * updated with the last xfer.
 914                  *
 915                  * We will also not process any remaning transfers in
 916                  * the message.
 917                  */
 918                 as->done_status = -EIO;
 919                 smp_wmb();
 920
 921                 /* Clear any overrun happening while cleaning up */
 922                 spi_readl(as, SR);
 923
 924                 complete(&as->xfer_completion);
 925
 926         } else if (pending & SPI_BIT(RDRF)) {
 927                 atmel_spi_lock(as);
 928
 929                 if (as->current_remaining_bytes) {
 930                         ret = IRQ_HANDLED;
 931                         xfer = as->current_transfer;
 932                         atmel_spi_pump_pio_data(as, xfer);
 933                         if (!as->current_remaining_bytes)
 934                                 spi_writel(as, IDR, pending);
 935
 936                         complete(&as->xfer_completion);
 937                 }
 938
 939                 atmel_spi_unlock(as);
 940         } else {
 941                 WARN_ONCE(pending, "IRQ not handled, pending = %x\n", pending);
 942                 ret = IRQ_HANDLED;
 943                 spi_writel(as, IDR, pending);
 944         }
 945
 946         return ret;
 947 }
 948
 949 static irqreturn_t
 950 atmel_spi_pdc_interrupt(int irq, void *dev_id)
 951 {
 952         struct spi_master       *master = dev_id;
 953         struct atmel_spi        *as = spi_master_get_devdata(master);
 954         u32                     status, pending, imr;
 955         int                     ret = IRQ_NONE;
 956
 957         imr = spi_readl(as, IMR);
 958         status = spi_readl(as, SR);
 959         pending = status & imr;
 960
 961         if (pending & SPI_BIT(OVRES)) {
 962
 963                 ret = IRQ_HANDLED;
 964
 965                 spi_writel(as, IDR, (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX)
 966                                      | SPI_BIT(OVRES)));
 967
 968                 /* Clear any overrun happening while cleaning up */
 969                 spi_readl(as, SR);
 970
 971                 as->done_status = -EIO;
 972
 973                 complete(&as->xfer_completion);
 974
 975         } else if (pending & (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX))) {
 976                 ret = IRQ_HANDLED;
 977
 978                 spi_writel(as, IDR, pending);
 979
 980                 complete(&as->xfer_completion);
 981         }
 982
 983         return ret;
 984 }
 985
 986 static int atmel_spi_setup(struct spi_device *spi)
 987 {
 988         struct atmel_spi        *as;
 989         struct atmel_spi_device *asd;
 990         u32                     csr;
 991         unsigned int            bits = spi->bits_per_word;
 992         unsigned int            npcs_pin;
 993         int                     ret;
 994
 995         as = spi_master_get_devdata(spi->master);
 996
 997         if (spi->chip_select > spi->master->num_chipselect) {
 998                 dev_dbg(&spi->dev,
 999                                 "setup: invalid chipselect %u (%u defined)\n",
1000                                 spi->chip_select, spi->master->num_chipselect);
1001                 return -EINVAL;
1002         }
1003
1004         /* see notes above re chipselect */
1005         if (!atmel_spi_is_v2(as)
1006                         && spi->chip_select == 0
1007                         && (spi->mode & SPI_CS_HIGH)) {
1008                 dev_dbg(&spi->dev, "setup: can't be active-high\n");
1009                 return -EINVAL;
1010         }
1011
1012         csr = SPI_BF(BITS, bits - 8);
1013         if (spi->mode & SPI_CPOL)
1014                 csr |= SPI_BIT(CPOL);
1015         if (!(spi->mode & SPI_CPHA))
1016                 csr |= SPI_BIT(NCPHA);
1017
1018         /* DLYBS is mostly irrelevant since we manage chipselect using GPIOs.
1019          *
1020          * DLYBCT would add delays between words, slowing down transfers.
1021          * It could potentially be useful to cope with DMA bottlenecks, but
1022          * in those cases it's probably best to just use a lower bitrate.
1023          */
1024         csr |= SPI_BF(DLYBS, 0);
1025         csr |= SPI_BF(DLYBCT, 0);
1026
1027         /* chipselect must have been muxed as GPIO (e.g. in board setup) */
1028         npcs_pin = (unsigned int)spi->controller_data;
1029
1030         if (gpio_is_valid(spi->cs_gpio))
1031                 npcs_pin = spi->cs_gpio;
1032
1033         asd = spi->controller_state;
1034         if (!asd) {
1035                 asd = kzalloc(sizeof(struct atmel_spi_device), GFP_KERNEL);
1036                 if (!asd)
1037                         return -ENOMEM;
1038
1039                 ret = gpio_request(npcs_pin, dev_name(&spi->dev));
1040                 if (ret) {
1041                         kfree(asd);
1042                         return ret;
1043                 }
1044
1045                 asd->npcs_pin = npcs_pin;
1046                 spi->controller_state = asd;
1047                 gpio_direction_output(npcs_pin, !(spi->mode & SPI_CS_HIGH));
1048         }
1049
1050         asd->csr = csr;
1051
1052         dev_dbg(&spi->dev,
1053                 "setup: bpw %u mode 0x%x -> csr%d %08x\n",
1054                 bits, spi->mode, spi->chip_select, csr);
1055
1056         if (!atmel_spi_is_v2(as))
1057                 spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
1058
1059         return 0;
1060 }
1061
1062 static int atmel_spi_one_transfer(struct spi_master *master,
1063                                         struct spi_message *msg,
1064                                         struct spi_transfer *xfer)
1065 {
1066         struct atmel_spi        *as;
1067         struct spi_device       *spi = msg->spi;
1068         u8                      bits;
1069         u32                     len;
1070         struct atmel_spi_device *asd;
1071         int                     timeout;
1072         int                     ret;
1073
1074         as = spi_master_get_devdata(master);
1075
1076         if (!(xfer->tx_buf || xfer->rx_buf) && xfer->len) {
1077                 dev_dbg(&spi->dev, "missing rx or tx buf\n");
1078                 return -EINVAL;
1079         }
1080
1081         if (xfer->bits_per_word) {
1082                 asd = spi->controller_state;
1083                 bits = (asd->csr >> 4) & 0xf;
1084                 if (bits != xfer->bits_per_word - 8) {
1085                         dev_dbg(&spi->dev,
1086                         "you can't yet change bits_per_word in transfers\n");
1087                         return -ENOPROTOOPT;
1088                 }
1089         }
1090
1091         /*
1092          * DMA map early, for performance (empties dcache ASAP) and
1093          * better fault reporting.
1094          */
1095         if ((!msg->is_dma_mapped)
1096                 && (atmel_spi_use_dma(as, xfer) || as->use_pdc)) {
1097                 if (atmel_spi_dma_map_xfer(as, xfer) < 0)
1098                         return -ENOMEM;
1099         }
1100
1101         atmel_spi_set_xfer_speed(as, msg->spi, xfer);
1102
1103         as->done_status = 0;
1104         as->current_transfer = xfer;
1105         as->current_remaining_bytes = xfer->len;
1106         while (as->current_remaining_bytes) {
1107                 reinit_completion(&as->xfer_completion);
1108
1109                 if (as->use_pdc) {
1110                         atmel_spi_pdc_next_xfer(master, msg, xfer);
1111                 } else if (atmel_spi_use_dma(as, xfer)) {
1112                         len = as->current_remaining_bytes;
1113                         ret = atmel_spi_next_xfer_dma_submit(master,
1114                                                                 xfer, &len);
1115                         if (ret) {
1116                                 dev_err(&spi->dev,
1117                                         "unable to use DMA, fallback to PIO\n");
1118                                 atmel_spi_next_xfer_pio(master, xfer);
1119                         } else {
1120                                 as->current_remaining_bytes -= len;
1121                         }
1122                 } else {
1123                         atmel_spi_next_xfer_pio(master, xfer);
1124                 }
1125
1126                 ret = wait_for_completion_timeout(&as->xfer_completion,
1127                                                         SPI_DMA_TIMEOUT);
1128                 if (WARN_ON(ret == 0)) {
1129                         dev_err(&spi->dev,
1130                                 "spi trasfer timeout, err %d\n", ret);
1131                         as->done_status = -EIO;
1132                 } else {
1133                         ret = 0;
1134                 }
1135
1136                 if (as->done_status)
1137                         break;
1138         }
1139
1140         if (as->done_status) {
1141                 if (as->use_pdc) {
1142                         dev_warn(master->dev.parent,
1143                                 "overrun (%u/%u remaining)\n",
1144                                 spi_readl(as, TCR), spi_readl(as, RCR));
1145
1146                         /*
1147                          * Clean up DMA registers and make sure the data
1148                          * registers are empty.
1149                          */
1150                         spi_writel(as, RNCR, 0);
1151                         spi_writel(as, TNCR, 0);
1152                         spi_writel(as, RCR, 0);
1153                         spi_writel(as, TCR, 0);
1154                         for (timeout = 1000; timeout; timeout--)
1155                                 if (spi_readl(as, SR) & SPI_BIT(TXEMPTY))
1156                                         break;
1157                         if (!timeout)
1158                                 dev_warn(master->dev.parent,
1159                                          "timeout waiting for TXEMPTY");
1160                         while (spi_readl(as, SR) & SPI_BIT(RDRF))
1161                                 spi_readl(as, RDR);
1162
1163                         /* Clear any overrun happening while cleaning up */
1164                         spi_readl(as, SR);
1165
1166                 } else if (atmel_spi_use_dma(as, xfer)) {
1167                         atmel_spi_stop_dma(as);
1168                 }
1169
1170                 if (!msg->is_dma_mapped
1171                         && (atmel_spi_use_dma(as, xfer) || as->use_pdc))
1172                         atmel_spi_dma_unmap_xfer(master, xfer);
1173
1174                 return 0;
1175
1176         } else {
1177                 /* only update length if no error */
1178                 msg->actual_length += xfer->len;
1179         }
1180
1181         if (!msg->is_dma_mapped
1182                 && (atmel_spi_use_dma(as, xfer) || as->use_pdc))
1183                 atmel_spi_dma_unmap_xfer(master, xfer);
1184
1185         if (xfer->delay_usecs)
1186                 udelay(xfer->delay_usecs);
1187
1188         if (xfer->cs_change) {
1189                 if (list_is_last(&xfer->transfer_list,
1190                                  &msg->transfers)) {
1191                         as->keep_cs = true;
1192                 } else {
1193                         as->cs_active = !as->cs_active;
1194                         if (as->cs_active)
1195                                 cs_activate(as, msg->spi);
1196                         else
1197                                 cs_deactivate(as, msg->spi);
1198                 }
1199         }
1200
1201         return 0;
1202 }
1203
1204 static int atmel_spi_transfer_one_message(struct spi_master *master,
1205                                                 struct spi_message *msg)
1206 {
1207         struct atmel_spi *as;
1208         struct spi_transfer *xfer;
1209         struct spi_device *spi = msg->spi;
1210         int ret = 0;
1211
1212         as = spi_master_get_devdata(master);
1213
1214         dev_dbg(&spi->dev, "new message %p submitted for %s\n",
1215                                         msg, dev_name(&spi->dev));
1216
1217         atmel_spi_lock(as);
1218         cs_activate(as, spi);
1219
1220         as->cs_active = true;
1221         as->keep_cs = false;
1222
1223         msg->status = 0;
1224         msg->actual_length = 0;
1225
1226         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
1227                 ret = atmel_spi_one_transfer(master, msg, xfer);
1228                 if (ret)
1229                         goto msg_done;
1230         }
1231
1232         if (as->use_pdc)
1233                 atmel_spi_disable_pdc_transfer(as);
1234
1235         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
1236                 dev_dbg(&spi->dev,
1237                         "  xfer %p: len %u tx %p/%pad rx %p/%pad\n",
1238                         xfer, xfer->len,
1239                         xfer->tx_buf, &xfer->tx_dma,
1240                         xfer->rx_buf, &xfer->rx_dma);
1241         }
1242
1243 msg_done:
1244         if (!as->keep_cs)
1245                 cs_deactivate(as, msg->spi);
1246
1247         atmel_spi_unlock(as);
1248
1249         msg->status = as->done_status;
1250         spi_finalize_current_message(spi->master);
1251
1252         return ret;
1253 }
1254
1255 static void atmel_spi_cleanup(struct spi_device *spi)
1256 {
1257         struct atmel_spi_device *asd = spi->controller_state;
1258         unsigned                gpio = (unsigned) spi->controller_data;
1259
1260         if (!asd)
1261                 return;
1262
1263         spi->controller_state = NULL;
1264         gpio_free(gpio);
1265         kfree(asd);
1266 }
1267
1268 static inline unsigned int atmel_get_version(struct atmel_spi *as)
1269 {
1270         return spi_readl(as, VERSION) & 0x00000fff;
1271 }
1272
1273 static void atmel_get_caps(struct atmel_spi *as)
1274 {
1275         unsigned int version;
1276
1277         version = atmel_get_version(as);
1278         dev_info(&as->pdev->dev, "version: 0x%x\n", version);
1279
1280         as->caps.is_spi2 = version > 0x121;
1281         as->caps.has_wdrbt = version >= 0x210;
1282         as->caps.has_dma_support = version >= 0x212;
1283 }
1284
1285 /*-------------------------------------------------------------------------*/
1286
1287 static int atmel_spi_probe(struct platform_device *pdev)
1288 {
1289         struct resource         *regs;
1290         int                     irq;
1291         struct clk              *clk;
1292         int                     ret;
1293         struct spi_master       *master;
1294         struct atmel_spi        *as;
1295
1296         /* Select default pin state */
1297         pinctrl_pm_select_default_state(&pdev->dev);
1298
1299         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1300         if (!regs)
1301                 return -ENXIO;
1302
1303         irq = platform_get_irq(pdev, 0);
1304         if (irq < 0)
1305                 return irq;
1306
1307         clk = devm_clk_get(&pdev->dev, "spi_clk");
1308         if (IS_ERR(clk))
1309                 return PTR_ERR(clk);
1310
1311         /* setup spi core then atmel-specific driver state */
1312         ret = -ENOMEM;
1313         master = spi_alloc_master(&pdev->dev, sizeof(*as));
1314         if (!master)
1315                 goto out_free;
1316
1317         /* the spi->mode bits understood by this driver: */
1318         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1319         master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 16);
1320         master->dev.of_node = pdev->dev.of_node;
1321         master->bus_num = pdev->id;
1322         master->num_chipselect = master->dev.of_node ? 0 : 4;
1323         master->setup = atmel_spi_setup;
1324         master->transfer_one_message = atmel_spi_transfer_one_message;
1325         master->cleanup = atmel_spi_cleanup;
1326         platform_set_drvdata(pdev, master);
1327
1328         as = spi_master_get_devdata(master);
1329
1330         /*
1331          * Scratch buffer is used for throwaway rx and tx data.
1332          * It's coherent to minimize dcache pollution.
1333          */
1334         as->buffer = dma_alloc_coherent(&pdev->dev, BUFFER_SIZE,
1335                                         &as->buffer_dma, GFP_KERNEL);
1336         if (!as->buffer)
1337                 goto out_free;
1338
1339         spin_lock_init(&as->lock);
1340
1341         as->pdev = pdev;
1342         as->regs = devm_ioremap_resource(&pdev->dev, regs);
1343         if (IS_ERR(as->regs)) {
1344                 ret = PTR_ERR(as->regs);
1345                 goto out_free_buffer;
1346         }
1347         as->phybase = regs->start;
1348         as->irq = irq;
1349         as->clk = clk;
1350
1351         init_completion(&as->xfer_completion);
1352
1353         atmel_get_caps(as);
1354
1355         as->use_dma = false;
1356         as->use_pdc = false;
1357         if (as->caps.has_dma_support) {
1358                 if (atmel_spi_configure_dma(as) == 0)
1359                         as->use_dma = true;
1360         } else {
1361                 as->use_pdc = true;
1362         }
1363
1364         if (as->caps.has_dma_support && !as->use_dma)
1365                 dev_info(&pdev->dev, "Atmel SPI Controller using PIO only\n");
1366
1367         if (as->use_pdc) {
1368                 ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pdc_interrupt,
1369                                         0, dev_name(&pdev->dev), master);
1370         } else {
1371                 ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pio_interrupt,
1372                                         0, dev_name(&pdev->dev), master);
1373         }
1374         if (ret)
1375                 goto out_unmap_regs;
1376
1377         /* Initialize the hardware */
1378         ret = clk_prepare_enable(clk);
1379         if (ret)
1380                 goto out_free_irq;
1381         spi_writel(as, CR, SPI_BIT(SWRST));
1382         spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1383         if (as->caps.has_wdrbt) {
1384                 spi_writel(as, MR, SPI_BIT(WDRBT) | SPI_BIT(MODFDIS)
1385                                 | SPI_BIT(MSTR));
1386         } else {
1387                 spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS));
1388         }
1389
1390         if (as->use_pdc)
1391                 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
1392         spi_writel(as, CR, SPI_BIT(SPIEN));
1393
1394         /* go! */
1395         dev_info(&pdev->dev, "Atmel SPI Controller at 0x%08lx (irq %d)\n",
1396                         (unsigned long)regs->start, irq);
1397
1398         ret = devm_spi_register_master(&pdev->dev, master);
1399         if (ret)
1400                 goto out_free_dma;
1401
1402         return 0;
1403
1404 out_free_dma:
1405         if (as->use_dma)
1406                 atmel_spi_release_dma(as);
1407
1408         spi_writel(as, CR, SPI_BIT(SWRST));
1409         spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1410         clk_disable_unprepare(clk);
1411 out_free_irq:
1412 out_unmap_regs:
1413 out_free_buffer:
1414         dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
1415                         as->buffer_dma);
1416 out_free:
1417         spi_master_put(master);
1418         return ret;
1419 }
1420
1421 static int atmel_spi_remove(struct platform_device *pdev)
1422 {
1423         struct spi_master       *master = platform_get_drvdata(pdev);
1424         struct atmel_spi        *as = spi_master_get_devdata(master);
1425
1426         /* reset the hardware and block queue progress */
1427         spin_lock_irq(&as->lock);
1428         if (as->use_dma) {
1429                 atmel_spi_stop_dma(as);
1430                 atmel_spi_release_dma(as);
1431         }
1432
1433         spi_writel(as, CR, SPI_BIT(SWRST));
1434         spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1435         spi_readl(as, SR);
1436         spin_unlock_irq(&as->lock);
1437
1438         dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
1439                         as->buffer_dma);
1440
1441         clk_disable_unprepare(as->clk);
1442
1443         return 0;
1444 }
1445
1446 #ifdef CONFIG_PM_SLEEP
1447 static int atmel_spi_suspend(struct device *dev)
1448 {
1449         struct spi_master       *master = dev_get_drvdata(dev);
1450         struct atmel_spi        *as = spi_master_get_devdata(master);
1451         int ret;
1452
1453         /* Stop the queue running */
1454         ret = spi_master_suspend(master);
1455         if (ret) {
1456                 dev_warn(dev, "cannot suspend master\n");
1457                 return ret;
1458         }
1459
1460         clk_disable_unprepare(as->clk);
1461
1462         pinctrl_pm_select_sleep_state(dev);
1463
1464         return 0;
1465 }
1466
1467 static int atmel_spi_resume(struct device *dev)
1468 {
1469         struct spi_master       *master = dev_get_drvdata(dev);
1470         struct atmel_spi        *as = spi_master_get_devdata(master);
1471         int ret;
1472
1473         pinctrl_pm_select_default_state(dev);
1474
1475         clk_prepare_enable(as->clk);
1476
1477         /* Start the queue running */
1478         ret = spi_master_resume(master);
1479         if (ret)
1480                 dev_err(dev, "problem starting queue (%d)\n", ret);
1481
1482         return ret;
1483 }
1484
1485 static SIMPLE_DEV_PM_OPS(atmel_spi_pm_ops, atmel_spi_suspend, atmel_spi_resume);
1486
1487 #define ATMEL_SPI_PM_OPS        (&atmel_spi_pm_ops)
1488 #else
1489 #define ATMEL_SPI_PM_OPS        NULL
1490 #endif
1491
1492 #if defined(CONFIG_OF)
1493 static const struct of_device_id atmel_spi_dt_ids[] = {
1494         { .compatible = "atmel,at91rm9200-spi" },
1495         { /* sentinel */ }
1496 };
1497
1498 MODULE_DEVICE_TABLE(of, atmel_spi_dt_ids);
1499 #endif
1500
1501 static struct platform_driver atmel_spi_driver = {
1502         .driver         = {
1503                 .name   = "atmel_spi",
1504                 .owner  = THIS_MODULE,
1505                 .pm     = ATMEL_SPI_PM_OPS,
1506                 .of_match_table = of_match_ptr(atmel_spi_dt_ids),
1507         },
1508         .probe          = atmel_spi_probe,
1509         .remove         = atmel_spi_remove,
1510 };
1511 module_platform_driver(atmel_spi_driver);
1512
1513 MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver");
1514 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1515 MODULE_LICENSE("GPL");
1516 MODULE_ALIAS("platform:atmel_spi");