2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
3 * Copyright (C) 2013, Intel Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
13 #include <linux/atomic.h>
14 #include <linux/dmaengine.h>
15 #include <linux/errno.h>
17 #include <linux/interrupt.h>
18 #include <linux/platform_device.h>
19 #include <linux/pxa2xx_ssp.h>
20 #include <linux/scatterlist.h>
21 #include <linux/sizes.h>
22 #include <linux/spi/spi.h>
23 #include <linux/spi/pxa2xx_spi.h>
26 /* Driver model hookup */
27 struct platform_device *pdev;
30 struct ssp_device *ssp;
32 /* SPI framework hookup */
33 enum pxa_ssp_type ssp_type;
34 struct spi_master *master;
37 struct pxa2xx_spi_master *master_info;
39 /* PXA private DMA setup stuff */
44 /* SSP register addresses */
54 /* Maximun clock rate */
55 unsigned long max_clk_rate;
57 /* Message Transfer pump */
58 struct tasklet_struct pump_transfers;
60 /* DMA engine support */
61 struct dma_chan *rx_chan;
62 struct dma_chan *tx_chan;
63 struct sg_table rx_sgt;
64 struct sg_table tx_sgt;
70 /* Current message transfer state info */
71 struct spi_message *cur_msg;
72 struct spi_transfer *cur_transfer;
73 struct chip_data *cur_chip;
85 int (*write)(struct driver_data *drv_data);
86 int (*read)(struct driver_data *drv_data);
87 irqreturn_t (*transfer_handler)(struct driver_data *drv_data);
88 void (*cs_control)(u32 command);
90 void __iomem *lpss_base;
102 u16 lpss_rx_threshold;
103 u16 lpss_tx_threshold;
111 int gpio_cs_inverted;
112 int (*write)(struct driver_data *drv_data);
113 int (*read)(struct driver_data *drv_data);
114 void (*cs_control)(u32 command);
117 #define DEFINE_SSP_REG(reg, off) \
118 static inline u32 read_##reg(void const __iomem *p) \
119 { return __raw_readl(p + (off)); } \
121 static inline void write_##reg(u32 v, void __iomem *p) \
122 { __raw_writel(v, p + (off)); }
124 DEFINE_SSP_REG(SSCR0, 0x00)
125 DEFINE_SSP_REG(SSCR1, 0x04)
126 DEFINE_SSP_REG(SSSR, 0x08)
127 DEFINE_SSP_REG(SSITR, 0x0c)
128 DEFINE_SSP_REG(SSDR, 0x10)
129 DEFINE_SSP_REG(SSTO, 0x28)
130 DEFINE_SSP_REG(SSPSP, 0x2c)
131 DEFINE_SSP_REG(SSITF, SSITF)
132 DEFINE_SSP_REG(SSIRF, SSIRF)
134 #define START_STATE ((void *)0)
135 #define RUNNING_STATE ((void *)1)
136 #define DONE_STATE ((void *)2)
137 #define ERROR_STATE ((void *)-1)
139 #define IS_DMA_ALIGNED(x) IS_ALIGNED((unsigned long)(x), DMA_ALIGNMENT)
140 #define DMA_ALIGNMENT 8
142 static inline int pxa25x_ssp_comp(struct driver_data *drv_data)
144 if (drv_data->ssp_type == PXA25x_SSP)
146 if (drv_data->ssp_type == CE4100_SSP)
151 static inline void write_SSSR_CS(struct driver_data *drv_data, u32 val)
153 void __iomem *reg = drv_data->ioaddr;
155 if (drv_data->ssp_type == CE4100_SSP)
156 val |= read_SSSR(reg) & SSSR_ALT_FRM_MASK;
158 write_SSSR(val, reg);
161 extern int pxa2xx_spi_flush(struct driver_data *drv_data);
162 extern void *pxa2xx_spi_next_transfer(struct driver_data *drv_data);
165 * Select the right DMA implementation.
167 #if defined(CONFIG_SPI_PXA2XX_PXADMA)
168 #define SPI_PXA2XX_USE_DMA 1
169 #define MAX_DMA_LEN 8191
170 #define DEFAULT_DMA_CR1 (SSCR1_TSRE | SSCR1_RSRE | SSCR1_TINTE)
171 #elif defined(CONFIG_SPI_PXA2XX_DMA)
172 #define SPI_PXA2XX_USE_DMA 1
173 #define MAX_DMA_LEN SZ_64K
174 #define DEFAULT_DMA_CR1 (SSCR1_TSRE | SSCR1_RSRE | SSCR1_TRAIL)
176 #undef SPI_PXA2XX_USE_DMA
177 #define MAX_DMA_LEN 0
178 #define DEFAULT_DMA_CR1 0
181 #ifdef SPI_PXA2XX_USE_DMA
182 extern bool pxa2xx_spi_dma_is_possible(size_t len);
183 extern int pxa2xx_spi_map_dma_buffers(struct driver_data *drv_data);
184 extern irqreturn_t pxa2xx_spi_dma_transfer(struct driver_data *drv_data);
185 extern int pxa2xx_spi_dma_prepare(struct driver_data *drv_data, u32 dma_burst);
186 extern void pxa2xx_spi_dma_start(struct driver_data *drv_data);
187 extern int pxa2xx_spi_dma_setup(struct driver_data *drv_data);
188 extern void pxa2xx_spi_dma_release(struct driver_data *drv_data);
189 extern void pxa2xx_spi_dma_resume(struct driver_data *drv_data);
190 extern int pxa2xx_spi_set_dma_burst_and_threshold(struct chip_data *chip,
191 struct spi_device *spi,
196 static inline bool pxa2xx_spi_dma_is_possible(size_t len) { return false; }
197 static inline int pxa2xx_spi_map_dma_buffers(struct driver_data *drv_data)
201 #define pxa2xx_spi_dma_transfer NULL
202 static inline void pxa2xx_spi_dma_prepare(struct driver_data *drv_data,
204 static inline void pxa2xx_spi_dma_start(struct driver_data *drv_data) {}
205 static inline int pxa2xx_spi_dma_setup(struct driver_data *drv_data)
209 static inline void pxa2xx_spi_dma_release(struct driver_data *drv_data) {}
210 static inline void pxa2xx_spi_dma_resume(struct driver_data *drv_data) {}
211 static inline int pxa2xx_spi_set_dma_burst_and_threshold(struct chip_data *chip,
212 struct spi_device *spi,
221 #endif /* SPI_PXA2XX_H */