2 * Sonics Silicon Backplane
5 * Copyright 2005, Broadcom Corporation
6 * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
8 * Licensed under the GNU/GPL. See COPYING for details.
11 #include "ssb_private.h"
13 #include <linux/delay.h>
15 #include <linux/module.h>
16 #include <linux/platform_device.h>
17 #include <linux/ssb/ssb.h>
18 #include <linux/ssb/ssb_regs.h>
19 #include <linux/ssb/ssb_driver_gige.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/pci.h>
22 #include <linux/mmc/sdio_func.h>
23 #include <linux/slab.h>
25 #include <pcmcia/cistpl.h>
26 #include <pcmcia/ds.h>
29 MODULE_DESCRIPTION("Sonics Silicon Backplane driver");
30 MODULE_LICENSE("GPL");
33 /* Temporary list of yet-to-be-attached buses */
34 static LIST_HEAD(attach_queue);
35 /* List if running buses */
36 static LIST_HEAD(buses);
37 /* Software ID counter */
38 static unsigned int next_busnumber;
39 /* buses_mutes locks the two buslists and the next_busnumber.
40 * Don't lock this directly, but use ssb_buses_[un]lock() below. */
41 static DEFINE_MUTEX(buses_mutex);
43 /* There are differences in the codeflow, if the bus is
44 * initialized from early boot, as various needed services
45 * are not available early. This is a mechanism to delay
46 * these initializations to after early boot has finished.
47 * It's also used to avoid mutex locking, as that's not
48 * available and needed early. */
49 static bool ssb_is_early_boot = 1;
51 static void ssb_buses_lock(void);
52 static void ssb_buses_unlock(void);
55 #ifdef CONFIG_SSB_PCIHOST
56 struct ssb_bus *ssb_pci_dev_to_bus(struct pci_dev *pdev)
61 list_for_each_entry(bus, &buses, list) {
62 if (bus->bustype == SSB_BUSTYPE_PCI &&
63 bus->host_pci == pdev)
72 #endif /* CONFIG_SSB_PCIHOST */
74 #ifdef CONFIG_SSB_PCMCIAHOST
75 struct ssb_bus *ssb_pcmcia_dev_to_bus(struct pcmcia_device *pdev)
80 list_for_each_entry(bus, &buses, list) {
81 if (bus->bustype == SSB_BUSTYPE_PCMCIA &&
82 bus->host_pcmcia == pdev)
91 #endif /* CONFIG_SSB_PCMCIAHOST */
93 int ssb_for_each_bus_call(unsigned long data,
94 int (*func)(struct ssb_bus *bus, unsigned long data))
100 list_for_each_entry(bus, &buses, list) {
101 res = func(bus, data);
112 static struct ssb_device *ssb_device_get(struct ssb_device *dev)
115 get_device(dev->dev);
119 static void ssb_device_put(struct ssb_device *dev)
122 put_device(dev->dev);
125 static int ssb_device_resume(struct device *dev)
127 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
128 struct ssb_driver *ssb_drv;
132 ssb_drv = drv_to_ssb_drv(dev->driver);
133 if (ssb_drv && ssb_drv->resume)
134 err = ssb_drv->resume(ssb_dev);
142 static int ssb_device_suspend(struct device *dev, pm_message_t state)
144 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
145 struct ssb_driver *ssb_drv;
149 ssb_drv = drv_to_ssb_drv(dev->driver);
150 if (ssb_drv && ssb_drv->suspend)
151 err = ssb_drv->suspend(ssb_dev, state);
159 int ssb_bus_resume(struct ssb_bus *bus)
163 /* Reset HW state information in memory, so that HW is
164 * completely reinitialized. */
165 bus->mapped_device = NULL;
166 #ifdef CONFIG_SSB_DRIVER_PCICORE
167 bus->pcicore.setup_done = 0;
170 err = ssb_bus_powerup(bus, 0);
173 err = ssb_pcmcia_hardware_setup(bus);
175 ssb_bus_may_powerdown(bus);
178 ssb_chipco_resume(&bus->chipco);
179 ssb_bus_may_powerdown(bus);
183 EXPORT_SYMBOL(ssb_bus_resume);
185 int ssb_bus_suspend(struct ssb_bus *bus)
187 ssb_chipco_suspend(&bus->chipco);
188 ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
192 EXPORT_SYMBOL(ssb_bus_suspend);
194 #ifdef CONFIG_SSB_SPROM
195 /** ssb_devices_freeze - Freeze all devices on the bus.
197 * After freezing no device driver will be handling a device
198 * on this bus anymore. ssb_devices_thaw() must be called after
199 * a successful freeze to reactivate the devices.
202 * @ctx: Context structure. Pass this to ssb_devices_thaw().
204 int ssb_devices_freeze(struct ssb_bus *bus, struct ssb_freeze_context *ctx)
206 struct ssb_device *sdev;
207 struct ssb_driver *sdrv;
210 memset(ctx, 0, sizeof(*ctx));
212 SSB_WARN_ON(bus->nr_devices > ARRAY_SIZE(ctx->device_frozen));
214 for (i = 0; i < bus->nr_devices; i++) {
215 sdev = ssb_device_get(&bus->devices[i]);
217 if (!sdev->dev || !sdev->dev->driver ||
218 !device_is_registered(sdev->dev)) {
219 ssb_device_put(sdev);
222 sdrv = drv_to_ssb_drv(sdev->dev->driver);
223 if (SSB_WARN_ON(!sdrv->remove))
226 ctx->device_frozen[i] = 1;
232 /** ssb_devices_thaw - Unfreeze all devices on the bus.
234 * This will re-attach the device drivers and re-init the devices.
236 * @ctx: The context structure from ssb_devices_freeze()
238 int ssb_devices_thaw(struct ssb_freeze_context *ctx)
240 struct ssb_bus *bus = ctx->bus;
241 struct ssb_device *sdev;
242 struct ssb_driver *sdrv;
246 for (i = 0; i < bus->nr_devices; i++) {
247 if (!ctx->device_frozen[i])
249 sdev = &bus->devices[i];
251 if (SSB_WARN_ON(!sdev->dev || !sdev->dev->driver))
253 sdrv = drv_to_ssb_drv(sdev->dev->driver);
254 if (SSB_WARN_ON(!sdrv || !sdrv->probe))
257 err = sdrv->probe(sdev, &sdev->id);
259 ssb_err("Failed to thaw device %s\n",
260 dev_name(sdev->dev));
263 ssb_device_put(sdev);
268 #endif /* CONFIG_SSB_SPROM */
270 static void ssb_device_shutdown(struct device *dev)
272 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
273 struct ssb_driver *ssb_drv;
277 ssb_drv = drv_to_ssb_drv(dev->driver);
278 if (ssb_drv && ssb_drv->shutdown)
279 ssb_drv->shutdown(ssb_dev);
282 static int ssb_device_remove(struct device *dev)
284 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
285 struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver);
287 if (ssb_drv && ssb_drv->remove)
288 ssb_drv->remove(ssb_dev);
289 ssb_device_put(ssb_dev);
294 static int ssb_device_probe(struct device *dev)
296 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
297 struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver);
300 ssb_device_get(ssb_dev);
301 if (ssb_drv && ssb_drv->probe)
302 err = ssb_drv->probe(ssb_dev, &ssb_dev->id);
304 ssb_device_put(ssb_dev);
309 static int ssb_match_devid(const struct ssb_device_id *tabid,
310 const struct ssb_device_id *devid)
312 if ((tabid->vendor != devid->vendor) &&
313 tabid->vendor != SSB_ANY_VENDOR)
315 if ((tabid->coreid != devid->coreid) &&
316 tabid->coreid != SSB_ANY_ID)
318 if ((tabid->revision != devid->revision) &&
319 tabid->revision != SSB_ANY_REV)
324 static int ssb_bus_match(struct device *dev, struct device_driver *drv)
326 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
327 struct ssb_driver *ssb_drv = drv_to_ssb_drv(drv);
328 const struct ssb_device_id *id;
330 for (id = ssb_drv->id_table;
331 id->vendor || id->coreid || id->revision;
333 if (ssb_match_devid(id, &ssb_dev->id))
334 return 1; /* found */
340 static int ssb_device_uevent(struct device *dev, struct kobj_uevent_env *env)
342 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
347 return add_uevent_var(env,
348 "MODALIAS=ssb:v%04Xid%04Xrev%02X",
349 ssb_dev->id.vendor, ssb_dev->id.coreid,
350 ssb_dev->id.revision);
353 #define ssb_config_attr(attrib, field, format_string) \
355 attrib##_show(struct device *dev, struct device_attribute *attr, char *buf) \
357 return sprintf(buf, format_string, dev_to_ssb_dev(dev)->field); \
359 static DEVICE_ATTR_RO(attrib);
361 ssb_config_attr(core_num, core_index, "%u\n")
362 ssb_config_attr(coreid, id.coreid, "0x%04x\n")
363 ssb_config_attr(vendor, id.vendor, "0x%04x\n")
364 ssb_config_attr(revision, id.revision, "%u\n")
365 ssb_config_attr(irq, irq, "%u\n")
367 name_show(struct device *dev, struct device_attribute *attr, char *buf)
369 return sprintf(buf, "%s\n",
370 ssb_core_name(dev_to_ssb_dev(dev)->id.coreid));
372 static DEVICE_ATTR_RO(name);
374 static struct attribute *ssb_device_attrs[] = {
376 &dev_attr_core_num.attr,
377 &dev_attr_coreid.attr,
378 &dev_attr_vendor.attr,
379 &dev_attr_revision.attr,
383 ATTRIBUTE_GROUPS(ssb_device);
385 static struct bus_type ssb_bustype = {
387 .match = ssb_bus_match,
388 .probe = ssb_device_probe,
389 .remove = ssb_device_remove,
390 .shutdown = ssb_device_shutdown,
391 .suspend = ssb_device_suspend,
392 .resume = ssb_device_resume,
393 .uevent = ssb_device_uevent,
394 .dev_groups = ssb_device_groups,
397 static void ssb_buses_lock(void)
399 /* See the comment at the ssb_is_early_boot definition */
400 if (!ssb_is_early_boot)
401 mutex_lock(&buses_mutex);
404 static void ssb_buses_unlock(void)
406 /* See the comment at the ssb_is_early_boot definition */
407 if (!ssb_is_early_boot)
408 mutex_unlock(&buses_mutex);
411 static void ssb_devices_unregister(struct ssb_bus *bus)
413 struct ssb_device *sdev;
416 for (i = bus->nr_devices - 1; i >= 0; i--) {
417 sdev = &(bus->devices[i]);
419 device_unregister(sdev->dev);
422 #ifdef CONFIG_SSB_EMBEDDED
423 if (bus->bustype == SSB_BUSTYPE_SSB)
424 platform_device_unregister(bus->watchdog);
428 void ssb_bus_unregister(struct ssb_bus *bus)
432 err = ssb_gpio_unregister(bus);
434 ssb_dbg("Some GPIOs are still in use\n");
436 ssb_dbg("Can not unregister GPIO driver: %i\n", err);
439 ssb_devices_unregister(bus);
440 list_del(&bus->list);
443 ssb_pcmcia_exit(bus);
447 EXPORT_SYMBOL(ssb_bus_unregister);
449 static void ssb_release_dev(struct device *dev)
451 struct __ssb_dev_wrapper *devwrap;
453 devwrap = container_of(dev, struct __ssb_dev_wrapper, dev);
457 static int ssb_devices_register(struct ssb_bus *bus)
459 struct ssb_device *sdev;
461 struct __ssb_dev_wrapper *devwrap;
465 for (i = 0; i < bus->nr_devices; i++) {
466 sdev = &(bus->devices[i]);
468 /* We don't register SSB-system devices to the kernel,
469 * as the drivers for them are built into SSB. */
470 switch (sdev->id.coreid) {
471 case SSB_DEV_CHIPCOMMON:
476 case SSB_DEV_MIPS_3302:
481 devwrap = kzalloc(sizeof(*devwrap), GFP_KERNEL);
483 ssb_err("Could not allocate device\n");
488 devwrap->sdev = sdev;
490 dev->release = ssb_release_dev;
491 dev->bus = &ssb_bustype;
492 dev_set_name(dev, "ssb%u:%d", bus->busnumber, dev_idx);
494 switch (bus->bustype) {
495 case SSB_BUSTYPE_PCI:
496 #ifdef CONFIG_SSB_PCIHOST
497 sdev->irq = bus->host_pci->irq;
498 dev->parent = &bus->host_pci->dev;
499 sdev->dma_dev = dev->parent;
502 case SSB_BUSTYPE_PCMCIA:
503 #ifdef CONFIG_SSB_PCMCIAHOST
504 sdev->irq = bus->host_pcmcia->irq;
505 dev->parent = &bus->host_pcmcia->dev;
508 case SSB_BUSTYPE_SDIO:
509 #ifdef CONFIG_SSB_SDIOHOST
510 dev->parent = &bus->host_sdio->dev;
513 case SSB_BUSTYPE_SSB:
514 dev->dma_mask = &dev->coherent_dma_mask;
520 err = device_register(dev);
522 ssb_err("Could not register %s\n", dev_name(dev));
523 /* Set dev to NULL to not unregister
524 * dev on error unwinding. */
532 #ifdef CONFIG_SSB_DRIVER_MIPS
533 if (bus->mipscore.pflash.present) {
534 err = platform_device_register(&ssb_pflash_dev);
536 pr_err("Error registering parallel flash\n");
540 #ifdef CONFIG_SSB_SFLASH
541 if (bus->mipscore.sflash.present) {
542 err = platform_device_register(&ssb_sflash_dev);
544 pr_err("Error registering serial flash\n");
550 /* Unwind the already registered devices. */
551 ssb_devices_unregister(bus);
555 /* Needs ssb_buses_lock() */
556 static int ssb_attach_queued_buses(void)
558 struct ssb_bus *bus, *n;
560 int drop_them_all = 0;
562 list_for_each_entry_safe(bus, n, &attach_queue, list) {
564 list_del(&bus->list);
567 /* Can't init the PCIcore in ssb_bus_register(), as that
568 * is too early in boot for embedded systems
569 * (no udelay() available). So do it here in attach stage.
571 err = ssb_bus_powerup(bus, 0);
574 ssb_pcicore_init(&bus->pcicore);
575 if (bus->bustype == SSB_BUSTYPE_SSB)
576 ssb_watchdog_register(bus);
578 err = ssb_gpio_init(bus);
579 if (err == -ENOTSUPP)
580 ssb_dbg("GPIO driver not activated\n");
582 ssb_dbg("Error registering GPIO driver: %i\n", err);
584 ssb_bus_may_powerdown(bus);
586 err = ssb_devices_register(bus);
590 list_del(&bus->list);
593 list_move_tail(&bus->list, &buses);
599 static u8 ssb_ssb_read8(struct ssb_device *dev, u16 offset)
601 struct ssb_bus *bus = dev->bus;
603 offset += dev->core_index * SSB_CORE_SIZE;
604 return readb(bus->mmio + offset);
607 static u16 ssb_ssb_read16(struct ssb_device *dev, u16 offset)
609 struct ssb_bus *bus = dev->bus;
611 offset += dev->core_index * SSB_CORE_SIZE;
612 return readw(bus->mmio + offset);
615 static u32 ssb_ssb_read32(struct ssb_device *dev, u16 offset)
617 struct ssb_bus *bus = dev->bus;
619 offset += dev->core_index * SSB_CORE_SIZE;
620 return readl(bus->mmio + offset);
623 #ifdef CONFIG_SSB_BLOCKIO
624 static void ssb_ssb_block_read(struct ssb_device *dev, void *buffer,
625 size_t count, u16 offset, u8 reg_width)
627 struct ssb_bus *bus = dev->bus;
630 offset += dev->core_index * SSB_CORE_SIZE;
631 addr = bus->mmio + offset;
638 *buf = __raw_readb(addr);
645 __le16 *buf = buffer;
647 SSB_WARN_ON(count & 1);
649 *buf = (__force __le16)__raw_readw(addr);
656 __le32 *buf = buffer;
658 SSB_WARN_ON(count & 3);
660 *buf = (__force __le32)__raw_readl(addr);
670 #endif /* CONFIG_SSB_BLOCKIO */
672 static void ssb_ssb_write8(struct ssb_device *dev, u16 offset, u8 value)
674 struct ssb_bus *bus = dev->bus;
676 offset += dev->core_index * SSB_CORE_SIZE;
677 writeb(value, bus->mmio + offset);
680 static void ssb_ssb_write16(struct ssb_device *dev, u16 offset, u16 value)
682 struct ssb_bus *bus = dev->bus;
684 offset += dev->core_index * SSB_CORE_SIZE;
685 writew(value, bus->mmio + offset);
688 static void ssb_ssb_write32(struct ssb_device *dev, u16 offset, u32 value)
690 struct ssb_bus *bus = dev->bus;
692 offset += dev->core_index * SSB_CORE_SIZE;
693 writel(value, bus->mmio + offset);
696 #ifdef CONFIG_SSB_BLOCKIO
697 static void ssb_ssb_block_write(struct ssb_device *dev, const void *buffer,
698 size_t count, u16 offset, u8 reg_width)
700 struct ssb_bus *bus = dev->bus;
703 offset += dev->core_index * SSB_CORE_SIZE;
704 addr = bus->mmio + offset;
708 const u8 *buf = buffer;
711 __raw_writeb(*buf, addr);
718 const __le16 *buf = buffer;
720 SSB_WARN_ON(count & 1);
722 __raw_writew((__force u16)(*buf), addr);
729 const __le32 *buf = buffer;
731 SSB_WARN_ON(count & 3);
733 __raw_writel((__force u32)(*buf), addr);
743 #endif /* CONFIG_SSB_BLOCKIO */
745 /* Ops for the plain SSB bus without a host-device (no PCI or PCMCIA). */
746 static const struct ssb_bus_ops ssb_ssb_ops = {
747 .read8 = ssb_ssb_read8,
748 .read16 = ssb_ssb_read16,
749 .read32 = ssb_ssb_read32,
750 .write8 = ssb_ssb_write8,
751 .write16 = ssb_ssb_write16,
752 .write32 = ssb_ssb_write32,
753 #ifdef CONFIG_SSB_BLOCKIO
754 .block_read = ssb_ssb_block_read,
755 .block_write = ssb_ssb_block_write,
759 static int ssb_fetch_invariants(struct ssb_bus *bus,
760 ssb_invariants_func_t get_invariants)
762 struct ssb_init_invariants iv;
765 memset(&iv, 0, sizeof(iv));
766 err = get_invariants(bus, &iv);
769 memcpy(&bus->boardinfo, &iv.boardinfo, sizeof(iv.boardinfo));
770 memcpy(&bus->sprom, &iv.sprom, sizeof(iv.sprom));
771 bus->has_cardbus_slot = iv.has_cardbus_slot;
776 static int ssb_bus_register(struct ssb_bus *bus,
777 ssb_invariants_func_t get_invariants,
778 unsigned long baseaddr)
782 spin_lock_init(&bus->bar_lock);
783 INIT_LIST_HEAD(&bus->list);
784 #ifdef CONFIG_SSB_EMBEDDED
785 spin_lock_init(&bus->gpio_lock);
788 /* Powerup the bus */
789 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
793 /* Init SDIO-host device (if any), before the scan */
794 err = ssb_sdio_init(bus);
796 goto err_disable_xtal;
799 bus->busnumber = next_busnumber;
800 /* Scan for devices (cores) */
801 err = ssb_bus_scan(bus, baseaddr);
805 /* Init PCI-host device (if any) */
806 err = ssb_pci_init(bus);
809 /* Init PCMCIA-host device (if any) */
810 err = ssb_pcmcia_init(bus);
814 /* Initialize basic system devices (if available) */
815 err = ssb_bus_powerup(bus, 0);
817 goto err_pcmcia_exit;
818 ssb_chipcommon_init(&bus->chipco);
819 ssb_extif_init(&bus->extif);
820 ssb_mipscore_init(&bus->mipscore);
821 err = ssb_fetch_invariants(bus, get_invariants);
823 ssb_bus_may_powerdown(bus);
824 goto err_pcmcia_exit;
826 ssb_bus_may_powerdown(bus);
828 /* Queue it for attach.
829 * See the comment at the ssb_is_early_boot definition. */
830 list_add_tail(&bus->list, &attach_queue);
831 if (!ssb_is_early_boot) {
832 /* This is not early boot, so we must attach the bus now */
833 err = ssb_attach_queued_buses();
844 list_del(&bus->list);
846 ssb_pcmcia_exit(bus);
855 ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
859 #ifdef CONFIG_SSB_PCIHOST
860 int ssb_bus_pcibus_register(struct ssb_bus *bus, struct pci_dev *host_pci)
864 bus->bustype = SSB_BUSTYPE_PCI;
865 bus->host_pci = host_pci;
866 bus->ops = &ssb_pci_ops;
868 err = ssb_bus_register(bus, ssb_pci_get_invariants, 0);
870 ssb_info("Sonics Silicon Backplane found on PCI device %s\n",
871 dev_name(&host_pci->dev));
873 ssb_err("Failed to register PCI version of SSB with error %d\n",
879 #endif /* CONFIG_SSB_PCIHOST */
881 #ifdef CONFIG_SSB_PCMCIAHOST
882 int ssb_bus_pcmciabus_register(struct ssb_bus *bus,
883 struct pcmcia_device *pcmcia_dev,
884 unsigned long baseaddr)
888 bus->bustype = SSB_BUSTYPE_PCMCIA;
889 bus->host_pcmcia = pcmcia_dev;
890 bus->ops = &ssb_pcmcia_ops;
892 err = ssb_bus_register(bus, ssb_pcmcia_get_invariants, baseaddr);
894 ssb_info("Sonics Silicon Backplane found on PCMCIA device %s\n",
895 pcmcia_dev->devname);
900 EXPORT_SYMBOL(ssb_bus_pcmciabus_register);
901 #endif /* CONFIG_SSB_PCMCIAHOST */
903 #ifdef CONFIG_SSB_SDIOHOST
904 int ssb_bus_sdiobus_register(struct ssb_bus *bus, struct sdio_func *func,
909 bus->bustype = SSB_BUSTYPE_SDIO;
910 bus->host_sdio = func;
911 bus->ops = &ssb_sdio_ops;
912 bus->quirks = quirks;
914 err = ssb_bus_register(bus, ssb_sdio_get_invariants, ~0);
916 ssb_info("Sonics Silicon Backplane found on SDIO device %s\n",
922 EXPORT_SYMBOL(ssb_bus_sdiobus_register);
923 #endif /* CONFIG_SSB_PCMCIAHOST */
925 int ssb_bus_ssbbus_register(struct ssb_bus *bus, unsigned long baseaddr,
926 ssb_invariants_func_t get_invariants)
930 bus->bustype = SSB_BUSTYPE_SSB;
931 bus->ops = &ssb_ssb_ops;
933 err = ssb_bus_register(bus, get_invariants, baseaddr);
935 ssb_info("Sonics Silicon Backplane found at address 0x%08lX\n",
942 int __ssb_driver_register(struct ssb_driver *drv, struct module *owner)
944 drv->drv.name = drv->name;
945 drv->drv.bus = &ssb_bustype;
946 drv->drv.owner = owner;
948 return driver_register(&drv->drv);
950 EXPORT_SYMBOL(__ssb_driver_register);
952 void ssb_driver_unregister(struct ssb_driver *drv)
954 driver_unregister(&drv->drv);
956 EXPORT_SYMBOL(ssb_driver_unregister);
958 void ssb_set_devtypedata(struct ssb_device *dev, void *data)
960 struct ssb_bus *bus = dev->bus;
961 struct ssb_device *ent;
964 for (i = 0; i < bus->nr_devices; i++) {
965 ent = &(bus->devices[i]);
966 if (ent->id.vendor != dev->id.vendor)
968 if (ent->id.coreid != dev->id.coreid)
971 ent->devtypedata = data;
974 EXPORT_SYMBOL(ssb_set_devtypedata);
976 static u32 clkfactor_f6_resolve(u32 v)
978 /* map the magic values */
980 case SSB_CHIPCO_CLK_F6_2:
982 case SSB_CHIPCO_CLK_F6_3:
984 case SSB_CHIPCO_CLK_F6_4:
986 case SSB_CHIPCO_CLK_F6_5:
988 case SSB_CHIPCO_CLK_F6_6:
990 case SSB_CHIPCO_CLK_F6_7:
996 /* Calculate the speed the backplane would run at a given set of clockcontrol values */
997 u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m)
999 u32 n1, n2, clock, m1, m2, m3, mc;
1001 n1 = (n & SSB_CHIPCO_CLK_N1);
1002 n2 = ((n & SSB_CHIPCO_CLK_N2) >> SSB_CHIPCO_CLK_N2_SHIFT);
1005 case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
1006 if (m & SSB_CHIPCO_CLK_T6_MMASK)
1007 return SSB_CHIPCO_CLK_T6_M1;
1008 return SSB_CHIPCO_CLK_T6_M0;
1009 case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
1010 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
1011 case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
1012 case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
1013 n1 = clkfactor_f6_resolve(n1);
1014 n2 += SSB_CHIPCO_CLK_F5_BIAS;
1016 case SSB_PLLTYPE_2: /* 48Mhz, 4 dividers */
1017 n1 += SSB_CHIPCO_CLK_T2_BIAS;
1018 n2 += SSB_CHIPCO_CLK_T2_BIAS;
1019 SSB_WARN_ON(!((n1 >= 2) && (n1 <= 7)));
1020 SSB_WARN_ON(!((n2 >= 5) && (n2 <= 23)));
1022 case SSB_PLLTYPE_5: /* 25Mhz, 4 dividers */
1029 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
1030 case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
1031 clock = SSB_CHIPCO_CLK_BASE2 * n1 * n2;
1034 clock = SSB_CHIPCO_CLK_BASE1 * n1 * n2;
1039 m1 = (m & SSB_CHIPCO_CLK_M1);
1040 m2 = ((m & SSB_CHIPCO_CLK_M2) >> SSB_CHIPCO_CLK_M2_SHIFT);
1041 m3 = ((m & SSB_CHIPCO_CLK_M3) >> SSB_CHIPCO_CLK_M3_SHIFT);
1042 mc = ((m & SSB_CHIPCO_CLK_MC) >> SSB_CHIPCO_CLK_MC_SHIFT);
1045 case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
1046 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
1047 case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
1048 case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
1049 m1 = clkfactor_f6_resolve(m1);
1050 if ((plltype == SSB_PLLTYPE_1) ||
1051 (plltype == SSB_PLLTYPE_3))
1052 m2 += SSB_CHIPCO_CLK_F5_BIAS;
1054 m2 = clkfactor_f6_resolve(m2);
1055 m3 = clkfactor_f6_resolve(m3);
1058 case SSB_CHIPCO_CLK_MC_BYPASS:
1060 case SSB_CHIPCO_CLK_MC_M1:
1061 return (clock / m1);
1062 case SSB_CHIPCO_CLK_MC_M1M2:
1063 return (clock / (m1 * m2));
1064 case SSB_CHIPCO_CLK_MC_M1M2M3:
1065 return (clock / (m1 * m2 * m3));
1066 case SSB_CHIPCO_CLK_MC_M1M3:
1067 return (clock / (m1 * m3));
1071 m1 += SSB_CHIPCO_CLK_T2_BIAS;
1072 m2 += SSB_CHIPCO_CLK_T2M2_BIAS;
1073 m3 += SSB_CHIPCO_CLK_T2_BIAS;
1074 SSB_WARN_ON(!((m1 >= 2) && (m1 <= 7)));
1075 SSB_WARN_ON(!((m2 >= 3) && (m2 <= 10)));
1076 SSB_WARN_ON(!((m3 >= 2) && (m3 <= 7)));
1078 if (!(mc & SSB_CHIPCO_CLK_T2MC_M1BYP))
1080 if (!(mc & SSB_CHIPCO_CLK_T2MC_M2BYP))
1082 if (!(mc & SSB_CHIPCO_CLK_T2MC_M3BYP))
1091 /* Get the current speed the backplane is running at */
1092 u32 ssb_clockspeed(struct ssb_bus *bus)
1096 u32 clkctl_n, clkctl_m;
1098 if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
1099 return ssb_pmu_get_controlclock(&bus->chipco);
1101 if (ssb_extif_available(&bus->extif))
1102 ssb_extif_get_clockcontrol(&bus->extif, &plltype,
1103 &clkctl_n, &clkctl_m);
1104 else if (bus->chipco.dev)
1105 ssb_chipco_get_clockcontrol(&bus->chipco, &plltype,
1106 &clkctl_n, &clkctl_m);
1110 if (bus->chip_id == 0x5365) {
1113 rate = ssb_calc_clock_rate(plltype, clkctl_n, clkctl_m);
1114 if (plltype == SSB_PLLTYPE_3) /* 25Mhz, 2 dividers */
1120 EXPORT_SYMBOL(ssb_clockspeed);
1122 static u32 ssb_tmslow_reject_bitmask(struct ssb_device *dev)
1124 u32 rev = ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_SSBREV;
1126 /* The REJECT bit seems to be different for Backplane rev 2.3 */
1128 case SSB_IDLOW_SSBREV_22:
1129 case SSB_IDLOW_SSBREV_24:
1130 case SSB_IDLOW_SSBREV_26:
1131 return SSB_TMSLOW_REJECT;
1132 case SSB_IDLOW_SSBREV_23:
1133 return SSB_TMSLOW_REJECT_23;
1134 case SSB_IDLOW_SSBREV_25: /* TODO - find the proper REJECT bit */
1135 case SSB_IDLOW_SSBREV_27: /* same here */
1136 return SSB_TMSLOW_REJECT; /* this is a guess */
1137 case SSB_IDLOW_SSBREV:
1140 WARN(1, KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
1142 return (SSB_TMSLOW_REJECT | SSB_TMSLOW_REJECT_23);
1145 int ssb_device_is_enabled(struct ssb_device *dev)
1150 reject = ssb_tmslow_reject_bitmask(dev);
1151 val = ssb_read32(dev, SSB_TMSLOW);
1152 val &= SSB_TMSLOW_CLOCK | SSB_TMSLOW_RESET | reject;
1154 return (val == SSB_TMSLOW_CLOCK);
1156 EXPORT_SYMBOL(ssb_device_is_enabled);
1158 static void ssb_flush_tmslow(struct ssb_device *dev)
1160 /* Make _really_ sure the device has finished the TMSLOW
1161 * register write transaction, as we risk running into
1162 * a machine check exception otherwise.
1163 * Do this by reading the register back to commit the
1164 * PCI write and delay an additional usec for the device
1165 * to react to the change. */
1166 ssb_read32(dev, SSB_TMSLOW);
1170 void ssb_device_enable(struct ssb_device *dev, u32 core_specific_flags)
1174 ssb_device_disable(dev, core_specific_flags);
1175 ssb_write32(dev, SSB_TMSLOW,
1176 SSB_TMSLOW_RESET | SSB_TMSLOW_CLOCK |
1177 SSB_TMSLOW_FGC | core_specific_flags);
1178 ssb_flush_tmslow(dev);
1180 /* Clear SERR if set. This is a hw bug workaround. */
1181 if (ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_SERR)
1182 ssb_write32(dev, SSB_TMSHIGH, 0);
1184 val = ssb_read32(dev, SSB_IMSTATE);
1185 if (val & (SSB_IMSTATE_IBE | SSB_IMSTATE_TO)) {
1186 val &= ~(SSB_IMSTATE_IBE | SSB_IMSTATE_TO);
1187 ssb_write32(dev, SSB_IMSTATE, val);
1190 ssb_write32(dev, SSB_TMSLOW,
1191 SSB_TMSLOW_CLOCK | SSB_TMSLOW_FGC |
1192 core_specific_flags);
1193 ssb_flush_tmslow(dev);
1195 ssb_write32(dev, SSB_TMSLOW, SSB_TMSLOW_CLOCK |
1196 core_specific_flags);
1197 ssb_flush_tmslow(dev);
1199 EXPORT_SYMBOL(ssb_device_enable);
1201 /* Wait for bitmask in a register to get set or cleared.
1202 * timeout is in units of ten-microseconds */
1203 static int ssb_wait_bits(struct ssb_device *dev, u16 reg, u32 bitmask,
1204 int timeout, int set)
1209 for (i = 0; i < timeout; i++) {
1210 val = ssb_read32(dev, reg);
1212 if ((val & bitmask) == bitmask)
1215 if (!(val & bitmask))
1220 printk(KERN_ERR PFX "Timeout waiting for bitmask %08X on "
1221 "register %04X to %s.\n",
1222 bitmask, reg, (set ? "set" : "clear"));
1227 void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags)
1231 if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_RESET)
1234 reject = ssb_tmslow_reject_bitmask(dev);
1236 if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_CLOCK) {
1237 ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK);
1238 ssb_wait_bits(dev, SSB_TMSLOW, reject, 1000, 1);
1239 ssb_wait_bits(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
1241 if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
1242 val = ssb_read32(dev, SSB_IMSTATE);
1243 val |= SSB_IMSTATE_REJECT;
1244 ssb_write32(dev, SSB_IMSTATE, val);
1245 ssb_wait_bits(dev, SSB_IMSTATE, SSB_IMSTATE_BUSY, 1000,
1249 ssb_write32(dev, SSB_TMSLOW,
1250 SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
1251 reject | SSB_TMSLOW_RESET |
1252 core_specific_flags);
1253 ssb_flush_tmslow(dev);
1255 if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
1256 val = ssb_read32(dev, SSB_IMSTATE);
1257 val &= ~SSB_IMSTATE_REJECT;
1258 ssb_write32(dev, SSB_IMSTATE, val);
1262 ssb_write32(dev, SSB_TMSLOW,
1263 reject | SSB_TMSLOW_RESET |
1264 core_specific_flags);
1265 ssb_flush_tmslow(dev);
1267 EXPORT_SYMBOL(ssb_device_disable);
1269 /* Some chipsets need routing known for PCIe and 64-bit DMA */
1270 static bool ssb_dma_translation_special_bit(struct ssb_device *dev)
1272 u16 chip_id = dev->bus->chip_id;
1274 if (dev->id.coreid == SSB_DEV_80211) {
1275 return (chip_id == 0x4322 || chip_id == 43221 ||
1276 chip_id == 43231 || chip_id == 43222);
1282 u32 ssb_dma_translation(struct ssb_device *dev)
1284 switch (dev->bus->bustype) {
1285 case SSB_BUSTYPE_SSB:
1287 case SSB_BUSTYPE_PCI:
1288 if (pci_is_pcie(dev->bus->host_pci) &&
1289 ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_DMA64) {
1290 return SSB_PCIE_DMA_H32;
1292 if (ssb_dma_translation_special_bit(dev))
1293 return SSB_PCIE_DMA_H32;
1298 __ssb_dma_not_implemented(dev);
1302 EXPORT_SYMBOL(ssb_dma_translation);
1304 int ssb_bus_may_powerdown(struct ssb_bus *bus)
1306 struct ssb_chipcommon *cc;
1309 /* On buses where more than one core may be working
1310 * at a time, we must not powerdown stuff if there are
1311 * still cores that may want to run. */
1312 if (bus->bustype == SSB_BUSTYPE_SSB)
1319 if (cc->dev->id.revision < 5)
1322 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_SLOW);
1323 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
1327 #ifdef CONFIG_SSB_DEBUG
1328 bus->powered_up = 0;
1332 ssb_err("Bus powerdown failed\n");
1335 EXPORT_SYMBOL(ssb_bus_may_powerdown);
1337 int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl)
1340 enum ssb_clkmode mode;
1342 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
1346 #ifdef CONFIG_SSB_DEBUG
1347 bus->powered_up = 1;
1350 mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
1351 ssb_chipco_set_clockmode(&bus->chipco, mode);
1355 ssb_err("Bus powerup failed\n");
1358 EXPORT_SYMBOL(ssb_bus_powerup);
1360 static void ssb_broadcast_value(struct ssb_device *dev,
1361 u32 address, u32 data)
1363 #ifdef CONFIG_SSB_DRIVER_PCICORE
1364 /* This is used for both, PCI and ChipCommon core, so be careful. */
1365 BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
1366 BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
1369 ssb_write32(dev, SSB_CHIPCO_BCAST_ADDR, address);
1370 ssb_read32(dev, SSB_CHIPCO_BCAST_ADDR); /* flush */
1371 ssb_write32(dev, SSB_CHIPCO_BCAST_DATA, data);
1372 ssb_read32(dev, SSB_CHIPCO_BCAST_DATA); /* flush */
1375 void ssb_commit_settings(struct ssb_bus *bus)
1377 struct ssb_device *dev;
1379 #ifdef CONFIG_SSB_DRIVER_PCICORE
1380 dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
1382 dev = bus->chipco.dev;
1386 /* This forces an update of the cached registers. */
1387 ssb_broadcast_value(dev, 0xFD8, 0);
1389 EXPORT_SYMBOL(ssb_commit_settings);
1391 u32 ssb_admatch_base(u32 adm)
1395 switch (adm & SSB_ADM_TYPE) {
1397 base = (adm & SSB_ADM_BASE0);
1400 SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
1401 base = (adm & SSB_ADM_BASE1);
1404 SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
1405 base = (adm & SSB_ADM_BASE2);
1413 EXPORT_SYMBOL(ssb_admatch_base);
1415 u32 ssb_admatch_size(u32 adm)
1419 switch (adm & SSB_ADM_TYPE) {
1421 size = ((adm & SSB_ADM_SZ0) >> SSB_ADM_SZ0_SHIFT);
1424 SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
1425 size = ((adm & SSB_ADM_SZ1) >> SSB_ADM_SZ1_SHIFT);
1428 SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
1429 size = ((adm & SSB_ADM_SZ2) >> SSB_ADM_SZ2_SHIFT);
1434 size = (1 << (size + 1));
1438 EXPORT_SYMBOL(ssb_admatch_size);
1440 static int __init ssb_modinit(void)
1444 /* See the comment at the ssb_is_early_boot definition */
1445 ssb_is_early_boot = 0;
1446 err = bus_register(&ssb_bustype);
1450 /* Maybe we already registered some buses at early boot.
1451 * Check for this and attach them
1454 err = ssb_attach_queued_buses();
1457 bus_unregister(&ssb_bustype);
1461 err = b43_pci_ssb_bridge_init();
1463 ssb_err("Broadcom 43xx PCI-SSB-bridge initialization failed\n");
1464 /* don't fail SSB init because of this */
1467 err = ssb_gige_init();
1469 ssb_err("SSB Broadcom Gigabit Ethernet driver initialization failed\n");
1470 /* don't fail SSB init because of this */
1476 /* ssb must be initialized after PCI but before the ssb drivers.
1477 * That means we must use some initcall between subsys_initcall
1478 * and device_initcall. */
1479 fs_initcall(ssb_modinit);
1481 static void __exit ssb_modexit(void)
1484 b43_pci_ssb_bridge_exit();
1485 bus_unregister(&ssb_bustype);
1487 module_exit(ssb_modexit)