2 comedi/drivers/gsc_hpdi.c
3 This is a driver for the General Standards Corporation High
4 Speed Parallel Digital Interface rs485 boards.
6 Author: Frank Mori Hess <fmhess@users.sourceforge.net>
7 Copyright (C) 2003 Coherent Imaging Systems
9 COMEDI - Linux Control and Measurement Device Interface
10 Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
25 * Description: General Standards Corporation High
26 * Speed Parallel Digital Interface rs485 boards
27 * Author: Frank Mori Hess <fmhess@users.sourceforge.net>
28 * Status: only receive mode works, transmit not supported
29 * Updated: Thu, 01 Nov 2012 16:17:38 +0000
30 * Devices: [General Standards Corporation] PCI-HPDI32 (gsc_hpdi),
33 * Configuration options:
36 * Manual configuration of supported devices is not supported; they are
37 * configured automatically.
39 * There are some additional hpdi models available from GSC for which
40 * support could be added to this driver.
43 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
45 #include <linux/module.h>
46 #include <linux/pci.h>
47 #include <linux/delay.h>
48 #include <linux/interrupt.h>
50 #include "../comedidev.h"
53 #include "comedi_fc.h"
55 static void abort_dma(struct comedi_device *dev, unsigned int channel);
56 static int hpdi_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
57 static int hpdi_cmd_test(struct comedi_device *dev, struct comedi_subdevice *s,
58 struct comedi_cmd *cmd);
59 static int hpdi_cancel(struct comedi_device *dev, struct comedi_subdevice *s);
60 static irqreturn_t handle_interrupt(int irq, void *d);
61 static int dio_config_block_size(struct comedi_device *dev, unsigned int *data);
63 #define TIMER_BASE 50 /* 20MHz master clock */
64 #define DMA_BUFFER_SIZE 0x10000
65 #define NUM_DMA_BUFFERS 4
66 #define NUM_DMA_DESCRIPTORS 256
69 FIRMWARE_REV_REG = 0x0,
70 BOARD_CONTROL_REG = 0x4,
71 BOARD_STATUS_REG = 0x8,
72 TX_PROG_ALMOST_REG = 0xc,
73 RX_PROG_ALMOST_REG = 0x10,
76 TX_STATUS_COUNT_REG = 0x1c,
77 TX_LINE_VALID_COUNT_REG = 0x20,
78 TX_LINE_INVALID_COUNT_REG = 0x24,
79 RX_STATUS_COUNT_REG = 0x28,
80 RX_LINE_COUNT_REG = 0x2c,
81 INTERRUPT_CONTROL_REG = 0x30,
82 INTERRUPT_STATUS_REG = 0x34,
83 TX_CLOCK_DIVIDER_REG = 0x38,
84 TX_FIFO_SIZE_REG = 0x40,
85 RX_FIFO_SIZE_REG = 0x44,
86 TX_FIFO_WORDS_REG = 0x48,
87 RX_FIFO_WORDS_REG = 0x4c,
88 INTERRUPT_EDGE_LEVEL_REG = 0x50,
89 INTERRUPT_POLARITY_REG = 0x54,
94 enum firmware_revision_bits {
95 FEATURES_REG_PRESENT_BIT = 0x8000,
98 enum board_control_bits {
99 BOARD_RESET_BIT = 0x1, /* wait 10usec before accessing fifos */
100 TX_FIFO_RESET_BIT = 0x2,
101 RX_FIFO_RESET_BIT = 0x4,
102 TX_ENABLE_BIT = 0x10,
103 RX_ENABLE_BIT = 0x20,
104 DEMAND_DMA_DIRECTION_TX_BIT = 0x40,
105 /* for ch 0, ch 1 can only transmit (when present) */
106 LINE_VALID_ON_STATUS_VALID_BIT = 0x80,
108 CABLE_THROTTLE_ENABLE_BIT = 0x20,
109 TEST_MODE_ENABLE_BIT = 0x80000000,
112 enum board_status_bits {
113 COMMAND_LINE_STATUS_MASK = 0x7f,
114 TX_IN_PROGRESS_BIT = 0x80,
115 TX_NOT_EMPTY_BIT = 0x100,
116 TX_NOT_ALMOST_EMPTY_BIT = 0x200,
117 TX_NOT_ALMOST_FULL_BIT = 0x400,
118 TX_NOT_FULL_BIT = 0x800,
119 RX_NOT_EMPTY_BIT = 0x1000,
120 RX_NOT_ALMOST_EMPTY_BIT = 0x2000,
121 RX_NOT_ALMOST_FULL_BIT = 0x4000,
122 RX_NOT_FULL_BIT = 0x8000,
123 BOARD_JUMPER0_INSTALLED_BIT = 0x10000,
124 BOARD_JUMPER1_INSTALLED_BIT = 0x20000,
125 TX_OVERRUN_BIT = 0x200000,
126 RX_UNDERRUN_BIT = 0x400000,
127 RX_OVERRUN_BIT = 0x800000,
130 static uint32_t almost_full_bits(unsigned int num_words)
132 /* XXX need to add or subtract one? */
133 return (num_words << 16) & 0xff0000;
136 static uint32_t almost_empty_bits(unsigned int num_words)
138 return num_words & 0xffff;
142 FIFO_SIZE_PRESENT_BIT = 0x1,
143 FIFO_WORDS_PRESENT_BIT = 0x2,
144 LEVEL_EDGE_INTERRUPTS_PRESENT_BIT = 0x4,
145 GPIO_SUPPORTED_BIT = 0x8,
146 PLX_DMA_CH1_SUPPORTED_BIT = 0x10,
147 OVERRUN_UNDERRUN_SUPPORTED_BIT = 0x20,
150 enum interrupt_sources {
151 FRAME_VALID_START_INTR = 0,
152 FRAME_VALID_END_INTR = 1,
153 TX_FIFO_EMPTY_INTR = 8,
154 TX_FIFO_ALMOST_EMPTY_INTR = 9,
155 TX_FIFO_ALMOST_FULL_INTR = 10,
156 TX_FIFO_FULL_INTR = 11,
158 RX_ALMOST_EMPTY_INTR = 13,
159 RX_ALMOST_FULL_INTR = 14,
163 static uint32_t intr_bit(int interrupt_source)
165 return 0x1 << interrupt_source;
168 static unsigned int fifo_size(uint32_t fifo_size_bits)
170 return fifo_size_bits & 0xfffff;
174 const char *name; /* board name */
175 int device_id; /* pci device id */
176 int subdevice_id; /* pci subdevice id */
179 static const struct hpdi_board hpdi_boards[] = {
181 .name = "pci-hpdi32",
182 .device_id = PCI_DEVICE_ID_PLX_9080,
183 .subdevice_id = 0x2400,
187 .name = "pxi-hpdi32",
189 .subdevice_id = 0x2705,
194 struct hpdi_private {
195 /* base addresses (ioremapped) */
196 void __iomem *plx9080_iobase;
197 void __iomem *hpdi_iobase;
198 uint32_t *dio_buffer[NUM_DMA_BUFFERS]; /* dma buffers */
199 /* physical addresses of dma buffers */
200 dma_addr_t dio_buffer_phys_addr[NUM_DMA_BUFFERS];
201 /* array of dma descriptors read by plx9080, allocated to get proper
203 struct plx_dma_desc *dma_desc;
204 /* physical address of dma descriptor array */
205 dma_addr_t dma_desc_phys_addr;
206 unsigned int num_dma_descriptors;
207 /* pointer to start of buffers indexed by descriptor */
208 uint32_t *desc_dio_buffer[NUM_DMA_DESCRIPTORS];
209 /* index of the dma descriptor that is currently being used */
210 volatile unsigned int dma_desc_index;
211 unsigned int tx_fifo_size;
212 unsigned int rx_fifo_size;
213 volatile unsigned long dio_count;
214 /* software copies of values written to hpdi registers */
215 volatile uint32_t bits[24];
216 /* number of bytes at which to generate COMEDI_CB_BLOCK events */
217 volatile unsigned int block_size;
220 static int dio_config_insn(struct comedi_device *dev,
221 struct comedi_subdevice *s,
222 struct comedi_insn *insn,
228 case INSN_CONFIG_BLOCK_SIZE:
229 return dio_config_block_size(dev, data);
231 ret = comedi_dio_insn_config(dev, s, insn, data, 0xffffffff);
240 static void disable_plx_interrupts(struct comedi_device *dev)
242 struct hpdi_private *devpriv = dev->private;
244 writel(0, devpriv->plx9080_iobase + PLX_INTRCS_REG);
247 /* initialize plx9080 chip */
248 static void init_plx9080(struct comedi_device *dev)
250 struct hpdi_private *devpriv = dev->private;
252 void __iomem *plx_iobase = devpriv->plx9080_iobase;
255 bits = BIGEND_DMA0 | BIGEND_DMA1;
259 writel(bits, devpriv->plx9080_iobase + PLX_BIGEND_REG);
261 disable_plx_interrupts(dev);
266 /* configure dma0 mode */
268 /* enable ready input */
269 bits |= PLX_DMA_EN_READYIN_BIT;
270 /* enable dma chaining */
271 bits |= PLX_EN_CHAIN_BIT;
272 /* enable interrupt on dma done
273 * (probably don't need this, since chain never finishes) */
274 bits |= PLX_EN_DMA_DONE_INTR_BIT;
275 /* don't increment local address during transfers
276 * (we are transferring from a fixed fifo register) */
277 bits |= PLX_LOCAL_ADDR_CONST_BIT;
278 /* route dma interrupt to pci bus */
279 bits |= PLX_DMA_INTR_PCI_BIT;
280 /* enable demand mode */
281 bits |= PLX_DEMAND_MODE_BIT;
282 /* enable local burst mode */
283 bits |= PLX_DMA_LOCAL_BURST_EN_BIT;
284 bits |= PLX_LOCAL_BUS_32_WIDE_BITS;
285 writel(bits, plx_iobase + PLX_DMA0_MODE_REG);
288 /* Allocate and initialize the subdevice structures.
290 static int setup_subdevices(struct comedi_device *dev)
292 struct comedi_subdevice *s;
295 ret = comedi_alloc_subdevices(dev, 1);
299 s = &dev->subdevices[0];
300 /* analog input subdevice */
301 dev->read_subdev = s;
302 /* dev->write_subdev = s; */
303 s->type = COMEDI_SUBD_DIO;
305 SDF_READABLE | SDF_WRITEABLE | SDF_LSAMPL | SDF_CMD_READ;
307 s->len_chanlist = 32;
309 s->range_table = &range_digital;
310 s->insn_config = dio_config_insn;
311 s->do_cmd = hpdi_cmd;
312 s->do_cmdtest = hpdi_cmd_test;
313 s->cancel = hpdi_cancel;
318 static int init_hpdi(struct comedi_device *dev)
320 struct hpdi_private *devpriv = dev->private;
321 uint32_t plx_intcsr_bits;
323 writel(BOARD_RESET_BIT, devpriv->hpdi_iobase + BOARD_CONTROL_REG);
326 writel(almost_empty_bits(32) | almost_full_bits(32),
327 devpriv->hpdi_iobase + RX_PROG_ALMOST_REG);
328 writel(almost_empty_bits(32) | almost_full_bits(32),
329 devpriv->hpdi_iobase + TX_PROG_ALMOST_REG);
331 devpriv->tx_fifo_size = fifo_size(readl(devpriv->hpdi_iobase +
333 devpriv->rx_fifo_size = fifo_size(readl(devpriv->hpdi_iobase +
336 writel(0, devpriv->hpdi_iobase + INTERRUPT_CONTROL_REG);
338 /* enable interrupts */
340 ICS_AERR | ICS_PERR | ICS_PIE | ICS_PLIE | ICS_PAIE | ICS_LIE |
342 writel(plx_intcsr_bits, devpriv->plx9080_iobase + PLX_INTRCS_REG);
347 /* setup dma descriptors so a link completes every 'transfer_size' bytes */
348 static int setup_dma_descriptors(struct comedi_device *dev,
349 unsigned int transfer_size)
351 struct hpdi_private *devpriv = dev->private;
352 unsigned int buffer_index, buffer_offset;
353 uint32_t next_bits = PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT |
354 PLX_XFER_LOCAL_TO_PCI;
357 if (transfer_size > DMA_BUFFER_SIZE)
358 transfer_size = DMA_BUFFER_SIZE;
359 transfer_size -= transfer_size % sizeof(uint32_t);
360 if (transfer_size == 0)
365 for (i = 0; i < NUM_DMA_DESCRIPTORS &&
366 buffer_index < NUM_DMA_BUFFERS; i++) {
367 devpriv->dma_desc[i].pci_start_addr =
368 cpu_to_le32(devpriv->dio_buffer_phys_addr[buffer_index] +
370 devpriv->dma_desc[i].local_start_addr = cpu_to_le32(FIFO_REG);
371 devpriv->dma_desc[i].transfer_size =
372 cpu_to_le32(transfer_size);
373 devpriv->dma_desc[i].next =
374 cpu_to_le32((devpriv->dma_desc_phys_addr + (i +
376 sizeof(devpriv->dma_desc[0])) | next_bits);
378 devpriv->desc_dio_buffer[i] =
379 devpriv->dio_buffer[buffer_index] +
380 (buffer_offset / sizeof(uint32_t));
382 buffer_offset += transfer_size;
383 if (transfer_size + buffer_offset > DMA_BUFFER_SIZE) {
388 devpriv->num_dma_descriptors = i;
389 /* fix last descriptor to point back to first */
390 devpriv->dma_desc[i - 1].next =
391 cpu_to_le32(devpriv->dma_desc_phys_addr | next_bits);
393 devpriv->block_size = transfer_size;
395 return transfer_size;
398 static const struct hpdi_board *hpdi_find_board(struct pci_dev *pcidev)
402 for (i = 0; i < ARRAY_SIZE(hpdi_boards); i++)
403 if (pcidev->device == hpdi_boards[i].device_id &&
404 pcidev->subsystem_device == hpdi_boards[i].subdevice_id)
405 return &hpdi_boards[i];
409 static int hpdi_auto_attach(struct comedi_device *dev,
410 unsigned long context_unused)
412 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
413 const struct hpdi_board *thisboard;
414 struct hpdi_private *devpriv;
418 thisboard = hpdi_find_board(pcidev);
420 dev_err(dev->class_dev, "gsc_hpdi: pci %s not supported\n",
424 dev->board_ptr = thisboard;
425 dev->board_name = thisboard->name;
427 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
431 retval = comedi_pci_enable(dev);
434 pci_set_master(pcidev);
436 devpriv->plx9080_iobase = pci_ioremap_bar(pcidev, 0);
437 devpriv->hpdi_iobase = pci_ioremap_bar(pcidev, 2);
438 if (!devpriv->plx9080_iobase || !devpriv->hpdi_iobase) {
439 dev_warn(dev->class_dev, "failed to remap io memory\n");
446 if (request_irq(pcidev->irq, handle_interrupt, IRQF_SHARED,
447 dev->board_name, dev)) {
448 dev_warn(dev->class_dev,
449 "unable to allocate irq %u\n", pcidev->irq);
452 dev->irq = pcidev->irq;
454 dev_dbg(dev->class_dev, " irq %u\n", dev->irq);
456 /* allocate pci dma buffers */
457 for (i = 0; i < NUM_DMA_BUFFERS; i++) {
458 devpriv->dio_buffer[i] =
459 pci_alloc_consistent(pcidev, DMA_BUFFER_SIZE,
460 &devpriv->dio_buffer_phys_addr[i]);
462 /* allocate dma descriptors */
463 devpriv->dma_desc = pci_alloc_consistent(pcidev,
464 sizeof(struct plx_dma_desc) *
466 &devpriv->dma_desc_phys_addr);
467 if (devpriv->dma_desc_phys_addr & 0xf) {
468 dev_warn(dev->class_dev,
469 " dma descriptors not quad-word aligned (bug)\n");
473 retval = setup_dma_descriptors(dev, 0x1000);
477 retval = setup_subdevices(dev);
481 return init_hpdi(dev);
484 static void hpdi_detach(struct comedi_device *dev)
486 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
487 struct hpdi_private *devpriv = dev->private;
491 free_irq(dev->irq, dev);
493 if (devpriv->plx9080_iobase) {
494 disable_plx_interrupts(dev);
495 iounmap(devpriv->plx9080_iobase);
497 if (devpriv->hpdi_iobase)
498 iounmap(devpriv->hpdi_iobase);
499 /* free pci dma buffers */
500 for (i = 0; i < NUM_DMA_BUFFERS; i++) {
501 if (devpriv->dio_buffer[i])
502 pci_free_consistent(pcidev,
504 devpriv->dio_buffer[i],
506 dio_buffer_phys_addr[i]);
508 /* free dma descriptors */
509 if (devpriv->dma_desc)
510 pci_free_consistent(pcidev,
511 sizeof(struct plx_dma_desc) *
514 devpriv->dma_desc_phys_addr);
516 comedi_pci_disable(dev);
519 static int dio_config_block_size(struct comedi_device *dev, unsigned int *data)
521 unsigned int requested_block_size;
524 requested_block_size = data[1];
526 retval = setup_dma_descriptors(dev, requested_block_size);
535 static int di_cmd_test(struct comedi_device *dev, struct comedi_subdevice *s,
536 struct comedi_cmd *cmd)
541 /* Step 1 : check if triggers are trivially valid */
543 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW);
544 err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
545 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
546 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
547 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
552 /* Step 2a : make sure trigger sources are unique */
554 err |= cfc_check_trigger_is_unique(cmd->stop_src);
556 /* Step 2b : and mutually compatible */
561 /* Step 3: check if arguments are trivially valid */
563 if (!cmd->chanlist_len) {
564 cmd->chanlist_len = 32;
567 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
569 switch (cmd->stop_src) {
571 err |= cfc_check_trigger_arg_min(&cmd->stop_arg, 1);
574 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
583 /* step 4: fix up any arguments */
591 for (i = 1; i < cmd->chanlist_len; i++) {
592 if (CR_CHAN(cmd->chanlist[i]) != i) {
593 /* XXX could support 8 or 16 channels */
595 "chanlist must be ch 0 to 31 in order");
607 static int hpdi_cmd_test(struct comedi_device *dev, struct comedi_subdevice *s,
608 struct comedi_cmd *cmd)
613 return di_cmd_test(dev, s, cmd);
616 static inline void hpdi_writel(struct comedi_device *dev, uint32_t bits,
619 struct hpdi_private *devpriv = dev->private;
621 writel(bits | devpriv->bits[offset / sizeof(uint32_t)],
622 devpriv->hpdi_iobase + offset);
625 static int di_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
627 struct hpdi_private *devpriv = dev->private;
630 struct comedi_async *async = s->async;
631 struct comedi_cmd *cmd = &async->cmd;
633 hpdi_writel(dev, RX_FIFO_RESET_BIT, BOARD_CONTROL_REG);
637 devpriv->dma_desc_index = 0;
639 /* These register are supposedly unused during chained dma,
640 * but I have found that left over values from last operation
641 * occasionally cause problems with transfer of first dma
642 * block. Initializing them to zero seems to fix the problem. */
643 writel(0, devpriv->plx9080_iobase + PLX_DMA0_TRANSFER_SIZE_REG);
644 writel(0, devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG);
645 writel(0, devpriv->plx9080_iobase + PLX_DMA0_LOCAL_ADDRESS_REG);
646 /* give location of first dma descriptor */
648 devpriv->dma_desc_phys_addr | PLX_DESC_IN_PCI_BIT |
649 PLX_INTR_TERM_COUNT | PLX_XFER_LOCAL_TO_PCI;
650 writel(bits, devpriv->plx9080_iobase + PLX_DMA0_DESCRIPTOR_REG);
652 /* spinlock for plx dma control/status reg */
653 spin_lock_irqsave(&dev->spinlock, flags);
654 /* enable dma transfer */
655 writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT | PLX_CLEAR_DMA_INTR_BIT,
656 devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
657 spin_unlock_irqrestore(&dev->spinlock, flags);
659 if (cmd->stop_src == TRIG_COUNT)
660 devpriv->dio_count = cmd->stop_arg;
662 devpriv->dio_count = 1;
664 /* clear over/under run status flags */
665 writel(RX_UNDERRUN_BIT | RX_OVERRUN_BIT,
666 devpriv->hpdi_iobase + BOARD_STATUS_REG);
667 /* enable interrupts */
668 writel(intr_bit(RX_FULL_INTR),
669 devpriv->hpdi_iobase + INTERRUPT_CONTROL_REG);
671 hpdi_writel(dev, RX_ENABLE_BIT, BOARD_CONTROL_REG);
676 static int hpdi_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
681 return di_cmd(dev, s);
684 static void drain_dma_buffers(struct comedi_device *dev, unsigned int channel)
686 struct hpdi_private *devpriv = dev->private;
687 struct comedi_async *async = dev->read_subdev->async;
688 uint32_t next_transfer_addr;
691 void __iomem *pci_addr_reg;
695 devpriv->plx9080_iobase + PLX_DMA1_PCI_ADDRESS_REG;
698 devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG;
700 /* loop until we have read all the full buffers */
702 for (next_transfer_addr = readl(pci_addr_reg);
703 (next_transfer_addr <
704 le32_to_cpu(devpriv->dma_desc[devpriv->dma_desc_index].
706 || next_transfer_addr >=
707 le32_to_cpu(devpriv->dma_desc[devpriv->dma_desc_index].
708 pci_start_addr) + devpriv->block_size)
709 && j < devpriv->num_dma_descriptors; j++) {
710 /* transfer data from dma buffer to comedi buffer */
711 num_samples = devpriv->block_size / sizeof(uint32_t);
712 if (async->cmd.stop_src == TRIG_COUNT) {
713 if (num_samples > devpriv->dio_count)
714 num_samples = devpriv->dio_count;
715 devpriv->dio_count -= num_samples;
717 cfc_write_array_to_buffer(dev->read_subdev,
718 devpriv->desc_dio_buffer[devpriv->
720 num_samples * sizeof(uint32_t));
721 devpriv->dma_desc_index++;
722 devpriv->dma_desc_index %= devpriv->num_dma_descriptors;
724 /* XXX check for buffer overrun somehow */
727 static irqreturn_t handle_interrupt(int irq, void *d)
729 struct comedi_device *dev = d;
730 struct hpdi_private *devpriv = dev->private;
731 struct comedi_subdevice *s = dev->read_subdev;
732 struct comedi_async *async = s->async;
733 uint32_t hpdi_intr_status, hpdi_board_status;
736 uint8_t dma0_status, dma1_status;
742 plx_status = readl(devpriv->plx9080_iobase + PLX_INTRCS_REG);
743 if ((plx_status & (ICS_DMA0_A | ICS_DMA1_A | ICS_LIA)) == 0)
746 hpdi_intr_status = readl(devpriv->hpdi_iobase + INTERRUPT_STATUS_REG);
747 hpdi_board_status = readl(devpriv->hpdi_iobase + BOARD_STATUS_REG);
751 if (hpdi_intr_status) {
752 writel(hpdi_intr_status,
753 devpriv->hpdi_iobase + INTERRUPT_STATUS_REG);
755 /* spin lock makes sure no one else changes plx dma control reg */
756 spin_lock_irqsave(&dev->spinlock, flags);
757 dma0_status = readb(devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
758 if (plx_status & ICS_DMA0_A) { /* dma chan 0 interrupt */
759 writeb((dma0_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
760 devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
762 if (dma0_status & PLX_DMA_EN_BIT)
763 drain_dma_buffers(dev, 0);
765 spin_unlock_irqrestore(&dev->spinlock, flags);
767 /* spin lock makes sure no one else changes plx dma control reg */
768 spin_lock_irqsave(&dev->spinlock, flags);
769 dma1_status = readb(devpriv->plx9080_iobase + PLX_DMA1_CS_REG);
770 if (plx_status & ICS_DMA1_A) { /* XXX *//* dma chan 1 interrupt */
771 writeb((dma1_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
772 devpriv->plx9080_iobase + PLX_DMA1_CS_REG);
774 spin_unlock_irqrestore(&dev->spinlock, flags);
776 /* clear possible plx9080 interrupt sources */
777 if (plx_status & ICS_LDIA) { /* clear local doorbell interrupt */
778 plx_bits = readl(devpriv->plx9080_iobase + PLX_DBR_OUT_REG);
779 writel(plx_bits, devpriv->plx9080_iobase + PLX_DBR_OUT_REG);
782 if (hpdi_board_status & RX_OVERRUN_BIT) {
783 comedi_error(dev, "rx fifo overrun");
784 async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
787 if (hpdi_board_status & RX_UNDERRUN_BIT) {
788 comedi_error(dev, "rx fifo underrun");
789 async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
792 if (devpriv->dio_count == 0)
793 async->events |= COMEDI_CB_EOA;
795 cfc_handle_events(dev, s);
800 static void abort_dma(struct comedi_device *dev, unsigned int channel)
802 struct hpdi_private *devpriv = dev->private;
805 /* spinlock for plx dma control/status reg */
806 spin_lock_irqsave(&dev->spinlock, flags);
808 plx9080_abort_dma(devpriv->plx9080_iobase, channel);
810 spin_unlock_irqrestore(&dev->spinlock, flags);
813 static int hpdi_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
815 struct hpdi_private *devpriv = dev->private;
817 hpdi_writel(dev, 0, BOARD_CONTROL_REG);
819 writel(0, devpriv->hpdi_iobase + INTERRUPT_CONTROL_REG);
826 static struct comedi_driver gsc_hpdi_driver = {
827 .driver_name = "gsc_hpdi",
828 .module = THIS_MODULE,
829 .auto_attach = hpdi_auto_attach,
830 .detach = hpdi_detach,
833 static int gsc_hpdi_pci_probe(struct pci_dev *dev,
834 const struct pci_device_id *id)
836 return comedi_pci_auto_config(dev, &gsc_hpdi_driver, id->driver_data);
839 static DEFINE_PCI_DEVICE_TABLE(gsc_hpdi_pci_table) = {
840 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9080, PCI_VENDOR_ID_PLX,
844 MODULE_DEVICE_TABLE(pci, gsc_hpdi_pci_table);
846 static struct pci_driver gsc_hpdi_pci_driver = {
848 .id_table = gsc_hpdi_pci_table,
849 .probe = gsc_hpdi_pci_probe,
850 .remove = comedi_pci_auto_unconfig,
852 module_comedi_pci_driver(gsc_hpdi_driver, gsc_hpdi_pci_driver);
854 MODULE_AUTHOR("Comedi http://www.comedi.org");
855 MODULE_DESCRIPTION("Comedi low-level driver");
856 MODULE_LICENSE("GPL");