2 comedi/drivers/me4000.c
3 Source code for the Meilhaus ME-4000 board family.
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 2000 David A. Schleef <ds@schleef.org>
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
20 Description: Meilhaus ME-4000 series boards
21 Devices: [Meilhaus] ME-4650 (me4000), ME-4670i, ME-4680, ME-4680i, ME-4680is
22 Author: gg (Guenter Gebhardt <g.gebhardt@meilhaus.com>)
23 Updated: Mon, 18 Mar 2002 15:34:01 -0800
24 Status: broken (no support for loading firmware)
33 Configuration Options: not applicable, uses PCI auto config
35 The firmware required by these boards is available in the
36 comedi_nonfree_firmware tarball available from
37 http://www.comedi.org. However, the driver's support for
38 loading the firmware through comedi_config is currently
43 #include <linux/module.h>
44 #include <linux/pci.h>
45 #include <linux/delay.h>
46 #include <linux/interrupt.h>
47 #include <linux/list.h>
48 #include <linux/spinlock.h>
50 #include "../comedidev.h"
52 #include "comedi_fc.h"
57 /* file removed due to GPL incompatibility */
58 #include "me4000_fw.h"
62 * ME4000 Register map and bit defines
64 #define ME4000_AO_CHAN(x) ((x) * 0x18)
66 #define ME4000_AO_CTRL_REG(x) (0x00 + ME4000_AO_CHAN(x))
67 #define ME4000_AO_CTRL_BIT_MODE_0 (1 << 0)
68 #define ME4000_AO_CTRL_BIT_MODE_1 (1 << 1)
69 #define ME4000_AO_CTRL_MASK_MODE (3 << 0)
70 #define ME4000_AO_CTRL_BIT_STOP (1 << 2)
71 #define ME4000_AO_CTRL_BIT_ENABLE_FIFO (1 << 3)
72 #define ME4000_AO_CTRL_BIT_ENABLE_EX_TRIG (1 << 4)
73 #define ME4000_AO_CTRL_BIT_EX_TRIG_EDGE (1 << 5)
74 #define ME4000_AO_CTRL_BIT_IMMEDIATE_STOP (1 << 7)
75 #define ME4000_AO_CTRL_BIT_ENABLE_DO (1 << 8)
76 #define ME4000_AO_CTRL_BIT_ENABLE_IRQ (1 << 9)
77 #define ME4000_AO_CTRL_BIT_RESET_IRQ (1 << 10)
78 #define ME4000_AO_STATUS_REG(x) (0x04 + ME4000_AO_CHAN(x))
79 #define ME4000_AO_STATUS_BIT_FSM (1 << 0)
80 #define ME4000_AO_STATUS_BIT_FF (1 << 1)
81 #define ME4000_AO_STATUS_BIT_HF (1 << 2)
82 #define ME4000_AO_STATUS_BIT_EF (1 << 3)
83 #define ME4000_AO_FIFO_REG(x) (0x08 + ME4000_AO_CHAN(x))
84 #define ME4000_AO_SINGLE_REG(x) (0x0c + ME4000_AO_CHAN(x))
85 #define ME4000_AO_TIMER_REG(x) (0x10 + ME4000_AO_CHAN(x))
86 #define ME4000_AI_CTRL_REG 0x74
87 #define ME4000_AI_STATUS_REG 0x74
88 #define ME4000_AI_CTRL_BIT_MODE_0 (1 << 0)
89 #define ME4000_AI_CTRL_BIT_MODE_1 (1 << 1)
90 #define ME4000_AI_CTRL_BIT_MODE_2 (1 << 2)
91 #define ME4000_AI_CTRL_BIT_SAMPLE_HOLD (1 << 3)
92 #define ME4000_AI_CTRL_BIT_IMMEDIATE_STOP (1 << 4)
93 #define ME4000_AI_CTRL_BIT_STOP (1 << 5)
94 #define ME4000_AI_CTRL_BIT_CHANNEL_FIFO (1 << 6)
95 #define ME4000_AI_CTRL_BIT_DATA_FIFO (1 << 7)
96 #define ME4000_AI_CTRL_BIT_FULLSCALE (1 << 8)
97 #define ME4000_AI_CTRL_BIT_OFFSET (1 << 9)
98 #define ME4000_AI_CTRL_BIT_EX_TRIG_ANALOG (1 << 10)
99 #define ME4000_AI_CTRL_BIT_EX_TRIG (1 << 11)
100 #define ME4000_AI_CTRL_BIT_EX_TRIG_FALLING (1 << 12)
101 #define ME4000_AI_CTRL_BIT_EX_IRQ (1 << 13)
102 #define ME4000_AI_CTRL_BIT_EX_IRQ_RESET (1 << 14)
103 #define ME4000_AI_CTRL_BIT_LE_IRQ (1 << 15)
104 #define ME4000_AI_CTRL_BIT_LE_IRQ_RESET (1 << 16)
105 #define ME4000_AI_CTRL_BIT_HF_IRQ (1 << 17)
106 #define ME4000_AI_CTRL_BIT_HF_IRQ_RESET (1 << 18)
107 #define ME4000_AI_CTRL_BIT_SC_IRQ (1 << 19)
108 #define ME4000_AI_CTRL_BIT_SC_IRQ_RESET (1 << 20)
109 #define ME4000_AI_CTRL_BIT_SC_RELOAD (1 << 21)
110 #define ME4000_AI_STATUS_BIT_EF_CHANNEL (1 << 22)
111 #define ME4000_AI_STATUS_BIT_HF_CHANNEL (1 << 23)
112 #define ME4000_AI_STATUS_BIT_FF_CHANNEL (1 << 24)
113 #define ME4000_AI_STATUS_BIT_EF_DATA (1 << 25)
114 #define ME4000_AI_STATUS_BIT_HF_DATA (1 << 26)
115 #define ME4000_AI_STATUS_BIT_FF_DATA (1 << 27)
116 #define ME4000_AI_STATUS_BIT_LE (1 << 28)
117 #define ME4000_AI_STATUS_BIT_FSM (1 << 29)
118 #define ME4000_AI_CTRL_BIT_EX_TRIG_BOTH (1 << 31)
119 #define ME4000_AI_CHANNEL_LIST_REG 0x78
120 #define ME4000_AI_LIST_INPUT_SINGLE_ENDED (0 << 5)
121 #define ME4000_AI_LIST_INPUT_DIFFERENTIAL (1 << 5)
122 #define ME4000_AI_LIST_RANGE_BIPOLAR_10 (0 << 6)
123 #define ME4000_AI_LIST_RANGE_BIPOLAR_2_5 (1 << 6)
124 #define ME4000_AI_LIST_RANGE_UNIPOLAR_10 (2 << 6)
125 #define ME4000_AI_LIST_RANGE_UNIPOLAR_2_5 (3 << 6)
126 #define ME4000_AI_LIST_LAST_ENTRY (1 << 8)
127 #define ME4000_AI_DATA_REG 0x7c
128 #define ME4000_AI_CHAN_TIMER_REG 0x80
129 #define ME4000_AI_CHAN_PRE_TIMER_REG 0x84
130 #define ME4000_AI_SCAN_TIMER_LOW_REG 0x88
131 #define ME4000_AI_SCAN_TIMER_HIGH_REG 0x8c
132 #define ME4000_AI_SCAN_PRE_TIMER_LOW_REG 0x90
133 #define ME4000_AI_SCAN_PRE_TIMER_HIGH_REG 0x94
134 #define ME4000_AI_START_REG 0x98
135 #define ME4000_IRQ_STATUS_REG 0x9c
136 #define ME4000_IRQ_STATUS_BIT_EX (1 << 0)
137 #define ME4000_IRQ_STATUS_BIT_LE (1 << 1)
138 #define ME4000_IRQ_STATUS_BIT_AI_HF (1 << 2)
139 #define ME4000_IRQ_STATUS_BIT_AO_0_HF (1 << 3)
140 #define ME4000_IRQ_STATUS_BIT_AO_1_HF (1 << 4)
141 #define ME4000_IRQ_STATUS_BIT_AO_2_HF (1 << 5)
142 #define ME4000_IRQ_STATUS_BIT_AO_3_HF (1 << 6)
143 #define ME4000_IRQ_STATUS_BIT_SC (1 << 7)
144 #define ME4000_DIO_PORT_0_REG 0xa0
145 #define ME4000_DIO_PORT_1_REG 0xa4
146 #define ME4000_DIO_PORT_2_REG 0xa8
147 #define ME4000_DIO_PORT_3_REG 0xac
148 #define ME4000_DIO_DIR_REG 0xb0
149 #define ME4000_AO_LOADSETREG_XX 0xb4
150 #define ME4000_DIO_CTRL_REG 0xb8
151 #define ME4000_DIO_CTRL_BIT_MODE_0 (1 << 0)
152 #define ME4000_DIO_CTRL_BIT_MODE_1 (1 << 1)
153 #define ME4000_DIO_CTRL_BIT_MODE_2 (1 << 2)
154 #define ME4000_DIO_CTRL_BIT_MODE_3 (1 << 3)
155 #define ME4000_DIO_CTRL_BIT_MODE_4 (1 << 4)
156 #define ME4000_DIO_CTRL_BIT_MODE_5 (1 << 5)
157 #define ME4000_DIO_CTRL_BIT_MODE_6 (1 << 6)
158 #define ME4000_DIO_CTRL_BIT_MODE_7 (1 << 7)
159 #define ME4000_DIO_CTRL_BIT_FUNCTION_0 (1 << 8)
160 #define ME4000_DIO_CTRL_BIT_FUNCTION_1 (1 << 9)
161 #define ME4000_DIO_CTRL_BIT_FIFO_HIGH_0 (1 << 10)
162 #define ME4000_DIO_CTRL_BIT_FIFO_HIGH_1 (1 << 11)
163 #define ME4000_DIO_CTRL_BIT_FIFO_HIGH_2 (1 << 12)
164 #define ME4000_DIO_CTRL_BIT_FIFO_HIGH_3 (1 << 13)
165 #define ME4000_AO_DEMUX_ADJUST_REG 0xbc
166 #define ME4000_AO_DEMUX_ADJUST_VALUE 0x4c
167 #define ME4000_AI_SAMPLE_COUNTER_REG 0xc0
169 #define ME4000_AI_FIFO_COUNT 2048
171 #define ME4000_AI_MIN_TICKS 66
172 #define ME4000_AI_MIN_SAMPLE_TIME 2000
173 #define ME4000_AI_BASE_FREQUENCY (unsigned int) 33E6
175 #define ME4000_AI_CHANNEL_LIST_COUNT 1024
178 unsigned long plx_regbase;
179 unsigned long timer_regbase;
181 unsigned int ao_readback[4];
184 enum me4000_boardid {
200 struct me4000_board {
212 static const struct me4000_board me4000_boards[] = {
330 static const struct comedi_lrange me4000_ai_range = {
340 #define FIRMWARE_NOT_AVAILABLE 1
341 #if FIRMWARE_NOT_AVAILABLE
342 extern unsigned char *xilinx_firm;
345 static int xilinx_download(struct comedi_device *dev)
347 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
348 struct me4000_info *info = dev->private;
349 unsigned long xilinx_iobase = pci_resource_start(pcidev, 5);
351 wait_queue_head_t queue;
359 init_waitqueue_head(&queue);
362 * Set PLX local interrupt 2 polarity to high.
363 * Interrupt is thrown by init pin of xilinx.
365 outl(PLX9052_INTCSR_LI2POL, info->plx_regbase + PLX9052_INTCSR);
367 /* Set /CS and /WRITE of the Xilinx */
368 value = inl(info->plx_regbase + PLX9052_CNTRL);
369 value |= PLX9052_CNTRL_UIO2_DATA;
370 outl(value, info->plx_regbase + PLX9052_CNTRL);
372 /* Init Xilinx with CS1 */
373 inb(xilinx_iobase + 0xC8);
375 /* Wait until /INIT pin is set */
377 intcsr = inl(info->plx_regbase + PLX9052_INTCSR);
378 if (!(intcsr & PLX9052_INTCSR_LI2STAT)) {
379 dev_err(dev->class_dev, "Can't init Xilinx\n");
383 /* Reset /CS and /WRITE of the Xilinx */
384 value = inl(info->plx_regbase + PLX9052_CNTRL);
385 value &= ~PLX9052_CNTRL_UIO2_DATA;
386 outl(value, info->plx_regbase + PLX9052_CNTRL);
387 if (FIRMWARE_NOT_AVAILABLE) {
388 dev_err(dev->class_dev,
389 "xilinx firmware unavailable due to licensing, aborting");
392 /* Download Xilinx firmware */
393 size = (xilinx_firm[0] << 24) + (xilinx_firm[1] << 16) +
394 (xilinx_firm[2] << 8) + xilinx_firm[3];
397 for (idx = 0; idx < size; idx++) {
398 outb(xilinx_firm[16 + idx], xilinx_iobase);
401 /* Check if BUSY flag is low */
402 if (inl(info->plx_regbase + PLX9052_CNTRL) & PLX9052_CNTRL_UIO1_DATA) {
403 dev_err(dev->class_dev,
404 "Xilinx is still busy (idx = %d)\n",
411 /* If done flag is high download was successful */
412 if (inl(info->plx_regbase + PLX9052_CNTRL) & PLX9052_CNTRL_UIO0_DATA) {
414 dev_err(dev->class_dev, "DONE flag is not set\n");
415 dev_err(dev->class_dev, "Download not successful\n");
419 /* Set /CS and /WRITE */
420 value = inl(info->plx_regbase + PLX9052_CNTRL);
421 value |= PLX9052_CNTRL_UIO2_DATA;
422 outl(value, info->plx_regbase + PLX9052_CNTRL);
427 static void me4000_reset(struct comedi_device *dev)
429 struct me4000_info *info = dev->private;
433 /* Make a hardware reset */
434 val = inl(info->plx_regbase + PLX9052_CNTRL);
435 val |= PLX9052_CNTRL_PCI_RESET;
436 outl(val, info->plx_regbase + PLX9052_CNTRL);
437 val &= ~PLX9052_CNTRL_PCI_RESET;
438 outl(val , info->plx_regbase + PLX9052_CNTRL);
440 /* 0x8000 to the DACs means an output voltage of 0V */
441 for (chan = 0; chan < 4; chan++)
442 outl(0x8000, dev->iobase + ME4000_AO_SINGLE_REG(chan));
444 /* Set both stop bits in the analog input control register */
445 outl(ME4000_AI_CTRL_BIT_IMMEDIATE_STOP | ME4000_AI_CTRL_BIT_STOP,
446 dev->iobase + ME4000_AI_CTRL_REG);
448 /* Set both stop bits in the analog output control register */
449 val = ME4000_AO_CTRL_BIT_IMMEDIATE_STOP | ME4000_AO_CTRL_BIT_STOP;
450 for (chan = 0; chan < 4; chan++)
451 outl(val, dev->iobase + ME4000_AO_CTRL_REG(chan));
453 /* Enable interrupts on the PLX */
454 outl(PLX9052_INTCSR_LI1ENAB |
455 PLX9052_INTCSR_LI1POL |
456 PLX9052_INTCSR_PCIENAB, info->plx_regbase + PLX9052_INTCSR);
458 /* Set the adustment register for AO demux */
459 outl(ME4000_AO_DEMUX_ADJUST_VALUE,
460 dev->iobase + ME4000_AO_DEMUX_ADJUST_REG);
463 * Set digital I/O direction for port 0
464 * to output on isolated versions
466 if (!(inl(dev->iobase + ME4000_DIO_DIR_REG) & 0x1))
467 outl(0x1, dev->iobase + ME4000_DIO_CTRL_REG);
470 /*=============================================================================
472 ===========================================================================*/
474 static int me4000_ai_insn_read(struct comedi_device *dev,
475 struct comedi_subdevice *subdevice,
476 struct comedi_insn *insn, unsigned int *data)
478 const struct me4000_board *thisboard = comedi_board(dev);
479 int chan = CR_CHAN(insn->chanspec);
480 int rang = CR_RANGE(insn->chanspec);
481 int aref = CR_AREF(insn->chanspec);
483 unsigned int entry = 0;
489 } else if (insn->n > 1) {
490 dev_err(dev->class_dev, "Invalid instruction length %d\n",
497 entry |= ME4000_AI_LIST_RANGE_UNIPOLAR_2_5;
500 entry |= ME4000_AI_LIST_RANGE_UNIPOLAR_10;
503 entry |= ME4000_AI_LIST_RANGE_BIPOLAR_2_5;
506 entry |= ME4000_AI_LIST_RANGE_BIPOLAR_10;
509 dev_err(dev->class_dev, "Invalid range specified\n");
516 if (chan >= thisboard->ai_nchan) {
517 dev_err(dev->class_dev,
518 "Analog input is not available\n");
521 entry |= ME4000_AI_LIST_INPUT_SINGLE_ENDED | chan;
525 if (rang == 0 || rang == 1) {
526 dev_err(dev->class_dev,
527 "Range must be bipolar when aref = diff\n");
531 if (chan >= thisboard->ai_diff_nchan) {
532 dev_err(dev->class_dev,
533 "Analog input is not available\n");
536 entry |= ME4000_AI_LIST_INPUT_DIFFERENTIAL | chan;
539 dev_err(dev->class_dev, "Invalid aref specified\n");
543 entry |= ME4000_AI_LIST_LAST_ENTRY;
545 /* Clear channel list, data fifo and both stop bits */
546 tmp = inl(dev->iobase + ME4000_AI_CTRL_REG);
547 tmp &= ~(ME4000_AI_CTRL_BIT_CHANNEL_FIFO |
548 ME4000_AI_CTRL_BIT_DATA_FIFO |
549 ME4000_AI_CTRL_BIT_STOP | ME4000_AI_CTRL_BIT_IMMEDIATE_STOP);
550 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
552 /* Set the acquisition mode to single */
553 tmp &= ~(ME4000_AI_CTRL_BIT_MODE_0 | ME4000_AI_CTRL_BIT_MODE_1 |
554 ME4000_AI_CTRL_BIT_MODE_2);
555 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
557 /* Enable channel list and data fifo */
558 tmp |= ME4000_AI_CTRL_BIT_CHANNEL_FIFO | ME4000_AI_CTRL_BIT_DATA_FIFO;
559 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
561 /* Generate channel list entry */
562 outl(entry, dev->iobase + ME4000_AI_CHANNEL_LIST_REG);
564 /* Set the timer to maximum sample rate */
565 outl(ME4000_AI_MIN_TICKS, dev->iobase + ME4000_AI_CHAN_TIMER_REG);
566 outl(ME4000_AI_MIN_TICKS, dev->iobase + ME4000_AI_CHAN_PRE_TIMER_REG);
568 /* Start conversion by dummy read */
569 inl(dev->iobase + ME4000_AI_START_REG);
571 /* Wait until ready */
573 if (!(inl(dev->iobase + ME4000_AI_STATUS_REG) &
574 ME4000_AI_STATUS_BIT_EF_DATA)) {
575 dev_err(dev->class_dev, "Value not available after wait\n");
579 /* Read value from data fifo */
580 lval = inl(dev->iobase + ME4000_AI_DATA_REG) & 0xFFFF;
581 data[0] = lval ^ 0x8000;
586 static int me4000_ai_cancel(struct comedi_device *dev,
587 struct comedi_subdevice *s)
591 /* Stop any running conversion */
592 tmp = inl(dev->iobase + ME4000_AI_CTRL_REG);
593 tmp &= ~(ME4000_AI_CTRL_BIT_STOP | ME4000_AI_CTRL_BIT_IMMEDIATE_STOP);
594 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
596 /* Clear the control register */
597 outl(0x0, dev->iobase + ME4000_AI_CTRL_REG);
602 static int ai_check_chanlist(struct comedi_device *dev,
603 struct comedi_subdevice *s, struct comedi_cmd *cmd)
605 const struct me4000_board *thisboard = comedi_board(dev);
609 /* Check whether a channel list is available */
610 if (!cmd->chanlist_len) {
611 dev_err(dev->class_dev, "No channel list available\n");
615 /* Check the channel list size */
616 if (cmd->chanlist_len > ME4000_AI_CHANNEL_LIST_COUNT) {
617 dev_err(dev->class_dev, "Channel list is to large\n");
621 /* Check the pointer */
622 if (!cmd->chanlist) {
623 dev_err(dev->class_dev, "NULL pointer to channel list\n");
627 /* Check whether aref is equal for all entries */
628 aref = CR_AREF(cmd->chanlist[0]);
629 for (i = 0; i < cmd->chanlist_len; i++) {
630 if (CR_AREF(cmd->chanlist[i]) != aref) {
631 dev_err(dev->class_dev,
632 "Mode is not equal for all entries\n");
637 /* Check whether channels are available for this ending */
638 if (aref == SDF_DIFF) {
639 for (i = 0; i < cmd->chanlist_len; i++) {
640 if (CR_CHAN(cmd->chanlist[i]) >=
641 thisboard->ai_diff_nchan) {
642 dev_err(dev->class_dev,
643 "Channel number to high\n");
648 for (i = 0; i < cmd->chanlist_len; i++) {
649 if (CR_CHAN(cmd->chanlist[i]) >= thisboard->ai_nchan) {
650 dev_err(dev->class_dev,
651 "Channel number to high\n");
657 /* Check if bipolar is set for all entries when in differential mode */
658 if (aref == SDF_DIFF) {
659 for (i = 0; i < cmd->chanlist_len; i++) {
660 if (CR_RANGE(cmd->chanlist[i]) != 1 &&
661 CR_RANGE(cmd->chanlist[i]) != 2) {
662 dev_err(dev->class_dev,
663 "Bipolar is not selected in differential mode\n");
672 static int ai_round_cmd_args(struct comedi_device *dev,
673 struct comedi_subdevice *s,
674 struct comedi_cmd *cmd,
675 unsigned int *init_ticks,
676 unsigned int *scan_ticks, unsigned int *chan_ticks)
685 if (cmd->start_arg) {
686 *init_ticks = (cmd->start_arg * 33) / 1000;
687 rest = (cmd->start_arg * 33) % 1000;
689 if ((cmd->flags & TRIG_ROUND_MASK) == TRIG_ROUND_NEAREST) {
692 } else if ((cmd->flags & TRIG_ROUND_MASK) == TRIG_ROUND_UP) {
698 if (cmd->scan_begin_arg) {
699 *scan_ticks = (cmd->scan_begin_arg * 33) / 1000;
700 rest = (cmd->scan_begin_arg * 33) % 1000;
702 if ((cmd->flags & TRIG_ROUND_MASK) == TRIG_ROUND_NEAREST) {
705 } else if ((cmd->flags & TRIG_ROUND_MASK) == TRIG_ROUND_UP) {
711 if (cmd->convert_arg) {
712 *chan_ticks = (cmd->convert_arg * 33) / 1000;
713 rest = (cmd->convert_arg * 33) % 1000;
715 if ((cmd->flags & TRIG_ROUND_MASK) == TRIG_ROUND_NEAREST) {
718 } else if ((cmd->flags & TRIG_ROUND_MASK) == TRIG_ROUND_UP) {
727 static void ai_write_timer(struct comedi_device *dev,
728 unsigned int init_ticks,
729 unsigned int scan_ticks, unsigned int chan_ticks)
731 outl(init_ticks - 1, dev->iobase + ME4000_AI_SCAN_PRE_TIMER_LOW_REG);
732 outl(0x0, dev->iobase + ME4000_AI_SCAN_PRE_TIMER_HIGH_REG);
735 outl(scan_ticks - 1, dev->iobase + ME4000_AI_SCAN_TIMER_LOW_REG);
736 outl(0x0, dev->iobase + ME4000_AI_SCAN_TIMER_HIGH_REG);
739 outl(chan_ticks - 1, dev->iobase + ME4000_AI_CHAN_PRE_TIMER_REG);
740 outl(chan_ticks - 1, dev->iobase + ME4000_AI_CHAN_TIMER_REG);
743 static int ai_write_chanlist(struct comedi_device *dev,
744 struct comedi_subdevice *s, struct comedi_cmd *cmd)
752 for (i = 0; i < cmd->chanlist_len; i++) {
753 chan = CR_CHAN(cmd->chanlist[i]);
754 rang = CR_RANGE(cmd->chanlist[i]);
755 aref = CR_AREF(cmd->chanlist[i]);
760 entry |= ME4000_AI_LIST_RANGE_UNIPOLAR_2_5;
762 entry |= ME4000_AI_LIST_RANGE_UNIPOLAR_10;
764 entry |= ME4000_AI_LIST_RANGE_BIPOLAR_2_5;
766 entry |= ME4000_AI_LIST_RANGE_BIPOLAR_10;
768 if (aref == SDF_DIFF)
769 entry |= ME4000_AI_LIST_INPUT_DIFFERENTIAL;
771 entry |= ME4000_AI_LIST_INPUT_SINGLE_ENDED;
773 outl(entry, dev->iobase + ME4000_AI_CHANNEL_LIST_REG);
779 static int ai_prepare(struct comedi_device *dev,
780 struct comedi_subdevice *s,
781 struct comedi_cmd *cmd,
782 unsigned int init_ticks,
783 unsigned int scan_ticks, unsigned int chan_ticks)
786 unsigned int tmp = 0;
788 /* Write timer arguments */
789 ai_write_timer(dev, init_ticks, scan_ticks, chan_ticks);
791 /* Reset control register */
792 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
795 if ((cmd->start_src == TRIG_EXT &&
796 cmd->scan_begin_src == TRIG_TIMER &&
797 cmd->convert_src == TRIG_TIMER) ||
798 (cmd->start_src == TRIG_EXT &&
799 cmd->scan_begin_src == TRIG_FOLLOW &&
800 cmd->convert_src == TRIG_TIMER)) {
801 tmp = ME4000_AI_CTRL_BIT_MODE_1 |
802 ME4000_AI_CTRL_BIT_CHANNEL_FIFO |
803 ME4000_AI_CTRL_BIT_DATA_FIFO;
804 } else if (cmd->start_src == TRIG_EXT &&
805 cmd->scan_begin_src == TRIG_EXT &&
806 cmd->convert_src == TRIG_TIMER) {
807 tmp = ME4000_AI_CTRL_BIT_MODE_2 |
808 ME4000_AI_CTRL_BIT_CHANNEL_FIFO |
809 ME4000_AI_CTRL_BIT_DATA_FIFO;
810 } else if (cmd->start_src == TRIG_EXT &&
811 cmd->scan_begin_src == TRIG_EXT &&
812 cmd->convert_src == TRIG_EXT) {
813 tmp = ME4000_AI_CTRL_BIT_MODE_0 |
814 ME4000_AI_CTRL_BIT_MODE_1 |
815 ME4000_AI_CTRL_BIT_CHANNEL_FIFO |
816 ME4000_AI_CTRL_BIT_DATA_FIFO;
818 tmp = ME4000_AI_CTRL_BIT_MODE_0 |
819 ME4000_AI_CTRL_BIT_CHANNEL_FIFO |
820 ME4000_AI_CTRL_BIT_DATA_FIFO;
824 if (cmd->stop_src == TRIG_COUNT) {
825 outl(cmd->chanlist_len * cmd->stop_arg,
826 dev->iobase + ME4000_AI_SAMPLE_COUNTER_REG);
827 tmp |= ME4000_AI_CTRL_BIT_HF_IRQ | ME4000_AI_CTRL_BIT_SC_IRQ;
828 } else if (cmd->stop_src == TRIG_NONE &&
829 cmd->scan_end_src == TRIG_COUNT) {
830 outl(cmd->scan_end_arg,
831 dev->iobase + ME4000_AI_SAMPLE_COUNTER_REG);
832 tmp |= ME4000_AI_CTRL_BIT_HF_IRQ | ME4000_AI_CTRL_BIT_SC_IRQ;
834 tmp |= ME4000_AI_CTRL_BIT_HF_IRQ;
837 /* Write the setup to the control register */
838 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
840 /* Write the channel list */
841 ai_write_chanlist(dev, s, cmd);
846 static int me4000_ai_do_cmd(struct comedi_device *dev,
847 struct comedi_subdevice *s)
850 unsigned int init_ticks = 0;
851 unsigned int scan_ticks = 0;
852 unsigned int chan_ticks = 0;
853 struct comedi_cmd *cmd = &s->async->cmd;
855 /* Reset the analog input */
856 err = me4000_ai_cancel(dev, s);
860 /* Round the timer arguments */
861 err = ai_round_cmd_args(dev,
862 s, cmd, &init_ticks, &scan_ticks, &chan_ticks);
866 /* Prepare the AI for acquisition */
867 err = ai_prepare(dev, s, cmd, init_ticks, scan_ticks, chan_ticks);
871 /* Start acquistion by dummy read */
872 inl(dev->iobase + ME4000_AI_START_REG);
877 static int me4000_ai_do_cmd_test(struct comedi_device *dev,
878 struct comedi_subdevice *s,
879 struct comedi_cmd *cmd)
882 unsigned int init_ticks;
883 unsigned int chan_ticks;
884 unsigned int scan_ticks;
887 /* Only rounding flags are implemented */
888 cmd->flags &= TRIG_ROUND_NEAREST | TRIG_ROUND_UP | TRIG_ROUND_DOWN;
890 /* Round the timer arguments */
891 ai_round_cmd_args(dev, s, cmd, &init_ticks, &scan_ticks, &chan_ticks);
893 /* Step 1 : check if triggers are trivially valid */
895 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_EXT);
896 err |= cfc_check_trigger_src(&cmd->scan_begin_src,
897 TRIG_FOLLOW | TRIG_TIMER | TRIG_EXT);
898 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_TIMER | TRIG_EXT);
899 err |= cfc_check_trigger_src(&cmd->scan_end_src,
900 TRIG_NONE | TRIG_COUNT);
901 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_NONE | TRIG_COUNT);
906 /* Step 2a : make sure trigger sources are unique */
908 err |= cfc_check_trigger_is_unique(cmd->start_src);
909 err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
910 err |= cfc_check_trigger_is_unique(cmd->convert_src);
911 err |= cfc_check_trigger_is_unique(cmd->scan_end_src);
912 err |= cfc_check_trigger_is_unique(cmd->stop_src);
914 /* Step 2b : and mutually compatible */
916 if (cmd->start_src == TRIG_NOW &&
917 cmd->scan_begin_src == TRIG_TIMER &&
918 cmd->convert_src == TRIG_TIMER) {
919 } else if (cmd->start_src == TRIG_NOW &&
920 cmd->scan_begin_src == TRIG_FOLLOW &&
921 cmd->convert_src == TRIG_TIMER) {
922 } else if (cmd->start_src == TRIG_EXT &&
923 cmd->scan_begin_src == TRIG_TIMER &&
924 cmd->convert_src == TRIG_TIMER) {
925 } else if (cmd->start_src == TRIG_EXT &&
926 cmd->scan_begin_src == TRIG_FOLLOW &&
927 cmd->convert_src == TRIG_TIMER) {
928 } else if (cmd->start_src == TRIG_EXT &&
929 cmd->scan_begin_src == TRIG_EXT &&
930 cmd->convert_src == TRIG_TIMER) {
931 } else if (cmd->start_src == TRIG_EXT &&
932 cmd->scan_begin_src == TRIG_EXT &&
933 cmd->convert_src == TRIG_EXT) {
938 if (cmd->stop_src == TRIG_NONE && cmd->scan_end_src == TRIG_NONE) {
939 } else if (cmd->stop_src == TRIG_COUNT &&
940 cmd->scan_end_src == TRIG_NONE) {
941 } else if (cmd->stop_src == TRIG_NONE &&
942 cmd->scan_end_src == TRIG_COUNT) {
943 } else if (cmd->stop_src == TRIG_COUNT &&
944 cmd->scan_end_src == TRIG_COUNT) {
952 /* Step 3: check if arguments are trivially valid */
954 if (cmd->chanlist_len < 1) {
955 cmd->chanlist_len = 1;
958 if (init_ticks < 66) {
959 cmd->start_arg = 2000;
962 if (scan_ticks && scan_ticks < 67) {
963 cmd->scan_begin_arg = 2031;
966 if (chan_ticks < 66) {
967 cmd->convert_arg = 2000;
975 * Stage 4. Check for argument conflicts.
977 if (cmd->start_src == TRIG_NOW &&
978 cmd->scan_begin_src == TRIG_TIMER &&
979 cmd->convert_src == TRIG_TIMER) {
981 /* Check timer arguments */
982 if (init_ticks < ME4000_AI_MIN_TICKS) {
983 dev_err(dev->class_dev, "Invalid start arg\n");
984 cmd->start_arg = 2000; /* 66 ticks at least */
987 if (chan_ticks < ME4000_AI_MIN_TICKS) {
988 dev_err(dev->class_dev, "Invalid convert arg\n");
989 cmd->convert_arg = 2000; /* 66 ticks at least */
992 if (scan_ticks <= cmd->chanlist_len * chan_ticks) {
993 dev_err(dev->class_dev, "Invalid scan end arg\n");
995 /* At least one tick more */
996 cmd->scan_end_arg = 2000 * cmd->chanlist_len + 31;
999 } else if (cmd->start_src == TRIG_NOW &&
1000 cmd->scan_begin_src == TRIG_FOLLOW &&
1001 cmd->convert_src == TRIG_TIMER) {
1003 /* Check timer arguments */
1004 if (init_ticks < ME4000_AI_MIN_TICKS) {
1005 dev_err(dev->class_dev, "Invalid start arg\n");
1006 cmd->start_arg = 2000; /* 66 ticks at least */
1009 if (chan_ticks < ME4000_AI_MIN_TICKS) {
1010 dev_err(dev->class_dev, "Invalid convert arg\n");
1011 cmd->convert_arg = 2000; /* 66 ticks at least */
1014 } else if (cmd->start_src == TRIG_EXT &&
1015 cmd->scan_begin_src == TRIG_TIMER &&
1016 cmd->convert_src == TRIG_TIMER) {
1018 /* Check timer arguments */
1019 if (init_ticks < ME4000_AI_MIN_TICKS) {
1020 dev_err(dev->class_dev, "Invalid start arg\n");
1021 cmd->start_arg = 2000; /* 66 ticks at least */
1024 if (chan_ticks < ME4000_AI_MIN_TICKS) {
1025 dev_err(dev->class_dev, "Invalid convert arg\n");
1026 cmd->convert_arg = 2000; /* 66 ticks at least */
1029 if (scan_ticks <= cmd->chanlist_len * chan_ticks) {
1030 dev_err(dev->class_dev, "Invalid scan end arg\n");
1032 /* At least one tick more */
1033 cmd->scan_end_arg = 2000 * cmd->chanlist_len + 31;
1036 } else if (cmd->start_src == TRIG_EXT &&
1037 cmd->scan_begin_src == TRIG_FOLLOW &&
1038 cmd->convert_src == TRIG_TIMER) {
1040 /* Check timer arguments */
1041 if (init_ticks < ME4000_AI_MIN_TICKS) {
1042 dev_err(dev->class_dev, "Invalid start arg\n");
1043 cmd->start_arg = 2000; /* 66 ticks at least */
1046 if (chan_ticks < ME4000_AI_MIN_TICKS) {
1047 dev_err(dev->class_dev, "Invalid convert arg\n");
1048 cmd->convert_arg = 2000; /* 66 ticks at least */
1051 } else if (cmd->start_src == TRIG_EXT &&
1052 cmd->scan_begin_src == TRIG_EXT &&
1053 cmd->convert_src == TRIG_TIMER) {
1055 /* Check timer arguments */
1056 if (init_ticks < ME4000_AI_MIN_TICKS) {
1057 dev_err(dev->class_dev, "Invalid start arg\n");
1058 cmd->start_arg = 2000; /* 66 ticks at least */
1061 if (chan_ticks < ME4000_AI_MIN_TICKS) {
1062 dev_err(dev->class_dev, "Invalid convert arg\n");
1063 cmd->convert_arg = 2000; /* 66 ticks at least */
1066 } else if (cmd->start_src == TRIG_EXT &&
1067 cmd->scan_begin_src == TRIG_EXT &&
1068 cmd->convert_src == TRIG_EXT) {
1070 /* Check timer arguments */
1071 if (init_ticks < ME4000_AI_MIN_TICKS) {
1072 dev_err(dev->class_dev, "Invalid start arg\n");
1073 cmd->start_arg = 2000; /* 66 ticks at least */
1077 if (cmd->stop_src == TRIG_COUNT) {
1078 if (cmd->stop_arg == 0) {
1079 dev_err(dev->class_dev, "Invalid stop arg\n");
1084 if (cmd->scan_end_src == TRIG_COUNT) {
1085 if (cmd->scan_end_arg == 0) {
1086 dev_err(dev->class_dev, "Invalid scan end arg\n");
1087 cmd->scan_end_arg = 1;
1096 * Stage 5. Check the channel list.
1098 if (ai_check_chanlist(dev, s, cmd))
1104 static irqreturn_t me4000_ai_isr(int irq, void *dev_id)
1107 struct comedi_device *dev = dev_id;
1108 struct comedi_subdevice *s = &dev->subdevices[0];
1116 /* Reset all events */
1117 s->async->events = 0;
1119 /* Check if irq number is right */
1120 if (irq != dev->irq) {
1121 dev_err(dev->class_dev, "Incorrect interrupt num: %d\n", irq);
1125 if (inl(dev->iobase + ME4000_IRQ_STATUS_REG) &
1126 ME4000_IRQ_STATUS_BIT_AI_HF) {
1127 /* Read status register to find out what happened */
1128 tmp = inl(dev->iobase + ME4000_AI_CTRL_REG);
1130 if (!(tmp & ME4000_AI_STATUS_BIT_FF_DATA) &&
1131 !(tmp & ME4000_AI_STATUS_BIT_HF_DATA) &&
1132 (tmp & ME4000_AI_STATUS_BIT_EF_DATA)) {
1133 c = ME4000_AI_FIFO_COUNT;
1136 * FIFO overflow, so stop conversion
1137 * and disable all interrupts
1139 tmp |= ME4000_AI_CTRL_BIT_IMMEDIATE_STOP;
1140 tmp &= ~(ME4000_AI_CTRL_BIT_HF_IRQ |
1141 ME4000_AI_CTRL_BIT_SC_IRQ);
1142 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
1144 s->async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1146 dev_err(dev->class_dev, "FIFO overflow\n");
1147 } else if ((tmp & ME4000_AI_STATUS_BIT_FF_DATA)
1148 && !(tmp & ME4000_AI_STATUS_BIT_HF_DATA)
1149 && (tmp & ME4000_AI_STATUS_BIT_EF_DATA)) {
1150 s->async->events |= COMEDI_CB_BLOCK;
1152 c = ME4000_AI_FIFO_COUNT / 2;
1154 dev_err(dev->class_dev,
1155 "Can't determine state of fifo\n");
1159 * Undefined state, so stop conversion
1160 * and disable all interrupts
1162 tmp |= ME4000_AI_CTRL_BIT_IMMEDIATE_STOP;
1163 tmp &= ~(ME4000_AI_CTRL_BIT_HF_IRQ |
1164 ME4000_AI_CTRL_BIT_SC_IRQ);
1165 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
1167 s->async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1169 dev_err(dev->class_dev, "Undefined FIFO state\n");
1172 for (i = 0; i < c; i++) {
1173 /* Read value from data fifo */
1174 lval = inl(dev->iobase + ME4000_AI_DATA_REG) & 0xFFFF;
1177 if (!comedi_buf_put(s->async, lval)) {
1179 * Buffer overflow, so stop conversion
1180 * and disable all interrupts
1182 tmp |= ME4000_AI_CTRL_BIT_IMMEDIATE_STOP;
1183 tmp &= ~(ME4000_AI_CTRL_BIT_HF_IRQ |
1184 ME4000_AI_CTRL_BIT_SC_IRQ);
1185 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
1187 s->async->events |= COMEDI_CB_OVERFLOW;
1189 dev_err(dev->class_dev, "Buffer overflow\n");
1195 /* Work is done, so reset the interrupt */
1196 tmp |= ME4000_AI_CTRL_BIT_HF_IRQ_RESET;
1197 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
1198 tmp &= ~ME4000_AI_CTRL_BIT_HF_IRQ_RESET;
1199 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
1202 if (inl(dev->iobase + ME4000_IRQ_STATUS_REG) &
1203 ME4000_IRQ_STATUS_BIT_SC) {
1204 s->async->events |= COMEDI_CB_BLOCK | COMEDI_CB_EOA;
1207 * Acquisition is complete, so stop
1208 * conversion and disable all interrupts
1210 tmp = inl(dev->iobase + ME4000_AI_CTRL_REG);
1211 tmp |= ME4000_AI_CTRL_BIT_IMMEDIATE_STOP;
1212 tmp &= ~(ME4000_AI_CTRL_BIT_HF_IRQ | ME4000_AI_CTRL_BIT_SC_IRQ);
1213 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
1215 /* Poll data until fifo empty */
1216 while (inl(dev->iobase + ME4000_AI_CTRL_REG) &
1217 ME4000_AI_STATUS_BIT_EF_DATA) {
1218 /* Read value from data fifo */
1219 lval = inl(dev->iobase + ME4000_AI_DATA_REG) & 0xFFFF;
1222 if (!comedi_buf_put(s->async, lval)) {
1223 dev_err(dev->class_dev, "Buffer overflow\n");
1224 s->async->events |= COMEDI_CB_OVERFLOW;
1229 /* Work is done, so reset the interrupt */
1230 tmp |= ME4000_AI_CTRL_BIT_SC_IRQ_RESET;
1231 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
1232 tmp &= ~ME4000_AI_CTRL_BIT_SC_IRQ_RESET;
1233 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
1236 if (s->async->events)
1237 comedi_event(dev, s);
1242 /*=============================================================================
1243 Analog output section
1244 ===========================================================================*/
1246 static int me4000_ao_insn_write(struct comedi_device *dev,
1247 struct comedi_subdevice *s,
1248 struct comedi_insn *insn, unsigned int *data)
1250 const struct me4000_board *thisboard = comedi_board(dev);
1251 struct me4000_info *info = dev->private;
1252 int chan = CR_CHAN(insn->chanspec);
1253 int rang = CR_RANGE(insn->chanspec);
1254 int aref = CR_AREF(insn->chanspec);
1259 } else if (insn->n > 1) {
1260 dev_err(dev->class_dev, "Invalid instruction length %d\n",
1265 if (chan >= thisboard->ao_nchan) {
1266 dev_err(dev->class_dev, "Invalid channel %d\n", insn->n);
1271 dev_err(dev->class_dev, "Invalid range %d\n", insn->n);
1275 if (aref != AREF_GROUND && aref != AREF_COMMON) {
1276 dev_err(dev->class_dev, "Invalid aref %d\n", insn->n);
1280 /* Stop any running conversion */
1281 tmp = inl(dev->iobase + ME4000_AO_CTRL_REG(chan));
1282 tmp |= ME4000_AO_CTRL_BIT_IMMEDIATE_STOP;
1283 outl(tmp, dev->iobase + ME4000_AO_CTRL_REG(chan));
1285 /* Clear control register and set to single mode */
1286 outl(0x0, dev->iobase + ME4000_AO_CTRL_REG(chan));
1288 /* Write data value */
1289 outl(data[0], dev->iobase + ME4000_AO_SINGLE_REG(chan));
1291 /* Store in the mirror */
1292 info->ao_readback[chan] = data[0];
1297 static int me4000_ao_insn_read(struct comedi_device *dev,
1298 struct comedi_subdevice *s,
1299 struct comedi_insn *insn, unsigned int *data)
1301 struct me4000_info *info = dev->private;
1302 int chan = CR_CHAN(insn->chanspec);
1306 } else if (insn->n > 1) {
1307 dev_err(dev->class_dev, "Invalid instruction length\n");
1311 data[0] = info->ao_readback[chan];
1316 static int me4000_dio_insn_bits(struct comedi_device *dev,
1317 struct comedi_subdevice *s,
1318 struct comedi_insn *insn,
1321 if (comedi_dio_update_state(s, data)) {
1322 outl((s->state >> 0) & 0xFF,
1323 dev->iobase + ME4000_DIO_PORT_0_REG);
1324 outl((s->state >> 8) & 0xFF,
1325 dev->iobase + ME4000_DIO_PORT_1_REG);
1326 outl((s->state >> 16) & 0xFF,
1327 dev->iobase + ME4000_DIO_PORT_2_REG);
1328 outl((s->state >> 24) & 0xFF,
1329 dev->iobase + ME4000_DIO_PORT_3_REG);
1332 data[1] = ((inl(dev->iobase + ME4000_DIO_PORT_0_REG) & 0xFF) << 0) |
1333 ((inl(dev->iobase + ME4000_DIO_PORT_1_REG) & 0xFF) << 8) |
1334 ((inl(dev->iobase + ME4000_DIO_PORT_2_REG) & 0xFF) << 16) |
1335 ((inl(dev->iobase + ME4000_DIO_PORT_3_REG) & 0xFF) << 24);
1340 static int me4000_dio_insn_config(struct comedi_device *dev,
1341 struct comedi_subdevice *s,
1342 struct comedi_insn *insn,
1345 unsigned int chan = CR_CHAN(insn->chanspec);
1359 ret = comedi_dio_insn_config(dev, s, insn, data, mask);
1363 tmp = inl(dev->iobase + ME4000_DIO_CTRL_REG);
1364 tmp &= ~(ME4000_DIO_CTRL_BIT_MODE_0 | ME4000_DIO_CTRL_BIT_MODE_1 |
1365 ME4000_DIO_CTRL_BIT_MODE_2 | ME4000_DIO_CTRL_BIT_MODE_3 |
1366 ME4000_DIO_CTRL_BIT_MODE_4 | ME4000_DIO_CTRL_BIT_MODE_5 |
1367 ME4000_DIO_CTRL_BIT_MODE_6 | ME4000_DIO_CTRL_BIT_MODE_7);
1368 if (s->io_bits & 0x000000ff)
1369 tmp |= ME4000_DIO_CTRL_BIT_MODE_0;
1370 if (s->io_bits & 0x0000ff00)
1371 tmp |= ME4000_DIO_CTRL_BIT_MODE_2;
1372 if (s->io_bits & 0x00ff0000)
1373 tmp |= ME4000_DIO_CTRL_BIT_MODE_4;
1374 if (s->io_bits & 0xff000000)
1375 tmp |= ME4000_DIO_CTRL_BIT_MODE_6;
1378 * Check for optoisolated ME-4000 version.
1379 * If one the first port is a fixed output
1380 * port and the second is a fixed input port.
1382 if (inl(dev->iobase + ME4000_DIO_DIR_REG)) {
1383 s->io_bits |= 0x000000ff;
1384 s->io_bits &= ~0x0000ff00;
1385 tmp |= ME4000_DIO_CTRL_BIT_MODE_0;
1386 tmp &= ~(ME4000_DIO_CTRL_BIT_MODE_2 |
1387 ME4000_DIO_CTRL_BIT_MODE_3);
1390 outl(tmp, dev->iobase + ME4000_DIO_CTRL_REG);
1395 /*=============================================================================
1397 ===========================================================================*/
1399 static int me4000_cnt_insn_config(struct comedi_device *dev,
1400 struct comedi_subdevice *s,
1401 struct comedi_insn *insn,
1404 struct me4000_info *info = dev->private;
1412 err = i8254_load(info->timer_regbase, 0, insn->chanspec, 0,
1413 I8254_MODE0 | I8254_BINARY);
1417 case GPCT_SET_OPERATION:
1421 err = i8254_set_mode(info->timer_regbase, 0, insn->chanspec,
1422 (data[1] << 1) | I8254_BINARY);
1433 static int me4000_cnt_insn_read(struct comedi_device *dev,
1434 struct comedi_subdevice *s,
1435 struct comedi_insn *insn, unsigned int *data)
1437 struct me4000_info *info = dev->private;
1443 dev_err(dev->class_dev, "Invalid instruction length %d\n",
1448 data[0] = i8254_read(info->timer_regbase, 0, insn->chanspec);
1453 static int me4000_cnt_insn_write(struct comedi_device *dev,
1454 struct comedi_subdevice *s,
1455 struct comedi_insn *insn, unsigned int *data)
1457 struct me4000_info *info = dev->private;
1461 } else if (insn->n > 1) {
1462 dev_err(dev->class_dev, "Invalid instruction length %d\n",
1467 i8254_write(info->timer_regbase, 0, insn->chanspec, data[0]);
1472 static int me4000_auto_attach(struct comedi_device *dev,
1473 unsigned long context)
1475 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1476 const struct me4000_board *thisboard = NULL;
1477 struct me4000_info *info;
1478 struct comedi_subdevice *s;
1481 if (context < ARRAY_SIZE(me4000_boards))
1482 thisboard = &me4000_boards[context];
1485 dev->board_ptr = thisboard;
1486 dev->board_name = thisboard->name;
1488 info = comedi_alloc_devpriv(dev, sizeof(*info));
1492 result = comedi_pci_enable(dev);
1496 info->plx_regbase = pci_resource_start(pcidev, 1);
1497 dev->iobase = pci_resource_start(pcidev, 2);
1498 info->timer_regbase = pci_resource_start(pcidev, 3);
1499 if (!info->plx_regbase || !dev->iobase || !info->timer_regbase)
1502 result = xilinx_download(dev);
1508 result = comedi_alloc_subdevices(dev, 4);
1512 /*=========================================================================
1513 Analog input subdevice
1514 ========================================================================*/
1516 s = &dev->subdevices[0];
1518 if (thisboard->ai_nchan) {
1519 s->type = COMEDI_SUBD_AI;
1521 SDF_READABLE | SDF_COMMON | SDF_GROUND | SDF_DIFF;
1522 s->n_chan = thisboard->ai_nchan;
1523 s->maxdata = 0xFFFF; /* 16 bit ADC */
1524 s->len_chanlist = ME4000_AI_CHANNEL_LIST_COUNT;
1525 s->range_table = &me4000_ai_range;
1526 s->insn_read = me4000_ai_insn_read;
1528 if (pcidev->irq > 0) {
1529 if (request_irq(pcidev->irq, me4000_ai_isr,
1530 IRQF_SHARED, dev->board_name, dev)) {
1531 dev_warn(dev->class_dev,
1532 "request_irq failed\n");
1534 dev->read_subdev = s;
1535 s->subdev_flags |= SDF_CMD_READ;
1536 s->cancel = me4000_ai_cancel;
1537 s->do_cmdtest = me4000_ai_do_cmd_test;
1538 s->do_cmd = me4000_ai_do_cmd;
1540 dev->irq = pcidev->irq;
1543 dev_warn(dev->class_dev, "No interrupt available\n");
1546 s->type = COMEDI_SUBD_UNUSED;
1549 /*=========================================================================
1550 Analog output subdevice
1551 ========================================================================*/
1553 s = &dev->subdevices[1];
1555 if (thisboard->ao_nchan) {
1556 s->type = COMEDI_SUBD_AO;
1557 s->subdev_flags = SDF_WRITEABLE | SDF_COMMON | SDF_GROUND;
1558 s->n_chan = thisboard->ao_nchan;
1559 s->maxdata = 0xFFFF; /* 16 bit DAC */
1560 s->range_table = &range_bipolar10;
1561 s->insn_write = me4000_ao_insn_write;
1562 s->insn_read = me4000_ao_insn_read;
1564 s->type = COMEDI_SUBD_UNUSED;
1567 /*=========================================================================
1568 Digital I/O subdevice
1569 ========================================================================*/
1571 s = &dev->subdevices[2];
1573 if (thisboard->dio_nchan) {
1574 s->type = COMEDI_SUBD_DIO;
1575 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
1576 s->n_chan = thisboard->dio_nchan;
1578 s->range_table = &range_digital;
1579 s->insn_bits = me4000_dio_insn_bits;
1580 s->insn_config = me4000_dio_insn_config;
1582 s->type = COMEDI_SUBD_UNUSED;
1586 * Check for optoisolated ME-4000 version. If one the first
1587 * port is a fixed output port and the second is a fixed input port.
1589 if (!inl(dev->iobase + ME4000_DIO_DIR_REG)) {
1591 outl(ME4000_DIO_CTRL_BIT_MODE_0,
1592 dev->iobase + ME4000_DIO_DIR_REG);
1595 /*=========================================================================
1597 ========================================================================*/
1599 s = &dev->subdevices[3];
1601 if (thisboard->has_counter) {
1602 s->type = COMEDI_SUBD_COUNTER;
1603 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
1605 s->maxdata = 0xFFFF; /* 16 bit counters */
1606 s->insn_read = me4000_cnt_insn_read;
1607 s->insn_write = me4000_cnt_insn_write;
1608 s->insn_config = me4000_cnt_insn_config;
1610 s->type = COMEDI_SUBD_UNUSED;
1616 static void me4000_detach(struct comedi_device *dev)
1619 free_irq(dev->irq, dev);
1622 comedi_pci_disable(dev);
1625 static struct comedi_driver me4000_driver = {
1626 .driver_name = "me4000",
1627 .module = THIS_MODULE,
1628 .auto_attach = me4000_auto_attach,
1629 .detach = me4000_detach,
1632 static int me4000_pci_probe(struct pci_dev *dev,
1633 const struct pci_device_id *id)
1635 return comedi_pci_auto_config(dev, &me4000_driver, id->driver_data);
1638 static const struct pci_device_id me4000_pci_table[] = {
1639 { PCI_VDEVICE(MEILHAUS, 0x4650), BOARD_ME4650 },
1640 { PCI_VDEVICE(MEILHAUS, 0x4660), BOARD_ME4660 },
1641 { PCI_VDEVICE(MEILHAUS, 0x4661), BOARD_ME4660I },
1642 { PCI_VDEVICE(MEILHAUS, 0x4662), BOARD_ME4660S },
1643 { PCI_VDEVICE(MEILHAUS, 0x4663), BOARD_ME4660IS },
1644 { PCI_VDEVICE(MEILHAUS, 0x4670), BOARD_ME4670 },
1645 { PCI_VDEVICE(MEILHAUS, 0x4671), BOARD_ME4670I },
1646 { PCI_VDEVICE(MEILHAUS, 0x4672), BOARD_ME4670S },
1647 { PCI_VDEVICE(MEILHAUS, 0x4673), BOARD_ME4670IS },
1648 { PCI_VDEVICE(MEILHAUS, 0x4680), BOARD_ME4680 },
1649 { PCI_VDEVICE(MEILHAUS, 0x4681), BOARD_ME4680I },
1650 { PCI_VDEVICE(MEILHAUS, 0x4682), BOARD_ME4680S },
1651 { PCI_VDEVICE(MEILHAUS, 0x4683), BOARD_ME4680IS },
1654 MODULE_DEVICE_TABLE(pci, me4000_pci_table);
1656 static struct pci_driver me4000_pci_driver = {
1658 .id_table = me4000_pci_table,
1659 .probe = me4000_pci_probe,
1660 .remove = comedi_pci_auto_unconfig,
1662 module_comedi_pci_driver(me4000_driver, me4000_pci_driver);
1664 MODULE_AUTHOR("Comedi http://www.comedi.org");
1665 MODULE_DESCRIPTION("Comedi low-level driver");
1666 MODULE_LICENSE("GPL");