drivers/staging/comedi/drivers/ni_mio_common.c

   1 /*
   2     comedi/drivers/ni_mio_common.c
   3     Hardware driver for DAQ-STC based boards
   4
   5     COMEDI - Linux Control and Measurement Device Interface
   6     Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org>
   7     Copyright (C) 2002-2006 Frank Mori Hess <fmhess@users.sourceforge.net>
   8
   9     This program is free software; you can redistribute it and/or modify
  10     it under the terms of the GNU General Public License as published by
  11     the Free Software Foundation; either version 2 of the License, or
  12     (at your option) any later version.
  13
  14     This program is distributed in the hope that it will be useful,
  15     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17     GNU General Public License for more details.
  18 */
  19
  20 /*
  21         This file is meant to be included by another file, e.g.,
  22         ni_atmio.c or ni_pcimio.c.
  23
  24         Interrupt support originally added by Truxton Fulton
  25         <trux@truxton.com>
  26
  27         References (from ftp://ftp.natinst.com/support/manuals):
  28
  29            340747b.pdf  AT-MIO E series Register Level Programmer Manual
  30            341079b.pdf  PCI E Series RLPM
  31            340934b.pdf  DAQ-STC reference manual
  32         67xx and 611x registers (from ftp://ftp.ni.com/support/daq/mhddk/documentation/)
  33         release_ni611x.pdf
  34         release_ni67xx.pdf
  35         Other possibly relevant info:
  36
  37            320517c.pdf  User manual (obsolete)
  38            320517f.pdf  User manual (new)
  39            320889a.pdf  delete
  40            320906c.pdf  maximum signal ratings
  41            321066a.pdf  about 16x
  42            321791a.pdf  discontinuation of at-mio-16e-10 rev. c
  43            321808a.pdf  about at-mio-16e-10 rev P
  44            321837a.pdf  discontinuation of at-mio-16de-10 rev d
  45            321838a.pdf  about at-mio-16de-10 rev N
  46
  47         ISSUES:
  48
  49          - the interrupt routine needs to be cleaned up
  50
  51         2006-02-07: S-Series PCI-6143: Support has been added but is not
  52                 fully tested as yet. Terry Barnaby, BEAM Ltd.
  53 */
  54
  55 /* #define DEBUG_INTERRUPT */
  56 /* #define DEBUG_STATUS_A */
  57 /* #define DEBUG_STATUS_B */
  58
  59 #include <linux/interrupt.h>
  60 #include <linux/sched.h>
  61 #include <linux/delay.h>
  62 #include "8255.h"
  63 #include "mite.h"
  64 #include "comedi_fc.h"
  65
  66 /* A timeout count */
  67 #define NI_TIMEOUT 1000
  68 static const unsigned old_RTSI_clock_channel = 7;
  69
  70 /* Note: this table must match the ai_gain_* definitions */
  71 static const short ni_gainlkup[][16] = {
  72         [ai_gain_16] = {0, 1, 2, 3, 4, 5, 6, 7,
  73                         0x100, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
  74         [ai_gain_8] = {1, 2, 4, 7, 0x101, 0x102, 0x104, 0x107},
  75         [ai_gain_14] = {1, 2, 3, 4, 5, 6, 7,
  76                         0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
  77         [ai_gain_4] = {0, 1, 4, 7},
  78         [ai_gain_611x] = {0x00a, 0x00b, 0x001, 0x002,
  79                           0x003, 0x004, 0x005, 0x006},
  80         [ai_gain_622x] = {0, 1, 4, 5},
  81         [ai_gain_628x] = {1, 2, 3, 4, 5, 6, 7},
  82         [ai_gain_6143] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
  83 };
  84
  85 static const struct comedi_lrange range_ni_E_ai = { 16, {
  86                                                          RANGE(-10, 10),
  87                                                          RANGE(-5, 5),
  88                                                          RANGE(-2.5, 2.5),
  89                                                          RANGE(-1, 1),
  90                                                          RANGE(-0.5, 0.5),
  91                                                          RANGE(-0.25, 0.25),
  92                                                          RANGE(-0.1, 0.1),
  93                                                          RANGE(-0.05, 0.05),
  94                                                          RANGE(0, 20),
  95                                                          RANGE(0, 10),
  96                                                          RANGE(0, 5),
  97                                                          RANGE(0, 2),
  98                                                          RANGE(0, 1),
  99                                                          RANGE(0, 0.5),
 100                                                          RANGE(0, 0.2),
 101                                                          RANGE(0, 0.1),
 102                                                          }
 103 };
 104
 105 static const struct comedi_lrange range_ni_E_ai_limited = { 8, {
 106                                                                 RANGE(-10, 10),
 107                                                                 RANGE(-5, 5),
 108                                                                 RANGE(-1, 1),
 109                                                                 RANGE(-0.1,
 110                                                                       0.1),
 111                                                                 RANGE(0, 10),
 112                                                                 RANGE(0, 5),
 113                                                                 RANGE(0, 1),
 114                                                                 RANGE(0, 0.1),
 115                                                                 }
 116 };
 117
 118 static const struct comedi_lrange range_ni_E_ai_limited14 = { 14, {
 119                                                                    RANGE(-10,
 120                                                                          10),
 121                                                                    RANGE(-5, 5),
 122                                                                    RANGE(-2, 2),
 123                                                                    RANGE(-1, 1),
 124                                                                    RANGE(-0.5,
 125                                                                          0.5),
 126                                                                    RANGE(-0.2,
 127                                                                          0.2),
 128                                                                    RANGE(-0.1,
 129                                                                          0.1),
 130                                                                    RANGE(0, 10),
 131                                                                    RANGE(0, 5),
 132                                                                    RANGE(0, 2),
 133                                                                    RANGE(0, 1),
 134                                                                    RANGE(0,
 135                                                                          0.5),
 136                                                                    RANGE(0,
 137                                                                          0.2),
 138                                                                    RANGE(0,
 139                                                                          0.1),
 140                                                                    }
 141 };
 142
 143 static const struct comedi_lrange range_ni_E_ai_bipolar4 = { 4, {
 144                                                                  RANGE(-10, 10),
 145                                                                  RANGE(-5, 5),
 146                                                                  RANGE(-0.5,
 147                                                                        0.5),
 148                                                                  RANGE(-0.05,
 149                                                                        0.05),
 150                                                                  }
 151 };
 152
 153 static const struct comedi_lrange range_ni_E_ai_611x = { 8, {
 154                                                              RANGE(-50, 50),
 155                                                              RANGE(-20, 20),
 156                                                              RANGE(-10, 10),
 157                                                              RANGE(-5, 5),
 158                                                              RANGE(-2, 2),
 159                                                              RANGE(-1, 1),
 160                                                              RANGE(-0.5, 0.5),
 161                                                              RANGE(-0.2, 0.2),
 162                                                              }
 163 };
 164
 165 static const struct comedi_lrange range_ni_M_ai_622x = { 4, {
 166                                                              RANGE(-10, 10),
 167                                                              RANGE(-5, 5),
 168                                                              RANGE(-1, 1),
 169                                                              RANGE(-0.2, 0.2),
 170                                                              }
 171 };
 172
 173 static const struct comedi_lrange range_ni_M_ai_628x = { 7, {
 174                                                              RANGE(-10, 10),
 175                                                              RANGE(-5, 5),
 176                                                              RANGE(-2, 2),
 177                                                              RANGE(-1, 1),
 178                                                              RANGE(-0.5, 0.5),
 179                                                              RANGE(-0.2, 0.2),
 180                                                              RANGE(-0.1, 0.1),
 181                                                              }
 182 };
 183
 184 static const struct comedi_lrange range_ni_E_ao_ext = { 4, {
 185                                                             RANGE(-10, 10),
 186                                                             RANGE(0, 10),
 187                                                             RANGE_ext(-1, 1),
 188                                                             RANGE_ext(0, 1),
 189                                                             }
 190 };
 191
 192 static const struct comedi_lrange *const ni_range_lkup[] = {
 193         [ai_gain_16] = &range_ni_E_ai,
 194         [ai_gain_8] = &range_ni_E_ai_limited,
 195         [ai_gain_14] = &range_ni_E_ai_limited14,
 196         [ai_gain_4] = &range_ni_E_ai_bipolar4,
 197         [ai_gain_611x] = &range_ni_E_ai_611x,
 198         [ai_gain_622x] = &range_ni_M_ai_622x,
 199         [ai_gain_628x] = &range_ni_M_ai_628x,
 200         [ai_gain_6143] = &range_bipolar5
 201 };
 202
 203 static int ni_dio_insn_config(struct comedi_device *dev,
 204                               struct comedi_subdevice *s,
 205                               struct comedi_insn *insn, unsigned int *data);
 206 static int ni_dio_insn_bits(struct comedi_device *dev,
 207                             struct comedi_subdevice *s,
 208                             struct comedi_insn *insn, unsigned int *data);
 209 static int ni_cdio_cmdtest(struct comedi_device *dev,
 210                            struct comedi_subdevice *s, struct comedi_cmd *cmd);
 211 static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
 212 static int ni_cdio_cancel(struct comedi_device *dev,
 213                           struct comedi_subdevice *s);
 214 static void handle_cdio_interrupt(struct comedi_device *dev);
 215 static int ni_cdo_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
 216                           unsigned int trignum);
 217
 218 static int ni_serial_insn_config(struct comedi_device *dev,
 219                                  struct comedi_subdevice *s,
 220                                  struct comedi_insn *insn, unsigned int *data);
 221 static int ni_serial_hw_readwrite8(struct comedi_device *dev,
 222                                    struct comedi_subdevice *s,
 223                                    unsigned char data_out,
 224                                    unsigned char *data_in);
 225 static int ni_serial_sw_readwrite8(struct comedi_device *dev,
 226                                    struct comedi_subdevice *s,
 227                                    unsigned char data_out,
 228                                    unsigned char *data_in);
 229
 230 static int ni_calib_insn_read(struct comedi_device *dev,
 231                               struct comedi_subdevice *s,
 232                               struct comedi_insn *insn, unsigned int *data);
 233 static int ni_calib_insn_write(struct comedi_device *dev,
 234                                struct comedi_subdevice *s,
 235                                struct comedi_insn *insn, unsigned int *data);
 236
 237 static int ni_eeprom_insn_read(struct comedi_device *dev,
 238                                struct comedi_subdevice *s,
 239                                struct comedi_insn *insn, unsigned int *data);
 240 static int ni_m_series_eeprom_insn_read(struct comedi_device *dev,
 241                                         struct comedi_subdevice *s,
 242                                         struct comedi_insn *insn,
 243                                         unsigned int *data);
 244
 245 static int ni_pfi_insn_bits(struct comedi_device *dev,
 246                             struct comedi_subdevice *s,
 247                             struct comedi_insn *insn, unsigned int *data);
 248 static int ni_pfi_insn_config(struct comedi_device *dev,
 249                               struct comedi_subdevice *s,
 250                               struct comedi_insn *insn, unsigned int *data);
 251 static unsigned ni_old_get_pfi_routing(struct comedi_device *dev,
 252                                        unsigned chan);
 253
 254 static void ni_rtsi_init(struct comedi_device *dev);
 255 static int ni_rtsi_insn_bits(struct comedi_device *dev,
 256                              struct comedi_subdevice *s,
 257                              struct comedi_insn *insn, unsigned int *data);
 258 static int ni_rtsi_insn_config(struct comedi_device *dev,
 259                                struct comedi_subdevice *s,
 260                                struct comedi_insn *insn, unsigned int *data);
 261
 262 static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s);
 263 static int ni_read_eeprom(struct comedi_device *dev, int addr);
 264
 265 #ifdef DEBUG_STATUS_A
 266 static void ni_mio_print_status_a(int status);
 267 #else
 268 #define ni_mio_print_status_a(a)
 269 #endif
 270 #ifdef DEBUG_STATUS_B
 271 static void ni_mio_print_status_b(int status);
 272 #else
 273 #define ni_mio_print_status_b(a)
 274 #endif
 275
 276 static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s);
 277 #ifndef PCIDMA
 278 static void ni_handle_fifo_half_full(struct comedi_device *dev);
 279 static int ni_ao_fifo_half_empty(struct comedi_device *dev,
 280                                  struct comedi_subdevice *s);
 281 #endif
 282 static void ni_handle_fifo_dregs(struct comedi_device *dev);
 283 static int ni_ai_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
 284                          unsigned int trignum);
 285 static void ni_load_channelgain_list(struct comedi_device *dev,
 286                                      unsigned int n_chan, unsigned int *list);
 287 static void shutdown_ai_command(struct comedi_device *dev);
 288
 289 static int ni_ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
 290                          unsigned int trignum);
 291
 292 static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s);
 293
 294 static int ni_8255_callback(int dir, int port, int data, unsigned long arg);
 295
 296 static int ni_gpct_insn_write(struct comedi_device *dev,
 297                               struct comedi_subdevice *s,
 298                               struct comedi_insn *insn, unsigned int *data);
 299 static int ni_gpct_insn_read(struct comedi_device *dev,
 300                              struct comedi_subdevice *s,
 301                              struct comedi_insn *insn, unsigned int *data);
 302 static int ni_gpct_insn_config(struct comedi_device *dev,
 303                                struct comedi_subdevice *s,
 304                                struct comedi_insn *insn, unsigned int *data);
 305 #ifdef PCIDMA
 306 static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
 307 static int ni_gpct_cmdtest(struct comedi_device *dev,
 308                            struct comedi_subdevice *s, struct comedi_cmd *cmd);
 309 #endif
 310 static int ni_gpct_cancel(struct comedi_device *dev,
 311                           struct comedi_subdevice *s);
 312 static void handle_gpct_interrupt(struct comedi_device *dev,
 313                                   unsigned short counter_index);
 314
 315 static int init_cs5529(struct comedi_device *dev);
 316 static int cs5529_do_conversion(struct comedi_device *dev,
 317                                 unsigned short *data);
 318 static int cs5529_ai_insn_read(struct comedi_device *dev,
 319                                struct comedi_subdevice *s,
 320                                struct comedi_insn *insn, unsigned int *data);
 321 static void cs5529_config_write(struct comedi_device *dev, unsigned int value,
 322                                 unsigned int reg_select_bits);
 323
 324 static int ni_m_series_pwm_config(struct comedi_device *dev,
 325                                   struct comedi_subdevice *s,
 326                                   struct comedi_insn *insn, unsigned int *data);
 327 static int ni_6143_pwm_config(struct comedi_device *dev,
 328                               struct comedi_subdevice *s,
 329                               struct comedi_insn *insn, unsigned int *data);
 330
 331 static int ni_set_master_clock(struct comedi_device *dev, unsigned source,
 332                                unsigned period_ns);
 333 static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status);
 334 static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status);
 335
 336 enum aimodes {
 337         AIMODE_NONE = 0,
 338         AIMODE_HALF_FULL = 1,
 339         AIMODE_SCAN = 2,
 340         AIMODE_SAMPLE = 3,
 341 };
 342
 343 enum ni_common_subdevices {
 344         NI_AI_SUBDEV,
 345         NI_AO_SUBDEV,
 346         NI_DIO_SUBDEV,
 347         NI_8255_DIO_SUBDEV,
 348         NI_UNUSED_SUBDEV,
 349         NI_CALIBRATION_SUBDEV,
 350         NI_EEPROM_SUBDEV,
 351         NI_PFI_DIO_SUBDEV,
 352         NI_CS5529_CALIBRATION_SUBDEV,
 353         NI_SERIAL_SUBDEV,
 354         NI_RTSI_SUBDEV,
 355         NI_GPCT0_SUBDEV,
 356         NI_GPCT1_SUBDEV,
 357         NI_FREQ_OUT_SUBDEV,
 358         NI_NUM_SUBDEVICES
 359 };
 360 static inline unsigned NI_GPCT_SUBDEV(unsigned counter_index)
 361 {
 362         switch (counter_index) {
 363         case 0:
 364                 return NI_GPCT0_SUBDEV;
 365                 break;
 366         case 1:
 367                 return NI_GPCT1_SUBDEV;
 368                 break;
 369         default:
 370                 break;
 371         }
 372         BUG();
 373         return NI_GPCT0_SUBDEV;
 374 }
 375
 376 enum timebase_nanoseconds {
 377         TIMEBASE_1_NS = 50,
 378         TIMEBASE_2_NS = 10000
 379 };
 380
 381 #define SERIAL_DISABLED         0
 382 #define SERIAL_600NS            600
 383 #define SERIAL_1_2US            1200
 384 #define SERIAL_10US                     10000
 385
 386 static const int num_adc_stages_611x = 3;
 387
 388 static void handle_a_interrupt(struct comedi_device *dev, unsigned short status,
 389                                unsigned ai_mite_status);
 390 static void handle_b_interrupt(struct comedi_device *dev, unsigned short status,
 391                                unsigned ao_mite_status);
 392 static void get_last_sample_611x(struct comedi_device *dev);
 393 static void get_last_sample_6143(struct comedi_device *dev);
 394
 395 static inline void ni_set_bitfield(struct comedi_device *dev, int reg,
 396                                    unsigned bit_mask, unsigned bit_values)
 397 {
 398         struct ni_private *devpriv = dev->private;
 399         unsigned long flags;
 400
 401         spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
 402         switch (reg) {
 403         case Interrupt_A_Enable_Register:
 404                 devpriv->int_a_enable_reg &= ~bit_mask;
 405                 devpriv->int_a_enable_reg |= bit_values & bit_mask;
 406                 devpriv->stc_writew(dev, devpriv->int_a_enable_reg,
 407                                     Interrupt_A_Enable_Register);
 408                 break;
 409         case Interrupt_B_Enable_Register:
 410                 devpriv->int_b_enable_reg &= ~bit_mask;
 411                 devpriv->int_b_enable_reg |= bit_values & bit_mask;
 412                 devpriv->stc_writew(dev, devpriv->int_b_enable_reg,
 413                                     Interrupt_B_Enable_Register);
 414                 break;
 415         case IO_Bidirection_Pin_Register:
 416                 devpriv->io_bidirection_pin_reg &= ~bit_mask;
 417                 devpriv->io_bidirection_pin_reg |= bit_values & bit_mask;
 418                 devpriv->stc_writew(dev, devpriv->io_bidirection_pin_reg,
 419                                     IO_Bidirection_Pin_Register);
 420                 break;
 421         case AI_AO_Select:
 422                 devpriv->ai_ao_select_reg &= ~bit_mask;
 423                 devpriv->ai_ao_select_reg |= bit_values & bit_mask;
 424                 ni_writeb(devpriv->ai_ao_select_reg, AI_AO_Select);
 425                 break;
 426         case G0_G1_Select:
 427                 devpriv->g0_g1_select_reg &= ~bit_mask;
 428                 devpriv->g0_g1_select_reg |= bit_values & bit_mask;
 429                 ni_writeb(devpriv->g0_g1_select_reg, G0_G1_Select);
 430                 break;
 431         default:
 432                 printk("Warning %s() called with invalid register\n", __func__);
 433                 printk("reg is %d\n", reg);
 434                 break;
 435         }
 436         mmiowb();
 437         spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
 438 }
 439
 440 #ifdef PCIDMA
 441 static int ni_ai_drain_dma(struct comedi_device *dev);
 442
 443 /* DMA channel setup */
 444
 445 /* negative channel means no channel */
 446 static inline void ni_set_ai_dma_channel(struct comedi_device *dev, int channel)
 447 {
 448         unsigned bitfield;
 449
 450         if (channel >= 0) {
 451                 bitfield =
 452                     (ni_stc_dma_channel_select_bitfield(channel) <<
 453                      AI_DMA_Select_Shift) & AI_DMA_Select_Mask;
 454         } else {
 455                 bitfield = 0;
 456         }
 457         ni_set_bitfield(dev, AI_AO_Select, AI_DMA_Select_Mask, bitfield);
 458 }
 459
 460 /* negative channel means no channel */
 461 static inline void ni_set_ao_dma_channel(struct comedi_device *dev, int channel)
 462 {
 463         unsigned bitfield;
 464
 465         if (channel >= 0) {
 466                 bitfield =
 467                     (ni_stc_dma_channel_select_bitfield(channel) <<
 468                      AO_DMA_Select_Shift) & AO_DMA_Select_Mask;
 469         } else {
 470                 bitfield = 0;
 471         }
 472         ni_set_bitfield(dev, AI_AO_Select, AO_DMA_Select_Mask, bitfield);
 473 }
 474
 475 /* negative mite_channel means no channel */
 476 static inline void ni_set_gpct_dma_channel(struct comedi_device *dev,
 477                                            unsigned gpct_index,
 478                                            int mite_channel)
 479 {
 480         unsigned bitfield;
 481
 482         if (mite_channel >= 0) {
 483                 bitfield = GPCT_DMA_Select_Bits(gpct_index, mite_channel);
 484         } else {
 485                 bitfield = 0;
 486         }
 487         ni_set_bitfield(dev, G0_G1_Select, GPCT_DMA_Select_Mask(gpct_index),
 488                         bitfield);
 489 }
 490
 491 /* negative mite_channel means no channel */
 492 static inline void ni_set_cdo_dma_channel(struct comedi_device *dev,
 493                                           int mite_channel)
 494 {
 495         struct ni_private *devpriv = dev->private;
 496         unsigned long flags;
 497
 498         spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
 499         devpriv->cdio_dma_select_reg &= ~CDO_DMA_Select_Mask;
 500         if (mite_channel >= 0) {
 501                 /*XXX just guessing ni_stc_dma_channel_select_bitfield() returns the right bits,
 502                    under the assumption the cdio dma selection works just like ai/ao/gpct.
 503                    Definitely works for dma channels 0 and 1. */
 504                 devpriv->cdio_dma_select_reg |=
 505                     (ni_stc_dma_channel_select_bitfield(mite_channel) <<
 506                      CDO_DMA_Select_Shift) & CDO_DMA_Select_Mask;
 507         }
 508         ni_writeb(devpriv->cdio_dma_select_reg, M_Offset_CDIO_DMA_Select);
 509         mmiowb();
 510         spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
 511 }
 512
 513 static int ni_request_ai_mite_channel(struct comedi_device *dev)
 514 {
 515         struct ni_private *devpriv = dev->private;
 516         unsigned long flags;
 517
 518         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 519         BUG_ON(devpriv->ai_mite_chan);
 520         devpriv->ai_mite_chan =
 521             mite_request_channel(devpriv->mite, devpriv->ai_mite_ring);
 522         if (devpriv->ai_mite_chan == NULL) {
 523                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 524                 comedi_error(dev,
 525                              "failed to reserve mite dma channel for analog input.");
 526                 return -EBUSY;
 527         }
 528         devpriv->ai_mite_chan->dir = COMEDI_INPUT;
 529         ni_set_ai_dma_channel(dev, devpriv->ai_mite_chan->channel);
 530         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 531         return 0;
 532 }
 533
 534 static int ni_request_ao_mite_channel(struct comedi_device *dev)
 535 {
 536         struct ni_private *devpriv = dev->private;
 537         unsigned long flags;
 538
 539         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 540         BUG_ON(devpriv->ao_mite_chan);
 541         devpriv->ao_mite_chan =
 542             mite_request_channel(devpriv->mite, devpriv->ao_mite_ring);
 543         if (devpriv->ao_mite_chan == NULL) {
 544                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 545                 comedi_error(dev,
 546                              "failed to reserve mite dma channel for analog outut.");
 547                 return -EBUSY;
 548         }
 549         devpriv->ao_mite_chan->dir = COMEDI_OUTPUT;
 550         ni_set_ao_dma_channel(dev, devpriv->ao_mite_chan->channel);
 551         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 552         return 0;
 553 }
 554
 555 static int ni_request_gpct_mite_channel(struct comedi_device *dev,
 556                                         unsigned gpct_index,
 557                                         enum comedi_io_direction direction)
 558 {
 559         struct ni_private *devpriv = dev->private;
 560         unsigned long flags;
 561         struct mite_channel *mite_chan;
 562
 563         BUG_ON(gpct_index >= NUM_GPCT);
 564         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 565         BUG_ON(devpriv->counter_dev->counters[gpct_index].mite_chan);
 566         mite_chan =
 567             mite_request_channel(devpriv->mite,
 568                                  devpriv->gpct_mite_ring[gpct_index]);
 569         if (mite_chan == NULL) {
 570                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 571                 comedi_error(dev,
 572                              "failed to reserve mite dma channel for counter.");
 573                 return -EBUSY;
 574         }
 575         mite_chan->dir = direction;
 576         ni_tio_set_mite_channel(&devpriv->counter_dev->counters[gpct_index],
 577                                 mite_chan);
 578         ni_set_gpct_dma_channel(dev, gpct_index, mite_chan->channel);
 579         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 580         return 0;
 581 }
 582
 583 #endif /*  PCIDMA */
 584
 585 static int ni_request_cdo_mite_channel(struct comedi_device *dev)
 586 {
 587 #ifdef PCIDMA
 588         struct ni_private *devpriv = dev->private;
 589         unsigned long flags;
 590
 591         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 592         BUG_ON(devpriv->cdo_mite_chan);
 593         devpriv->cdo_mite_chan =
 594             mite_request_channel(devpriv->mite, devpriv->cdo_mite_ring);
 595         if (devpriv->cdo_mite_chan == NULL) {
 596                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 597                 comedi_error(dev,
 598                              "failed to reserve mite dma channel for correlated digital outut.");
 599                 return -EBUSY;
 600         }
 601         devpriv->cdo_mite_chan->dir = COMEDI_OUTPUT;
 602         ni_set_cdo_dma_channel(dev, devpriv->cdo_mite_chan->channel);
 603         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 604 #endif /*  PCIDMA */
 605         return 0;
 606 }
 607
 608 static void ni_release_ai_mite_channel(struct comedi_device *dev)
 609 {
 610 #ifdef PCIDMA
 611         struct ni_private *devpriv = dev->private;
 612         unsigned long flags;
 613
 614         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 615         if (devpriv->ai_mite_chan) {
 616                 ni_set_ai_dma_channel(dev, -1);
 617                 mite_release_channel(devpriv->ai_mite_chan);
 618                 devpriv->ai_mite_chan = NULL;
 619         }
 620         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 621 #endif /*  PCIDMA */
 622 }
 623
 624 static void ni_release_ao_mite_channel(struct comedi_device *dev)
 625 {
 626 #ifdef PCIDMA
 627         struct ni_private *devpriv = dev->private;
 628         unsigned long flags;
 629
 630         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 631         if (devpriv->ao_mite_chan) {
 632                 ni_set_ao_dma_channel(dev, -1);
 633                 mite_release_channel(devpriv->ao_mite_chan);
 634                 devpriv->ao_mite_chan = NULL;
 635         }
 636         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 637 #endif /*  PCIDMA */
 638 }
 639
 640 #ifdef PCIDMA
 641 static void ni_release_gpct_mite_channel(struct comedi_device *dev,
 642                                          unsigned gpct_index)
 643 {
 644         struct ni_private *devpriv = dev->private;
 645         unsigned long flags;
 646
 647         BUG_ON(gpct_index >= NUM_GPCT);
 648         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 649         if (devpriv->counter_dev->counters[gpct_index].mite_chan) {
 650                 struct mite_channel *mite_chan =
 651                     devpriv->counter_dev->counters[gpct_index].mite_chan;
 652
 653                 ni_set_gpct_dma_channel(dev, gpct_index, -1);
 654                 ni_tio_set_mite_channel(&devpriv->
 655                                         counter_dev->counters[gpct_index],
 656                                         NULL);
 657                 mite_release_channel(mite_chan);
 658         }
 659         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 660 }
 661 #endif /*  PCIDMA */
 662
 663 static void ni_release_cdo_mite_channel(struct comedi_device *dev)
 664 {
 665 #ifdef PCIDMA
 666         struct ni_private *devpriv = dev->private;
 667         unsigned long flags;
 668
 669         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 670         if (devpriv->cdo_mite_chan) {
 671                 ni_set_cdo_dma_channel(dev, -1);
 672                 mite_release_channel(devpriv->cdo_mite_chan);
 673                 devpriv->cdo_mite_chan = NULL;
 674         }
 675         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 676 #endif /*  PCIDMA */
 677 }
 678
 679 /* e-series boards use the second irq signals to generate dma requests for their counters */
 680 #ifdef PCIDMA
 681 static void ni_e_series_enable_second_irq(struct comedi_device *dev,
 682                                           unsigned gpct_index, short enable)
 683 {
 684         const struct ni_board_struct *board = comedi_board(dev);
 685         struct ni_private *devpriv = dev->private;
 686
 687         if (board->reg_type & ni_reg_m_series_mask)
 688                 return;
 689         switch (gpct_index) {
 690         case 0:
 691                 if (enable) {
 692                         devpriv->stc_writew(dev, G0_Gate_Second_Irq_Enable,
 693                                             Second_IRQ_A_Enable_Register);
 694                 } else {
 695                         devpriv->stc_writew(dev, 0,
 696                                             Second_IRQ_A_Enable_Register);
 697                 }
 698                 break;
 699         case 1:
 700                 if (enable) {
 701                         devpriv->stc_writew(dev, G1_Gate_Second_Irq_Enable,
 702                                             Second_IRQ_B_Enable_Register);
 703                 } else {
 704                         devpriv->stc_writew(dev, 0,
 705                                             Second_IRQ_B_Enable_Register);
 706                 }
 707                 break;
 708         default:
 709                 BUG();
 710                 break;
 711         }
 712 }
 713 #endif /*  PCIDMA */
 714
 715 static void ni_clear_ai_fifo(struct comedi_device *dev)
 716 {
 717         const struct ni_board_struct *board = comedi_board(dev);
 718         struct ni_private *devpriv = dev->private;
 719
 720         if (board->reg_type == ni_reg_6143) {
 721                 /*  Flush the 6143 data FIFO */
 722                 ni_writel(0x10, AIFIFO_Control_6143);   /*  Flush fifo */
 723                 ni_writel(0x00, AIFIFO_Control_6143);   /*  Flush fifo */
 724                 while (ni_readl(AIFIFO_Status_6143) & 0x10) ;   /*  Wait for complete */
 725         } else {
 726                 devpriv->stc_writew(dev, 1, ADC_FIFO_Clear);
 727                 if (board->reg_type == ni_reg_625x) {
 728                         ni_writeb(0, M_Offset_Static_AI_Control(0));
 729                         ni_writeb(1, M_Offset_Static_AI_Control(0));
 730 #if 0
 731                         /* the NI example code does 3 convert pulses for 625x boards,
 732                            but that appears to be wrong in practice. */
 733                         devpriv->stc_writew(dev, AI_CONVERT_Pulse,
 734                                             AI_Command_1_Register);
 735                         devpriv->stc_writew(dev, AI_CONVERT_Pulse,
 736                                             AI_Command_1_Register);
 737                         devpriv->stc_writew(dev, AI_CONVERT_Pulse,
 738                                             AI_Command_1_Register);
 739 #endif
 740                 }
 741         }
 742 }
 743
 744 static void win_out2(struct comedi_device *dev, uint32_t data, int reg)
 745 {
 746         struct ni_private *devpriv = dev->private;
 747
 748         devpriv->stc_writew(dev, data >> 16, reg);
 749         devpriv->stc_writew(dev, data & 0xffff, reg + 1);
 750 }
 751
 752 static uint32_t win_in2(struct comedi_device *dev, int reg)
 753 {
 754         struct ni_private *devpriv = dev->private;
 755         uint32_t bits;
 756
 757         bits = devpriv->stc_readw(dev, reg) << 16;
 758         bits |= devpriv->stc_readw(dev, reg + 1);
 759         return bits;
 760 }
 761
 762 #define ao_win_out(data, addr) ni_ao_win_outw(dev, data, addr)
 763 static inline void ni_ao_win_outw(struct comedi_device *dev, uint16_t data,
 764                                   int addr)
 765 {
 766         struct ni_private *devpriv = dev->private;
 767         unsigned long flags;
 768
 769         spin_lock_irqsave(&devpriv->window_lock, flags);
 770         ni_writew(addr, AO_Window_Address_611x);
 771         ni_writew(data, AO_Window_Data_611x);
 772         spin_unlock_irqrestore(&devpriv->window_lock, flags);
 773 }
 774
 775 static inline void ni_ao_win_outl(struct comedi_device *dev, uint32_t data,
 776                                   int addr)
 777 {
 778         struct ni_private *devpriv = dev->private;
 779         unsigned long flags;
 780
 781         spin_lock_irqsave(&devpriv->window_lock, flags);
 782         ni_writew(addr, AO_Window_Address_611x);
 783         ni_writel(data, AO_Window_Data_611x);
 784         spin_unlock_irqrestore(&devpriv->window_lock, flags);
 785 }
 786
 787 static inline unsigned short ni_ao_win_inw(struct comedi_device *dev, int addr)
 788 {
 789         struct ni_private *devpriv = dev->private;
 790         unsigned long flags;
 791         unsigned short data;
 792
 793         spin_lock_irqsave(&devpriv->window_lock, flags);
 794         ni_writew(addr, AO_Window_Address_611x);
 795         data = ni_readw(AO_Window_Data_611x);
 796         spin_unlock_irqrestore(&devpriv->window_lock, flags);
 797         return data;
 798 }
 799
 800 /* ni_set_bits( ) allows different parts of the ni_mio_common driver to
 801 * share registers (such as Interrupt_A_Register) without interfering with
 802 * each other.
 803 *
 804 * NOTE: the switch/case statements are optimized out for a constant argument
 805 * so this is actually quite fast---  If you must wrap another function around this
 806 * make it inline to avoid a large speed penalty.
 807 *
 808 * value should only be 1 or 0.
 809 */
 810 static inline void ni_set_bits(struct comedi_device *dev, int reg,
 811                                unsigned bits, unsigned value)
 812 {
 813         unsigned bit_values;
 814
 815         if (value)
 816                 bit_values = bits;
 817         else
 818                 bit_values = 0;
 819         ni_set_bitfield(dev, reg, bits, bit_values);
 820 }
 821
 822 static irqreturn_t ni_E_interrupt(int irq, void *d)
 823 {
 824         struct comedi_device *dev = d;
 825         struct ni_private *devpriv = dev->private;
 826         unsigned short a_status;
 827         unsigned short b_status;
 828         unsigned int ai_mite_status = 0;
 829         unsigned int ao_mite_status = 0;
 830         unsigned long flags;
 831 #ifdef PCIDMA
 832         struct mite_struct *mite = devpriv->mite;
 833 #endif
 834
 835         if (!dev->attached)
 836                 return IRQ_NONE;
 837         smp_mb();               /*  make sure dev->attached is checked before handler does anything else. */
 838
 839         /*  lock to avoid race with comedi_poll */
 840         spin_lock_irqsave(&dev->spinlock, flags);
 841         a_status = devpriv->stc_readw(dev, AI_Status_1_Register);
 842         b_status = devpriv->stc_readw(dev, AO_Status_1_Register);
 843 #ifdef PCIDMA
 844         if (mite) {
 845                 unsigned long flags_too;
 846
 847                 spin_lock_irqsave(&devpriv->mite_channel_lock, flags_too);
 848                 if (devpriv->ai_mite_chan) {
 849                         ai_mite_status = mite_get_status(devpriv->ai_mite_chan);
 850                         if (ai_mite_status & CHSR_LINKC)
 851                                 writel(CHOR_CLRLC,
 852                                        devpriv->mite->mite_io_addr +
 853                                        MITE_CHOR(devpriv->
 854                                                  ai_mite_chan->channel));
 855                 }
 856                 if (devpriv->ao_mite_chan) {
 857                         ao_mite_status = mite_get_status(devpriv->ao_mite_chan);
 858                         if (ao_mite_status & CHSR_LINKC)
 859                                 writel(CHOR_CLRLC,
 860                                        mite->mite_io_addr +
 861                                        MITE_CHOR(devpriv->
 862                                                  ao_mite_chan->channel));
 863                 }
 864                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags_too);
 865         }
 866 #endif
 867         ack_a_interrupt(dev, a_status);
 868         ack_b_interrupt(dev, b_status);
 869         if ((a_status & Interrupt_A_St) || (ai_mite_status & CHSR_INT))
 870                 handle_a_interrupt(dev, a_status, ai_mite_status);
 871         if ((b_status & Interrupt_B_St) || (ao_mite_status & CHSR_INT))
 872                 handle_b_interrupt(dev, b_status, ao_mite_status);
 873         handle_gpct_interrupt(dev, 0);
 874         handle_gpct_interrupt(dev, 1);
 875         handle_cdio_interrupt(dev);
 876
 877         spin_unlock_irqrestore(&dev->spinlock, flags);
 878         return IRQ_HANDLED;
 879 }
 880
 881 #ifdef PCIDMA
 882 static void ni_sync_ai_dma(struct comedi_device *dev)
 883 {
 884         struct ni_private *devpriv = dev->private;
 885         struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
 886         unsigned long flags;
 887
 888         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 889         if (devpriv->ai_mite_chan)
 890                 mite_sync_input_dma(devpriv->ai_mite_chan, s->async);
 891         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 892 }
 893
 894 static void mite_handle_b_linkc(struct mite_struct *mite,
 895                                 struct comedi_device *dev)
 896 {
 897         struct ni_private *devpriv = dev->private;
 898         struct comedi_subdevice *s = &dev->subdevices[NI_AO_SUBDEV];
 899         unsigned long flags;
 900
 901         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 902         if (devpriv->ao_mite_chan) {
 903                 mite_sync_output_dma(devpriv->ao_mite_chan, s->async);
 904         }
 905         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 906 }
 907
 908 static int ni_ao_wait_for_dma_load(struct comedi_device *dev)
 909 {
 910         struct ni_private *devpriv = dev->private;
 911         static const int timeout = 10000;
 912         int i;
 913         for (i = 0; i < timeout; i++) {
 914                 unsigned short b_status;
 915
 916                 b_status = devpriv->stc_readw(dev, AO_Status_1_Register);
 917                 if (b_status & AO_FIFO_Half_Full_St)
 918                         break;
 919                 /* if we poll too often, the pci bus activity seems
 920                    to slow the dma transfer down */
 921                 udelay(10);
 922         }
 923         if (i == timeout) {
 924                 comedi_error(dev, "timed out waiting for dma load");
 925                 return -EPIPE;
 926         }
 927         return 0;
 928 }
 929
 930 #endif /* PCIDMA */
 931 static void ni_handle_eos(struct comedi_device *dev, struct comedi_subdevice *s)
 932 {
 933         struct ni_private *devpriv = dev->private;
 934
 935         if (devpriv->aimode == AIMODE_SCAN) {
 936 #ifdef PCIDMA
 937                 static const int timeout = 10;
 938                 int i;
 939
 940                 for (i = 0; i < timeout; i++) {
 941                         ni_sync_ai_dma(dev);
 942                         if ((s->async->events & COMEDI_CB_EOS))
 943                                 break;
 944                         udelay(1);
 945                 }
 946 #else
 947                 ni_handle_fifo_dregs(dev);
 948                 s->async->events |= COMEDI_CB_EOS;
 949 #endif
 950         }
 951         /* handle special case of single scan using AI_End_On_End_Of_Scan */
 952         if ((devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)) {
 953                 shutdown_ai_command(dev);
 954         }
 955 }
 956
 957 static void shutdown_ai_command(struct comedi_device *dev)
 958 {
 959         struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
 960
 961 #ifdef PCIDMA
 962         ni_ai_drain_dma(dev);
 963 #endif
 964         ni_handle_fifo_dregs(dev);
 965         get_last_sample_611x(dev);
 966         get_last_sample_6143(dev);
 967
 968         s->async->events |= COMEDI_CB_EOA;
 969 }
 970
 971 static void ni_event(struct comedi_device *dev, struct comedi_subdevice *s)
 972 {
 973         if (s->
 974             async->events & (COMEDI_CB_ERROR | COMEDI_CB_OVERFLOW |
 975                              COMEDI_CB_EOA)) {
 976                 switch (s->index) {
 977                 case NI_AI_SUBDEV:
 978                         ni_ai_reset(dev, s);
 979                         break;
 980                 case NI_AO_SUBDEV:
 981                         ni_ao_reset(dev, s);
 982                         break;
 983                 case NI_GPCT0_SUBDEV:
 984                 case NI_GPCT1_SUBDEV:
 985                         ni_gpct_cancel(dev, s);
 986                         break;
 987                 case NI_DIO_SUBDEV:
 988                         ni_cdio_cancel(dev, s);
 989                         break;
 990                 default:
 991                         break;
 992                 }
 993         }
 994         comedi_event(dev, s);
 995 }
 996
 997 static void handle_gpct_interrupt(struct comedi_device *dev,
 998                                   unsigned short counter_index)
 999 {
1000 #ifdef PCIDMA
1001         struct ni_private *devpriv = dev->private;
1002         struct comedi_subdevice *s;
1003
1004         s = &dev->subdevices[NI_GPCT_SUBDEV(counter_index)];
1005
1006         ni_tio_handle_interrupt(&devpriv->counter_dev->counters[counter_index],
1007                                 s);
1008         if (s->async->events)
1009                 ni_event(dev, s);
1010 #endif
1011 }
1012
1013 static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status)
1014 {
1015         struct ni_private *devpriv = dev->private;
1016         unsigned short ack = 0;
1017
1018         if (a_status & AI_SC_TC_St) {
1019                 ack |= AI_SC_TC_Interrupt_Ack;
1020         }
1021         if (a_status & AI_START1_St) {
1022                 ack |= AI_START1_Interrupt_Ack;
1023         }
1024         if (a_status & AI_START_St) {
1025                 ack |= AI_START_Interrupt_Ack;
1026         }
1027         if (a_status & AI_STOP_St) {
1028                 /* not sure why we used to ack the START here also, instead of doing it independently. Frank Hess 2007-07-06 */
1029                 ack |= AI_STOP_Interrupt_Ack /*| AI_START_Interrupt_Ack */ ;
1030         }
1031         if (ack)
1032                 devpriv->stc_writew(dev, ack, Interrupt_A_Ack_Register);
1033 }
1034
1035 static void handle_a_interrupt(struct comedi_device *dev, unsigned short status,
1036                                unsigned ai_mite_status)
1037 {
1038         struct ni_private *devpriv = dev->private;
1039         struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1040
1041         /* 67xx boards don't have ai subdevice, but their gpct0 might generate an a interrupt */
1042         if (s->type == COMEDI_SUBD_UNUSED)
1043                 return;
1044
1045 #ifdef DEBUG_INTERRUPT
1046         printk
1047             ("ni_mio_common: interrupt: a_status=%04x ai_mite_status=%08x\n",
1048              status, ai_mite_status);
1049         ni_mio_print_status_a(status);
1050 #endif
1051 #ifdef PCIDMA
1052         if (ai_mite_status & CHSR_LINKC) {
1053                 ni_sync_ai_dma(dev);
1054         }
1055
1056         if (ai_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
1057                                CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1058                                CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
1059                 printk
1060                     ("unknown mite interrupt, ack! (ai_mite_status=%08x)\n",
1061                      ai_mite_status);
1062                 s->async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1063                 /* disable_irq(dev->irq); */
1064         }
1065 #endif
1066
1067         /* test for all uncommon interrupt events at the same time */
1068         if (status & (AI_Overrun_St | AI_Overflow_St | AI_SC_TC_Error_St |
1069                       AI_SC_TC_St | AI_START1_St)) {
1070                 if (status == 0xffff) {
1071                         printk
1072                             ("ni_mio_common: a_status=0xffff.  Card removed?\n");
1073                         /* we probably aren't even running a command now,
1074                          * so it's a good idea to be careful. */
1075                         if (comedi_is_subdevice_running(s)) {
1076                                 s->async->events |=
1077                                     COMEDI_CB_ERROR | COMEDI_CB_EOA;
1078                                 ni_event(dev, s);
1079                         }
1080                         return;
1081                 }
1082                 if (status & (AI_Overrun_St | AI_Overflow_St |
1083                               AI_SC_TC_Error_St)) {
1084                         printk("ni_mio_common: ai error a_status=%04x\n",
1085                                status);
1086                         ni_mio_print_status_a(status);
1087
1088                         shutdown_ai_command(dev);
1089
1090                         s->async->events |= COMEDI_CB_ERROR;
1091                         if (status & (AI_Overrun_St | AI_Overflow_St))
1092                                 s->async->events |= COMEDI_CB_OVERFLOW;
1093
1094                         ni_event(dev, s);
1095
1096                         return;
1097                 }
1098                 if (status & AI_SC_TC_St) {
1099 #ifdef DEBUG_INTERRUPT
1100                         printk("ni_mio_common: SC_TC interrupt\n");
1101 #endif
1102                         if (!devpriv->ai_continuous) {
1103                                 shutdown_ai_command(dev);
1104                         }
1105                 }
1106         }
1107 #ifndef PCIDMA
1108         if (status & AI_FIFO_Half_Full_St) {
1109                 int i;
1110                 static const int timeout = 10;
1111                 /* pcmcia cards (at least 6036) seem to stop producing interrupts if we
1112                  *fail to get the fifo less than half full, so loop to be sure.*/
1113                 for (i = 0; i < timeout; ++i) {
1114                         ni_handle_fifo_half_full(dev);
1115                         if ((devpriv->stc_readw(dev,
1116                                                 AI_Status_1_Register) &
1117                              AI_FIFO_Half_Full_St) == 0)
1118                                 break;
1119                 }
1120         }
1121 #endif /*  !PCIDMA */
1122
1123         if ((status & AI_STOP_St)) {
1124                 ni_handle_eos(dev, s);
1125         }
1126
1127         ni_event(dev, s);
1128
1129 #ifdef DEBUG_INTERRUPT
1130         status = devpriv->stc_readw(dev, AI_Status_1_Register);
1131         if (status & Interrupt_A_St) {
1132                 printk
1133                     ("handle_a_interrupt: didn't clear interrupt? status=0x%x\n",
1134                      status);
1135         }
1136 #endif
1137 }
1138
1139 static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status)
1140 {
1141         struct ni_private *devpriv = dev->private;
1142         unsigned short ack = 0;
1143
1144         if (b_status & AO_BC_TC_St) {
1145                 ack |= AO_BC_TC_Interrupt_Ack;
1146         }
1147         if (b_status & AO_Overrun_St) {
1148                 ack |= AO_Error_Interrupt_Ack;
1149         }
1150         if (b_status & AO_START_St) {
1151                 ack |= AO_START_Interrupt_Ack;
1152         }
1153         if (b_status & AO_START1_St) {
1154                 ack |= AO_START1_Interrupt_Ack;
1155         }
1156         if (b_status & AO_UC_TC_St) {
1157                 ack |= AO_UC_TC_Interrupt_Ack;
1158         }
1159         if (b_status & AO_UI2_TC_St) {
1160                 ack |= AO_UI2_TC_Interrupt_Ack;
1161         }
1162         if (b_status & AO_UPDATE_St) {
1163                 ack |= AO_UPDATE_Interrupt_Ack;
1164         }
1165         if (ack)
1166                 devpriv->stc_writew(dev, ack, Interrupt_B_Ack_Register);
1167 }
1168
1169 static void handle_b_interrupt(struct comedi_device *dev,
1170                                unsigned short b_status, unsigned ao_mite_status)
1171 {
1172         struct ni_private *devpriv = dev->private;
1173         struct comedi_subdevice *s = &dev->subdevices[NI_AO_SUBDEV];
1174         /* unsigned short ack=0; */
1175
1176 #ifdef DEBUG_INTERRUPT
1177         printk("ni_mio_common: interrupt: b_status=%04x m1_status=%08x\n",
1178                b_status, ao_mite_status);
1179         ni_mio_print_status_b(b_status);
1180 #endif
1181
1182 #ifdef PCIDMA
1183         /* Currently, mite.c requires us to handle LINKC */
1184         if (ao_mite_status & CHSR_LINKC) {
1185                 mite_handle_b_linkc(devpriv->mite, dev);
1186         }
1187
1188         if (ao_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
1189                                CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1190                                CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
1191                 printk
1192                     ("unknown mite interrupt, ack! (ao_mite_status=%08x)\n",
1193                      ao_mite_status);
1194                 s->async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
1195         }
1196 #endif
1197
1198         if (b_status == 0xffff)
1199                 return;
1200         if (b_status & AO_Overrun_St) {
1201                 printk
1202                     ("ni_mio_common: AO FIFO underrun status=0x%04x status2=0x%04x\n",
1203                      b_status, devpriv->stc_readw(dev, AO_Status_2_Register));
1204                 s->async->events |= COMEDI_CB_OVERFLOW;
1205         }
1206
1207         if (b_status & AO_BC_TC_St)
1208                 s->async->events |= COMEDI_CB_EOA;
1209
1210 #ifndef PCIDMA
1211         if (b_status & AO_FIFO_Request_St) {
1212                 int ret;
1213
1214                 ret = ni_ao_fifo_half_empty(dev, s);
1215                 if (!ret) {
1216                         printk("ni_mio_common: AO buffer underrun\n");
1217                         ni_set_bits(dev, Interrupt_B_Enable_Register,
1218                                     AO_FIFO_Interrupt_Enable |
1219                                     AO_Error_Interrupt_Enable, 0);
1220                         s->async->events |= COMEDI_CB_OVERFLOW;
1221                 }
1222         }
1223 #endif
1224
1225         ni_event(dev, s);
1226 }
1227
1228 #ifdef DEBUG_STATUS_A
1229 static const char *const status_a_strings[] = {
1230         "passthru0", "fifo", "G0_gate", "G0_TC",
1231         "stop", "start", "sc_tc", "start1",
1232         "start2", "sc_tc_error", "overflow", "overrun",
1233         "fifo_empty", "fifo_half_full", "fifo_full", "interrupt_a"
1234 };
1235
1236 static void ni_mio_print_status_a(int status)
1237 {
1238         int i;
1239
1240         printk("A status:");
1241         for (i = 15; i >= 0; i--) {
1242                 if (status & (1 << i)) {
1243                         printk(" %s", status_a_strings[i]);
1244                 }
1245         }
1246         printk("\n");
1247 }
1248 #endif
1249
1250 #ifdef DEBUG_STATUS_B
1251 static const char *const status_b_strings[] = {
1252         "passthru1", "fifo", "G1_gate", "G1_TC",
1253         "UI2_TC", "UPDATE", "UC_TC", "BC_TC",
1254         "start1", "overrun", "start", "bc_tc_error",
1255         "fifo_empty", "fifo_half_full", "fifo_full", "interrupt_b"
1256 };
1257
1258 static void ni_mio_print_status_b(int status)
1259 {
1260         int i;
1261
1262         printk("B status:");
1263         for (i = 15; i >= 0; i--) {
1264                 if (status & (1 << i)) {
1265                         printk(" %s", status_b_strings[i]);
1266                 }
1267         }
1268         printk("\n");
1269 }
1270 #endif
1271
1272 #ifndef PCIDMA
1273
1274 static void ni_ao_fifo_load(struct comedi_device *dev,
1275                             struct comedi_subdevice *s, int n)
1276 {
1277         const struct ni_board_struct *board = comedi_board(dev);
1278         struct comedi_async *async = s->async;
1279         struct comedi_cmd *cmd = &async->cmd;
1280         int chan;
1281         int i;
1282         unsigned short d;
1283         u32 packed_data;
1284         int range;
1285         int err = 1;
1286
1287         chan = async->cur_chan;
1288         for (i = 0; i < n; i++) {
1289                 err &= comedi_buf_get(async, &d);
1290                 if (err == 0)
1291                         break;
1292
1293                 range = CR_RANGE(cmd->chanlist[chan]);
1294
1295                 if (board->reg_type & ni_reg_6xxx_mask) {
1296                         packed_data = d & 0xffff;
1297                         /* 6711 only has 16 bit wide ao fifo */
1298                         if (board->reg_type != ni_reg_6711) {
1299                                 err &= comedi_buf_get(async, &d);
1300                                 if (err == 0)
1301                                         break;
1302                                 chan++;
1303                                 i++;
1304                                 packed_data |= (d << 16) & 0xffff0000;
1305                         }
1306                         ni_writel(packed_data, DAC_FIFO_Data_611x);
1307                 } else {
1308                         ni_writew(d, DAC_FIFO_Data);
1309                 }
1310                 chan++;
1311                 chan %= cmd->chanlist_len;
1312         }
1313         async->cur_chan = chan;
1314         if (err == 0) {
1315                 async->events |= COMEDI_CB_OVERFLOW;
1316         }
1317 }
1318
1319 /*
1320  *  There's a small problem if the FIFO gets really low and we
1321  *  don't have the data to fill it.  Basically, if after we fill
1322  *  the FIFO with all the data available, the FIFO is _still_
1323  *  less than half full, we never clear the interrupt.  If the
1324  *  IRQ is in edge mode, we never get another interrupt, because
1325  *  this one wasn't cleared.  If in level mode, we get flooded
1326  *  with interrupts that we can't fulfill, because nothing ever
1327  *  gets put into the buffer.
1328  *
1329  *  This kind of situation is recoverable, but it is easier to
1330  *  just pretend we had a FIFO underrun, since there is a good
1331  *  chance it will happen anyway.  This is _not_ the case for
1332  *  RT code, as RT code might purposely be running close to the
1333  *  metal.  Needs to be fixed eventually.
1334  */
1335 static int ni_ao_fifo_half_empty(struct comedi_device *dev,
1336                                  struct comedi_subdevice *s)
1337 {
1338         const struct ni_board_struct *board = comedi_board(dev);
1339         int n;
1340
1341         n = comedi_buf_read_n_available(s->async);
1342         if (n == 0) {
1343                 s->async->events |= COMEDI_CB_OVERFLOW;
1344                 return 0;
1345         }
1346
1347         n /= sizeof(short);
1348         if (n > board->ao_fifo_depth / 2)
1349                 n = board->ao_fifo_depth / 2;
1350
1351         ni_ao_fifo_load(dev, s, n);
1352
1353         s->async->events |= COMEDI_CB_BLOCK;
1354
1355         return 1;
1356 }
1357
1358 static int ni_ao_prep_fifo(struct comedi_device *dev,
1359                            struct comedi_subdevice *s)
1360 {
1361         const struct ni_board_struct *board = comedi_board(dev);
1362         struct ni_private *devpriv = dev->private;
1363         int n;
1364
1365         /* reset fifo */
1366         devpriv->stc_writew(dev, 1, DAC_FIFO_Clear);
1367         if (board->reg_type & ni_reg_6xxx_mask)
1368                 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
1369
1370         /* load some data */
1371         n = comedi_buf_read_n_available(s->async);
1372         if (n == 0)
1373                 return 0;
1374
1375         n /= sizeof(short);
1376         if (n > board->ao_fifo_depth)
1377                 n = board->ao_fifo_depth;
1378
1379         ni_ao_fifo_load(dev, s, n);
1380
1381         return n;
1382 }
1383
1384 static void ni_ai_fifo_read(struct comedi_device *dev,
1385                             struct comedi_subdevice *s, int n)
1386 {
1387         const struct ni_board_struct *board = comedi_board(dev);
1388         struct ni_private *devpriv = dev->private;
1389         struct comedi_async *async = s->async;
1390         int i;
1391
1392         if (board->reg_type == ni_reg_611x) {
1393                 unsigned short data[2];
1394                 u32 dl;
1395
1396                 for (i = 0; i < n / 2; i++) {
1397                         dl = ni_readl(ADC_FIFO_Data_611x);
1398                         /* This may get the hi/lo data in the wrong order */
1399                         data[0] = (dl >> 16) & 0xffff;
1400                         data[1] = dl & 0xffff;
1401                         cfc_write_array_to_buffer(s, data, sizeof(data));
1402                 }
1403                 /* Check if there's a single sample stuck in the FIFO */
1404                 if (n % 2) {
1405                         dl = ni_readl(ADC_FIFO_Data_611x);
1406                         data[0] = dl & 0xffff;
1407                         cfc_write_to_buffer(s, data[0]);
1408                 }
1409         } else if (board->reg_type == ni_reg_6143) {
1410                 unsigned short data[2];
1411                 u32 dl;
1412
1413                 /*  This just reads the FIFO assuming the data is present, no checks on the FIFO status are performed */
1414                 for (i = 0; i < n / 2; i++) {
1415                         dl = ni_readl(AIFIFO_Data_6143);
1416
1417                         data[0] = (dl >> 16) & 0xffff;
1418                         data[1] = dl & 0xffff;
1419                         cfc_write_array_to_buffer(s, data, sizeof(data));
1420                 }
1421                 if (n % 2) {
1422                         /* Assume there is a single sample stuck in the FIFO */
1423                         ni_writel(0x01, AIFIFO_Control_6143);   /*  Get stranded sample into FIFO */
1424                         dl = ni_readl(AIFIFO_Data_6143);
1425                         data[0] = (dl >> 16) & 0xffff;
1426                         cfc_write_to_buffer(s, data[0]);
1427                 }
1428         } else {
1429                 if (n > sizeof(devpriv->ai_fifo_buffer) /
1430                     sizeof(devpriv->ai_fifo_buffer[0])) {
1431                         comedi_error(dev, "bug! ai_fifo_buffer too small");
1432                         async->events |= COMEDI_CB_ERROR;
1433                         return;
1434                 }
1435                 for (i = 0; i < n; i++) {
1436                         devpriv->ai_fifo_buffer[i] =
1437                             ni_readw(ADC_FIFO_Data_Register);
1438                 }
1439                 cfc_write_array_to_buffer(s, devpriv->ai_fifo_buffer,
1440                                           n *
1441                                           sizeof(devpriv->ai_fifo_buffer[0]));
1442         }
1443 }
1444
1445 static void ni_handle_fifo_half_full(struct comedi_device *dev)
1446 {
1447         const struct ni_board_struct *board = comedi_board(dev);
1448         struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1449         int n;
1450
1451         n = board->ai_fifo_depth / 2;
1452
1453         ni_ai_fifo_read(dev, s, n);
1454 }
1455 #endif
1456
1457 #ifdef PCIDMA
1458 static int ni_ai_drain_dma(struct comedi_device *dev)
1459 {
1460         struct ni_private *devpriv = dev->private;
1461         int i;
1462         static const int timeout = 10000;
1463         unsigned long flags;
1464         int retval = 0;
1465
1466         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1467         if (devpriv->ai_mite_chan) {
1468                 for (i = 0; i < timeout; i++) {
1469                         if ((devpriv->stc_readw(dev,
1470                                                 AI_Status_1_Register) &
1471                              AI_FIFO_Empty_St)
1472                             && mite_bytes_in_transit(devpriv->ai_mite_chan) ==
1473                             0)
1474                                 break;
1475                         udelay(5);
1476                 }
1477                 if (i == timeout) {
1478                         printk("ni_mio_common: wait for dma drain timed out\n");
1479                         printk
1480                             ("mite_bytes_in_transit=%i, AI_Status1_Register=0x%x\n",
1481                              mite_bytes_in_transit(devpriv->ai_mite_chan),
1482                              devpriv->stc_readw(dev, AI_Status_1_Register));
1483                         retval = -1;
1484                 }
1485         }
1486         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1487
1488         ni_sync_ai_dma(dev);
1489
1490         return retval;
1491 }
1492 #endif
1493 /*
1494    Empties the AI fifo
1495 */
1496 static void ni_handle_fifo_dregs(struct comedi_device *dev)
1497 {
1498         const struct ni_board_struct *board = comedi_board(dev);
1499         struct ni_private *devpriv = dev->private;
1500         struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1501         unsigned short data[2];
1502         u32 dl;
1503         unsigned short fifo_empty;
1504         int i;
1505
1506         if (board->reg_type == ni_reg_611x) {
1507                 while ((devpriv->stc_readw(dev,
1508                                            AI_Status_1_Register) &
1509                         AI_FIFO_Empty_St) == 0) {
1510                         dl = ni_readl(ADC_FIFO_Data_611x);
1511
1512                         /* This may get the hi/lo data in the wrong order */
1513                         data[0] = (dl >> 16);
1514                         data[1] = (dl & 0xffff);
1515                         cfc_write_array_to_buffer(s, data, sizeof(data));
1516                 }
1517         } else if (board->reg_type == ni_reg_6143) {
1518                 i = 0;
1519                 while (ni_readl(AIFIFO_Status_6143) & 0x04) {
1520                         dl = ni_readl(AIFIFO_Data_6143);
1521
1522                         /* This may get the hi/lo data in the wrong order */
1523                         data[0] = (dl >> 16);
1524                         data[1] = (dl & 0xffff);
1525                         cfc_write_array_to_buffer(s, data, sizeof(data));
1526                         i += 2;
1527                 }
1528                 /*  Check if stranded sample is present */
1529                 if (ni_readl(AIFIFO_Status_6143) & 0x01) {
1530                         ni_writel(0x01, AIFIFO_Control_6143);   /*  Get stranded sample into FIFO */
1531                         dl = ni_readl(AIFIFO_Data_6143);
1532                         data[0] = (dl >> 16) & 0xffff;
1533                         cfc_write_to_buffer(s, data[0]);
1534                 }
1535
1536         } else {
1537                 fifo_empty =
1538                     devpriv->stc_readw(dev,
1539                                        AI_Status_1_Register) & AI_FIFO_Empty_St;
1540                 while (fifo_empty == 0) {
1541                         for (i = 0;
1542                              i <
1543                              sizeof(devpriv->ai_fifo_buffer) /
1544                              sizeof(devpriv->ai_fifo_buffer[0]); i++) {
1545                                 fifo_empty =
1546                                     devpriv->stc_readw(dev,
1547                                                        AI_Status_1_Register) &
1548                                     AI_FIFO_Empty_St;
1549                                 if (fifo_empty)
1550                                         break;
1551                                 devpriv->ai_fifo_buffer[i] =
1552                                     ni_readw(ADC_FIFO_Data_Register);
1553                         }
1554                         cfc_write_array_to_buffer(s, devpriv->ai_fifo_buffer,
1555                                                   i *
1556                                                   sizeof(devpriv->
1557                                                          ai_fifo_buffer[0]));
1558                 }
1559         }
1560 }
1561
1562 static void get_last_sample_611x(struct comedi_device *dev)
1563 {
1564         const struct ni_board_struct *board = comedi_board(dev);
1565         struct ni_private *devpriv __maybe_unused = dev->private;
1566         struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1567         unsigned short data;
1568         u32 dl;
1569
1570         if (board->reg_type != ni_reg_611x)
1571                 return;
1572
1573         /* Check if there's a single sample stuck in the FIFO */
1574         if (ni_readb(XXX_Status) & 0x80) {
1575                 dl = ni_readl(ADC_FIFO_Data_611x);
1576                 data = (dl & 0xffff);
1577                 cfc_write_to_buffer(s, data);
1578         }
1579 }
1580
1581 static void get_last_sample_6143(struct comedi_device *dev)
1582 {
1583         const struct ni_board_struct *board = comedi_board(dev);
1584         struct ni_private *devpriv __maybe_unused = dev->private;
1585         struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1586         unsigned short data;
1587         u32 dl;
1588
1589         if (board->reg_type != ni_reg_6143)
1590                 return;
1591
1592         /* Check if there's a single sample stuck in the FIFO */
1593         if (ni_readl(AIFIFO_Status_6143) & 0x01) {
1594                 ni_writel(0x01, AIFIFO_Control_6143);   /*  Get stranded sample into FIFO */
1595                 dl = ni_readl(AIFIFO_Data_6143);
1596
1597                 /* This may get the hi/lo data in the wrong order */
1598                 data = (dl >> 16) & 0xffff;
1599                 cfc_write_to_buffer(s, data);
1600         }
1601 }
1602
1603 static void ni_ai_munge(struct comedi_device *dev, struct comedi_subdevice *s,
1604                         void *data, unsigned int num_bytes,
1605                         unsigned int chan_index)
1606 {
1607         struct ni_private *devpriv = dev->private;
1608         struct comedi_async *async = s->async;
1609         unsigned int i;
1610         unsigned int length = num_bytes / bytes_per_sample(s);
1611         unsigned short *array = data;
1612         unsigned int *larray = data;
1613
1614         for (i = 0; i < length; i++) {
1615 #ifdef PCIDMA
1616                 if (s->subdev_flags & SDF_LSAMPL)
1617                         larray[i] = le32_to_cpu(larray[i]);
1618                 else
1619                         array[i] = le16_to_cpu(array[i]);
1620 #endif
1621                 if (s->subdev_flags & SDF_LSAMPL)
1622                         larray[i] += devpriv->ai_offset[chan_index];
1623                 else
1624                         array[i] += devpriv->ai_offset[chan_index];
1625                 chan_index++;
1626                 chan_index %= async->cmd.chanlist_len;
1627         }
1628 }
1629
1630 #ifdef PCIDMA
1631
1632 static int ni_ai_setup_MITE_dma(struct comedi_device *dev)
1633 {
1634         const struct ni_board_struct *board = comedi_board(dev);
1635         struct ni_private *devpriv = dev->private;
1636         struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1637         int retval;
1638         unsigned long flags;
1639
1640         retval = ni_request_ai_mite_channel(dev);
1641         if (retval)
1642                 return retval;
1643 /* printk("comedi_debug: using mite channel %i for ai.\n", devpriv->ai_mite_chan->channel); */
1644
1645         /* write alloc the entire buffer */
1646         comedi_buf_write_alloc(s->async, s->async->prealloc_bufsz);
1647
1648         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1649         if (devpriv->ai_mite_chan == NULL) {
1650                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1651                 return -EIO;
1652         }
1653
1654         switch (board->reg_type) {
1655         case ni_reg_611x:
1656         case ni_reg_6143:
1657                 mite_prep_dma(devpriv->ai_mite_chan, 32, 16);
1658                 break;
1659         case ni_reg_628x:
1660                 mite_prep_dma(devpriv->ai_mite_chan, 32, 32);
1661                 break;
1662         default:
1663                 mite_prep_dma(devpriv->ai_mite_chan, 16, 16);
1664                 break;
1665         }
1666         /*start the MITE */
1667         mite_dma_arm(devpriv->ai_mite_chan);
1668         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1669
1670         return 0;
1671 }
1672
1673 static int ni_ao_setup_MITE_dma(struct comedi_device *dev)
1674 {
1675         const struct ni_board_struct *board = comedi_board(dev);
1676         struct ni_private *devpriv = dev->private;
1677         struct comedi_subdevice *s = &dev->subdevices[NI_AO_SUBDEV];
1678         int retval;
1679         unsigned long flags;
1680
1681         retval = ni_request_ao_mite_channel(dev);
1682         if (retval)
1683                 return retval;
1684
1685         /* read alloc the entire buffer */
1686         comedi_buf_read_alloc(s->async, s->async->prealloc_bufsz);
1687
1688         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1689         if (devpriv->ao_mite_chan) {
1690                 if (board->reg_type & (ni_reg_611x | ni_reg_6713)) {
1691                         mite_prep_dma(devpriv->ao_mite_chan, 32, 32);
1692                 } else {
1693                         /* doing 32 instead of 16 bit wide transfers from memory
1694                            makes the mite do 32 bit pci transfers, doubling pci bandwidth. */
1695                         mite_prep_dma(devpriv->ao_mite_chan, 16, 32);
1696                 }
1697                 mite_dma_arm(devpriv->ao_mite_chan);
1698         } else
1699                 retval = -EIO;
1700         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1701
1702         return retval;
1703 }
1704
1705 #endif /*  PCIDMA */
1706
1707 /*
1708    used for both cancel ioctl and board initialization
1709
1710    this is pretty harsh for a cancel, but it works...
1711  */
1712
1713 static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s)
1714 {
1715         const struct ni_board_struct *board = comedi_board(dev);
1716         struct ni_private *devpriv = dev->private;
1717
1718         ni_release_ai_mite_channel(dev);
1719         /* ai configuration */
1720         devpriv->stc_writew(dev, AI_Configuration_Start | AI_Reset,
1721                             Joint_Reset_Register);
1722
1723         ni_set_bits(dev, Interrupt_A_Enable_Register,
1724                     AI_SC_TC_Interrupt_Enable | AI_START1_Interrupt_Enable |
1725                     AI_START2_Interrupt_Enable | AI_START_Interrupt_Enable |
1726                     AI_STOP_Interrupt_Enable | AI_Error_Interrupt_Enable |
1727                     AI_FIFO_Interrupt_Enable, 0);
1728
1729         ni_clear_ai_fifo(dev);
1730
1731         if (board->reg_type != ni_reg_6143)
1732                 ni_writeb(0, Misc_Command);
1733
1734         devpriv->stc_writew(dev, AI_Disarm, AI_Command_1_Register);     /* reset pulses */
1735         devpriv->stc_writew(dev,
1736                             AI_Start_Stop | AI_Mode_1_Reserved
1737                             /*| AI_Trigger_Once */ ,
1738                             AI_Mode_1_Register);
1739         devpriv->stc_writew(dev, 0x0000, AI_Mode_2_Register);
1740         /* generate FIFO interrupts on non-empty */
1741         devpriv->stc_writew(dev, (0 << 6) | 0x0000, AI_Mode_3_Register);
1742         if (board->reg_type == ni_reg_611x) {
1743                 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1744                                     AI_SOC_Polarity |
1745                                     AI_LOCALMUX_CLK_Pulse_Width,
1746                                     AI_Personal_Register);
1747                 devpriv->stc_writew(dev,
1748                                     AI_SCAN_IN_PROG_Output_Select(3) |
1749                                     AI_EXTMUX_CLK_Output_Select(0) |
1750                                     AI_LOCALMUX_CLK_Output_Select(2) |
1751                                     AI_SC_TC_Output_Select(3) |
1752                                     AI_CONVERT_Output_Select
1753                                     (AI_CONVERT_Output_Enable_High),
1754                                     AI_Output_Control_Register);
1755         } else if (board->reg_type == ni_reg_6143) {
1756                 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1757                                     AI_SOC_Polarity |
1758                                     AI_LOCALMUX_CLK_Pulse_Width,
1759                                     AI_Personal_Register);
1760                 devpriv->stc_writew(dev,
1761                                     AI_SCAN_IN_PROG_Output_Select(3) |
1762                                     AI_EXTMUX_CLK_Output_Select(0) |
1763                                     AI_LOCALMUX_CLK_Output_Select(2) |
1764                                     AI_SC_TC_Output_Select(3) |
1765                                     AI_CONVERT_Output_Select
1766                                     (AI_CONVERT_Output_Enable_Low),
1767                                     AI_Output_Control_Register);
1768         } else {
1769                 unsigned ai_output_control_bits;
1770                 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1771                                     AI_SOC_Polarity |
1772                                     AI_CONVERT_Pulse_Width |
1773                                     AI_LOCALMUX_CLK_Pulse_Width,
1774                                     AI_Personal_Register);
1775                 ai_output_control_bits =
1776                     AI_SCAN_IN_PROG_Output_Select(3) |
1777                     AI_EXTMUX_CLK_Output_Select(0) |
1778                     AI_LOCALMUX_CLK_Output_Select(2) |
1779                     AI_SC_TC_Output_Select(3);
1780                 if (board->reg_type == ni_reg_622x)
1781                         ai_output_control_bits |=
1782                             AI_CONVERT_Output_Select
1783                             (AI_CONVERT_Output_Enable_High);
1784                 else
1785                         ai_output_control_bits |=
1786                             AI_CONVERT_Output_Select
1787                             (AI_CONVERT_Output_Enable_Low);
1788                 devpriv->stc_writew(dev, ai_output_control_bits,
1789                                     AI_Output_Control_Register);
1790         }
1791         /* the following registers should not be changed, because there
1792          * are no backup registers in devpriv.  If you want to change
1793          * any of these, add a backup register and other appropriate code:
1794          *      AI_Mode_1_Register
1795          *      AI_Mode_3_Register
1796          *      AI_Personal_Register
1797          *      AI_Output_Control_Register
1798          */
1799         devpriv->stc_writew(dev, AI_SC_TC_Error_Confirm | AI_START_Interrupt_Ack | AI_START2_Interrupt_Ack | AI_START1_Interrupt_Ack | AI_SC_TC_Interrupt_Ack | AI_Error_Interrupt_Ack | AI_STOP_Interrupt_Ack, Interrupt_A_Ack_Register);      /* clear interrupts */
1800
1801         devpriv->stc_writew(dev, AI_Configuration_End, Joint_Reset_Register);
1802
1803         return 0;
1804 }
1805
1806 static int ni_ai_poll(struct comedi_device *dev, struct comedi_subdevice *s)
1807 {
1808         unsigned long flags;
1809         int count;
1810
1811         /*  lock to avoid race with interrupt handler */
1812         spin_lock_irqsave(&dev->spinlock, flags);
1813 #ifndef PCIDMA
1814         ni_handle_fifo_dregs(dev);
1815 #else
1816         ni_sync_ai_dma(dev);
1817 #endif
1818         count = s->async->buf_write_count - s->async->buf_read_count;
1819         spin_unlock_irqrestore(&dev->spinlock, flags);
1820
1821         return count;
1822 }
1823
1824 static int ni_ai_insn_read(struct comedi_device *dev,
1825                            struct comedi_subdevice *s, struct comedi_insn *insn,
1826                            unsigned int *data)
1827 {
1828         const struct ni_board_struct *board = comedi_board(dev);
1829         struct ni_private *devpriv = dev->private;
1830         int i, n;
1831         const unsigned int mask = (1 << board->adbits) - 1;
1832         unsigned signbits;
1833         unsigned short d;
1834         unsigned long dl;
1835
1836         ni_load_channelgain_list(dev, 1, &insn->chanspec);
1837
1838         ni_clear_ai_fifo(dev);
1839
1840         signbits = devpriv->ai_offset[0];
1841         if (board->reg_type == ni_reg_611x) {
1842                 for (n = 0; n < num_adc_stages_611x; n++) {
1843                         devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1844                                             AI_Command_1_Register);
1845                         udelay(1);
1846                 }
1847                 for (n = 0; n < insn->n; n++) {
1848                         devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1849                                             AI_Command_1_Register);
1850                         /* The 611x has screwy 32-bit FIFOs. */
1851                         d = 0;
1852                         for (i = 0; i < NI_TIMEOUT; i++) {
1853                                 if (ni_readb(XXX_Status) & 0x80) {
1854                                         d = (ni_readl(ADC_FIFO_Data_611x) >> 16)
1855                                             & 0xffff;
1856                                         break;
1857                                 }
1858                                 if (!(devpriv->stc_readw(dev,
1859                                                          AI_Status_1_Register) &
1860                                       AI_FIFO_Empty_St)) {
1861                                         d = ni_readl(ADC_FIFO_Data_611x) &
1862                                             0xffff;
1863                                         break;
1864                                 }
1865                         }
1866                         if (i == NI_TIMEOUT) {
1867                                 printk
1868                                     ("ni_mio_common: timeout in 611x ni_ai_insn_read\n");
1869                                 return -ETIME;
1870                         }
1871                         d += signbits;
1872                         data[n] = d;
1873                 }
1874         } else if (board->reg_type == ni_reg_6143) {
1875                 for (n = 0; n < insn->n; n++) {
1876                         devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1877                                             AI_Command_1_Register);
1878
1879                         /* The 6143 has 32-bit FIFOs. You need to strobe a bit to move a single 16bit stranded sample into the FIFO */
1880                         dl = 0;
1881                         for (i = 0; i < NI_TIMEOUT; i++) {
1882                                 if (ni_readl(AIFIFO_Status_6143) & 0x01) {
1883                                         ni_writel(0x01, AIFIFO_Control_6143);   /*  Get stranded sample into FIFO */
1884                                         dl = ni_readl(AIFIFO_Data_6143);
1885                                         break;
1886                                 }
1887                         }
1888                         if (i == NI_TIMEOUT) {
1889                                 printk
1890                                     ("ni_mio_common: timeout in 6143 ni_ai_insn_read\n");
1891                                 return -ETIME;
1892                         }
1893                         data[n] = (((dl >> 16) & 0xFFFF) + signbits) & 0xFFFF;
1894                 }
1895         } else {
1896                 for (n = 0; n < insn->n; n++) {
1897                         devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1898                                             AI_Command_1_Register);
1899                         for (i = 0; i < NI_TIMEOUT; i++) {
1900                                 if (!(devpriv->stc_readw(dev,
1901                                                          AI_Status_1_Register) &
1902                                       AI_FIFO_Empty_St))
1903                                         break;
1904                         }
1905                         if (i == NI_TIMEOUT) {
1906                                 printk
1907                                     ("ni_mio_common: timeout in ni_ai_insn_read\n");
1908                                 return -ETIME;
1909                         }
1910                         if (board->reg_type & ni_reg_m_series_mask) {
1911                                 data[n] =
1912                                     ni_readl(M_Offset_AI_FIFO_Data) & mask;
1913                         } else {
1914                                 d = ni_readw(ADC_FIFO_Data_Register);
1915                                 d += signbits;  /* subtle: needs to be short addition */
1916                                 data[n] = d;
1917                         }
1918                 }
1919         }
1920         return insn->n;
1921 }
1922
1923 static void ni_prime_channelgain_list(struct comedi_device *dev)
1924 {
1925         struct ni_private *devpriv = dev->private;
1926         int i;
1927
1928         devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1929         for (i = 0; i < NI_TIMEOUT; ++i) {
1930                 if (!(devpriv->stc_readw(dev,
1931                                          AI_Status_1_Register) &
1932                       AI_FIFO_Empty_St)) {
1933                         devpriv->stc_writew(dev, 1, ADC_FIFO_Clear);
1934                         return;
1935                 }
1936                 udelay(1);
1937         }
1938         printk("ni_mio_common: timeout loading channel/gain list\n");
1939 }
1940
1941 static void ni_m_series_load_channelgain_list(struct comedi_device *dev,
1942                                               unsigned int n_chan,
1943                                               unsigned int *list)
1944 {
1945         const struct ni_board_struct *board = comedi_board(dev);
1946         struct ni_private *devpriv = dev->private;
1947         unsigned int chan, range, aref;
1948         unsigned int i;
1949         unsigned offset;
1950         unsigned int dither;
1951         unsigned range_code;
1952
1953         devpriv->stc_writew(dev, 1, Configuration_Memory_Clear);
1954
1955 /* offset = 1 << (board->adbits - 1); */
1956         if ((list[0] & CR_ALT_SOURCE)) {
1957                 unsigned bypass_bits;
1958                 chan = CR_CHAN(list[0]);
1959                 range = CR_RANGE(list[0]);
1960                 range_code = ni_gainlkup[board->gainlkup][range];
1961                 dither = ((list[0] & CR_ALT_FILTER) != 0);
1962                 bypass_bits = MSeries_AI_Bypass_Config_FIFO_Bit;
1963                 bypass_bits |= chan;
1964                 bypass_bits |=
1965                     (devpriv->ai_calib_source) &
1966                     (MSeries_AI_Bypass_Cal_Sel_Pos_Mask |
1967                      MSeries_AI_Bypass_Cal_Sel_Neg_Mask |
1968                      MSeries_AI_Bypass_Mode_Mux_Mask |
1969                      MSeries_AO_Bypass_AO_Cal_Sel_Mask);
1970                 bypass_bits |= MSeries_AI_Bypass_Gain_Bits(range_code);
1971                 if (dither)
1972                         bypass_bits |= MSeries_AI_Bypass_Dither_Bit;
1973                 /*  don't use 2's complement encoding */
1974                 bypass_bits |= MSeries_AI_Bypass_Polarity_Bit;
1975                 ni_writel(bypass_bits, M_Offset_AI_Config_FIFO_Bypass);
1976         } else {
1977                 ni_writel(0, M_Offset_AI_Config_FIFO_Bypass);
1978         }
1979         offset = 0;
1980         for (i = 0; i < n_chan; i++) {
1981                 unsigned config_bits = 0;
1982                 chan = CR_CHAN(list[i]);
1983                 aref = CR_AREF(list[i]);
1984                 range = CR_RANGE(list[i]);
1985                 dither = ((list[i] & CR_ALT_FILTER) != 0);
1986
1987                 range_code = ni_gainlkup[board->gainlkup][range];
1988                 devpriv->ai_offset[i] = offset;
1989                 switch (aref) {
1990                 case AREF_DIFF:
1991                         config_bits |=
1992                             MSeries_AI_Config_Channel_Type_Differential_Bits;
1993                         break;
1994                 case AREF_COMMON:
1995                         config_bits |=
1996                             MSeries_AI_Config_Channel_Type_Common_Ref_Bits;
1997                         break;
1998                 case AREF_GROUND:
1999                         config_bits |=
2000                             MSeries_AI_Config_Channel_Type_Ground_Ref_Bits;
2001                         break;
2002                 case AREF_OTHER:
2003                         break;
2004                 }
2005                 config_bits |= MSeries_AI_Config_Channel_Bits(chan);
2006                 config_bits |=
2007                     MSeries_AI_Config_Bank_Bits(board->reg_type, chan);
2008                 config_bits |= MSeries_AI_Config_Gain_Bits(range_code);
2009                 if (i == n_chan - 1)
2010                         config_bits |= MSeries_AI_Config_Last_Channel_Bit;
2011                 if (dither)
2012                         config_bits |= MSeries_AI_Config_Dither_Bit;
2013                 /*  don't use 2's complement encoding */
2014                 config_bits |= MSeries_AI_Config_Polarity_Bit;
2015                 ni_writew(config_bits, M_Offset_AI_Config_FIFO_Data);
2016         }
2017         ni_prime_channelgain_list(dev);
2018 }
2019
2020 /*
2021  * Notes on the 6110 and 6111:
2022  * These boards a slightly different than the rest of the series, since
2023  * they have multiple A/D converters.
2024  * From the driver side, the configuration memory is a
2025  * little different.
2026  * Configuration Memory Low:
2027  *   bits 15-9: same
2028  *   bit 8: unipolar/bipolar (should be 0 for bipolar)
2029  *   bits 0-3: gain.  This is 4 bits instead of 3 for the other boards
2030  *       1001 gain=0.1 (+/- 50)
2031  *       1010 0.2
2032  *       1011 0.1
2033  *       0001 1
2034  *       0010 2
2035  *       0011 5
2036  *       0100 10
2037  *       0101 20
2038  *       0110 50
2039  * Configuration Memory High:
2040  *   bits 12-14: Channel Type
2041  *       001 for differential
2042  *       000 for calibration
2043  *   bit 11: coupling  (this is not currently handled)
2044  *       1 AC coupling
2045  *       0 DC coupling
2046  *   bits 0-2: channel
2047  *       valid channels are 0-3
2048  */
2049 static void ni_load_channelgain_list(struct comedi_device *dev,
2050                                      unsigned int n_chan, unsigned int *list)
2051 {
2052         const struct ni_board_struct *board = comedi_board(dev);
2053         struct ni_private *devpriv = dev->private;
2054         unsigned int chan, range, aref;
2055         unsigned int i;
2056         unsigned int hi, lo;
2057         unsigned offset;
2058         unsigned int dither;
2059
2060         if (board->reg_type & ni_reg_m_series_mask) {
2061                 ni_m_series_load_channelgain_list(dev, n_chan, list);
2062                 return;
2063         }
2064         if (n_chan == 1 && (board->reg_type != ni_reg_611x)
2065             && (board->reg_type != ni_reg_6143)) {
2066                 if (devpriv->changain_state
2067                     && devpriv->changain_spec == list[0]) {
2068                         /*  ready to go. */
2069                         return;
2070                 }
2071                 devpriv->changain_state = 1;
2072                 devpriv->changain_spec = list[0];
2073         } else {
2074                 devpriv->changain_state = 0;
2075         }
2076
2077         devpriv->stc_writew(dev, 1, Configuration_Memory_Clear);
2078
2079         /*  Set up Calibration mode if required */
2080         if (board->reg_type == ni_reg_6143) {
2081                 if ((list[0] & CR_ALT_SOURCE)
2082                     && !devpriv->ai_calib_source_enabled) {
2083                         /*  Strobe Relay enable bit */
2084                         ni_writew(devpriv->ai_calib_source |
2085                                   Calibration_Channel_6143_RelayOn,
2086                                   Calibration_Channel_6143);
2087                         ni_writew(devpriv->ai_calib_source,
2088                                   Calibration_Channel_6143);
2089                         devpriv->ai_calib_source_enabled = 1;
2090                         msleep_interruptible(100);      /*  Allow relays to change */
2091                 } else if (!(list[0] & CR_ALT_SOURCE)
2092                            && devpriv->ai_calib_source_enabled) {
2093                         /*  Strobe Relay disable bit */
2094                         ni_writew(devpriv->ai_calib_source |
2095                                   Calibration_Channel_6143_RelayOff,
2096                                   Calibration_Channel_6143);
2097                         ni_writew(devpriv->ai_calib_source,
2098                                   Calibration_Channel_6143);
2099                         devpriv->ai_calib_source_enabled = 0;
2100                         msleep_interruptible(100);      /*  Allow relays to change */
2101                 }
2102         }
2103
2104         offset = 1 << (board->adbits - 1);
2105         for (i = 0; i < n_chan; i++) {
2106                 if ((board->reg_type != ni_reg_6143)
2107                     && (list[i] & CR_ALT_SOURCE)) {
2108                         chan = devpriv->ai_calib_source;
2109                 } else {
2110                         chan = CR_CHAN(list[i]);
2111                 }
2112                 aref = CR_AREF(list[i]);
2113                 range = CR_RANGE(list[i]);
2114                 dither = ((list[i] & CR_ALT_FILTER) != 0);
2115
2116                 /* fix the external/internal range differences */
2117                 range = ni_gainlkup[board->gainlkup][range];
2118                 if (board->reg_type == ni_reg_611x)
2119                         devpriv->ai_offset[i] = offset;
2120                 else
2121                         devpriv->ai_offset[i] = (range & 0x100) ? 0 : offset;
2122
2123                 hi = 0;
2124                 if ((list[i] & CR_ALT_SOURCE)) {
2125                         if (board->reg_type == ni_reg_611x)
2126                                 ni_writew(CR_CHAN(list[i]) & 0x0003,
2127                                           Calibration_Channel_Select_611x);
2128                 } else {
2129                         if (board->reg_type == ni_reg_611x)
2130                                 aref = AREF_DIFF;
2131                         else if (board->reg_type == ni_reg_6143)
2132                                 aref = AREF_OTHER;
2133                         switch (aref) {
2134                         case AREF_DIFF:
2135                                 hi |= AI_DIFFERENTIAL;
2136                                 break;
2137                         case AREF_COMMON:
2138                                 hi |= AI_COMMON;
2139                                 break;
2140                         case AREF_GROUND:
2141                                 hi |= AI_GROUND;
2142                                 break;
2143                         case AREF_OTHER:
2144                                 break;
2145                         }
2146                 }
2147                 hi |= AI_CONFIG_CHANNEL(chan);
2148
2149                 ni_writew(hi, Configuration_Memory_High);
2150
2151                 if (board->reg_type != ni_reg_6143) {
2152                         lo = range;
2153                         if (i == n_chan - 1)
2154                                 lo |= AI_LAST_CHANNEL;
2155                         if (dither)
2156                                 lo |= AI_DITHER;
2157
2158                         ni_writew(lo, Configuration_Memory_Low);
2159                 }
2160         }
2161
2162         /* prime the channel/gain list */
2163         if ((board->reg_type != ni_reg_611x)
2164             && (board->reg_type != ni_reg_6143)) {
2165                 ni_prime_channelgain_list(dev);
2166         }
2167 }
2168
2169 static int ni_ns_to_timer(const struct comedi_device *dev, unsigned nanosec,
2170                           int round_mode)
2171 {
2172         struct ni_private *devpriv = dev->private;
2173         int divider;
2174
2175         switch (round_mode) {
2176         case TRIG_ROUND_NEAREST:
2177         default:
2178                 divider = (nanosec + devpriv->clock_ns / 2) / devpriv->clock_ns;
2179                 break;
2180         case TRIG_ROUND_DOWN:
2181                 divider = (nanosec) / devpriv->clock_ns;
2182                 break;
2183         case TRIG_ROUND_UP:
2184                 divider = (nanosec + devpriv->clock_ns - 1) / devpriv->clock_ns;
2185                 break;
2186         }
2187         return divider - 1;
2188 }
2189
2190 static unsigned ni_timer_to_ns(const struct comedi_device *dev, int timer)
2191 {
2192         struct ni_private *devpriv = dev->private;
2193
2194         return devpriv->clock_ns * (timer + 1);
2195 }
2196
2197 static unsigned ni_min_ai_scan_period_ns(struct comedi_device *dev,
2198                                          unsigned num_channels)
2199 {
2200         const struct ni_board_struct *board = comedi_board(dev);
2201
2202         switch (board->reg_type) {
2203         case ni_reg_611x:
2204         case ni_reg_6143:
2205                 /*  simultaneously-sampled inputs */
2206                 return board->ai_speed;
2207                 break;
2208         default:
2209                 /*  multiplexed inputs */
2210                 break;
2211         }
2212         return board->ai_speed * num_channels;
2213 }
2214
2215 static int ni_ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
2216                          struct comedi_cmd *cmd)
2217 {
2218         const struct ni_board_struct *board = comedi_board(dev);
2219         struct ni_private *devpriv = dev->private;
2220         int err = 0;
2221         int tmp;
2222         unsigned int sources;
2223
2224         /* Step 1 : check if triggers are trivially valid */
2225
2226         if ((cmd->flags & CMDF_WRITE))
2227                 cmd->flags &= ~CMDF_WRITE;
2228
2229         err |= cfc_check_trigger_src(&cmd->start_src,
2230                                         TRIG_NOW | TRIG_INT | TRIG_EXT);
2231         err |= cfc_check_trigger_src(&cmd->scan_begin_src,
2232                                         TRIG_TIMER | TRIG_EXT);
2233
2234         sources = TRIG_TIMER | TRIG_EXT;
2235         if (board->reg_type == ni_reg_611x ||
2236             board->reg_type == ni_reg_6143)
2237                 sources |= TRIG_NOW;
2238         err |= cfc_check_trigger_src(&cmd->convert_src, sources);
2239
2240         err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
2241         err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
2242
2243         if (err)
2244                 return 1;
2245
2246         /* Step 2a : make sure trigger sources are unique */
2247
2248         err |= cfc_check_trigger_is_unique(cmd->start_src);
2249         err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
2250         err |= cfc_check_trigger_is_unique(cmd->convert_src);
2251         err |= cfc_check_trigger_is_unique(cmd->stop_src);
2252
2253         /* Step 2b : and mutually compatible */
2254
2255         if (err)
2256                 return 2;
2257
2258         /* Step 3: check if arguments are trivially valid */
2259
2260         if (cmd->start_src == TRIG_EXT) {
2261                 /* external trigger */
2262                 unsigned int tmp = CR_CHAN(cmd->start_arg);
2263
2264                 if (tmp > 16)
2265                         tmp = 16;
2266                 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
2267                 err |= cfc_check_trigger_arg_is(&cmd->start_arg, tmp);
2268         } else {
2269                 /* true for both TRIG_NOW and TRIG_INT */
2270                 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
2271         }
2272
2273         if (cmd->scan_begin_src == TRIG_TIMER) {
2274                 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
2275                         ni_min_ai_scan_period_ns(dev, cmd->chanlist_len));
2276                 err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg,
2277                                                  devpriv->clock_ns * 0xffffff);
2278         } else if (cmd->scan_begin_src == TRIG_EXT) {
2279                 /* external trigger */
2280                 unsigned int tmp = CR_CHAN(cmd->scan_begin_arg);
2281
2282                 if (tmp > 16)
2283                         tmp = 16;
2284                 tmp |= (cmd->scan_begin_arg & (CR_INVERT | CR_EDGE));
2285                 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, tmp);
2286         } else {                /* TRIG_OTHER */
2287                 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
2288         }
2289
2290         if (cmd->convert_src == TRIG_TIMER) {
2291                 if ((board->reg_type == ni_reg_611x)
2292                     || (board->reg_type == ni_reg_6143)) {
2293                         err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
2294                 } else {
2295                         err |= cfc_check_trigger_arg_min(&cmd->convert_arg,
2296                                                          board->ai_speed);
2297                         err |= cfc_check_trigger_arg_max(&cmd->convert_arg,
2298                                                 devpriv->clock_ns * 0xffff);
2299                 }
2300         } else if (cmd->convert_src == TRIG_EXT) {
2301                 /* external trigger */
2302                 unsigned int tmp = CR_CHAN(cmd->convert_arg);
2303
2304                 if (tmp > 16)
2305                         tmp = 16;
2306                 tmp |= (cmd->convert_arg & (CR_ALT_FILTER | CR_INVERT));
2307                 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, tmp);
2308         } else if (cmd->convert_src == TRIG_NOW) {
2309                 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
2310         }
2311
2312         err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
2313
2314         if (cmd->stop_src == TRIG_COUNT) {
2315                 unsigned int max_count = 0x01000000;
2316
2317                 if (board->reg_type == ni_reg_611x)
2318                         max_count -= num_adc_stages_611x;
2319                 err |= cfc_check_trigger_arg_max(&cmd->stop_arg, max_count);
2320                 err |= cfc_check_trigger_arg_min(&cmd->stop_arg, 1);
2321         } else {
2322                 /* TRIG_NONE */
2323                 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
2324         }
2325
2326         if (err)
2327                 return 3;
2328
2329         /* step 4: fix up any arguments */
2330
2331         if (cmd->scan_begin_src == TRIG_TIMER) {
2332                 tmp = cmd->scan_begin_arg;
2333                 cmd->scan_begin_arg =
2334                     ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2335                                                        cmd->scan_begin_arg,
2336                                                        cmd->
2337                                                        flags &
2338                                                        TRIG_ROUND_MASK));
2339                 if (tmp != cmd->scan_begin_arg)
2340                         err++;
2341         }
2342         if (cmd->convert_src == TRIG_TIMER) {
2343                 if ((board->reg_type != ni_reg_611x)
2344                     && (board->reg_type != ni_reg_6143)) {
2345                         tmp = cmd->convert_arg;
2346                         cmd->convert_arg =
2347                             ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2348                                                                cmd->convert_arg,
2349                                                                cmd->
2350                                                                flags &
2351                                                                TRIG_ROUND_MASK));
2352                         if (tmp != cmd->convert_arg)
2353                                 err++;
2354                         if (cmd->scan_begin_src == TRIG_TIMER &&
2355                             cmd->scan_begin_arg <
2356                             cmd->convert_arg * cmd->scan_end_arg) {
2357                                 cmd->scan_begin_arg =
2358                                     cmd->convert_arg * cmd->scan_end_arg;
2359                                 err++;
2360                         }
2361                 }
2362         }
2363
2364         if (err)
2365                 return 4;
2366
2367         return 0;
2368 }
2369
2370 static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2371 {
2372         const struct ni_board_struct *board = comedi_board(dev);
2373         struct ni_private *devpriv = dev->private;
2374         const struct comedi_cmd *cmd = &s->async->cmd;
2375         int timer;
2376         int mode1 = 0;          /* mode1 is needed for both stop and convert */
2377         int mode2 = 0;
2378         int start_stop_select = 0;
2379         unsigned int stop_count;
2380         int interrupt_a_enable = 0;
2381
2382         if (dev->irq == 0) {
2383                 comedi_error(dev, "cannot run command without an irq");
2384                 return -EIO;
2385         }
2386         ni_clear_ai_fifo(dev);
2387
2388         ni_load_channelgain_list(dev, cmd->chanlist_len, cmd->chanlist);
2389
2390         /* start configuration */
2391         devpriv->stc_writew(dev, AI_Configuration_Start, Joint_Reset_Register);
2392
2393         /* disable analog triggering for now, since it
2394          * interferes with the use of pfi0 */
2395         devpriv->an_trig_etc_reg &= ~Analog_Trigger_Enable;
2396         devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
2397                             Analog_Trigger_Etc_Register);
2398
2399         switch (cmd->start_src) {
2400         case TRIG_INT:
2401         case TRIG_NOW:
2402                 devpriv->stc_writew(dev, AI_START2_Select(0) |
2403                                     AI_START1_Sync | AI_START1_Edge |
2404                                     AI_START1_Select(0),
2405                                     AI_Trigger_Select_Register);
2406                 break;
2407         case TRIG_EXT:
2408                 {
2409                         int chan = CR_CHAN(cmd->start_arg);
2410                         unsigned int bits = AI_START2_Select(0) |
2411                             AI_START1_Sync | AI_START1_Select(chan + 1);
2412
2413                         if (cmd->start_arg & CR_INVERT)
2414                                 bits |= AI_START1_Polarity;
2415                         if (cmd->start_arg & CR_EDGE)
2416                                 bits |= AI_START1_Edge;
2417                         devpriv->stc_writew(dev, bits,
2418                                             AI_Trigger_Select_Register);
2419                         break;
2420                 }
2421         }
2422
2423         mode2 &= ~AI_Pre_Trigger;
2424         mode2 &= ~AI_SC_Initial_Load_Source;
2425         mode2 &= ~AI_SC_Reload_Mode;
2426         devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2427
2428         if (cmd->chanlist_len == 1 || (board->reg_type == ni_reg_611x)
2429             || (board->reg_type == ni_reg_6143)) {
2430                 start_stop_select |= AI_STOP_Polarity;
2431                 start_stop_select |= AI_STOP_Select(31);        /*  logic low */
2432                 start_stop_select |= AI_STOP_Sync;
2433         } else {
2434                 start_stop_select |= AI_STOP_Select(19);        /*  ai configuration memory */
2435         }
2436         devpriv->stc_writew(dev, start_stop_select,
2437                             AI_START_STOP_Select_Register);
2438
2439         devpriv->ai_cmd2 = 0;
2440         switch (cmd->stop_src) {
2441         case TRIG_COUNT:
2442                 stop_count = cmd->stop_arg - 1;
2443
2444                 if (board->reg_type == ni_reg_611x) {
2445                         /*  have to take 3 stage adc pipeline into account */
2446                         stop_count += num_adc_stages_611x;
2447                 }
2448                 /* stage number of scans */
2449                 devpriv->stc_writel(dev, stop_count, AI_SC_Load_A_Registers);
2450
2451                 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Trigger_Once;
2452                 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register);
2453                 /* load SC (Scan Count) */
2454                 devpriv->stc_writew(dev, AI_SC_Load, AI_Command_1_Register);
2455
2456                 devpriv->ai_continuous = 0;
2457                 if (stop_count == 0) {
2458                         devpriv->ai_cmd2 |= AI_End_On_End_Of_Scan;
2459                         interrupt_a_enable |= AI_STOP_Interrupt_Enable;
2460                         /*  this is required to get the last sample for chanlist_len > 1, not sure why */
2461                         if (cmd->chanlist_len > 1)
2462                                 start_stop_select |=
2463                                     AI_STOP_Polarity | AI_STOP_Edge;
2464                 }
2465                 break;
2466         case TRIG_NONE:
2467                 /* stage number of scans */
2468                 devpriv->stc_writel(dev, 0, AI_SC_Load_A_Registers);
2469
2470                 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Continuous;
2471                 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register);
2472
2473                 /* load SC (Scan Count) */
2474                 devpriv->stc_writew(dev, AI_SC_Load, AI_Command_1_Register);
2475
2476                 devpriv->ai_continuous = 1;
2477
2478                 break;
2479         }
2480
2481         switch (cmd->scan_begin_src) {
2482         case TRIG_TIMER:
2483                 /*
2484                    stop bits for non 611x boards
2485                    AI_SI_Special_Trigger_Delay=0
2486                    AI_Pre_Trigger=0
2487                    AI_START_STOP_Select_Register:
2488                    AI_START_Polarity=0 (?)      rising edge
2489                    AI_START_Edge=1              edge triggered
2490                    AI_START_Sync=1 (?)
2491                    AI_START_Select=0            SI_TC
2492                    AI_STOP_Polarity=0           rising edge
2493                    AI_STOP_Edge=0               level
2494                    AI_STOP_Sync=1
2495                    AI_STOP_Select=19            external pin (configuration mem)
2496                  */
2497                 start_stop_select |= AI_START_Edge | AI_START_Sync;
2498                 devpriv->stc_writew(dev, start_stop_select,
2499                                     AI_START_STOP_Select_Register);
2500
2501                 mode2 |= AI_SI_Reload_Mode(0);
2502                 /* AI_SI_Initial_Load_Source=A */
2503                 mode2 &= ~AI_SI_Initial_Load_Source;
2504                 /* mode2 |= AI_SC_Reload_Mode; */
2505                 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2506
2507                 /* load SI */
2508                 timer = ni_ns_to_timer(dev, cmd->scan_begin_arg,
2509                                        TRIG_ROUND_NEAREST);
2510                 devpriv->stc_writel(dev, timer, AI_SI_Load_A_Registers);
2511                 devpriv->stc_writew(dev, AI_SI_Load, AI_Command_1_Register);
2512                 break;
2513         case TRIG_EXT:
2514                 if (cmd->scan_begin_arg & CR_EDGE)
2515                         start_stop_select |= AI_START_Edge;
2516                 /* AI_START_Polarity==1 is falling edge */
2517                 if (cmd->scan_begin_arg & CR_INVERT)
2518                         start_stop_select |= AI_START_Polarity;
2519                 if (cmd->scan_begin_src != cmd->convert_src ||
2520                     (cmd->scan_begin_arg & ~CR_EDGE) !=
2521                     (cmd->convert_arg & ~CR_EDGE))
2522                         start_stop_select |= AI_START_Sync;
2523                 start_stop_select |=
2524                     AI_START_Select(1 + CR_CHAN(cmd->scan_begin_arg));
2525                 devpriv->stc_writew(dev, start_stop_select,
2526                                     AI_START_STOP_Select_Register);
2527                 break;
2528         }
2529
2530         switch (cmd->convert_src) {
2531         case TRIG_TIMER:
2532         case TRIG_NOW:
2533                 if (cmd->convert_arg == 0 || cmd->convert_src == TRIG_NOW)
2534                         timer = 1;
2535                 else
2536                         timer = ni_ns_to_timer(dev, cmd->convert_arg,
2537                                                TRIG_ROUND_NEAREST);
2538                 devpriv->stc_writew(dev, 1, AI_SI2_Load_A_Register);    /* 0,0 does not work. */
2539                 devpriv->stc_writew(dev, timer, AI_SI2_Load_B_Register);
2540
2541                 /* AI_SI2_Reload_Mode = alternate */
2542                 /* AI_SI2_Initial_Load_Source = A */
2543                 mode2 &= ~AI_SI2_Initial_Load_Source;
2544                 mode2 |= AI_SI2_Reload_Mode;
2545                 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2546
2547                 /* AI_SI2_Load */
2548                 devpriv->stc_writew(dev, AI_SI2_Load, AI_Command_1_Register);
2549
2550                 mode2 |= AI_SI2_Reload_Mode;    /*  alternate */
2551                 mode2 |= AI_SI2_Initial_Load_Source;    /*  B */
2552
2553                 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2554                 break;
2555         case TRIG_EXT:
2556                 mode1 |= AI_CONVERT_Source_Select(1 + cmd->convert_arg);
2557                 if ((cmd->convert_arg & CR_INVERT) == 0)
2558                         mode1 |= AI_CONVERT_Source_Polarity;
2559                 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register);
2560
2561                 mode2 |= AI_Start_Stop_Gate_Enable | AI_SC_Gate_Enable;
2562                 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2563
2564                 break;
2565         }
2566
2567         if (dev->irq) {
2568
2569                 /* interrupt on FIFO, errors, SC_TC */
2570                 interrupt_a_enable |= AI_Error_Interrupt_Enable |
2571                     AI_SC_TC_Interrupt_Enable;
2572
2573 #ifndef PCIDMA
2574                 interrupt_a_enable |= AI_FIFO_Interrupt_Enable;
2575 #endif
2576
2577                 if (cmd->flags & TRIG_WAKE_EOS
2578                     || (devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)) {
2579                         /* wake on end-of-scan */
2580                         devpriv->aimode = AIMODE_SCAN;
2581                 } else {
2582                         devpriv->aimode = AIMODE_HALF_FULL;
2583                 }
2584
2585                 switch (devpriv->aimode) {
2586                 case AIMODE_HALF_FULL:
2587                         /*generate FIFO interrupts and DMA requests on half-full */
2588 #ifdef PCIDMA
2589                         devpriv->stc_writew(dev, AI_FIFO_Mode_HF_to_E,
2590                                             AI_Mode_3_Register);
2591 #else
2592                         devpriv->stc_writew(dev, AI_FIFO_Mode_HF,
2593                                             AI_Mode_3_Register);
2594 #endif
2595                         break;
2596                 case AIMODE_SAMPLE:
2597                         /*generate FIFO interrupts on non-empty */
2598                         devpriv->stc_writew(dev, AI_FIFO_Mode_NE,
2599                                             AI_Mode_3_Register);
2600                         break;
2601                 case AIMODE_SCAN:
2602 #ifdef PCIDMA
2603                         devpriv->stc_writew(dev, AI_FIFO_Mode_NE,
2604                                             AI_Mode_3_Register);
2605 #else
2606                         devpriv->stc_writew(dev, AI_FIFO_Mode_HF,
2607                                             AI_Mode_3_Register);
2608 #endif
2609                         interrupt_a_enable |= AI_STOP_Interrupt_Enable;
2610                         break;
2611                 default:
2612                         break;
2613                 }
2614
2615                 devpriv->stc_writew(dev, AI_Error_Interrupt_Ack | AI_STOP_Interrupt_Ack | AI_START_Interrupt_Ack | AI_START2_Interrupt_Ack | AI_START1_Interrupt_Ack | AI_SC_TC_Interrupt_Ack | AI_SC_TC_Error_Confirm, Interrupt_A_Ack_Register);      /* clear interrupts */
2616
2617                 ni_set_bits(dev, Interrupt_A_Enable_Register,
2618                             interrupt_a_enable, 1);
2619         } else {
2620                 /* interrupt on nothing */
2621                 ni_set_bits(dev, Interrupt_A_Enable_Register, ~0, 0);
2622
2623                 /* XXX start polling if necessary */
2624         }
2625
2626         /* end configuration */
2627         devpriv->stc_writew(dev, AI_Configuration_End, Joint_Reset_Register);
2628
2629         switch (cmd->scan_begin_src) {
2630         case TRIG_TIMER:
2631                 devpriv->stc_writew(dev,
2632                                     AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm |
2633                                     AI_SC_Arm, AI_Command_1_Register);
2634                 break;
2635         case TRIG_EXT:
2636                 /* XXX AI_SI_Arm? */
2637                 devpriv->stc_writew(dev,
2638                                     AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm |
2639                                     AI_SC_Arm, AI_Command_1_Register);
2640                 break;
2641         }
2642
2643 #ifdef PCIDMA
2644         {
2645                 int retval = ni_ai_setup_MITE_dma(dev);
2646                 if (retval)
2647                         return retval;
2648         }
2649 #endif
2650
2651         switch (cmd->start_src) {
2652         case TRIG_NOW:
2653                 /* AI_START1_Pulse */
2654                 devpriv->stc_writew(dev, AI_START1_Pulse | devpriv->ai_cmd2,
2655                                     AI_Command_2_Register);
2656                 s->async->inttrig = NULL;
2657                 break;
2658         case TRIG_EXT:
2659                 s->async->inttrig = NULL;
2660                 break;
2661         case TRIG_INT:
2662                 s->async->inttrig = &ni_ai_inttrig;
2663                 break;
2664         }
2665
2666         return 0;
2667 }
2668
2669 static int ni_ai_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
2670                          unsigned int trignum)
2671 {
2672         struct ni_private *devpriv = dev->private;
2673
2674         if (trignum != 0)
2675                 return -EINVAL;
2676
2677         devpriv->stc_writew(dev, AI_START1_Pulse | devpriv->ai_cmd2,
2678                             AI_Command_2_Register);
2679         s->async->inttrig = NULL;
2680
2681         return 1;
2682 }
2683
2684 static int ni_ai_config_analog_trig(struct comedi_device *dev,
2685                                     struct comedi_subdevice *s,
2686                                     struct comedi_insn *insn,
2687                                     unsigned int *data);
2688
2689 static int ni_ai_insn_config(struct comedi_device *dev,
2690                              struct comedi_subdevice *s,
2691                              struct comedi_insn *insn, unsigned int *data)
2692 {
2693         const struct ni_board_struct *board = comedi_board(dev);
2694         struct ni_private *devpriv = dev->private;
2695
2696         if (insn->n < 1)
2697                 return -EINVAL;
2698
2699         switch (data[0]) {
2700         case INSN_CONFIG_ANALOG_TRIG:
2701                 return ni_ai_config_analog_trig(dev, s, insn, data);
2702         case INSN_CONFIG_ALT_SOURCE:
2703                 if (board->reg_type & ni_reg_m_series_mask) {
2704                         if (data[1] & ~(MSeries_AI_Bypass_Cal_Sel_Pos_Mask |
2705                                         MSeries_AI_Bypass_Cal_Sel_Neg_Mask |
2706                                         MSeries_AI_Bypass_Mode_Mux_Mask |
2707                                         MSeries_AO_Bypass_AO_Cal_Sel_Mask)) {
2708                                 return -EINVAL;
2709                         }
2710                         devpriv->ai_calib_source = data[1];
2711                 } else if (board->reg_type == ni_reg_6143) {
2712                         unsigned int calib_source;
2713
2714                         calib_source = data[1] & 0xf;
2715
2716                         if (calib_source > 0xF)
2717                                 return -EINVAL;
2718
2719                         devpriv->ai_calib_source = calib_source;
2720                         ni_writew(calib_source, Calibration_Channel_6143);
2721                 } else {
2722                         unsigned int calib_source;
2723                         unsigned int calib_source_adjust;
2724
2725                         calib_source = data[1] & 0xf;
2726                         calib_source_adjust = (data[1] >> 4) & 0xff;
2727
2728                         if (calib_source >= 8)
2729                                 return -EINVAL;
2730                         devpriv->ai_calib_source = calib_source;
2731                         if (board->reg_type == ni_reg_611x) {
2732                                 ni_writeb(calib_source_adjust,
2733                                           Cal_Gain_Select_611x);
2734                         }
2735                 }
2736                 return 2;
2737         default:
2738                 break;
2739         }
2740
2741         return -EINVAL;
2742 }
2743
2744 static int ni_ai_config_analog_trig(struct comedi_device *dev,
2745                                     struct comedi_subdevice *s,
2746                                     struct comedi_insn *insn,
2747                                     unsigned int *data)
2748 {
2749         const struct ni_board_struct *board = comedi_board(dev);
2750         struct ni_private *devpriv = dev->private;
2751         unsigned int a, b, modebits;
2752         int err = 0;
2753
2754         /* data[1] is flags
2755          * data[2] is analog line
2756          * data[3] is set level
2757          * data[4] is reset level */
2758         if (!board->has_analog_trig)
2759                 return -EINVAL;
2760         if ((data[1] & 0xffff0000) != COMEDI_EV_SCAN_BEGIN) {
2761                 data[1] &= (COMEDI_EV_SCAN_BEGIN | 0xffff);
2762                 err++;
2763         }
2764         if (data[2] >= board->n_adchan) {
2765                 data[2] = board->n_adchan - 1;
2766                 err++;
2767         }
2768         if (data[3] > 255) {    /* a */
2769                 data[3] = 255;
2770                 err++;
2771         }
2772         if (data[4] > 255) {    /* b */
2773                 data[4] = 255;
2774                 err++;
2775         }
2776         /*
2777          * 00 ignore
2778          * 01 set
2779          * 10 reset
2780          *
2781          * modes:
2782          *   1 level:                    +b-   +a-
2783          *     high mode                00 00 01 10
2784          *     low mode                 00 00 10 01
2785          *   2 level: (a<b)
2786          *     hysteresis low mode      10 00 00 01
2787          *     hysteresis high mode     01 00 00 10
2788          *     middle mode              10 01 01 10
2789          */
2790
2791         a = data[3];
2792         b = data[4];
2793         modebits = data[1] & 0xff;
2794         if (modebits & 0xf0) {
2795                 /* two level mode */
2796                 if (b < a) {
2797                         /* swap order */
2798                         a = data[4];
2799                         b = data[3];
2800                         modebits =
2801                             ((data[1] & 0xf) << 4) | ((data[1] & 0xf0) >> 4);
2802                 }
2803                 devpriv->atrig_low = a;
2804                 devpriv->atrig_high = b;
2805                 switch (modebits) {
2806                 case 0x81:      /* low hysteresis mode */
2807                         devpriv->atrig_mode = 6;
2808                         break;
2809                 case 0x42:      /* high hysteresis mode */
2810                         devpriv->atrig_mode = 3;
2811                         break;
2812                 case 0x96:      /* middle window mode */
2813                         devpriv->atrig_mode = 2;
2814                         break;
2815                 default:
2816                         data[1] &= ~0xff;
2817                         err++;
2818                 }
2819         } else {
2820                 /* one level mode */
2821                 if (b != 0) {
2822                         data[4] = 0;
2823                         err++;
2824                 }
2825                 switch (modebits) {
2826                 case 0x06:      /* high window mode */
2827                         devpriv->atrig_high = a;
2828                         devpriv->atrig_mode = 0;
2829                         break;
2830                 case 0x09:      /* low window mode */
2831                         devpriv->atrig_low = a;
2832                         devpriv->atrig_mode = 1;
2833                         break;
2834                 default:
2835                         data[1] &= ~0xff;
2836                         err++;
2837                 }
2838         }
2839         if (err)
2840                 return -EAGAIN;
2841         return 5;
2842 }
2843
2844 /* munge data from unsigned to 2's complement for analog output bipolar modes */
2845 static void ni_ao_munge(struct comedi_device *dev, struct comedi_subdevice *s,
2846                         void *data, unsigned int num_bytes,
2847                         unsigned int chan_index)
2848 {
2849         const struct ni_board_struct *board = comedi_board(dev);
2850         struct comedi_async *async = s->async;
2851         unsigned int range;
2852         unsigned int i;
2853         unsigned int offset;
2854         unsigned int length = num_bytes / sizeof(short);
2855         unsigned short *array = data;
2856
2857         offset = 1 << (board->aobits - 1);
2858         for (i = 0; i < length; i++) {
2859                 range = CR_RANGE(async->cmd.chanlist[chan_index]);
2860                 if (board->ao_unipolar == 0 || (range & 1) == 0)
2861                         array[i] -= offset;
2862 #ifdef PCIDMA
2863                 array[i] = cpu_to_le16(array[i]);
2864 #endif
2865                 chan_index++;
2866                 chan_index %= async->cmd.chanlist_len;
2867         }
2868 }
2869
2870 static int ni_m_series_ao_config_chanlist(struct comedi_device *dev,
2871                                           struct comedi_subdevice *s,
2872                                           unsigned int chanspec[],
2873                                           unsigned int n_chans, int timed)
2874 {
2875         const struct ni_board_struct *board = comedi_board(dev);
2876         struct ni_private *devpriv = dev->private;
2877         unsigned int range;
2878         unsigned int chan;
2879         unsigned int conf;
2880         int i;
2881         int invert = 0;
2882
2883         if (timed) {
2884                 for (i = 0; i < board->n_aochan; ++i) {
2885                         devpriv->ao_conf[i] &= ~MSeries_AO_Update_Timed_Bit;
2886                         ni_writeb(devpriv->ao_conf[i],
2887                                   M_Offset_AO_Config_Bank(i));
2888                         ni_writeb(0xf, M_Offset_AO_Waveform_Order(i));
2889                 }
2890         }
2891         for (i = 0; i < n_chans; i++) {
2892                 const struct comedi_krange *krange;
2893                 chan = CR_CHAN(chanspec[i]);
2894                 range = CR_RANGE(chanspec[i]);
2895                 krange = s->range_table->range + range;
2896                 invert = 0;
2897                 conf = 0;
2898                 switch (krange->max - krange->min) {
2899                 case 20000000:
2900                         conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2901                         ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan));
2902                         break;
2903                 case 10000000:
2904                         conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2905                         ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan));
2906                         break;
2907                 case 4000000:
2908                         conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2909                         ni_writeb(MSeries_Attenuate_x5_Bit,
2910                                   M_Offset_AO_Reference_Attenuation(chan));
2911                         break;
2912                 case 2000000:
2913                         conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2914                         ni_writeb(MSeries_Attenuate_x5_Bit,
2915                                   M_Offset_AO_Reference_Attenuation(chan));
2916                         break;
2917                 default:
2918                         printk("%s: bug! unhandled ao reference voltage\n",
2919                                __func__);
2920                         break;
2921                 }
2922                 switch (krange->max + krange->min) {
2923                 case 0:
2924                         conf |= MSeries_AO_DAC_Offset_0V_Bits;
2925                         break;
2926                 case 10000000:
2927                         conf |= MSeries_AO_DAC_Offset_5V_Bits;
2928                         break;
2929                 default:
2930                         printk("%s: bug! unhandled ao offset voltage\n",
2931                                __func__);
2932                         break;
2933                 }
2934                 if (timed)
2935                         conf |= MSeries_AO_Update_Timed_Bit;
2936                 ni_writeb(conf, M_Offset_AO_Config_Bank(chan));
2937                 devpriv->ao_conf[chan] = conf;
2938                 ni_writeb(i, M_Offset_AO_Waveform_Order(chan));
2939         }
2940         return invert;
2941 }
2942
2943 static int ni_old_ao_config_chanlist(struct comedi_device *dev,
2944                                      struct comedi_subdevice *s,
2945                                      unsigned int chanspec[],
2946                                      unsigned int n_chans)
2947 {
2948         const struct ni_board_struct *board = comedi_board(dev);
2949         struct ni_private *devpriv = dev->private;
2950         unsigned int range;
2951         unsigned int chan;
2952         unsigned int conf;
2953         int i;
2954         int invert = 0;
2955
2956         for (i = 0; i < n_chans; i++) {
2957                 chan = CR_CHAN(chanspec[i]);
2958                 range = CR_RANGE(chanspec[i]);
2959                 conf = AO_Channel(chan);
2960
2961                 if (board->ao_unipolar) {
2962                         if ((range & 1) == 0) {
2963                                 conf |= AO_Bipolar;
2964                                 invert = (1 << (board->aobits - 1));
2965                         } else {
2966                                 invert = 0;
2967                         }
2968                         if (range & 2)
2969                                 conf |= AO_Ext_Ref;
2970                 } else {
2971                         conf |= AO_Bipolar;
2972                         invert = (1 << (board->aobits - 1));
2973                 }
2974
2975                 /* not all boards can deglitch, but this shouldn't hurt */
2976                 if (chanspec[i] & CR_DEGLITCH)
2977                         conf |= AO_Deglitch;
2978
2979                 /* analog reference */
2980                 /* AREF_OTHER connects AO ground to AI ground, i think */
2981                 conf |= (CR_AREF(chanspec[i]) ==
2982                          AREF_OTHER) ? AO_Ground_Ref : 0;
2983
2984                 ni_writew(conf, AO_Configuration);
2985                 devpriv->ao_conf[chan] = conf;
2986         }
2987         return invert;
2988 }
2989
2990 static int ni_ao_config_chanlist(struct comedi_device *dev,
2991                                  struct comedi_subdevice *s,
2992                                  unsigned int chanspec[], unsigned int n_chans,
2993                                  int timed)
2994 {
2995         const struct ni_board_struct *board = comedi_board(dev);
2996
2997         if (board->reg_type & ni_reg_m_series_mask)
2998                 return ni_m_series_ao_config_chanlist(dev, s, chanspec, n_chans,
2999                                                       timed);
3000         else
3001                 return ni_old_ao_config_chanlist(dev, s, chanspec, n_chans);
3002 }
3003
3004 static int ni_ao_insn_read(struct comedi_device *dev,
3005                            struct comedi_subdevice *s, struct comedi_insn *insn,
3006                            unsigned int *data)
3007 {
3008         struct ni_private *devpriv = dev->private;
3009
3010         data[0] = devpriv->ao[CR_CHAN(insn->chanspec)];
3011
3012         return 1;
3013 }
3014
3015 static int ni_ao_insn_write(struct comedi_device *dev,
3016                             struct comedi_subdevice *s,
3017                             struct comedi_insn *insn, unsigned int *data)
3018 {
3019         const struct ni_board_struct *board = comedi_board(dev);
3020         struct ni_private *devpriv = dev->private;
3021         unsigned int chan = CR_CHAN(insn->chanspec);
3022         unsigned int invert;
3023
3024         invert = ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
3025
3026         devpriv->ao[chan] = data[0];
3027
3028         if (board->reg_type & ni_reg_m_series_mask) {
3029                 ni_writew(data[0], M_Offset_DAC_Direct_Data(chan));
3030         } else
3031                 ni_writew(data[0] ^ invert,
3032                           (chan) ? DAC1_Direct_Data : DAC0_Direct_Data);
3033
3034         return 1;
3035 }
3036
3037 static int ni_ao_insn_write_671x(struct comedi_device *dev,
3038                                  struct comedi_subdevice *s,
3039                                  struct comedi_insn *insn, unsigned int *data)
3040 {
3041         const struct ni_board_struct *board = comedi_board(dev);
3042         struct ni_private *devpriv = dev->private;
3043         unsigned int chan = CR_CHAN(insn->chanspec);
3044         unsigned int invert;
3045
3046         ao_win_out(1 << chan, AO_Immediate_671x);
3047         invert = 1 << (board->aobits - 1);
3048
3049         ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
3050
3051         devpriv->ao[chan] = data[0];
3052         ao_win_out(data[0] ^ invert, DACx_Direct_Data_671x(chan));
3053
3054         return 1;
3055 }
3056
3057 static int ni_ao_insn_config(struct comedi_device *dev,
3058                              struct comedi_subdevice *s,
3059                              struct comedi_insn *insn, unsigned int *data)
3060 {
3061         const struct ni_board_struct *board = comedi_board(dev);
3062         struct ni_private *devpriv = dev->private;
3063
3064         switch (data[0]) {
3065         case INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE:
3066                 switch (data[1]) {
3067                 case COMEDI_OUTPUT:
3068                         data[2] = 1 + board->ao_fifo_depth * sizeof(short);
3069                         if (devpriv->mite)
3070                                 data[2] += devpriv->mite->fifo_size;
3071                         break;
3072                 case COMEDI_INPUT:
3073                         data[2] = 0;
3074                         break;
3075                 default:
3076                         return -EINVAL;
3077                         break;
3078                 }
3079                 return 0;
3080         default:
3081                 break;
3082         }
3083
3084         return -EINVAL;
3085 }
3086
3087 static int ni_ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
3088                          unsigned int trignum)
3089 {
3090         const struct ni_board_struct *board __maybe_unused = comedi_board(dev);
3091         struct ni_private *devpriv = dev->private;
3092         int ret;
3093         int interrupt_b_bits;
3094         int i;
3095         static const int timeout = 1000;
3096
3097         if (trignum != 0)
3098                 return -EINVAL;
3099
3100         /* Null trig at beginning prevent ao start trigger from executing more than
3101            once per command (and doing things like trying to allocate the ao dma channel
3102            multiple times) */
3103         s->async->inttrig = NULL;
3104
3105         ni_set_bits(dev, Interrupt_B_Enable_Register,
3106                     AO_FIFO_Interrupt_Enable | AO_Error_Interrupt_Enable, 0);
3107         interrupt_b_bits = AO_Error_Interrupt_Enable;
3108 #ifdef PCIDMA
3109         devpriv->stc_writew(dev, 1, DAC_FIFO_Clear);
3110         if (board->reg_type & ni_reg_6xxx_mask)
3111                 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
3112         ret = ni_ao_setup_MITE_dma(dev);
3113         if (ret)
3114                 return ret;
3115         ret = ni_ao_wait_for_dma_load(dev);
3116         if (ret < 0)
3117                 return ret;
3118 #else
3119         ret = ni_ao_prep_fifo(dev, s);
3120         if (ret == 0)
3121                 return -EPIPE;
3122
3123         interrupt_b_bits |= AO_FIFO_Interrupt_Enable;
3124 #endif
3125
3126         devpriv->stc_writew(dev, devpriv->ao_mode3 | AO_Not_An_UPDATE,
3127                             AO_Mode_3_Register);
3128         devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3129         /* wait for DACs to be loaded */
3130         for (i = 0; i < timeout; i++) {
3131                 udelay(1);
3132                 if ((devpriv->stc_readw(dev,
3133                                         Joint_Status_2_Register) &
3134                      AO_TMRDACWRs_In_Progress_St) == 0)
3135                         break;
3136         }
3137         if (i == timeout) {
3138                 comedi_error(dev,
3139                              "timed out waiting for AO_TMRDACWRs_In_Progress_St to clear");
3140                 return -EIO;
3141         }
3142         /*  stc manual says we are need to clear error interrupt after AO_TMRDACWRs_In_Progress_St clears */
3143         devpriv->stc_writew(dev, AO_Error_Interrupt_Ack,
3144                             Interrupt_B_Ack_Register);
3145
3146         ni_set_bits(dev, Interrupt_B_Enable_Register, interrupt_b_bits, 1);
3147
3148         devpriv->stc_writew(dev,
3149                             devpriv->ao_cmd1 | AO_UI_Arm | AO_UC_Arm | AO_BC_Arm
3150                             | AO_DAC1_Update_Mode | AO_DAC0_Update_Mode,
3151                             AO_Command_1_Register);
3152
3153         devpriv->stc_writew(dev, devpriv->ao_cmd2 | AO_START1_Pulse,
3154                             AO_Command_2_Register);
3155
3156         return 0;
3157 }
3158
3159 static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3160 {
3161         const struct ni_board_struct *board = comedi_board(dev);
3162         struct ni_private *devpriv = dev->private;
3163         const struct comedi_cmd *cmd = &s->async->cmd;
3164         int bits;
3165         int i;
3166         unsigned trigvar;
3167
3168         if (dev->irq == 0) {
3169                 comedi_error(dev, "cannot run command without an irq");
3170                 return -EIO;
3171         }
3172
3173         devpriv->stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register);
3174
3175         devpriv->stc_writew(dev, AO_Disarm, AO_Command_1_Register);
3176
3177         if (board->reg_type & ni_reg_6xxx_mask) {
3178                 ao_win_out(CLEAR_WG, AO_Misc_611x);
3179
3180                 bits = 0;
3181                 for (i = 0; i < cmd->chanlist_len; i++) {
3182                         int chan;
3183
3184                         chan = CR_CHAN(cmd->chanlist[i]);
3185                         bits |= 1 << chan;
3186                         ao_win_out(chan, AO_Waveform_Generation_611x);
3187                 }
3188                 ao_win_out(bits, AO_Timed_611x);
3189         }
3190
3191         ni_ao_config_chanlist(dev, s, cmd->chanlist, cmd->chanlist_len, 1);
3192
3193         if (cmd->stop_src == TRIG_NONE) {
3194                 devpriv->ao_mode1 |= AO_Continuous;
3195                 devpriv->ao_mode1 &= ~AO_Trigger_Once;
3196         } else {
3197                 devpriv->ao_mode1 &= ~AO_Continuous;
3198                 devpriv->ao_mode1 |= AO_Trigger_Once;
3199         }
3200         devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3201         switch (cmd->start_src) {
3202         case TRIG_INT:
3203         case TRIG_NOW:
3204                 devpriv->ao_trigger_select &=
3205                     ~(AO_START1_Polarity | AO_START1_Select(-1));
3206                 devpriv->ao_trigger_select |= AO_START1_Edge | AO_START1_Sync;
3207                 devpriv->stc_writew(dev, devpriv->ao_trigger_select,
3208                                     AO_Trigger_Select_Register);
3209                 break;
3210         case TRIG_EXT:
3211                 devpriv->ao_trigger_select =
3212                     AO_START1_Select(CR_CHAN(cmd->start_arg) + 1);
3213                 if (cmd->start_arg & CR_INVERT)
3214                         devpriv->ao_trigger_select |= AO_START1_Polarity;       /*  0=active high, 1=active low. see daq-stc 3-24 (p186) */
3215                 if (cmd->start_arg & CR_EDGE)
3216                         devpriv->ao_trigger_select |= AO_START1_Edge;   /*  0=edge detection disabled, 1=enabled */
3217                 devpriv->stc_writew(dev, devpriv->ao_trigger_select,
3218                                     AO_Trigger_Select_Register);
3219                 break;
3220         default:
3221                 BUG();
3222                 break;
3223         }
3224         devpriv->ao_mode3 &= ~AO_Trigger_Length;
3225         devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3226
3227         devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3228         devpriv->ao_mode2 &= ~AO_BC_Initial_Load_Source;
3229         devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3230         if (cmd->stop_src == TRIG_NONE) {
3231                 devpriv->stc_writel(dev, 0xffffff, AO_BC_Load_A_Register);
3232         } else {
3233                 devpriv->stc_writel(dev, 0, AO_BC_Load_A_Register);
3234         }
3235         devpriv->stc_writew(dev, AO_BC_Load, AO_Command_1_Register);
3236         devpriv->ao_mode2 &= ~AO_UC_Initial_Load_Source;
3237         devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3238         switch (cmd->stop_src) {
3239         case TRIG_COUNT:
3240                 if (board->reg_type & ni_reg_m_series_mask) {
3241                         /*  this is how the NI example code does it for m-series boards, verified correct with 6259 */
3242                         devpriv->stc_writel(dev, cmd->stop_arg - 1,
3243                                             AO_UC_Load_A_Register);
3244                         devpriv->stc_writew(dev, AO_UC_Load,
3245                                             AO_Command_1_Register);
3246                 } else {
3247                         devpriv->stc_writel(dev, cmd->stop_arg,
3248                                             AO_UC_Load_A_Register);
3249                         devpriv->stc_writew(dev, AO_UC_Load,
3250                                             AO_Command_1_Register);
3251                         devpriv->stc_writel(dev, cmd->stop_arg - 1,
3252                                             AO_UC_Load_A_Register);
3253                 }
3254                 break;
3255         case TRIG_NONE:
3256                 devpriv->stc_writel(dev, 0xffffff, AO_UC_Load_A_Register);
3257                 devpriv->stc_writew(dev, AO_UC_Load, AO_Command_1_Register);
3258                 devpriv->stc_writel(dev, 0xffffff, AO_UC_Load_A_Register);
3259                 break;
3260         default:
3261                 devpriv->stc_writel(dev, 0, AO_UC_Load_A_Register);
3262                 devpriv->stc_writew(dev, AO_UC_Load, AO_Command_1_Register);
3263                 devpriv->stc_writel(dev, cmd->stop_arg, AO_UC_Load_A_Register);
3264         }
3265
3266         devpriv->ao_mode1 &=
3267             ~(AO_UI_Source_Select(0x1f) | AO_UI_Source_Polarity |
3268               AO_UPDATE_Source_Select(0x1f) | AO_UPDATE_Source_Polarity);
3269         switch (cmd->scan_begin_src) {
3270         case TRIG_TIMER:
3271                 devpriv->ao_cmd2 &= ~AO_BC_Gate_Enable;
3272                 trigvar =
3273                     ni_ns_to_timer(dev, cmd->scan_begin_arg,
3274                                    TRIG_ROUND_NEAREST);
3275                 devpriv->stc_writel(dev, 1, AO_UI_Load_A_Register);
3276                 devpriv->stc_writew(dev, AO_UI_Load, AO_Command_1_Register);
3277                 devpriv->stc_writel(dev, trigvar, AO_UI_Load_A_Register);
3278                 break;
3279         case TRIG_EXT:
3280                 devpriv->ao_mode1 |=
3281                     AO_UPDATE_Source_Select(cmd->scan_begin_arg);
3282                 if (cmd->scan_begin_arg & CR_INVERT)
3283                         devpriv->ao_mode1 |= AO_UPDATE_Source_Polarity;
3284                 devpriv->ao_cmd2 |= AO_BC_Gate_Enable;
3285                 break;
3286         default:
3287                 BUG();
3288                 break;
3289         }
3290         devpriv->stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register);
3291         devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3292         devpriv->ao_mode2 &=
3293             ~(AO_UI_Reload_Mode(3) | AO_UI_Initial_Load_Source);
3294         devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3295
3296         if (cmd->scan_end_arg > 1) {
3297                 devpriv->ao_mode1 |= AO_Multiple_Channels;
3298                 devpriv->stc_writew(dev,
3299                                     AO_Number_Of_Channels(cmd->scan_end_arg -
3300                                                           1) |
3301                                     AO_UPDATE_Output_Select
3302                                     (AO_Update_Output_High_Z),
3303                                     AO_Output_Control_Register);
3304         } else {
3305                 unsigned bits;
3306                 devpriv->ao_mode1 &= ~AO_Multiple_Channels;
3307                 bits = AO_UPDATE_Output_Select(AO_Update_Output_High_Z);
3308                 if (board->reg_type &
3309                     (ni_reg_m_series_mask | ni_reg_6xxx_mask)) {
3310                         bits |= AO_Number_Of_Channels(0);
3311                 } else {
3312                         bits |=
3313                             AO_Number_Of_Channels(CR_CHAN(cmd->chanlist[0]));
3314                 }
3315                 devpriv->stc_writew(dev, bits, AO_Output_Control_Register);
3316         }
3317         devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3318
3319         devpriv->stc_writew(dev, AO_DAC0_Update_Mode | AO_DAC1_Update_Mode,
3320                             AO_Command_1_Register);
3321
3322         devpriv->ao_mode3 |= AO_Stop_On_Overrun_Error;
3323         devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3324
3325         devpriv->ao_mode2 &= ~AO_FIFO_Mode_Mask;
3326 #ifdef PCIDMA
3327         devpriv->ao_mode2 |= AO_FIFO_Mode_HF_to_F;
3328 #else
3329         devpriv->ao_mode2 |= AO_FIFO_Mode_HF;
3330 #endif
3331         devpriv->ao_mode2 &= ~AO_FIFO_Retransmit_Enable;
3332         devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3333
3334         bits = AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
3335             AO_TMRDACWR_Pulse_Width;
3336         if (board->ao_fifo_depth)
3337                 bits |= AO_FIFO_Enable;
3338         else
3339                 bits |= AO_DMA_PIO_Control;
3340 #if 0
3341         /* F Hess: windows driver does not set AO_Number_Of_DAC_Packages bit for 6281,
3342            verified with bus analyzer. */
3343         if (board->reg_type & ni_reg_m_series_mask)
3344                 bits |= AO_Number_Of_DAC_Packages;
3345 #endif
3346         devpriv->stc_writew(dev, bits, AO_Personal_Register);
3347         /*  enable sending of ao dma requests */
3348         devpriv->stc_writew(dev, AO_AOFREQ_Enable, AO_Start_Select_Register);
3349
3350         devpriv->stc_writew(dev, AO_Configuration_End, Joint_Reset_Register);
3351
3352         if (cmd->stop_src == TRIG_COUNT) {
3353                 devpriv->stc_writew(dev, AO_BC_TC_Interrupt_Ack,
3354                                     Interrupt_B_Ack_Register);
3355                 ni_set_bits(dev, Interrupt_B_Enable_Register,
3356                             AO_BC_TC_Interrupt_Enable, 1);
3357         }
3358
3359         s->async->inttrig = &ni_ao_inttrig;
3360
3361         return 0;
3362 }
3363
3364 static int ni_ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
3365                          struct comedi_cmd *cmd)
3366 {
3367         const struct ni_board_struct *board = comedi_board(dev);
3368         struct ni_private *devpriv = dev->private;
3369         int err = 0;
3370         int tmp;
3371
3372         /* Step 1 : check if triggers are trivially valid */
3373
3374         if ((cmd->flags & CMDF_WRITE) == 0)
3375                 cmd->flags |= CMDF_WRITE;
3376
3377         err |= cfc_check_trigger_src(&cmd->start_src, TRIG_INT | TRIG_EXT);
3378         err |= cfc_check_trigger_src(&cmd->scan_begin_src,
3379                                         TRIG_TIMER | TRIG_EXT);
3380         err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3381         err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3382         err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
3383
3384         if (err)
3385                 return 1;
3386
3387         /* Step 2a : make sure trigger sources are unique */
3388
3389         err |= cfc_check_trigger_is_unique(cmd->start_src);
3390         err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
3391         err |= cfc_check_trigger_is_unique(cmd->stop_src);
3392
3393         /* Step 2b : and mutually compatible */
3394
3395         if (err)
3396                 return 2;
3397
3398         /* Step 3: check if arguments are trivially valid */
3399
3400         if (cmd->start_src == TRIG_EXT) {
3401                 /* external trigger */
3402                 unsigned int tmp = CR_CHAN(cmd->start_arg);
3403
3404                 if (tmp > 18)
3405                         tmp = 18;
3406                 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
3407                 err |= cfc_check_trigger_arg_is(&cmd->start_arg, tmp);
3408         } else {
3409                 /* true for both TRIG_NOW and TRIG_INT */
3410                 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
3411         }
3412
3413         if (cmd->scan_begin_src == TRIG_TIMER) {
3414                 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
3415                                                  board->ao_speed);
3416                 err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg,
3417                                                  devpriv->clock_ns * 0xffffff);
3418         }
3419
3420         err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
3421         err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
3422
3423         if (cmd->stop_src == TRIG_COUNT)
3424                 err |= cfc_check_trigger_arg_max(&cmd->stop_arg, 0x00ffffff);
3425         else    /* TRIG_NONE */
3426                 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
3427
3428         if (err)
3429                 return 3;
3430
3431         /* step 4: fix up any arguments */
3432         if (cmd->scan_begin_src == TRIG_TIMER) {
3433                 tmp = cmd->scan_begin_arg;
3434                 cmd->scan_begin_arg =
3435                     ni_timer_to_ns(dev, ni_ns_to_timer(dev,
3436                                                        cmd->scan_begin_arg,
3437                                                        cmd->
3438                                                        flags &
3439                                                        TRIG_ROUND_MASK));
3440                 if (tmp != cmd->scan_begin_arg)
3441                         err++;
3442         }
3443         if (err)
3444                 return 4;
3445
3446         /* step 5: fix up chanlist */
3447
3448         if (err)
3449                 return 5;
3450
3451         return 0;
3452 }
3453
3454 static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s)
3455 {
3456         const struct ni_board_struct *board = comedi_board(dev);
3457         struct ni_private *devpriv = dev->private;
3458
3459         /* devpriv->ao0p=0x0000; */
3460         /* ni_writew(devpriv->ao0p,AO_Configuration); */
3461
3462         /* devpriv->ao1p=AO_Channel(1); */
3463         /* ni_writew(devpriv->ao1p,AO_Configuration); */
3464
3465         ni_release_ao_mite_channel(dev);
3466
3467         devpriv->stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register);
3468         devpriv->stc_writew(dev, AO_Disarm, AO_Command_1_Register);
3469         ni_set_bits(dev, Interrupt_B_Enable_Register, ~0, 0);
3470         devpriv->stc_writew(dev, AO_BC_Source_Select, AO_Personal_Register);
3471         devpriv->stc_writew(dev, 0x3f98, Interrupt_B_Ack_Register);
3472         devpriv->stc_writew(dev, AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
3473                             AO_TMRDACWR_Pulse_Width, AO_Personal_Register);
3474         devpriv->stc_writew(dev, 0, AO_Output_Control_Register);
3475         devpriv->stc_writew(dev, 0, AO_Start_Select_Register);
3476         devpriv->ao_cmd1 = 0;
3477         devpriv->stc_writew(dev, devpriv->ao_cmd1, AO_Command_1_Register);
3478         devpriv->ao_cmd2 = 0;
3479         devpriv->stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register);
3480         devpriv->ao_mode1 = 0;
3481         devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3482         devpriv->ao_mode2 = 0;
3483         devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3484         if (board->reg_type & ni_reg_m_series_mask)
3485                 devpriv->ao_mode3 = AO_Last_Gate_Disable;
3486         else
3487                 devpriv->ao_mode3 = 0;
3488         devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3489         devpriv->ao_trigger_select = 0;
3490         devpriv->stc_writew(dev, devpriv->ao_trigger_select,
3491                             AO_Trigger_Select_Register);
3492         if (board->reg_type & ni_reg_6xxx_mask) {
3493                 unsigned immediate_bits = 0;
3494                 unsigned i;
3495                 for (i = 0; i < s->n_chan; ++i) {
3496                         immediate_bits |= 1 << i;
3497                 }
3498                 ao_win_out(immediate_bits, AO_Immediate_671x);
3499                 ao_win_out(CLEAR_WG, AO_Misc_611x);
3500         }
3501         devpriv->stc_writew(dev, AO_Configuration_End, Joint_Reset_Register);
3502
3503         return 0;
3504 }
3505
3506 /* digital io */
3507
3508 static int ni_dio_insn_config(struct comedi_device *dev,
3509                               struct comedi_subdevice *s,
3510                               struct comedi_insn *insn,
3511                               unsigned int *data)
3512 {
3513         struct ni_private *devpriv = dev->private;
3514         int ret;
3515
3516         ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3517         if (ret)
3518                 return ret;
3519
3520         devpriv->dio_control &= ~DIO_Pins_Dir_Mask;
3521         devpriv->dio_control |= DIO_Pins_Dir(s->io_bits);
3522         devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3523
3524         return insn->n;
3525 }
3526
3527 static int ni_dio_insn_bits(struct comedi_device *dev,
3528                             struct comedi_subdevice *s,
3529                             struct comedi_insn *insn,
3530                             unsigned int *data)
3531 {
3532         struct ni_private *devpriv = dev->private;
3533
3534         /* Make sure we're not using the serial part of the dio */
3535         if ((data[0] & (DIO_SDIN | DIO_SDOUT)) && devpriv->serial_interval_ns)
3536                 return -EBUSY;
3537
3538         if (comedi_dio_update_state(s, data)) {
3539                 devpriv->dio_output &= ~DIO_Parallel_Data_Mask;
3540                 devpriv->dio_output |= DIO_Parallel_Data_Out(s->state);
3541                 devpriv->stc_writew(dev, devpriv->dio_output,
3542                                     DIO_Output_Register);
3543         }
3544
3545         data[1] = devpriv->stc_readw(dev, DIO_Parallel_Input_Register);
3546
3547         return insn->n;
3548 }
3549
3550 static int ni_m_series_dio_insn_config(struct comedi_device *dev,
3551                                        struct comedi_subdevice *s,
3552                                        struct comedi_insn *insn,
3553                                        unsigned int *data)
3554 {
3555         struct ni_private *devpriv __maybe_unused = dev->private;
3556         int ret;
3557
3558         ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3559         if (ret)
3560                 return ret;
3561
3562         ni_writel(s->io_bits, M_Offset_DIO_Direction);
3563
3564         return insn->n;
3565 }
3566
3567 static int ni_m_series_dio_insn_bits(struct comedi_device *dev,
3568                                      struct comedi_subdevice *s,
3569                                      struct comedi_insn *insn,
3570                                      unsigned int *data)
3571 {
3572         struct ni_private *devpriv __maybe_unused = dev->private;
3573
3574         if (comedi_dio_update_state(s, data))
3575                 ni_writel(s->state, M_Offset_Static_Digital_Output);
3576
3577         data[1] = ni_readl(M_Offset_Static_Digital_Input);
3578
3579         return insn->n;
3580 }
3581
3582 static int ni_cdio_cmdtest(struct comedi_device *dev,
3583                            struct comedi_subdevice *s, struct comedi_cmd *cmd)
3584 {
3585         int err = 0;
3586         int tmp;
3587         unsigned i;
3588
3589         /* Step 1 : check if triggers are trivially valid */
3590
3591         err |= cfc_check_trigger_src(&cmd->start_src, TRIG_INT);
3592         err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
3593         err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3594         err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3595         err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_NONE);
3596
3597         if (err)
3598                 return 1;
3599
3600         /* Step 2a : make sure trigger sources are unique */
3601         /* Step 2b : and mutually compatible */
3602
3603         if (err)
3604                 return 2;
3605
3606         /* Step 3: check if arguments are trivially valid */
3607
3608         err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
3609
3610         tmp = cmd->scan_begin_arg;
3611         tmp &= CR_PACK_FLAGS(CDO_Sample_Source_Select_Mask, 0, 0, CR_INVERT);
3612         if (tmp != cmd->scan_begin_arg)
3613                 err |= -EINVAL;
3614
3615         err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
3616         err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
3617         err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
3618
3619         if (err)
3620                 return 3;
3621
3622         /* step 4: fix up any arguments */
3623
3624         if (err)
3625                 return 4;
3626
3627         /* step 5: check chanlist */
3628
3629         for (i = 0; i < cmd->chanlist_len; ++i) {
3630                 if (cmd->chanlist[i] != i)
3631                         err = 1;
3632         }
3633
3634         if (err)
3635                 return 5;
3636
3637         return 0;
3638 }
3639
3640 static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3641 {
3642         struct ni_private *devpriv __maybe_unused = dev->private;
3643         const struct comedi_cmd *cmd = &s->async->cmd;
3644         unsigned cdo_mode_bits = CDO_FIFO_Mode_Bit | CDO_Halt_On_Error_Bit;
3645         int retval;
3646
3647         ni_writel(CDO_Reset_Bit, M_Offset_CDIO_Command);
3648         switch (cmd->scan_begin_src) {
3649         case TRIG_EXT:
3650                 cdo_mode_bits |=
3651                     CR_CHAN(cmd->scan_begin_arg) &
3652                     CDO_Sample_Source_Select_Mask;
3653                 break;
3654         default:
3655                 BUG();
3656                 break;
3657         }
3658         if (cmd->scan_begin_arg & CR_INVERT)
3659                 cdo_mode_bits |= CDO_Polarity_Bit;
3660         ni_writel(cdo_mode_bits, M_Offset_CDO_Mode);
3661         if (s->io_bits) {
3662                 ni_writel(s->state, M_Offset_CDO_FIFO_Data);
3663                 ni_writel(CDO_SW_Update_Bit, M_Offset_CDIO_Command);
3664                 ni_writel(s->io_bits, M_Offset_CDO_Mask_Enable);
3665         } else {
3666                 comedi_error(dev,
3667                              "attempted to run digital output command with no lines configured as outputs");
3668                 return -EIO;
3669         }
3670         retval = ni_request_cdo_mite_channel(dev);
3671         if (retval < 0) {
3672                 return retval;
3673         }
3674         s->async->inttrig = &ni_cdo_inttrig;
3675         return 0;
3676 }
3677
3678 static int ni_cdo_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
3679                           unsigned int trignum)
3680 {
3681 #ifdef PCIDMA
3682         struct ni_private *devpriv = dev->private;
3683         unsigned long flags;
3684 #endif
3685         int retval = 0;
3686         unsigned i;
3687         const unsigned timeout = 1000;
3688
3689         s->async->inttrig = NULL;
3690
3691         /* read alloc the entire buffer */
3692         comedi_buf_read_alloc(s->async, s->async->prealloc_bufsz);
3693
3694 #ifdef PCIDMA
3695         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3696         if (devpriv->cdo_mite_chan) {
3697                 mite_prep_dma(devpriv->cdo_mite_chan, 32, 32);
3698                 mite_dma_arm(devpriv->cdo_mite_chan);
3699         } else {
3700                 comedi_error(dev, "BUG: no cdo mite channel?");
3701                 retval = -EIO;
3702         }
3703         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3704         if (retval < 0)
3705                 return retval;
3706 #endif
3707 /*
3708 * XXX not sure what interrupt C group does
3709 * ni_writeb(Interrupt_Group_C_Enable_Bit,
3710 * M_Offset_Interrupt_C_Enable); wait for dma to fill output fifo
3711 */
3712         for (i = 0; i < timeout; ++i) {
3713                 if (ni_readl(M_Offset_CDIO_Status) & CDO_FIFO_Full_Bit)
3714                         break;
3715                 udelay(10);
3716         }
3717         if (i == timeout) {
3718                 comedi_error(dev, "dma failed to fill cdo fifo!");
3719                 ni_cdio_cancel(dev, s);
3720                 return -EIO;
3721         }
3722         ni_writel(CDO_Arm_Bit | CDO_Error_Interrupt_Enable_Set_Bit |
3723                   CDO_Empty_FIFO_Interrupt_Enable_Set_Bit,
3724                   M_Offset_CDIO_Command);
3725         return retval;
3726 }
3727
3728 static int ni_cdio_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3729 {
3730         struct ni_private *devpriv __maybe_unused = dev->private;
3731
3732         ni_writel(CDO_Disarm_Bit | CDO_Error_Interrupt_Enable_Clear_Bit |
3733                   CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit |
3734                   CDO_FIFO_Request_Interrupt_Enable_Clear_Bit,
3735                   M_Offset_CDIO_Command);
3736 /*
3737 * XXX not sure what interrupt C group does ni_writeb(0,
3738 * M_Offset_Interrupt_C_Enable);
3739 */
3740         ni_writel(0, M_Offset_CDO_Mask_Enable);
3741         ni_release_cdo_mite_channel(dev);
3742         return 0;
3743 }
3744
3745 static void handle_cdio_interrupt(struct comedi_device *dev)
3746 {
3747         const struct ni_board_struct *board = comedi_board(dev);
3748         struct ni_private *devpriv __maybe_unused = dev->private;
3749         unsigned cdio_status;
3750         struct comedi_subdevice *s = &dev->subdevices[NI_DIO_SUBDEV];
3751 #ifdef PCIDMA
3752         unsigned long flags;
3753 #endif
3754
3755         if ((board->reg_type & ni_reg_m_series_mask) == 0) {
3756                 return;
3757         }
3758 #ifdef PCIDMA
3759         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3760         if (devpriv->cdo_mite_chan) {
3761                 unsigned cdo_mite_status =
3762                     mite_get_status(devpriv->cdo_mite_chan);
3763                 if (cdo_mite_status & CHSR_LINKC) {
3764                         writel(CHOR_CLRLC,
3765                                devpriv->mite->mite_io_addr +
3766                                MITE_CHOR(devpriv->cdo_mite_chan->channel));
3767                 }
3768                 mite_sync_output_dma(devpriv->cdo_mite_chan, s->async);
3769         }
3770         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3771 #endif
3772
3773         cdio_status = ni_readl(M_Offset_CDIO_Status);
3774         if (cdio_status & (CDO_Overrun_Bit | CDO_Underflow_Bit)) {
3775 /* printk("cdio error: statux=0x%x\n", cdio_status); */
3776                 ni_writel(CDO_Error_Interrupt_Confirm_Bit, M_Offset_CDIO_Command);      /*  XXX just guessing this is needed and does something useful */
3777                 s->async->events |= COMEDI_CB_OVERFLOW;
3778         }
3779         if (cdio_status & CDO_FIFO_Empty_Bit) {
3780 /* printk("cdio fifo empty\n"); */
3781                 ni_writel(CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit,
3782                           M_Offset_CDIO_Command);
3783 /* s->async->events |= COMEDI_CB_EOA; */
3784         }
3785         ni_event(dev, s);
3786 }
3787
3788 static int ni_serial_insn_config(struct comedi_device *dev,
3789                                  struct comedi_subdevice *s,
3790                                  struct comedi_insn *insn, unsigned int *data)
3791 {
3792         struct ni_private *devpriv = dev->private;
3793         int err = insn->n;
3794         unsigned char byte_out, byte_in = 0;
3795
3796         if (insn->n != 2)
3797                 return -EINVAL;
3798
3799         switch (data[0]) {
3800         case INSN_CONFIG_SERIAL_CLOCK:
3801                 devpriv->serial_hw_mode = 1;
3802                 devpriv->dio_control |= DIO_HW_Serial_Enable;
3803
3804                 if (data[1] == SERIAL_DISABLED) {
3805                         devpriv->serial_hw_mode = 0;
3806                         devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
3807                                                   DIO_Software_Serial_Control);
3808                         data[1] = SERIAL_DISABLED;
3809                         devpriv->serial_interval_ns = data[1];
3810                 } else if (data[1] <= SERIAL_600NS) {
3811                         /* Warning: this clock speed is too fast to reliably
3812                            control SCXI. */
3813                         devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
3814                         devpriv->clock_and_fout |= Slow_Internal_Timebase;
3815                         devpriv->clock_and_fout &= ~DIO_Serial_Out_Divide_By_2;
3816                         data[1] = SERIAL_600NS;
3817                         devpriv->serial_interval_ns = data[1];
3818                 } else if (data[1] <= SERIAL_1_2US) {
3819                         devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
3820                         devpriv->clock_and_fout |= Slow_Internal_Timebase |
3821                             DIO_Serial_Out_Divide_By_2;
3822                         data[1] = SERIAL_1_2US;
3823                         devpriv->serial_interval_ns = data[1];
3824                 } else if (data[1] <= SERIAL_10US) {
3825                         devpriv->dio_control |= DIO_HW_Serial_Timebase;
3826                         devpriv->clock_and_fout |= Slow_Internal_Timebase |
3827                             DIO_Serial_Out_Divide_By_2;
3828                         /* Note: DIO_Serial_Out_Divide_By_2 only affects
3829                            600ns/1.2us. If you turn divide_by_2 off with the
3830                            slow clock, you will still get 10us, except then
3831                            all your delays are wrong. */
3832                         data[1] = SERIAL_10US;
3833                         devpriv->serial_interval_ns = data[1];
3834                 } else {
3835                         devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
3836                                                   DIO_Software_Serial_Control);
3837                         devpriv->serial_hw_mode = 0;
3838                         data[1] = (data[1] / 1000) * 1000;
3839                         devpriv->serial_interval_ns = data[1];
3840                 }
3841
3842                 devpriv->stc_writew(dev, devpriv->dio_control,
3843                                     DIO_Control_Register);
3844                 devpriv->stc_writew(dev, devpriv->clock_and_fout,
3845                                     Clock_and_FOUT_Register);
3846                 return 1;
3847
3848                 break;
3849
3850         case INSN_CONFIG_BIDIRECTIONAL_DATA:
3851
3852                 if (devpriv->serial_interval_ns == 0) {
3853                         return -EINVAL;
3854                 }
3855
3856                 byte_out = data[1] & 0xFF;
3857
3858                 if (devpriv->serial_hw_mode) {
3859                         err = ni_serial_hw_readwrite8(dev, s, byte_out,
3860                                                       &byte_in);
3861                 } else if (devpriv->serial_interval_ns > 0) {
3862                         err = ni_serial_sw_readwrite8(dev, s, byte_out,
3863                                                       &byte_in);
3864                 } else {
3865                         printk("ni_serial_insn_config: serial disabled!\n");
3866                         return -EINVAL;
3867                 }
3868                 if (err < 0)
3869                         return err;
3870                 data[1] = byte_in & 0xFF;
3871                 return insn->n;
3872
3873                 break;
3874         default:
3875                 return -EINVAL;
3876         }
3877
3878 }
3879
3880 static int ni_serial_hw_readwrite8(struct comedi_device *dev,
3881                                    struct comedi_subdevice *s,
3882                                    unsigned char data_out,
3883                                    unsigned char *data_in)
3884 {
3885         struct ni_private *devpriv = dev->private;
3886         unsigned int status1;
3887         int err = 0, count = 20;
3888
3889         devpriv->dio_output &= ~DIO_Serial_Data_Mask;
3890         devpriv->dio_output |= DIO_Serial_Data_Out(data_out);
3891         devpriv->stc_writew(dev, devpriv->dio_output, DIO_Output_Register);
3892
3893         status1 = devpriv->stc_readw(dev, Joint_Status_1_Register);
3894         if (status1 & DIO_Serial_IO_In_Progress_St) {
3895                 err = -EBUSY;
3896                 goto Error;
3897         }
3898
3899         devpriv->dio_control |= DIO_HW_Serial_Start;
3900         devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3901         devpriv->dio_control &= ~DIO_HW_Serial_Start;
3902
3903         /* Wait until STC says we're done, but don't loop infinitely. */
3904         while ((status1 =
3905                 devpriv->stc_readw(dev,
3906                                    Joint_Status_1_Register)) &
3907                DIO_Serial_IO_In_Progress_St) {
3908                 /* Delay one bit per loop */
3909                 udelay((devpriv->serial_interval_ns + 999) / 1000);
3910                 if (--count < 0) {
3911                         printk
3912                             ("ni_serial_hw_readwrite8: SPI serial I/O didn't finish in time!\n");
3913                         err = -ETIME;
3914                         goto Error;
3915                 }
3916         }
3917
3918         /* Delay for last bit. This delay is absolutely necessary, because
3919            DIO_Serial_IO_In_Progress_St goes high one bit too early. */
3920         udelay((devpriv->serial_interval_ns + 999) / 1000);
3921
3922         if (data_in != NULL)
3923                 *data_in = devpriv->stc_readw(dev, DIO_Serial_Input_Register);
3924
3925 Error:
3926         devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3927
3928         return err;
3929 }
3930
3931 static int ni_serial_sw_readwrite8(struct comedi_device *dev,
3932                                    struct comedi_subdevice *s,
3933                                    unsigned char data_out,
3934                                    unsigned char *data_in)
3935 {
3936         struct ni_private *devpriv = dev->private;
3937         unsigned char mask, input = 0;
3938
3939         /* Wait for one bit before transfer */
3940         udelay((devpriv->serial_interval_ns + 999) / 1000);
3941
3942         for (mask = 0x80; mask; mask >>= 1) {
3943                 /* Output current bit; note that we cannot touch s->state
3944                    because it is a per-subdevice field, and serial is
3945                    a separate subdevice from DIO. */
3946                 devpriv->dio_output &= ~DIO_SDOUT;
3947                 if (data_out & mask) {
3948                         devpriv->dio_output |= DIO_SDOUT;
3949                 }
3950                 devpriv->stc_writew(dev, devpriv->dio_output,
3951                                     DIO_Output_Register);
3952
3953                 /* Assert SDCLK (active low, inverted), wait for half of
3954                    the delay, deassert SDCLK, and wait for the other half. */
3955                 devpriv->dio_control |= DIO_Software_Serial_Control;
3956                 devpriv->stc_writew(dev, devpriv->dio_control,
3957                                     DIO_Control_Register);
3958
3959                 udelay((devpriv->serial_interval_ns + 999) / 2000);
3960
3961                 devpriv->dio_control &= ~DIO_Software_Serial_Control;
3962                 devpriv->stc_writew(dev, devpriv->dio_control,
3963                                     DIO_Control_Register);
3964
3965                 udelay((devpriv->serial_interval_ns + 999) / 2000);
3966
3967                 /* Input current bit */
3968                 if (devpriv->stc_readw(dev,
3969                                        DIO_Parallel_Input_Register) & DIO_SDIN)
3970                 {
3971 /*                      printk("DIO_P_I_R: 0x%x\n", devpriv->stc_readw(dev, DIO_Parallel_Input_Register)); */
3972                         input |= mask;
3973                 }
3974         }
3975
3976         if (data_in)
3977                 *data_in = input;
3978
3979         return 0;
3980 }
3981
3982 static void mio_common_detach(struct comedi_device *dev)
3983 {
3984         struct ni_private *devpriv = dev->private;
3985
3986         if (devpriv) {
3987                 if (devpriv->counter_dev) {
3988                         ni_gpct_device_destroy(devpriv->counter_dev);
3989                 }
3990         }
3991 }
3992
3993 static void init_ao_67xx(struct comedi_device *dev, struct comedi_subdevice *s)
3994 {
3995         int i;
3996
3997         for (i = 0; i < s->n_chan; i++) {
3998                 ni_ao_win_outw(dev, AO_Channel(i) | 0x0,
3999                                AO_Configuration_2_67xx);
4000         }
4001         ao_win_out(0x0, AO_Later_Single_Point_Updates);
4002 }
4003
4004 static unsigned ni_gpct_to_stc_register(enum ni_gpct_register reg)
4005 {
4006         unsigned stc_register;
4007         switch (reg) {
4008         case NITIO_G0_Autoincrement_Reg:
4009                 stc_register = G_Autoincrement_Register(0);
4010                 break;
4011         case NITIO_G1_Autoincrement_Reg:
4012                 stc_register = G_Autoincrement_Register(1);
4013                 break;
4014         case NITIO_G0_Command_Reg:
4015                 stc_register = G_Command_Register(0);
4016                 break;
4017         case NITIO_G1_Command_Reg:
4018                 stc_register = G_Command_Register(1);
4019                 break;
4020         case NITIO_G0_HW_Save_Reg:
4021                 stc_register = G_HW_Save_Register(0);
4022                 break;
4023         case NITIO_G1_HW_Save_Reg:
4024                 stc_register = G_HW_Save_Register(1);
4025                 break;
4026         case NITIO_G0_SW_Save_Reg:
4027                 stc_register = G_Save_Register(0);
4028                 break;
4029         case NITIO_G1_SW_Save_Reg:
4030                 stc_register = G_Save_Register(1);
4031                 break;
4032         case NITIO_G0_Mode_Reg:
4033                 stc_register = G_Mode_Register(0);
4034                 break;
4035         case NITIO_G1_Mode_Reg:
4036                 stc_register = G_Mode_Register(1);
4037                 break;
4038         case NITIO_G0_LoadA_Reg:
4039                 stc_register = G_Load_A_Register(0);
4040                 break;
4041         case NITIO_G1_LoadA_Reg:
4042                 stc_register = G_Load_A_Register(1);
4043                 break;
4044         case NITIO_G0_LoadB_Reg:
4045                 stc_register = G_Load_B_Register(0);
4046                 break;
4047         case NITIO_G1_LoadB_Reg:
4048                 stc_register = G_Load_B_Register(1);
4049                 break;
4050         case NITIO_G0_Input_Select_Reg:
4051                 stc_register = G_Input_Select_Register(0);
4052                 break;
4053         case NITIO_G1_Input_Select_Reg:
4054                 stc_register = G_Input_Select_Register(1);
4055                 break;
4056         case NITIO_G01_Status_Reg:
4057                 stc_register = G_Status_Register;
4058                 break;
4059         case NITIO_G01_Joint_Reset_Reg:
4060                 stc_register = Joint_Reset_Register;
4061                 break;
4062         case NITIO_G01_Joint_Status1_Reg:
4063                 stc_register = Joint_Status_1_Register;
4064                 break;
4065         case NITIO_G01_Joint_Status2_Reg:
4066                 stc_register = Joint_Status_2_Register;
4067                 break;
4068         case NITIO_G0_Interrupt_Acknowledge_Reg:
4069                 stc_register = Interrupt_A_Ack_Register;
4070                 break;
4071         case NITIO_G1_Interrupt_Acknowledge_Reg:
4072                 stc_register = Interrupt_B_Ack_Register;
4073                 break;
4074         case NITIO_G0_Status_Reg:
4075                 stc_register = AI_Status_1_Register;
4076                 break;
4077         case NITIO_G1_Status_Reg:
4078                 stc_register = AO_Status_1_Register;
4079                 break;
4080         case NITIO_G0_Interrupt_Enable_Reg:
4081                 stc_register = Interrupt_A_Enable_Register;
4082                 break;
4083         case NITIO_G1_Interrupt_Enable_Reg:
4084                 stc_register = Interrupt_B_Enable_Register;
4085                 break;
4086         default:
4087                 printk("%s: unhandled register 0x%x in switch.\n",
4088                        __func__, reg);
4089                 BUG();
4090                 return 0;
4091                 break;
4092         }
4093         return stc_register;
4094 }
4095
4096 static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits,
4097                                    enum ni_gpct_register reg)
4098 {
4099         struct comedi_device *dev = counter->counter_dev->dev;
4100         struct ni_private *devpriv = dev->private;
4101         unsigned stc_register;
4102         /* bits in the join reset register which are relevant to counters */
4103         static const unsigned gpct_joint_reset_mask = G0_Reset | G1_Reset;
4104         static const unsigned gpct_interrupt_a_enable_mask =
4105             G0_Gate_Interrupt_Enable | G0_TC_Interrupt_Enable;
4106         static const unsigned gpct_interrupt_b_enable_mask =
4107             G1_Gate_Interrupt_Enable | G1_TC_Interrupt_Enable;
4108
4109         switch (reg) {
4110                 /* m-series-only registers */
4111         case NITIO_G0_Counting_Mode_Reg:
4112                 ni_writew(bits, M_Offset_G0_Counting_Mode);
4113                 break;
4114         case NITIO_G1_Counting_Mode_Reg:
4115                 ni_writew(bits, M_Offset_G1_Counting_Mode);
4116                 break;
4117         case NITIO_G0_Second_Gate_Reg:
4118                 ni_writew(bits, M_Offset_G0_Second_Gate);
4119                 break;
4120         case NITIO_G1_Second_Gate_Reg:
4121                 ni_writew(bits, M_Offset_G1_Second_Gate);
4122                 break;
4123         case NITIO_G0_DMA_Config_Reg:
4124                 ni_writew(bits, M_Offset_G0_DMA_Config);
4125                 break;
4126         case NITIO_G1_DMA_Config_Reg:
4127                 ni_writew(bits, M_Offset_G1_DMA_Config);
4128                 break;
4129         case NITIO_G0_ABZ_Reg:
4130                 ni_writew(bits, M_Offset_G0_MSeries_ABZ);
4131                 break;
4132         case NITIO_G1_ABZ_Reg:
4133                 ni_writew(bits, M_Offset_G1_MSeries_ABZ);
4134                 break;
4135
4136                 /* 32 bit registers */
4137         case NITIO_G0_LoadA_Reg:
4138         case NITIO_G1_LoadA_Reg:
4139         case NITIO_G0_LoadB_Reg:
4140         case NITIO_G1_LoadB_Reg:
4141                 stc_register = ni_gpct_to_stc_register(reg);
4142                 devpriv->stc_writel(dev, bits, stc_register);
4143                 break;
4144
4145                 /* 16 bit registers */
4146         case NITIO_G0_Interrupt_Enable_Reg:
4147                 BUG_ON(bits & ~gpct_interrupt_a_enable_mask);
4148                 ni_set_bitfield(dev, Interrupt_A_Enable_Register,
4149                                 gpct_interrupt_a_enable_mask, bits);
4150                 break;
4151         case NITIO_G1_Interrupt_Enable_Reg:
4152                 BUG_ON(bits & ~gpct_interrupt_b_enable_mask);
4153                 ni_set_bitfield(dev, Interrupt_B_Enable_Register,
4154                                 gpct_interrupt_b_enable_mask, bits);
4155                 break;
4156         case NITIO_G01_Joint_Reset_Reg:
4157                 BUG_ON(bits & ~gpct_joint_reset_mask);
4158                 /* fall-through */
4159         default:
4160                 stc_register = ni_gpct_to_stc_register(reg);
4161                 devpriv->stc_writew(dev, bits, stc_register);
4162         }
4163 }
4164
4165 static unsigned ni_gpct_read_register(struct ni_gpct *counter,
4166                                       enum ni_gpct_register reg)
4167 {
4168         struct comedi_device *dev = counter->counter_dev->dev;
4169         struct ni_private *devpriv = dev->private;
4170         unsigned stc_register;
4171
4172         switch (reg) {
4173                 /* m-series only registers */
4174         case NITIO_G0_DMA_Status_Reg:
4175                 return ni_readw(M_Offset_G0_DMA_Status);
4176                 break;
4177         case NITIO_G1_DMA_Status_Reg:
4178                 return ni_readw(M_Offset_G1_DMA_Status);
4179                 break;
4180
4181                 /* 32 bit registers */
4182         case NITIO_G0_HW_Save_Reg:
4183         case NITIO_G1_HW_Save_Reg:
4184         case NITIO_G0_SW_Save_Reg:
4185         case NITIO_G1_SW_Save_Reg:
4186                 stc_register = ni_gpct_to_stc_register(reg);
4187                 return devpriv->stc_readl(dev, stc_register);
4188                 break;
4189
4190                 /* 16 bit registers */
4191         default:
4192                 stc_register = ni_gpct_to_stc_register(reg);
4193                 return devpriv->stc_readw(dev, stc_register);
4194                 break;
4195         }
4196         return 0;
4197 }
4198
4199 static int ni_freq_out_insn_read(struct comedi_device *dev,
4200                                  struct comedi_subdevice *s,
4201                                  struct comedi_insn *insn, unsigned int *data)
4202 {
4203         struct ni_private *devpriv = dev->private;
4204
4205         data[0] = devpriv->clock_and_fout & FOUT_Divider_mask;
4206         return 1;
4207 }
4208
4209 static int ni_freq_out_insn_write(struct comedi_device *dev,
4210                                   struct comedi_subdevice *s,
4211                                   struct comedi_insn *insn, unsigned int *data)
4212 {
4213         struct ni_private *devpriv = dev->private;
4214
4215         devpriv->clock_and_fout &= ~FOUT_Enable;
4216         devpriv->stc_writew(dev, devpriv->clock_and_fout,
4217                             Clock_and_FOUT_Register);
4218         devpriv->clock_and_fout &= ~FOUT_Divider_mask;
4219         devpriv->clock_and_fout |= FOUT_Divider(data[0]);
4220         devpriv->clock_and_fout |= FOUT_Enable;
4221         devpriv->stc_writew(dev, devpriv->clock_and_fout,
4222                             Clock_and_FOUT_Register);
4223         return insn->n;
4224 }
4225
4226 static int ni_set_freq_out_clock(struct comedi_device *dev,
4227                                  unsigned int clock_source)
4228 {
4229         struct ni_private *devpriv = dev->private;
4230
4231         switch (clock_source) {
4232         case NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC:
4233                 devpriv->clock_and_fout &= ~FOUT_Timebase_Select;
4234                 break;
4235         case NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC:
4236                 devpriv->clock_and_fout |= FOUT_Timebase_Select;
4237                 break;
4238         default:
4239                 return -EINVAL;
4240         }
4241         devpriv->stc_writew(dev, devpriv->clock_and_fout,
4242                             Clock_and_FOUT_Register);
4243         return 3;
4244 }
4245
4246 static void ni_get_freq_out_clock(struct comedi_device *dev,
4247                                   unsigned int *clock_source,
4248                                   unsigned int *clock_period_ns)
4249 {
4250         struct ni_private *devpriv = dev->private;
4251
4252         if (devpriv->clock_and_fout & FOUT_Timebase_Select) {
4253                 *clock_source = NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC;
4254                 *clock_period_ns = TIMEBASE_2_NS;
4255         } else {
4256                 *clock_source = NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC;
4257                 *clock_period_ns = TIMEBASE_1_NS * 2;
4258         }
4259 }
4260
4261 static int ni_freq_out_insn_config(struct comedi_device *dev,
4262                                    struct comedi_subdevice *s,
4263                                    struct comedi_insn *insn, unsigned int *data)
4264 {
4265         switch (data[0]) {
4266         case INSN_CONFIG_SET_CLOCK_SRC:
4267                 return ni_set_freq_out_clock(dev, data[1]);
4268                 break;
4269         case INSN_CONFIG_GET_CLOCK_SRC:
4270                 ni_get_freq_out_clock(dev, &data[1], &data[2]);
4271                 return 3;
4272         default:
4273                 break;
4274         }
4275         return -EINVAL;
4276 }
4277
4278 static int ni_alloc_private(struct comedi_device *dev)
4279 {
4280         struct ni_private *devpriv;
4281
4282         devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
4283         if (!devpriv)
4284                 return -ENOMEM;
4285
4286         spin_lock_init(&devpriv->window_lock);
4287         spin_lock_init(&devpriv->soft_reg_copy_lock);
4288         spin_lock_init(&devpriv->mite_channel_lock);
4289
4290         return 0;
4291 };
4292
4293 static int ni_E_init(struct comedi_device *dev)
4294 {
4295         const struct ni_board_struct *board = comedi_board(dev);
4296         struct ni_private *devpriv = dev->private;
4297         struct comedi_subdevice *s;
4298         unsigned j;
4299         enum ni_gpct_variant counter_variant;
4300         int ret;
4301
4302         if (board->n_aochan > MAX_N_AO_CHAN) {
4303                 printk("bug! n_aochan > MAX_N_AO_CHAN\n");
4304                 return -EINVAL;
4305         }
4306
4307         ret = comedi_alloc_subdevices(dev, NI_NUM_SUBDEVICES);
4308         if (ret)
4309                 return ret;
4310
4311         /* analog input subdevice */
4312
4313         s = &dev->subdevices[NI_AI_SUBDEV];
4314         dev->read_subdev = s;
4315         if (board->n_adchan) {
4316                 s->type = COMEDI_SUBD_AI;
4317                 s->subdev_flags =
4318                     SDF_READABLE | SDF_DIFF | SDF_DITHER | SDF_CMD_READ;
4319                 if (board->reg_type != ni_reg_611x)
4320                         s->subdev_flags |= SDF_GROUND | SDF_COMMON | SDF_OTHER;
4321                 if (board->adbits > 16)
4322                         s->subdev_flags |= SDF_LSAMPL;
4323                 if (board->reg_type & ni_reg_m_series_mask)
4324                         s->subdev_flags |= SDF_SOFT_CALIBRATED;
4325                 s->n_chan = board->n_adchan;
4326                 s->len_chanlist = 512;
4327                 s->maxdata = (1 << board->adbits) - 1;
4328                 s->range_table = ni_range_lkup[board->gainlkup];
4329                 s->insn_read = &ni_ai_insn_read;
4330                 s->insn_config = &ni_ai_insn_config;
4331                 s->do_cmdtest = &ni_ai_cmdtest;
4332                 s->do_cmd = &ni_ai_cmd;
4333                 s->cancel = &ni_ai_reset;
4334                 s->poll = &ni_ai_poll;
4335                 s->munge = &ni_ai_munge;
4336 #ifdef PCIDMA
4337                 s->async_dma_dir = DMA_FROM_DEVICE;
4338 #endif
4339         } else {
4340                 s->type = COMEDI_SUBD_UNUSED;
4341         }
4342
4343         /* analog output subdevice */
4344
4345         s = &dev->subdevices[NI_AO_SUBDEV];
4346         if (board->n_aochan) {
4347                 s->type = COMEDI_SUBD_AO;
4348                 s->subdev_flags = SDF_WRITABLE | SDF_DEGLITCH | SDF_GROUND;
4349                 if (board->reg_type & ni_reg_m_series_mask)
4350                         s->subdev_flags |= SDF_SOFT_CALIBRATED;
4351                 s->n_chan = board->n_aochan;
4352                 s->maxdata = (1 << board->aobits) - 1;
4353                 s->range_table = board->ao_range_table;
4354                 s->insn_read = &ni_ao_insn_read;
4355                 if (board->reg_type & ni_reg_6xxx_mask) {
4356                         s->insn_write = &ni_ao_insn_write_671x;
4357                 } else {
4358                         s->insn_write = &ni_ao_insn_write;
4359                 }
4360                 s->insn_config = &ni_ao_insn_config;
4361 #ifdef PCIDMA
4362                 if (board->n_aochan) {
4363                         s->async_dma_dir = DMA_TO_DEVICE;
4364 #else
4365                 if (board->ao_fifo_depth) {
4366 #endif
4367                         dev->write_subdev = s;
4368                         s->subdev_flags |= SDF_CMD_WRITE;
4369                         s->do_cmd = &ni_ao_cmd;
4370                         s->do_cmdtest = &ni_ao_cmdtest;
4371                         s->len_chanlist = board->n_aochan;
4372                         if ((board->reg_type & ni_reg_m_series_mask) == 0)
4373                                 s->munge = ni_ao_munge;
4374                 }
4375                 s->cancel = &ni_ao_reset;
4376         } else {
4377                 s->type = COMEDI_SUBD_UNUSED;
4378         }
4379         if ((board->reg_type & ni_reg_67xx_mask))
4380                 init_ao_67xx(dev, s);
4381
4382         /* digital i/o subdevice */
4383
4384         s = &dev->subdevices[NI_DIO_SUBDEV];
4385         s->type = COMEDI_SUBD_DIO;
4386         s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
4387         s->maxdata = 1;
4388         s->io_bits = 0;         /* all bits input */
4389         s->range_table = &range_digital;
4390         s->n_chan = board->num_p0_dio_channels;
4391         if (board->reg_type & ni_reg_m_series_mask) {
4392                 s->subdev_flags |=
4393                     SDF_LSAMPL | SDF_CMD_WRITE /* | SDF_CMD_READ */ ;
4394                 s->insn_bits = &ni_m_series_dio_insn_bits;
4395                 s->insn_config = &ni_m_series_dio_insn_config;
4396                 s->do_cmd = &ni_cdio_cmd;
4397                 s->do_cmdtest = &ni_cdio_cmdtest;
4398                 s->cancel = &ni_cdio_cancel;
4399                 s->async_dma_dir = DMA_BIDIRECTIONAL;
4400                 s->len_chanlist = s->n_chan;
4401
4402                 ni_writel(CDO_Reset_Bit | CDI_Reset_Bit, M_Offset_CDIO_Command);
4403                 ni_writel(s->io_bits, M_Offset_DIO_Direction);
4404         } else {
4405                 s->insn_bits = &ni_dio_insn_bits;
4406                 s->insn_config = &ni_dio_insn_config;
4407                 devpriv->dio_control = DIO_Pins_Dir(s->io_bits);
4408                 ni_writew(devpriv->dio_control, DIO_Control_Register);
4409         }
4410
4411         /* 8255 device */
4412         s = &dev->subdevices[NI_8255_DIO_SUBDEV];
4413         if (board->has_8255) {
4414                 subdev_8255_init(dev, s, ni_8255_callback, (unsigned long)dev);
4415         } else {
4416                 s->type = COMEDI_SUBD_UNUSED;
4417         }
4418
4419         /* formerly general purpose counter/timer device, but no longer used */
4420         s = &dev->subdevices[NI_UNUSED_SUBDEV];
4421         s->type = COMEDI_SUBD_UNUSED;
4422
4423         /* calibration subdevice -- ai and ao */
4424         s = &dev->subdevices[NI_CALIBRATION_SUBDEV];
4425         s->type = COMEDI_SUBD_CALIB;
4426         if (board->reg_type & ni_reg_m_series_mask) {
4427                 /*  internal PWM analog output used for AI nonlinearity calibration */
4428                 s->subdev_flags = SDF_INTERNAL;
4429                 s->insn_config = &ni_m_series_pwm_config;
4430                 s->n_chan = 1;
4431                 s->maxdata = 0;
4432                 ni_writel(0x0, M_Offset_Cal_PWM);
4433         } else if (board->reg_type == ni_reg_6143) {
4434                 /*  internal PWM analog output used for AI nonlinearity calibration */
4435                 s->subdev_flags = SDF_INTERNAL;
4436                 s->insn_config = &ni_6143_pwm_config;
4437                 s->n_chan = 1;
4438                 s->maxdata = 0;
4439         } else {
4440                 s->subdev_flags = SDF_WRITABLE | SDF_INTERNAL;
4441                 s->insn_read = &ni_calib_insn_read;
4442                 s->insn_write = &ni_calib_insn_write;
4443                 caldac_setup(dev, s);
4444         }
4445
4446         /* EEPROM */
4447         s = &dev->subdevices[NI_EEPROM_SUBDEV];
4448         s->type = COMEDI_SUBD_MEMORY;
4449         s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
4450         s->maxdata = 0xff;
4451         if (board->reg_type & ni_reg_m_series_mask) {
4452                 s->n_chan = M_SERIES_EEPROM_SIZE;
4453                 s->insn_read = &ni_m_series_eeprom_insn_read;
4454         } else {
4455                 s->n_chan = 512;
4456                 s->insn_read = &ni_eeprom_insn_read;
4457         }
4458
4459         /* PFI */
4460         s = &dev->subdevices[NI_PFI_DIO_SUBDEV];
4461         s->type = COMEDI_SUBD_DIO;
4462         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4463         if (board->reg_type & ni_reg_m_series_mask) {
4464                 unsigned i;
4465                 s->n_chan = 16;
4466                 ni_writew(s->state, M_Offset_PFI_DO);
4467                 for (i = 0; i < NUM_PFI_OUTPUT_SELECT_REGS; ++i) {
4468                         ni_writew(devpriv->pfi_output_select_reg[i],
4469                                   M_Offset_PFI_Output_Select(i + 1));
4470                 }
4471         } else {
4472                 s->n_chan = 10;
4473         }
4474         s->maxdata = 1;
4475         if (board->reg_type & ni_reg_m_series_mask) {
4476                 s->insn_bits = &ni_pfi_insn_bits;
4477         }
4478         s->insn_config = &ni_pfi_insn_config;
4479         ni_set_bits(dev, IO_Bidirection_Pin_Register, ~0, 0);
4480
4481         /* cs5529 calibration adc */
4482         s = &dev->subdevices[NI_CS5529_CALIBRATION_SUBDEV];
4483         if (board->reg_type & ni_reg_67xx_mask) {
4484                 s->type = COMEDI_SUBD_AI;
4485                 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_INTERNAL;
4486                 /*  one channel for each analog output channel */
4487                 s->n_chan = board->n_aochan;
4488                 s->maxdata = (1 << 16) - 1;
4489                 s->range_table = &range_unknown;        /* XXX */
4490                 s->insn_read = cs5529_ai_insn_read;
4491                 s->insn_config = NULL;
4492                 init_cs5529(dev);
4493         } else {
4494                 s->type = COMEDI_SUBD_UNUSED;
4495         }
4496
4497         /* Serial */
4498         s = &dev->subdevices[NI_SERIAL_SUBDEV];
4499         s->type = COMEDI_SUBD_SERIAL;
4500         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4501         s->n_chan = 1;
4502         s->maxdata = 0xff;
4503         s->insn_config = ni_serial_insn_config;
4504         devpriv->serial_interval_ns = 0;
4505         devpriv->serial_hw_mode = 0;
4506
4507         /* RTSI */
4508         s = &dev->subdevices[NI_RTSI_SUBDEV];
4509         s->type = COMEDI_SUBD_DIO;
4510         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4511         s->n_chan = 8;
4512         s->maxdata = 1;
4513         s->insn_bits = ni_rtsi_insn_bits;
4514         s->insn_config = ni_rtsi_insn_config;
4515         ni_rtsi_init(dev);
4516
4517         if (board->reg_type & ni_reg_m_series_mask) {
4518                 counter_variant = ni_gpct_variant_m_series;
4519         } else {
4520                 counter_variant = ni_gpct_variant_e_series;
4521         }
4522         devpriv->counter_dev = ni_gpct_device_construct(dev,
4523                                                         &ni_gpct_write_register,
4524                                                         &ni_gpct_read_register,
4525                                                         counter_variant,
4526                                                         NUM_GPCT);
4527         /* General purpose counters */
4528         for (j = 0; j < NUM_GPCT; ++j) {
4529                 s = &dev->subdevices[NI_GPCT_SUBDEV(j)];
4530                 s->type = COMEDI_SUBD_COUNTER;
4531                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL;
4532                 s->n_chan = 3;
4533                 if (board->reg_type & ni_reg_m_series_mask)
4534                         s->maxdata = 0xffffffff;
4535                 else
4536                         s->maxdata = 0xffffff;
4537                 s->insn_read = &ni_gpct_insn_read;
4538                 s->insn_write = &ni_gpct_insn_write;
4539                 s->insn_config = &ni_gpct_insn_config;
4540 #ifdef PCIDMA
4541                 s->subdev_flags |= SDF_CMD_READ /* | SDF_CMD_WRITE */;
4542                 s->do_cmd = &ni_gpct_cmd;
4543                 s->len_chanlist = 1;
4544                 s->do_cmdtest = &ni_gpct_cmdtest;
4545                 s->cancel = &ni_gpct_cancel;
4546                 s->async_dma_dir = DMA_BIDIRECTIONAL;
4547 #endif
4548                 s->private = &devpriv->counter_dev->counters[j];
4549
4550                 devpriv->counter_dev->counters[j].chip_index = 0;
4551                 devpriv->counter_dev->counters[j].counter_index = j;
4552                 ni_tio_init_counter(&devpriv->counter_dev->counters[j]);
4553         }
4554
4555         /* Frequency output */
4556         s = &dev->subdevices[NI_FREQ_OUT_SUBDEV];
4557         s->type = COMEDI_SUBD_COUNTER;
4558         s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
4559         s->n_chan = 1;
4560         s->maxdata = 0xf;
4561         s->insn_read = &ni_freq_out_insn_read;
4562         s->insn_write = &ni_freq_out_insn_write;
4563         s->insn_config = &ni_freq_out_insn_config;
4564
4565         /* ai configuration */
4566         s = &dev->subdevices[NI_AI_SUBDEV];
4567         ni_ai_reset(dev, s);
4568         if ((board->reg_type & ni_reg_6xxx_mask) == 0) {
4569                 /*  BEAM is this needed for PCI-6143 ?? */
4570                 devpriv->clock_and_fout =
4571                     Slow_Internal_Time_Divide_By_2 |
4572                     Slow_Internal_Timebase |
4573                     Clock_To_Board_Divide_By_2 |
4574                     Clock_To_Board |
4575                     AI_Output_Divide_By_2 | AO_Output_Divide_By_2;
4576         } else {
4577                 devpriv->clock_and_fout =
4578                     Slow_Internal_Time_Divide_By_2 |
4579                     Slow_Internal_Timebase |
4580                     Clock_To_Board_Divide_By_2 | Clock_To_Board;
4581         }
4582         devpriv->stc_writew(dev, devpriv->clock_and_fout,
4583                             Clock_and_FOUT_Register);
4584
4585         /* analog output configuration */
4586         s = &dev->subdevices[NI_AO_SUBDEV];
4587         ni_ao_reset(dev, s);
4588
4589         if (dev->irq) {
4590                 devpriv->stc_writew(dev,
4591                                     (IRQ_POLARITY ? Interrupt_Output_Polarity :
4592                                      0) | (Interrupt_Output_On_3_Pins & 0) |
4593                                     Interrupt_A_Enable | Interrupt_B_Enable |
4594                                     Interrupt_A_Output_Select(interrupt_pin
4595                                                               (dev->irq)) |
4596                                     Interrupt_B_Output_Select(interrupt_pin
4597                                                               (dev->irq)),
4598                                     Interrupt_Control_Register);
4599         }
4600
4601         /* DMA setup */
4602         ni_writeb(devpriv->ai_ao_select_reg, AI_AO_Select);
4603         ni_writeb(devpriv->g0_g1_select_reg, G0_G1_Select);
4604
4605         if (board->reg_type & ni_reg_6xxx_mask) {
4606                 ni_writeb(0, Magic_611x);
4607         } else if (board->reg_type & ni_reg_m_series_mask) {
4608                 int channel;
4609                 for (channel = 0; channel < board->n_aochan; ++channel) {
4610                         ni_writeb(0xf, M_Offset_AO_Waveform_Order(channel));
4611                         ni_writeb(0x0,
4612                                   M_Offset_AO_Reference_Attenuation(channel));
4613                 }
4614                 ni_writeb(0x0, M_Offset_AO_Calibration);
4615         }
4616
4617         printk("\n");
4618         return 0;
4619 }
4620
4621 static int ni_8255_callback(int dir, int port, int data, unsigned long arg)
4622 {
4623         struct comedi_device *dev = (struct comedi_device *)arg;
4624         struct ni_private *devpriv __maybe_unused = dev->private;
4625
4626         if (dir) {
4627                 ni_writeb(data, Port_A + 2 * port);
4628                 return 0;
4629         } else {
4630                 return ni_readb(Port_A + 2 * port);
4631         }
4632 }
4633
4634 /*
4635         presents the EEPROM as a subdevice
4636 */
4637
4638 static int ni_eeprom_insn_read(struct comedi_device *dev,
4639                                struct comedi_subdevice *s,
4640                                struct comedi_insn *insn, unsigned int *data)
4641 {
4642         data[0] = ni_read_eeprom(dev, CR_CHAN(insn->chanspec));
4643
4644         return 1;
4645 }
4646
4647 /*
4648         reads bytes out of eeprom
4649 */
4650
4651 static int ni_read_eeprom(struct comedi_device *dev, int addr)
4652 {
4653         struct ni_private *devpriv __maybe_unused = dev->private;
4654         int bit;
4655         int bitstring;
4656
4657         bitstring = 0x0300 | ((addr & 0x100) << 3) | (addr & 0xff);
4658         ni_writeb(0x04, Serial_Command);
4659         for (bit = 0x8000; bit; bit >>= 1) {
4660                 ni_writeb(0x04 | ((bit & bitstring) ? 0x02 : 0),
4661                           Serial_Command);
4662                 ni_writeb(0x05 | ((bit & bitstring) ? 0x02 : 0),
4663                           Serial_Command);
4664         }
4665         bitstring = 0;
4666         for (bit = 0x80; bit; bit >>= 1) {
4667                 ni_writeb(0x04, Serial_Command);
4668                 ni_writeb(0x05, Serial_Command);
4669                 bitstring |= ((ni_readb(XXX_Status) & PROMOUT) ? bit : 0);
4670         }
4671         ni_writeb(0x00, Serial_Command);
4672
4673         return bitstring;
4674 }
4675
4676 static int ni_m_series_eeprom_insn_read(struct comedi_device *dev,
4677                                         struct comedi_subdevice *s,
4678                                         struct comedi_insn *insn,
4679                                         unsigned int *data)
4680 {
4681         struct ni_private *devpriv = dev->private;
4682
4683         data[0] = devpriv->eeprom_buffer[CR_CHAN(insn->chanspec)];
4684
4685         return 1;
4686 }
4687
4688 static int ni_get_pwm_config(struct comedi_device *dev, unsigned int *data)
4689 {
4690         struct ni_private *devpriv = dev->private;
4691
4692         data[1] = devpriv->pwm_up_count * devpriv->clock_ns;
4693         data[2] = devpriv->pwm_down_count * devpriv->clock_ns;
4694         return 3;
4695 }
4696
4697 static int ni_m_series_pwm_config(struct comedi_device *dev,
4698                                   struct comedi_subdevice *s,
4699                                   struct comedi_insn *insn, unsigned int *data)
4700 {
4701         struct ni_private *devpriv = dev->private;
4702         unsigned up_count, down_count;
4703
4704         switch (data[0]) {
4705         case INSN_CONFIG_PWM_OUTPUT:
4706                 switch (data[1]) {
4707                 case TRIG_ROUND_NEAREST:
4708                         up_count =
4709                             (data[2] +
4710                              devpriv->clock_ns / 2) / devpriv->clock_ns;
4711                         break;
4712                 case TRIG_ROUND_DOWN:
4713                         up_count = data[2] / devpriv->clock_ns;
4714                         break;
4715                 case TRIG_ROUND_UP:
4716                         up_count =
4717                             (data[2] + devpriv->clock_ns -
4718                              1) / devpriv->clock_ns;
4719                         break;
4720                 default:
4721                         return -EINVAL;
4722                         break;
4723                 }
4724                 switch (data[3]) {
4725                 case TRIG_ROUND_NEAREST:
4726                         down_count =
4727                             (data[4] +
4728                              devpriv->clock_ns / 2) / devpriv->clock_ns;
4729                         break;
4730                 case TRIG_ROUND_DOWN:
4731                         down_count = data[4] / devpriv->clock_ns;
4732                         break;
4733                 case TRIG_ROUND_UP:
4734                         down_count =
4735                             (data[4] + devpriv->clock_ns -
4736                              1) / devpriv->clock_ns;
4737                         break;
4738                 default:
4739                         return -EINVAL;
4740                         break;
4741                 }
4742                 if (up_count * devpriv->clock_ns != data[2] ||
4743                     down_count * devpriv->clock_ns != data[4]) {
4744                         data[2] = up_count * devpriv->clock_ns;
4745                         data[4] = down_count * devpriv->clock_ns;
4746                         return -EAGAIN;
4747                 }
4748                 ni_writel(MSeries_Cal_PWM_High_Time_Bits(up_count) |
4749                           MSeries_Cal_PWM_Low_Time_Bits(down_count),
4750                           M_Offset_Cal_PWM);
4751                 devpriv->pwm_up_count = up_count;
4752                 devpriv->pwm_down_count = down_count;
4753                 return 5;
4754                 break;
4755         case INSN_CONFIG_GET_PWM_OUTPUT:
4756                 return ni_get_pwm_config(dev, data);
4757                 break;
4758         default:
4759                 return -EINVAL;
4760                 break;
4761         }
4762         return 0;
4763 }
4764
4765 static int ni_6143_pwm_config(struct comedi_device *dev,
4766                               struct comedi_subdevice *s,
4767                               struct comedi_insn *insn, unsigned int *data)
4768 {
4769         struct ni_private *devpriv = dev->private;
4770         unsigned up_count, down_count;
4771
4772         switch (data[0]) {
4773         case INSN_CONFIG_PWM_OUTPUT:
4774                 switch (data[1]) {
4775                 case TRIG_ROUND_NEAREST:
4776                         up_count =
4777                             (data[2] +
4778                              devpriv->clock_ns / 2) / devpriv->clock_ns;
4779                         break;
4780                 case TRIG_ROUND_DOWN:
4781                         up_count = data[2] / devpriv->clock_ns;
4782                         break;
4783                 case TRIG_ROUND_UP:
4784                         up_count =
4785                             (data[2] + devpriv->clock_ns -
4786                              1) / devpriv->clock_ns;
4787                         break;
4788                 default:
4789                         return -EINVAL;
4790                         break;
4791                 }
4792                 switch (data[3]) {
4793                 case TRIG_ROUND_NEAREST:
4794                         down_count =
4795                             (data[4] +
4796                              devpriv->clock_ns / 2) / devpriv->clock_ns;
4797                         break;
4798                 case TRIG_ROUND_DOWN:
4799                         down_count = data[4] / devpriv->clock_ns;
4800                         break;
4801                 case TRIG_ROUND_UP:
4802                         down_count =
4803                             (data[4] + devpriv->clock_ns -
4804                              1) / devpriv->clock_ns;
4805                         break;
4806                 default:
4807                         return -EINVAL;
4808                         break;
4809                 }
4810                 if (up_count * devpriv->clock_ns != data[2] ||
4811                     down_count * devpriv->clock_ns != data[4]) {
4812                         data[2] = up_count * devpriv->clock_ns;
4813                         data[4] = down_count * devpriv->clock_ns;
4814                         return -EAGAIN;
4815                 }
4816                 ni_writel(up_count, Calibration_HighTime_6143);
4817                 devpriv->pwm_up_count = up_count;
4818                 ni_writel(down_count, Calibration_LowTime_6143);
4819                 devpriv->pwm_down_count = down_count;
4820                 return 5;
4821                 break;
4822         case INSN_CONFIG_GET_PWM_OUTPUT:
4823                 return ni_get_pwm_config(dev, data);
4824         default:
4825                 return -EINVAL;
4826                 break;
4827         }
4828         return 0;
4829 }
4830
4831 static void ni_write_caldac(struct comedi_device *dev, int addr, int val);
4832 /*
4833         calibration subdevice
4834 */
4835 static int ni_calib_insn_write(struct comedi_device *dev,
4836                                struct comedi_subdevice *s,
4837                                struct comedi_insn *insn, unsigned int *data)
4838 {
4839         ni_write_caldac(dev, CR_CHAN(insn->chanspec), data[0]);
4840
4841         return 1;
4842 }
4843
4844 static int ni_calib_insn_read(struct comedi_device *dev,
4845                               struct comedi_subdevice *s,
4846                               struct comedi_insn *insn, unsigned int *data)
4847 {
4848         struct ni_private *devpriv = dev->private;
4849
4850         data[0] = devpriv->caldacs[CR_CHAN(insn->chanspec)];
4851
4852         return 1;
4853 }
4854
4855 static int pack_mb88341(int addr, int val, int *bitstring);
4856 static int pack_dac8800(int addr, int val, int *bitstring);
4857 static int pack_dac8043(int addr, int val, int *bitstring);
4858 static int pack_ad8522(int addr, int val, int *bitstring);
4859 static int pack_ad8804(int addr, int val, int *bitstring);
4860 static int pack_ad8842(int addr, int val, int *bitstring);
4861
4862 struct caldac_struct {
4863         int n_chans;
4864         int n_bits;
4865         int (*packbits) (int, int, int *);
4866 };
4867
4868 static struct caldac_struct caldacs[] = {
4869         [mb88341] = {12, 8, pack_mb88341},
4870         [dac8800] = {8, 8, pack_dac8800},
4871         [dac8043] = {1, 12, pack_dac8043},
4872         [ad8522] = {2, 12, pack_ad8522},
4873         [ad8804] = {12, 8, pack_ad8804},
4874         [ad8842] = {8, 8, pack_ad8842},
4875         [ad8804_debug] = {16, 8, pack_ad8804},
4876 };
4877
4878 static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s)
4879 {
4880         const struct ni_board_struct *board = comedi_board(dev);
4881         struct ni_private *devpriv = dev->private;
4882         int i, j;
4883         int n_dacs;
4884         int n_chans = 0;
4885         int n_bits;
4886         int diffbits = 0;
4887         int type;
4888         int chan;
4889
4890         type = board->caldac[0];
4891         if (type == caldac_none)
4892                 return;
4893         n_bits = caldacs[type].n_bits;
4894         for (i = 0; i < 3; i++) {
4895                 type = board->caldac[i];
4896                 if (type == caldac_none)
4897                         break;
4898                 if (caldacs[type].n_bits != n_bits)
4899                         diffbits = 1;
4900                 n_chans += caldacs[type].n_chans;
4901         }
4902         n_dacs = i;
4903         s->n_chan = n_chans;
4904
4905         if (diffbits) {
4906                 unsigned int *maxdata_list;
4907
4908                 if (n_chans > MAX_N_CALDACS) {
4909                         printk("BUG! MAX_N_CALDACS too small\n");
4910                 }
4911                 s->maxdata_list = maxdata_list = devpriv->caldac_maxdata_list;
4912                 chan = 0;
4913                 for (i = 0; i < n_dacs; i++) {
4914                         type = board->caldac[i];
4915                         for (j = 0; j < caldacs[type].n_chans; j++) {
4916                                 maxdata_list[chan] =
4917                                     (1 << caldacs[type].n_bits) - 1;
4918                                 chan++;
4919                         }
4920                 }
4921
4922                 for (chan = 0; chan < s->n_chan; chan++)
4923                         ni_write_caldac(dev, i, s->maxdata_list[i] / 2);
4924         } else {
4925                 type = board->caldac[0];
4926                 s->maxdata = (1 << caldacs[type].n_bits) - 1;
4927
4928                 for (chan = 0; chan < s->n_chan; chan++)
4929                         ni_write_caldac(dev, i, s->maxdata / 2);
4930         }
4931 }
4932
4933 static void ni_write_caldac(struct comedi_device *dev, int addr, int val)
4934 {
4935         const struct ni_board_struct *board = comedi_board(dev);
4936         struct ni_private *devpriv = dev->private;
4937         unsigned int loadbit = 0, bits = 0, bit, bitstring = 0;
4938         int i;
4939         int type;
4940
4941         /* printk("ni_write_caldac: chan=%d val=%d\n",addr,val); */
4942         if (devpriv->caldacs[addr] == val)
4943                 return;
4944         devpriv->caldacs[addr] = val;
4945
4946         for (i = 0; i < 3; i++) {
4947                 type = board->caldac[i];
4948                 if (type == caldac_none)
4949                         break;
4950                 if (addr < caldacs[type].n_chans) {
4951                         bits = caldacs[type].packbits(addr, val, &bitstring);
4952                         loadbit = SerDacLd(i);
4953                         /* printk("caldac: using i=%d addr=%d %x\n",i,addr,bitstring); */
4954                         break;
4955                 }
4956                 addr -= caldacs[type].n_chans;
4957         }
4958
4959         for (bit = 1 << (bits - 1); bit; bit >>= 1) {
4960                 ni_writeb(((bit & bitstring) ? 0x02 : 0), Serial_Command);
4961                 udelay(1);
4962                 ni_writeb(1 | ((bit & bitstring) ? 0x02 : 0), Serial_Command);
4963                 udelay(1);
4964         }
4965         ni_writeb(loadbit, Serial_Command);
4966         udelay(1);
4967         ni_writeb(0, Serial_Command);
4968 }
4969
4970 static int pack_mb88341(int addr, int val, int *bitstring)
4971 {
4972         /*
4973            Fujitsu MB 88341
4974            Note that address bits are reversed.  Thanks to
4975            Ingo Keen for noticing this.
4976
4977            Note also that the 88341 expects address values from
4978            1-12, whereas we use channel numbers 0-11.  The NI
4979            docs use 1-12, also, so be careful here.
4980          */
4981         addr++;
4982         *bitstring = ((addr & 0x1) << 11) |
4983             ((addr & 0x2) << 9) |
4984             ((addr & 0x4) << 7) | ((addr & 0x8) << 5) | (val & 0xff);
4985         return 12;
4986 }
4987
4988 static int pack_dac8800(int addr, int val, int *bitstring)
4989 {
4990         *bitstring = ((addr & 0x7) << 8) | (val & 0xff);
4991         return 11;
4992 }
4993
4994 static int pack_dac8043(int addr, int val, int *bitstring)
4995 {
4996         *bitstring = val & 0xfff;
4997         return 12;
4998 }
4999
5000 static int pack_ad8522(int addr, int val, int *bitstring)
5001 {
5002         *bitstring = (val & 0xfff) | (addr ? 0xc000 : 0xa000);
5003         return 16;
5004 }
5005
5006 static int pack_ad8804(int addr, int val, int *bitstring)
5007 {
5008         *bitstring = ((addr & 0xf) << 8) | (val & 0xff);
5009         return 12;
5010 }
5011
5012 static int pack_ad8842(int addr, int val, int *bitstring)
5013 {
5014         *bitstring = ((addr + 1) << 8) | (val & 0xff);
5015         return 12;
5016 }
5017
5018 #if 0
5019 /*
5020  *      Read the GPCTs current value.
5021  */
5022 static int GPCT_G_Watch(struct comedi_device *dev, int chan)
5023 {
5024         unsigned int hi1, hi2, lo;
5025
5026         devpriv->gpct_command[chan] &= ~G_Save_Trace;
5027         devpriv->stc_writew(dev, devpriv->gpct_command[chan],
5028                             G_Command_Register(chan));
5029
5030         devpriv->gpct_command[chan] |= G_Save_Trace;
5031         devpriv->stc_writew(dev, devpriv->gpct_command[chan],
5032                             G_Command_Register(chan));
5033
5034         /* This procedure is used because the two registers cannot
5035          * be read atomically. */
5036         do {
5037                 hi1 = devpriv->stc_readw(dev, G_Save_Register_High(chan));
5038                 lo = devpriv->stc_readw(dev, G_Save_Register_Low(chan));
5039                 hi2 = devpriv->stc_readw(dev, G_Save_Register_High(chan));
5040         } while (hi1 != hi2);
5041
5042         return (hi1 << 16) | lo;
5043 }
5044
5045 static void GPCT_Reset(struct comedi_device *dev, int chan)
5046 {
5047         int temp_ack_reg = 0;
5048
5049         /* printk("GPCT_Reset..."); */
5050         devpriv->gpct_cur_operation[chan] = GPCT_RESET;
5051
5052         switch (chan) {
5053         case 0:
5054                 devpriv->stc_writew(dev, G0_Reset, Joint_Reset_Register);
5055                 ni_set_bits(dev, Interrupt_A_Enable_Register,
5056                             G0_TC_Interrupt_Enable, 0);
5057                 ni_set_bits(dev, Interrupt_A_Enable_Register,
5058                             G0_Gate_Interrupt_Enable, 0);
5059                 temp_ack_reg |= G0_Gate_Error_Confirm;
5060                 temp_ack_reg |= G0_TC_Error_Confirm;
5061                 temp_ack_reg |= G0_TC_Interrupt_Ack;
5062                 temp_ack_reg |= G0_Gate_Interrupt_Ack;
5063                 devpriv->stc_writew(dev, temp_ack_reg,
5064                                     Interrupt_A_Ack_Register);
5065
5066                 /* problem...this interferes with the other ctr... */
5067                 devpriv->an_trig_etc_reg |= GPFO_0_Output_Enable;
5068                 devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
5069                                     Analog_Trigger_Etc_Register);
5070                 break;
5071         case 1:
5072                 devpriv->stc_writew(dev, G1_Reset, Joint_Reset_Register);
5073                 ni_set_bits(dev, Interrupt_B_Enable_Register,
5074                             G1_TC_Interrupt_Enable, 0);
5075                 ni_set_bits(dev, Interrupt_B_Enable_Register,
5076                             G0_Gate_Interrupt_Enable, 0);
5077                 temp_ack_reg |= G1_Gate_Error_Confirm;
5078                 temp_ack_reg |= G1_TC_Error_Confirm;
5079                 temp_ack_reg |= G1_TC_Interrupt_Ack;
5080                 temp_ack_reg |= G1_Gate_Interrupt_Ack;
5081                 devpriv->stc_writew(dev, temp_ack_reg,
5082                                     Interrupt_B_Ack_Register);
5083
5084                 devpriv->an_trig_etc_reg |= GPFO_1_Output_Enable;
5085                 devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
5086                                     Analog_Trigger_Etc_Register);
5087                 break;
5088         }
5089
5090         devpriv->gpct_mode[chan] = 0;
5091         devpriv->gpct_input_select[chan] = 0;
5092         devpriv->gpct_command[chan] = 0;
5093
5094         devpriv->gpct_command[chan] |= G_Synchronized_Gate;
5095
5096         devpriv->stc_writew(dev, devpriv->gpct_mode[chan],
5097                             G_Mode_Register(chan));
5098         devpriv->stc_writew(dev, devpriv->gpct_input_select[chan],
5099                             G_Input_Select_Register(chan));
5100         devpriv->stc_writew(dev, 0, G_Autoincrement_Register(chan));
5101
5102         /* printk("exit GPCT_Reset\n"); */
5103 }
5104
5105 #endif
5106
5107 static int ni_gpct_insn_config(struct comedi_device *dev,
5108                                struct comedi_subdevice *s,
5109                                struct comedi_insn *insn, unsigned int *data)
5110 {
5111         struct ni_gpct *counter = s->private;
5112         return ni_tio_insn_config(counter, insn, data);
5113 }
5114
5115 static int ni_gpct_insn_read(struct comedi_device *dev,
5116                              struct comedi_subdevice *s,
5117                              struct comedi_insn *insn, unsigned int *data)
5118 {
5119         struct ni_gpct *counter = s->private;
5120         return ni_tio_rinsn(counter, insn, data);
5121 }
5122
5123 static int ni_gpct_insn_write(struct comedi_device *dev,
5124                               struct comedi_subdevice *s,
5125                               struct comedi_insn *insn, unsigned int *data)
5126 {
5127         struct ni_gpct *counter = s->private;
5128         return ni_tio_winsn(counter, insn, data);
5129 }
5130
5131 #ifdef PCIDMA
5132 static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
5133 {
5134         int retval;
5135         struct ni_gpct *counter = s->private;
5136 /* const struct comedi_cmd *cmd = &s->async->cmd; */
5137
5138         retval = ni_request_gpct_mite_channel(dev, counter->counter_index,
5139                                               COMEDI_INPUT);
5140         if (retval) {
5141                 comedi_error(dev,
5142                              "no dma channel available for use by counter");
5143                 return retval;
5144         }
5145         ni_tio_acknowledge_and_confirm(counter, NULL, NULL, NULL, NULL);
5146         ni_e_series_enable_second_irq(dev, counter->counter_index, 1);
5147         retval = ni_tio_cmd(counter, s->async);
5148         return retval;
5149 }
5150 #endif
5151
5152 #ifdef PCIDMA
5153 static int ni_gpct_cmdtest(struct comedi_device *dev,
5154                            struct comedi_subdevice *s, struct comedi_cmd *cmd)
5155 {
5156         struct ni_gpct *counter = s->private;
5157
5158         return ni_tio_cmdtest(counter, cmd);
5159         return -ENOTSUPP;
5160 }
5161 #endif
5162
5163 static int ni_gpct_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
5164 {
5165 #ifdef PCIDMA
5166         struct ni_gpct *counter = s->private;
5167         int retval;
5168
5169         retval = ni_tio_cancel(counter);
5170         ni_e_series_enable_second_irq(dev, counter->counter_index, 0);
5171         ni_release_gpct_mite_channel(dev, counter->counter_index);
5172         return retval;
5173 #else
5174         return 0;
5175 #endif
5176 }
5177
5178 /*
5179  *
5180  *  Programmable Function Inputs
5181  *
5182  */
5183
5184 static int ni_m_series_set_pfi_routing(struct comedi_device *dev, unsigned chan,
5185                                        unsigned source)
5186 {
5187         struct ni_private *devpriv = dev->private;
5188         unsigned pfi_reg_index;
5189         unsigned array_offset;
5190
5191         if ((source & 0x1f) != source)
5192                 return -EINVAL;
5193         pfi_reg_index = 1 + chan / 3;
5194         array_offset = pfi_reg_index - 1;
5195         devpriv->pfi_output_select_reg[array_offset] &=
5196             ~MSeries_PFI_Output_Select_Mask(chan);
5197         devpriv->pfi_output_select_reg[array_offset] |=
5198             MSeries_PFI_Output_Select_Bits(chan, source);
5199         ni_writew(devpriv->pfi_output_select_reg[array_offset],
5200                   M_Offset_PFI_Output_Select(pfi_reg_index));
5201         return 2;
5202 }
5203
5204 static int ni_old_set_pfi_routing(struct comedi_device *dev, unsigned chan,
5205                                   unsigned source)
5206 {
5207         /*  pre-m-series boards have fixed signals on pfi pins */
5208         if (source != ni_old_get_pfi_routing(dev, chan))
5209                 return -EINVAL;
5210         return 2;
5211 }
5212
5213 static int ni_set_pfi_routing(struct comedi_device *dev, unsigned chan,
5214                               unsigned source)
5215 {
5216         const struct ni_board_struct *board = comedi_board(dev);
5217
5218         if (board->reg_type & ni_reg_m_series_mask)
5219                 return ni_m_series_set_pfi_routing(dev, chan, source);
5220         else
5221                 return ni_old_set_pfi_routing(dev, chan, source);
5222 }
5223
5224 static unsigned ni_m_series_get_pfi_routing(struct comedi_device *dev,
5225                                             unsigned chan)
5226 {
5227         struct ni_private *devpriv = dev->private;
5228         const unsigned array_offset = chan / 3;
5229
5230         return MSeries_PFI_Output_Select_Source(chan,
5231                                                 devpriv->
5232                                                 pfi_output_select_reg
5233                                                 [array_offset]);
5234 }
5235
5236 static unsigned ni_old_get_pfi_routing(struct comedi_device *dev, unsigned chan)
5237 {
5238         /*  pre-m-series boards have fixed signals on pfi pins */
5239         switch (chan) {
5240         case 0:
5241                 return NI_PFI_OUTPUT_AI_START1;
5242                 break;
5243         case 1:
5244                 return NI_PFI_OUTPUT_AI_START2;
5245                 break;
5246         case 2:
5247                 return NI_PFI_OUTPUT_AI_CONVERT;
5248                 break;
5249         case 3:
5250                 return NI_PFI_OUTPUT_G_SRC1;
5251                 break;
5252         case 4:
5253                 return NI_PFI_OUTPUT_G_GATE1;
5254                 break;
5255         case 5:
5256                 return NI_PFI_OUTPUT_AO_UPDATE_N;
5257                 break;
5258         case 6:
5259                 return NI_PFI_OUTPUT_AO_START1;
5260                 break;
5261         case 7:
5262                 return NI_PFI_OUTPUT_AI_START_PULSE;
5263                 break;
5264         case 8:
5265                 return NI_PFI_OUTPUT_G_SRC0;
5266                 break;
5267         case 9:
5268                 return NI_PFI_OUTPUT_G_GATE0;
5269                 break;
5270         default:
5271                 printk("%s: bug, unhandled case in switch.\n", __func__);
5272                 break;
5273         }
5274         return 0;
5275 }
5276
5277 static unsigned ni_get_pfi_routing(struct comedi_device *dev, unsigned chan)
5278 {
5279         const struct ni_board_struct *board = comedi_board(dev);
5280
5281         if (board->reg_type & ni_reg_m_series_mask)
5282                 return ni_m_series_get_pfi_routing(dev, chan);
5283         else
5284                 return ni_old_get_pfi_routing(dev, chan);
5285 }
5286
5287 static int ni_config_filter(struct comedi_device *dev, unsigned pfi_channel,
5288                             enum ni_pfi_filter_select filter)
5289 {
5290         const struct ni_board_struct *board = comedi_board(dev);
5291         struct ni_private *devpriv __maybe_unused = dev->private;
5292         unsigned bits;
5293
5294         if ((board->reg_type & ni_reg_m_series_mask) == 0) {
5295                 return -ENOTSUPP;
5296         }
5297         bits = ni_readl(M_Offset_PFI_Filter);
5298         bits &= ~MSeries_PFI_Filter_Select_Mask(pfi_channel);
5299         bits |= MSeries_PFI_Filter_Select_Bits(pfi_channel, filter);
5300         ni_writel(bits, M_Offset_PFI_Filter);
5301         return 0;
5302 }
5303
5304 static int ni_pfi_insn_bits(struct comedi_device *dev,
5305                             struct comedi_subdevice *s,
5306                             struct comedi_insn *insn,
5307                             unsigned int *data)
5308 {
5309         const struct ni_board_struct *board = comedi_board(dev);
5310         struct ni_private *devpriv __maybe_unused = dev->private;
5311
5312         if (!(board->reg_type & ni_reg_m_series_mask))
5313                 return -ENOTSUPP;
5314
5315         if (comedi_dio_update_state(s, data))
5316                 ni_writew(s->state, M_Offset_PFI_DO);
5317
5318         data[1] = ni_readw(M_Offset_PFI_DI);
5319
5320         return insn->n;
5321 }
5322
5323 static int ni_pfi_insn_config(struct comedi_device *dev,
5324                               struct comedi_subdevice *s,
5325                               struct comedi_insn *insn, unsigned int *data)
5326 {
5327         struct ni_private *devpriv = dev->private;
5328         unsigned int chan;
5329
5330         if (insn->n < 1)
5331                 return -EINVAL;
5332
5333         chan = CR_CHAN(insn->chanspec);
5334
5335         switch (data[0]) {
5336         case COMEDI_OUTPUT:
5337                 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1 << chan, 1);
5338                 break;
5339         case COMEDI_INPUT:
5340                 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1 << chan, 0);
5341                 break;
5342         case INSN_CONFIG_DIO_QUERY:
5343                 data[1] =
5344                     (devpriv->io_bidirection_pin_reg & (1 << chan)) ?
5345                     COMEDI_OUTPUT : COMEDI_INPUT;
5346                 return 0;
5347                 break;
5348         case INSN_CONFIG_SET_ROUTING:
5349                 return ni_set_pfi_routing(dev, chan, data[1]);
5350                 break;
5351         case INSN_CONFIG_GET_ROUTING:
5352                 data[1] = ni_get_pfi_routing(dev, chan);
5353                 break;
5354         case INSN_CONFIG_FILTER:
5355                 return ni_config_filter(dev, chan, data[1]);
5356                 break;
5357         default:
5358                 return -EINVAL;
5359         }
5360         return 0;
5361 }
5362
5363 /*
5364  *
5365  *  NI RTSI Bus Functions
5366  *
5367  */
5368 static void ni_rtsi_init(struct comedi_device *dev)
5369 {
5370         const struct ni_board_struct *board = comedi_board(dev);
5371         struct ni_private *devpriv = dev->private;
5372
5373         /*  Initialises the RTSI bus signal switch to a default state */
5374
5375         /*  Set clock mode to internal */
5376         devpriv->clock_and_fout2 = MSeries_RTSI_10MHz_Bit;
5377         if (ni_set_master_clock(dev, NI_MIO_INTERNAL_CLOCK, 0) < 0) {
5378                 printk("ni_set_master_clock failed, bug?");
5379         }
5380         /*  default internal lines routing to RTSI bus lines */
5381         devpriv->rtsi_trig_a_output_reg =
5382             RTSI_Trig_Output_Bits(0,
5383                                   NI_RTSI_OUTPUT_ADR_START1) |
5384             RTSI_Trig_Output_Bits(1,
5385                                   NI_RTSI_OUTPUT_ADR_START2) |
5386             RTSI_Trig_Output_Bits(2,
5387                                   NI_RTSI_OUTPUT_SCLKG) |
5388             RTSI_Trig_Output_Bits(3, NI_RTSI_OUTPUT_DACUPDN);
5389         devpriv->stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5390                             RTSI_Trig_A_Output_Register);
5391         devpriv->rtsi_trig_b_output_reg =
5392             RTSI_Trig_Output_Bits(4,
5393                                   NI_RTSI_OUTPUT_DA_START1) |
5394             RTSI_Trig_Output_Bits(5,
5395                                   NI_RTSI_OUTPUT_G_SRC0) |
5396             RTSI_Trig_Output_Bits(6, NI_RTSI_OUTPUT_G_GATE0);
5397         if (board->reg_type & ni_reg_m_series_mask)
5398                 devpriv->rtsi_trig_b_output_reg |=
5399                     RTSI_Trig_Output_Bits(7, NI_RTSI_OUTPUT_RTSI_OSC);
5400         devpriv->stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5401                             RTSI_Trig_B_Output_Register);
5402
5403 /*
5404 * Sets the source and direction of the 4 on board lines
5405 * devpriv->stc_writew(dev, 0x0000, RTSI_Board_Register);
5406 */
5407 }
5408
5409 static int ni_rtsi_insn_bits(struct comedi_device *dev,
5410                              struct comedi_subdevice *s,
5411                              struct comedi_insn *insn, unsigned int *data)
5412 {
5413         data[1] = 0;
5414
5415         return insn->n;
5416 }
5417
5418 /* Find best multiplier/divider to try and get the PLL running at 80 MHz
5419  * given an arbitrary frequency input clock */
5420 static int ni_mseries_get_pll_parameters(unsigned reference_period_ns,
5421                                          unsigned *freq_divider,
5422                                          unsigned *freq_multiplier,
5423                                          unsigned *actual_period_ns)
5424 {
5425         unsigned div;
5426         unsigned best_div = 1;
5427         static const unsigned max_div = 0x10;
5428         unsigned mult;
5429         unsigned best_mult = 1;
5430         static const unsigned max_mult = 0x100;
5431         static const unsigned pico_per_nano = 1000;
5432
5433         const unsigned reference_picosec = reference_period_ns * pico_per_nano;
5434         /* m-series wants the phased-locked loop to output 80MHz, which is divided by 4 to
5435          * 20 MHz for most timing clocks */
5436         static const unsigned target_picosec = 12500;
5437         static const unsigned fudge_factor_80_to_20Mhz = 4;
5438         int best_period_picosec = 0;
5439         for (div = 1; div <= max_div; ++div) {
5440                 for (mult = 1; mult <= max_mult; ++mult) {
5441                         unsigned new_period_ps =
5442                             (reference_picosec * div) / mult;
5443                         if (abs(new_period_ps - target_picosec) <
5444                             abs(best_period_picosec - target_picosec)) {
5445                                 best_period_picosec = new_period_ps;
5446                                 best_div = div;
5447                                 best_mult = mult;
5448                         }
5449                 }
5450         }
5451         if (best_period_picosec == 0) {
5452                 printk("%s: bug, failed to find pll parameters\n", __func__);
5453                 return -EIO;
5454         }
5455         *freq_divider = best_div;
5456         *freq_multiplier = best_mult;
5457         *actual_period_ns =
5458             (best_period_picosec * fudge_factor_80_to_20Mhz +
5459              (pico_per_nano / 2)) / pico_per_nano;
5460         return 0;
5461 }
5462
5463 static inline unsigned num_configurable_rtsi_channels(struct comedi_device *dev)
5464 {
5465         const struct ni_board_struct *board = comedi_board(dev);
5466
5467         if (board->reg_type & ni_reg_m_series_mask)
5468                 return 8;
5469         else
5470                 return 7;
5471 }
5472
5473 static int ni_mseries_set_pll_master_clock(struct comedi_device *dev,
5474                                            unsigned source, unsigned period_ns)
5475 {
5476         struct ni_private *devpriv = dev->private;
5477         static const unsigned min_period_ns = 50;
5478         static const unsigned max_period_ns = 1000;
5479         static const unsigned timeout = 1000;
5480         unsigned pll_control_bits;
5481         unsigned freq_divider;
5482         unsigned freq_multiplier;
5483         unsigned i;
5484         int retval;
5485
5486         if (source == NI_MIO_PLL_PXI10_CLOCK)
5487                 period_ns = 100;
5488         /*  these limits are somewhat arbitrary, but NI advertises 1 to 20MHz range so we'll use that */
5489         if (period_ns < min_period_ns || period_ns > max_period_ns) {
5490                 printk
5491                     ("%s: you must specify an input clock frequency between %i and %i nanosec "
5492                      "for the phased-lock loop.\n", __func__,
5493                      min_period_ns, max_period_ns);
5494                 return -EINVAL;
5495         }
5496         devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
5497         devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5498                             RTSI_Trig_Direction_Register);
5499         pll_control_bits =
5500             MSeries_PLL_Enable_Bit | MSeries_PLL_VCO_Mode_75_150MHz_Bits;
5501         devpriv->clock_and_fout2 |=
5502             MSeries_Timebase1_Select_Bit | MSeries_Timebase3_Select_Bit;
5503         devpriv->clock_and_fout2 &= ~MSeries_PLL_In_Source_Select_Mask;
5504         switch (source) {
5505         case NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK:
5506                 devpriv->clock_and_fout2 |=
5507                     MSeries_PLL_In_Source_Select_Star_Trigger_Bits;
5508                 retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
5509                                                        &freq_multiplier,
5510                                                        &devpriv->clock_ns);
5511                 if (retval < 0)
5512                         return retval;
5513                 break;
5514         case NI_MIO_PLL_PXI10_CLOCK:
5515                 /* pxi clock is 10MHz */
5516                 devpriv->clock_and_fout2 |=
5517                     MSeries_PLL_In_Source_Select_PXI_Clock10;
5518                 retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
5519                                                        &freq_multiplier,
5520                                                        &devpriv->clock_ns);
5521                 if (retval < 0)
5522                         return retval;
5523                 break;
5524         default:
5525                 {
5526                         unsigned rtsi_channel;
5527                         static const unsigned max_rtsi_channel = 7;
5528                         for (rtsi_channel = 0; rtsi_channel <= max_rtsi_channel;
5529                              ++rtsi_channel) {
5530                                 if (source ==
5531                                     NI_MIO_PLL_RTSI_CLOCK(rtsi_channel)) {
5532                                         devpriv->clock_and_fout2 |=
5533                                             MSeries_PLL_In_Source_Select_RTSI_Bits
5534                                             (rtsi_channel);
5535                                         break;
5536                                 }
5537                         }
5538                         if (rtsi_channel > max_rtsi_channel)
5539                                 return -EINVAL;
5540                         retval = ni_mseries_get_pll_parameters(period_ns,
5541                                                                &freq_divider,
5542                                                                &freq_multiplier,
5543                                                                &devpriv->
5544                                                                clock_ns);
5545                         if (retval < 0)
5546                                 return retval;
5547                 }
5548                 break;
5549         }
5550         ni_writew(devpriv->clock_and_fout2, M_Offset_Clock_and_Fout2);
5551         pll_control_bits |=
5552             MSeries_PLL_Divisor_Bits(freq_divider) |
5553             MSeries_PLL_Multiplier_Bits(freq_multiplier);
5554
5555         /* printk("using divider=%i, multiplier=%i for PLL. pll_control_bits = 0x%x\n",
5556          * freq_divider, freq_multiplier, pll_control_bits); */
5557         /* printk("clock_ns=%d\n", devpriv->clock_ns); */
5558         ni_writew(pll_control_bits, M_Offset_PLL_Control);
5559         devpriv->clock_source = source;
5560         /* it seems to typically take a few hundred microseconds for PLL to lock */
5561         for (i = 0; i < timeout; ++i) {
5562                 if (ni_readw(M_Offset_PLL_Status) & MSeries_PLL_Locked_Bit) {
5563                         break;
5564                 }
5565                 udelay(1);
5566         }
5567         if (i == timeout) {
5568                 printk
5569                     ("%s: timed out waiting for PLL to lock to reference clock source %i with period %i ns.\n",
5570                      __func__, source, period_ns);
5571                 return -ETIMEDOUT;
5572         }
5573         return 3;
5574 }
5575
5576 static int ni_set_master_clock(struct comedi_device *dev, unsigned source,
5577                                unsigned period_ns)
5578 {
5579         const struct ni_board_struct *board = comedi_board(dev);
5580         struct ni_private *devpriv = dev->private;
5581
5582         if (source == NI_MIO_INTERNAL_CLOCK) {
5583                 devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
5584                 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5585                                     RTSI_Trig_Direction_Register);
5586                 devpriv->clock_ns = TIMEBASE_1_NS;
5587                 if (board->reg_type & ni_reg_m_series_mask) {
5588                         devpriv->clock_and_fout2 &=
5589                             ~(MSeries_Timebase1_Select_Bit |
5590                               MSeries_Timebase3_Select_Bit);
5591                         ni_writew(devpriv->clock_and_fout2,
5592                                   M_Offset_Clock_and_Fout2);
5593                         ni_writew(0, M_Offset_PLL_Control);
5594                 }
5595                 devpriv->clock_source = source;
5596         } else {
5597                 if (board->reg_type & ni_reg_m_series_mask) {
5598                         return ni_mseries_set_pll_master_clock(dev, source,
5599                                                                period_ns);
5600                 } else {
5601                         if (source == NI_MIO_RTSI_CLOCK) {
5602                                 devpriv->rtsi_trig_direction_reg |=
5603                                     Use_RTSI_Clock_Bit;
5604                                 devpriv->stc_writew(dev,
5605                                                     devpriv->
5606                                                     rtsi_trig_direction_reg,
5607                                                     RTSI_Trig_Direction_Register);
5608                                 if (period_ns == 0) {
5609                                         printk
5610                                             ("%s: we don't handle an unspecified clock period correctly yet, returning error.\n",
5611                                              __func__);
5612                                         return -EINVAL;
5613                                 } else {
5614                                         devpriv->clock_ns = period_ns;
5615                                 }
5616                                 devpriv->clock_source = source;
5617                         } else
5618                                 return -EINVAL;
5619                 }
5620         }
5621         return 3;
5622 }
5623
5624 static int ni_valid_rtsi_output_source(struct comedi_device *dev, unsigned chan,
5625                                        unsigned source)
5626 {
5627         const struct ni_board_struct *board = comedi_board(dev);
5628
5629         if (chan >= num_configurable_rtsi_channels(dev)) {
5630                 if (chan == old_RTSI_clock_channel) {
5631                         if (source == NI_RTSI_OUTPUT_RTSI_OSC)
5632                                 return 1;
5633                         else {
5634                                 printk
5635                                     ("%s: invalid source for channel=%i, channel %i is always the RTSI clock for pre-m-series boards.\n",
5636                                      __func__, chan, old_RTSI_clock_channel);
5637                                 return 0;
5638                         }
5639                 }
5640                 return 0;
5641         }
5642         switch (source) {
5643         case NI_RTSI_OUTPUT_ADR_START1:
5644         case NI_RTSI_OUTPUT_ADR_START2:
5645         case NI_RTSI_OUTPUT_SCLKG:
5646         case NI_RTSI_OUTPUT_DACUPDN:
5647         case NI_RTSI_OUTPUT_DA_START1:
5648         case NI_RTSI_OUTPUT_G_SRC0:
5649         case NI_RTSI_OUTPUT_G_GATE0:
5650         case NI_RTSI_OUTPUT_RGOUT0:
5651         case NI_RTSI_OUTPUT_RTSI_BRD_0:
5652                 return 1;
5653                 break;
5654         case NI_RTSI_OUTPUT_RTSI_OSC:
5655                 if (board->reg_type & ni_reg_m_series_mask)
5656                         return 1;
5657                 else
5658                         return 0;
5659                 break;
5660         default:
5661                 return 0;
5662                 break;
5663         }
5664 }
5665
5666 static int ni_set_rtsi_routing(struct comedi_device *dev, unsigned chan,
5667                                unsigned source)
5668 {
5669         struct ni_private *devpriv = dev->private;
5670
5671         if (ni_valid_rtsi_output_source(dev, chan, source) == 0)
5672                 return -EINVAL;
5673         if (chan < 4) {
5674                 devpriv->rtsi_trig_a_output_reg &= ~RTSI_Trig_Output_Mask(chan);
5675                 devpriv->rtsi_trig_a_output_reg |=
5676                     RTSI_Trig_Output_Bits(chan, source);
5677                 devpriv->stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5678                                     RTSI_Trig_A_Output_Register);
5679         } else if (chan < 8) {
5680                 devpriv->rtsi_trig_b_output_reg &= ~RTSI_Trig_Output_Mask(chan);
5681                 devpriv->rtsi_trig_b_output_reg |=
5682                     RTSI_Trig_Output_Bits(chan, source);
5683                 devpriv->stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5684                                     RTSI_Trig_B_Output_Register);
5685         }
5686         return 2;
5687 }
5688
5689 static unsigned ni_get_rtsi_routing(struct comedi_device *dev, unsigned chan)
5690 {
5691         struct ni_private *devpriv = dev->private;
5692
5693         if (chan < 4) {
5694                 return RTSI_Trig_Output_Source(chan,
5695                                                devpriv->rtsi_trig_a_output_reg);
5696         } else if (chan < num_configurable_rtsi_channels(dev)) {
5697                 return RTSI_Trig_Output_Source(chan,
5698                                                devpriv->rtsi_trig_b_output_reg);
5699         } else {
5700                 if (chan == old_RTSI_clock_channel)
5701                         return NI_RTSI_OUTPUT_RTSI_OSC;
5702                 printk("%s: bug! should never get here?\n", __func__);
5703                 return 0;
5704         }
5705 }
5706
5707 static int ni_rtsi_insn_config(struct comedi_device *dev,
5708                                struct comedi_subdevice *s,
5709                                struct comedi_insn *insn, unsigned int *data)
5710 {
5711         const struct ni_board_struct *board = comedi_board(dev);
5712         struct ni_private *devpriv = dev->private;
5713         unsigned int chan = CR_CHAN(insn->chanspec);
5714
5715         switch (data[0]) {
5716         case INSN_CONFIG_DIO_OUTPUT:
5717                 if (chan < num_configurable_rtsi_channels(dev)) {
5718                         devpriv->rtsi_trig_direction_reg |=
5719                             RTSI_Output_Bit(chan,
5720                                 (board->reg_type & ni_reg_m_series_mask) != 0);
5721                 } else if (chan == old_RTSI_clock_channel) {
5722                         devpriv->rtsi_trig_direction_reg |=
5723                             Drive_RTSI_Clock_Bit;
5724                 }
5725                 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5726                                     RTSI_Trig_Direction_Register);
5727                 break;
5728         case INSN_CONFIG_DIO_INPUT:
5729                 if (chan < num_configurable_rtsi_channels(dev)) {
5730                         devpriv->rtsi_trig_direction_reg &=
5731                             ~RTSI_Output_Bit(chan,
5732                                 (board->reg_type & ni_reg_m_series_mask) != 0);
5733                 } else if (chan == old_RTSI_clock_channel) {
5734                         devpriv->rtsi_trig_direction_reg &=
5735                             ~Drive_RTSI_Clock_Bit;
5736                 }
5737                 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5738                                     RTSI_Trig_Direction_Register);
5739                 break;
5740         case INSN_CONFIG_DIO_QUERY:
5741                 if (chan < num_configurable_rtsi_channels(dev)) {
5742                         data[1] =
5743                             (devpriv->rtsi_trig_direction_reg &
5744                              RTSI_Output_Bit(chan,
5745                                 (board->reg_type & ni_reg_m_series_mask) != 0))
5746                                 ? INSN_CONFIG_DIO_OUTPUT
5747                                 : INSN_CONFIG_DIO_INPUT;
5748                 } else if (chan == old_RTSI_clock_channel) {
5749                         data[1] =
5750                             (devpriv->rtsi_trig_direction_reg &
5751                              Drive_RTSI_Clock_Bit)
5752                             ? INSN_CONFIG_DIO_OUTPUT : INSN_CONFIG_DIO_INPUT;
5753                 }
5754                 return 2;
5755                 break;
5756         case INSN_CONFIG_SET_CLOCK_SRC:
5757                 return ni_set_master_clock(dev, data[1], data[2]);
5758                 break;
5759         case INSN_CONFIG_GET_CLOCK_SRC:
5760                 data[1] = devpriv->clock_source;
5761                 data[2] = devpriv->clock_ns;
5762                 return 3;
5763                 break;
5764         case INSN_CONFIG_SET_ROUTING:
5765                 return ni_set_rtsi_routing(dev, chan, data[1]);
5766                 break;
5767         case INSN_CONFIG_GET_ROUTING:
5768                 data[1] = ni_get_rtsi_routing(dev, chan);
5769                 return 2;
5770                 break;
5771         default:
5772                 return -EINVAL;
5773                 break;
5774         }
5775         return 1;
5776 }
5777
5778 static int cs5529_wait_for_idle(struct comedi_device *dev)
5779 {
5780         unsigned short status;
5781         const int timeout = HZ;
5782         int i;
5783
5784         for (i = 0; i < timeout; i++) {
5785                 status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
5786                 if ((status & CSS_ADC_BUSY) == 0) {
5787                         break;
5788                 }
5789                 set_current_state(TASK_INTERRUPTIBLE);
5790                 if (schedule_timeout(1)) {
5791                         return -EIO;
5792                 }
5793         }
5794 /* printk("looped %i times waiting for idle\n", i); */
5795         if (i == timeout) {
5796                 printk("%s: %s: timeout\n", __FILE__, __func__);
5797                 return -ETIME;
5798         }
5799         return 0;
5800 }
5801
5802 static void cs5529_command(struct comedi_device *dev, unsigned short value)
5803 {
5804         static const int timeout = 100;
5805         int i;
5806
5807         ni_ao_win_outw(dev, value, CAL_ADC_Command_67xx);
5808         /* give time for command to start being serially clocked into cs5529.
5809          * this insures that the CSS_ADC_BUSY bit will get properly
5810          * set before we exit this function.
5811          */
5812         for (i = 0; i < timeout; i++) {
5813                 if ((ni_ao_win_inw(dev, CAL_ADC_Status_67xx) & CSS_ADC_BUSY))
5814                         break;
5815                 udelay(1);
5816         }
5817 /* printk("looped %i times writing command to cs5529\n", i); */
5818         if (i == timeout) {
5819                 comedi_error(dev, "possible problem - never saw adc go busy?");
5820         }
5821 }
5822
5823 /* write to cs5529 register */
5824 static void cs5529_config_write(struct comedi_device *dev, unsigned int value,
5825                                 unsigned int reg_select_bits)
5826 {
5827         ni_ao_win_outw(dev, ((value >> 16) & 0xff),
5828                        CAL_ADC_Config_Data_High_Word_67xx);
5829         ni_ao_win_outw(dev, (value & 0xffff),
5830                        CAL_ADC_Config_Data_Low_Word_67xx);
5831         reg_select_bits &= CSCMD_REGISTER_SELECT_MASK;
5832         cs5529_command(dev, CSCMD_COMMAND | reg_select_bits);
5833         if (cs5529_wait_for_idle(dev))
5834                 comedi_error(dev, "time or signal in cs5529_config_write()");
5835 }
5836
5837 static int cs5529_do_conversion(struct comedi_device *dev, unsigned short *data)
5838 {
5839         int retval;
5840         unsigned short status;
5841
5842         cs5529_command(dev, CSCMD_COMMAND | CSCMD_SINGLE_CONVERSION);
5843         retval = cs5529_wait_for_idle(dev);
5844         if (retval) {
5845                 comedi_error(dev,
5846                              "timeout or signal in cs5529_do_conversion()");
5847                 return -ETIME;
5848         }
5849         status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
5850         if (status & CSS_OSC_DETECT) {
5851                 printk
5852                     ("ni_mio_common: cs5529 conversion error, status CSS_OSC_DETECT\n");
5853                 return -EIO;
5854         }
5855         if (status & CSS_OVERRANGE) {
5856                 printk
5857                     ("ni_mio_common: cs5529 conversion error, overrange (ignoring)\n");
5858         }
5859         if (data) {
5860                 *data = ni_ao_win_inw(dev, CAL_ADC_Data_67xx);
5861                 /* cs5529 returns 16 bit signed data in bipolar mode */
5862                 *data ^= (1 << 15);
5863         }
5864         return 0;
5865 }
5866
5867 static int cs5529_ai_insn_read(struct comedi_device *dev,
5868                                struct comedi_subdevice *s,
5869                                struct comedi_insn *insn, unsigned int *data)
5870 {
5871         int n, retval;
5872         unsigned short sample;
5873         unsigned int channel_select;
5874         const unsigned int INTERNAL_REF = 0x1000;
5875
5876         /* Set calibration adc source.  Docs lie, reference select bits 8 to 11
5877          * do nothing. bit 12 seems to chooses internal reference voltage, bit
5878          * 13 causes the adc input to go overrange (maybe reads external reference?) */
5879         if (insn->chanspec & CR_ALT_SOURCE)
5880                 channel_select = INTERNAL_REF;
5881         else
5882                 channel_select = CR_CHAN(insn->chanspec);
5883         ni_ao_win_outw(dev, channel_select, AO_Calibration_Channel_Select_67xx);
5884
5885         for (n = 0; n < insn->n; n++) {
5886                 retval = cs5529_do_conversion(dev, &sample);
5887                 if (retval < 0)
5888                         return retval;
5889                 data[n] = sample;
5890         }
5891         return insn->n;
5892 }
5893
5894 static int init_cs5529(struct comedi_device *dev)
5895 {
5896         unsigned int config_bits =
5897             CSCFG_PORT_MODE | CSCFG_WORD_RATE_2180_CYCLES;
5898
5899 #if 1
5900         /* do self-calibration */
5901         cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET_GAIN,
5902                             CSCMD_CONFIG_REGISTER);
5903         /* need to force a conversion for calibration to run */
5904         cs5529_do_conversion(dev, NULL);
5905 #else
5906         /* force gain calibration to 1 */
5907         cs5529_config_write(dev, 0x400000, CSCMD_GAIN_REGISTER);
5908         cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET,
5909                             CSCMD_CONFIG_REGISTER);
5910         if (cs5529_wait_for_idle(dev))
5911                 comedi_error(dev, "timeout or signal in init_cs5529()\n");
5912 #endif
5913         return 0;
5914 }