2 comedi/drivers/ni_pcimio.c
3 Hardware driver for NI PCI-MIO E series cards
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 Description: National Instruments PCI-MIO-E series and M series (all boards)
25 Author: ds, John Hallen, Frank Mori Hess, Rolf Mueller, Herbert Peremans,
26 Herman Bruyninckx, Terry Barnaby
28 Devices: [National Instruments] PCI-MIO-16XE-50 (ni_pcimio),
29 PCI-MIO-16XE-10, PXI-6030E, PCI-MIO-16E-1, PCI-MIO-16E-4, PCI-6014, PCI-6040E,
30 PXI-6040E, PCI-6030E, PCI-6031E, PCI-6032E, PCI-6033E, PCI-6071E, PCI-6023E,
31 PCI-6024E, PCI-6025E, PXI-6025E, PCI-6034E, PCI-6035E, PCI-6052E,
32 PCI-6110, PCI-6111, PCI-6220, PCI-6221, PCI-6224, PXI-6224,
33 PCI-6225, PXI-6225, PCI-6229, PCI-6250, PCI-6251, PCIe-6251, PXIe-6251,
34 PCI-6254, PCI-6259, PCIe-6259,
35 PCI-6280, PCI-6281, PXI-6281, PCI-6284, PCI-6289,
36 PCI-6711, PXI-6711, PCI-6713, PXI-6713,
37 PXI-6071E, PCI-6070E, PXI-6070E,
38 PXI-6052E, PCI-6036E, PCI-6731, PCI-6733, PXI-6733,
40 Updated: Mon, 09 Jan 2012 14:52:48 +0000
42 These boards are almost identical to the AT-MIO E series, except that
43 they use the PCI bus instead of ISA (i.e., AT). See the notes for
44 the ni_atmio.o driver for additional information about these boards.
46 Autocalibration is supported on many of the devices, using the
47 comedi_calibrate (or comedi_soft_calibrate for m-series) utility.
48 M-Series boards do analog input and analog output calibration entirely
49 in software. The software calibration corrects
50 the analog input for offset, gain and
51 nonlinearity. The analog outputs are corrected for offset and gain.
52 See the comedilib documentation on comedi_get_softcal_converter() for
55 By default, the driver uses DMA to transfer analog input data to
56 memory. When DMA is enabled, not all triggering features are
59 Digital I/O may not work on 673x.
61 Note that the PCI-6143 is a simultaineous sampling device with 8 convertors.
62 With this board all of the convertors perform one simultaineous sample during
63 a scan interval. The period for a scan is used for the convert time in a
64 Comedi cmd. The convert trigger source is normally set to TRIG_NOW by default.
66 The RTSI trigger bus is supported on these cards on
67 subdevice 10. See the comedilib documentation for details.
69 Information (number of channels, bits, etc.) for some devices may be
70 incorrect. Please check this and submit a bug if there are problems
73 SCXI is probably broken for m-series boards.
76 - When DMA is enabled, COMEDI_EV_CONVERT does
81 The PCI-MIO E series driver was originally written by
82 Tomasz Motylewski <...>, and ported to comedi by ds.
86 341079b.pdf PCI E Series Register-Level Programmer Manual
87 340934b.pdf DAQ-STC reference manual
89 322080b.pdf 6711/6713/6715 User Manual
91 320945c.pdf PCI E Series User Manual
92 322138a.pdf PCI-6052E and DAQPad-6052E User Manual
96 need to deal with external reference for DAC, and other DAC
97 properties in board properties
99 deal with at-mio-16de-10 revision D to N changes, etc.
101 need to add other CALDAC type
103 need to slow down DAC loading. I don't trust NI's claim that
104 two writes to the PCI bus slows IO enough. I would prefer to
105 use udelay(). Timing specs: (clock)
113 #include "../comedidev.h"
115 #include <asm/byteorder.h>
116 #include <linux/delay.h>
121 /* #define PCI_DEBUG */
128 #define MAX_N_CALDACS (16+16+2)
130 #define DRV_NAME "ni_pcimio"
132 /* These are not all the possible ao ranges for 628x boards.
133 They can do OFFSET +- REFERENCE where OFFSET can be
134 0V, 5V, APFI<0,1>, or AO<0...3> and RANGE can
135 be 10V, 5V, 2V, 1V, APFI<0,1>, AO<0...3>. That's
136 63 different possibilities. An AO channel
137 can not act as it's own OFFSET or REFERENCE.
139 static const struct comedi_lrange range_ni_M_628x_ao = { 8, {
152 static const struct comedi_lrange range_ni_M_625x_ao = { 3, {
159 static const struct comedi_lrange range_ni_M_622x_ao = { 1, {
164 static const struct ni_board_struct ni_boards[] = {
166 .device_id = 0x0162, /* NI also says 0x1620. typo? */
167 .name = "pci-mio-16xe-50",
170 .ai_fifo_depth = 2048,
172 .gainlkup = ai_gain_8,
177 .ao_range_table = &range_bipolar10,
180 .num_p0_dio_channels = 8,
181 .caldac = {dac8800, dac8043},
186 .name = "pci-mio-16xe-10", /* aka pci-6030E */
189 .ai_fifo_depth = 512,
191 .gainlkup = ai_gain_14,
195 .ao_fifo_depth = 2048,
196 .ao_range_table = &range_ni_E_ao_ext,
199 .num_p0_dio_channels = 8,
200 .caldac = {dac8800, dac8043, ad8522},
208 .ai_fifo_depth = 512,
210 .gainlkup = ai_gain_4,
215 .ao_range_table = &range_bipolar10,
218 .num_p0_dio_channels = 8,
219 .caldac = {ad8804_debug},
227 .ai_fifo_depth = 512,
229 .gainlkup = ai_gain_14,
233 .ao_fifo_depth = 2048,
234 .ao_range_table = &range_ni_E_ao_ext,
237 .num_p0_dio_channels = 8,
238 .caldac = {dac8800, dac8043, ad8522},
243 .name = "pci-mio-16e-1", /* aka pci-6070e */
246 .ai_fifo_depth = 512,
248 .gainlkup = ai_gain_16,
252 .ao_fifo_depth = 2048,
253 .ao_range_table = &range_ni_E_ao_ext,
256 .num_p0_dio_channels = 8,
262 .name = "pci-mio-16e-4", /* aka pci-6040e */
265 .ai_fifo_depth = 512,
267 .gainlkup = ai_gain_16,
268 /* .Note = there have been reported problems with full speed
273 .ao_fifo_depth = 512,
274 .ao_range_table = &range_ni_E_ao_ext,
277 .num_p0_dio_channels = 8,
278 .caldac = {ad8804_debug}, /* doc says mb88341 */
286 .ai_fifo_depth = 512,
288 .gainlkup = ai_gain_16,
292 .ao_fifo_depth = 512,
293 .ao_range_table = &range_ni_E_ao_ext,
296 .num_p0_dio_channels = 8,
306 .ai_fifo_depth = 512,
308 .gainlkup = ai_gain_14,
312 .ao_fifo_depth = 2048,
313 .ao_range_table = &range_ni_E_ao_ext,
316 .num_p0_dio_channels = 8,
317 .caldac = {dac8800, dac8043, ad8522},
325 .ai_fifo_depth = 512,
327 .gainlkup = ai_gain_14,
333 .num_p0_dio_channels = 8,
334 .caldac = {dac8800, dac8043, ad8522},
342 .ai_fifo_depth = 512,
344 .gainlkup = ai_gain_14,
350 .num_p0_dio_channels = 8,
351 .caldac = {dac8800, dac8043, ad8522},
359 .ai_fifo_depth = 512,
361 .gainlkup = ai_gain_16,
365 .ao_fifo_depth = 2048,
366 .ao_range_table = &range_ni_E_ao_ext,
369 .num_p0_dio_channels = 8,
370 .caldac = {ad8804_debug},
378 .ai_fifo_depth = 512,
380 .gainlkup = ai_gain_4,
385 .num_p0_dio_channels = 8,
386 .caldac = {ad8804_debug}, /* manual is wrong */
394 .ai_fifo_depth = 512,
396 .gainlkup = ai_gain_4,
401 .ao_range_table = &range_bipolar10,
404 .num_p0_dio_channels = 8,
405 .caldac = {ad8804_debug}, /* manual is wrong */
413 .ai_fifo_depth = 512,
415 .gainlkup = ai_gain_4,
420 .ao_range_table = &range_bipolar10,
423 .num_p0_dio_channels = 8,
424 .caldac = {ad8804_debug}, /* manual is wrong */
432 .ai_fifo_depth = 512,
434 .gainlkup = ai_gain_4,
439 .ao_range_table = &range_ni_E_ao_ext,
442 .num_p0_dio_channels = 8,
443 .caldac = {ad8804_debug}, /* manual is wrong */
452 .ai_fifo_depth = 512,
454 .gainlkup = ai_gain_4,
460 .num_p0_dio_channels = 8,
461 .caldac = {ad8804_debug},
469 .ai_fifo_depth = 512,
471 .gainlkup = ai_gain_4,
476 .ao_range_table = &range_bipolar10,
479 .num_p0_dio_channels = 8,
480 .caldac = {ad8804_debug},
488 .ai_fifo_depth = 512,
490 .gainlkup = ai_gain_16,
495 .ao_fifo_depth = 2048,
496 .ao_range_table = &range_ni_E_ao_ext,
498 .num_p0_dio_channels = 8,
499 .caldac = {ad8804_debug, ad8804_debug, ad8522}, /* manual is wrong */
501 {.device_id = 0x14e0,
505 .ai_fifo_depth = 8192,
507 .gainlkup = ai_gain_611x,
511 .reg_type = ni_reg_611x,
512 .ao_range_table = &range_bipolar10,
514 .ao_fifo_depth = 2048,
516 .num_p0_dio_channels = 8,
517 .caldac = {ad8804, ad8804},
524 .ai_fifo_depth = 8192,
526 .gainlkup = ai_gain_611x,
530 .reg_type = ni_reg_611x,
531 .ao_range_table = &range_bipolar10,
533 .ao_fifo_depth = 2048,
535 .num_p0_dio_channels = 8,
536 .caldac = {ad8804, ad8804},
539 /* The 6115 boards probably need their own driver */
545 .ai_fifo_depth = 8192,
547 .gainlkup = ai_gain_611x,
553 .ao_fifo_depth = 2048,
555 .num_p0_dio_channels = 8,
557 .caldac = {ad8804_debug, ad8804_debug, ad8804_debug}, /* XXX */
566 .ai_fifo_depth = 8192,
568 .gainlkup = ai_gain_611x,
574 .ao_fifo_depth = 2048,
577 .num_p0_dio_channels = 8,
578 caldac = {ad8804_debug, ad8804_debug, ad8804_debug}, /* XXX */
584 .n_adchan = 0, /* no analog input */
588 .ao_fifo_depth = 16384,
589 /* data sheet says 8192, but fifo really holds 16384 samples */
590 .ao_range_table = &range_bipolar10,
592 .num_p0_dio_channels = 8,
593 .reg_type = ni_reg_6711,
594 .caldac = {ad8804_debug},
599 .n_adchan = 0, /* no analog input */
603 .ao_fifo_depth = 16384,
604 .ao_range_table = &range_bipolar10,
606 .num_p0_dio_channels = 8,
607 .reg_type = ni_reg_6711,
608 .caldac = {ad8804_debug},
613 .n_adchan = 0, /* no analog input */
617 .ao_fifo_depth = 16384,
618 .ao_range_table = &range_bipolar10,
620 .num_p0_dio_channels = 8,
621 .reg_type = ni_reg_6713,
622 .caldac = {ad8804_debug, ad8804_debug},
627 .n_adchan = 0, /* no analog input */
631 .ao_fifo_depth = 16384,
632 .ao_range_table = &range_bipolar10,
634 .num_p0_dio_channels = 8,
635 .reg_type = ni_reg_6713,
636 .caldac = {ad8804_debug, ad8804_debug},
641 .n_adchan = 0, /* no analog input */
645 .ao_fifo_depth = 8192,
646 .ao_range_table = &range_bipolar10,
648 .num_p0_dio_channels = 8,
649 .reg_type = ni_reg_6711,
650 .caldac = {ad8804_debug},
652 #if 0 /* need device ids */
656 .n_adchan = 0, /* no analog input */
660 .ao_fifo_depth = 8192,
661 .ao_range_table = &range_bipolar10,
662 .num_p0_dio_channels = 8,
663 .reg_type = ni_reg_6711,
664 .caldac = {ad8804_debug},
670 .n_adchan = 0, /* no analog input */
674 .ao_fifo_depth = 16384,
675 .ao_range_table = &range_bipolar10,
677 .num_p0_dio_channels = 8,
678 .reg_type = ni_reg_6713,
679 .caldac = {ad8804_debug, ad8804_debug},
684 .n_adchan = 0, /* no analog input */
688 .ao_fifo_depth = 16384,
689 .ao_range_table = &range_bipolar10,
691 .num_p0_dio_channels = 8,
692 .reg_type = ni_reg_6713,
693 .caldac = {ad8804_debug, ad8804_debug},
700 .ai_fifo_depth = 512,
702 .gainlkup = ai_gain_16,
706 .ao_fifo_depth = 2048,
707 .ao_range_table = &range_ni_E_ao_ext,
710 .num_p0_dio_channels = 8,
711 .caldac = {ad8804_debug},
719 .ai_fifo_depth = 512,
721 .gainlkup = ai_gain_16,
725 .ao_fifo_depth = 2048,
726 .ao_range_table = &range_ni_E_ao_ext,
729 .num_p0_dio_channels = 8,
730 .caldac = {ad8804_debug},
738 .ai_fifo_depth = 512,
740 .gainlkup = ai_gain_16,
745 .ao_fifo_depth = 2048,
746 .ao_range_table = &range_ni_E_ao_ext,
748 .num_p0_dio_channels = 8,
749 .caldac = {mb88341, mb88341, ad8522},
756 .ai_fifo_depth = 512,
758 .gainlkup = ai_gain_14,
762 .ao_fifo_depth = 2048,
763 .ao_range_table = &range_ni_E_ao_ext,
766 .num_p0_dio_channels = 8,
767 .caldac = {dac8800, dac8043, ad8522},
774 .ai_fifo_depth = 512,
776 .gainlkup = ai_gain_4,
781 .ao_range_table = &range_bipolar10,
784 .num_p0_dio_channels = 8,
785 .caldac = {ad8804_debug},
793 .ai_fifo_depth = 512,
795 .gainlkup = ai_gain_622x,
800 .num_p0_dio_channels = 8,
801 .reg_type = ni_reg_622x,
803 .caldac = {caldac_none},
811 .ai_fifo_depth = 4095,
812 .gainlkup = ai_gain_622x,
816 .ao_fifo_depth = 8191,
817 .ao_range_table = &range_ni_M_622x_ao,
818 .reg_type = ni_reg_622x,
821 .num_p0_dio_channels = 8,
822 .caldac = {caldac_none},
827 .name = "pci-6221_37pin",
830 .ai_fifo_depth = 4095,
831 .gainlkup = ai_gain_622x,
835 .ao_fifo_depth = 8191,
836 .ao_range_table = &range_ni_M_622x_ao,
837 .reg_type = ni_reg_622x,
840 .num_p0_dio_channels = 8,
841 .caldac = {caldac_none},
849 .ai_fifo_depth = 4095,
850 .gainlkup = ai_gain_622x,
855 .reg_type = ni_reg_622x,
857 .num_p0_dio_channels = 32,
858 .caldac = {caldac_none},
866 .ai_fifo_depth = 4095,
867 .gainlkup = ai_gain_622x,
872 .reg_type = ni_reg_622x,
874 .num_p0_dio_channels = 32,
875 .caldac = {caldac_none},
883 .ai_fifo_depth = 4095,
884 .gainlkup = ai_gain_622x,
888 .ao_fifo_depth = 8191,
889 .ao_range_table = &range_ni_M_622x_ao,
890 .reg_type = ni_reg_622x,
893 .num_p0_dio_channels = 32,
894 .caldac = {caldac_none},
902 .ai_fifo_depth = 4095,
903 .gainlkup = ai_gain_622x,
907 .ao_fifo_depth = 8191,
908 .ao_range_table = &range_ni_M_622x_ao,
909 .reg_type = ni_reg_622x,
912 .num_p0_dio_channels = 32,
913 .caldac = {caldac_none},
921 .ai_fifo_depth = 4095,
922 .gainlkup = ai_gain_622x,
926 .ao_fifo_depth = 8191,
927 .ao_range_table = &range_ni_M_622x_ao,
928 .reg_type = ni_reg_622x,
931 .num_p0_dio_channels = 32,
932 .caldac = {caldac_none},
940 .ai_fifo_depth = 4095,
941 .gainlkup = ai_gain_628x,
946 .reg_type = ni_reg_625x,
948 .num_p0_dio_channels = 8,
949 .caldac = {caldac_none},
957 .ai_fifo_depth = 4095,
958 .gainlkup = ai_gain_628x,
962 .ao_fifo_depth = 8191,
963 .ao_range_table = &range_ni_M_625x_ao,
964 .reg_type = ni_reg_625x,
967 .num_p0_dio_channels = 8,
968 .caldac = {caldac_none},
976 .ai_fifo_depth = 4095,
977 .gainlkup = ai_gain_628x,
981 .ao_fifo_depth = 8191,
982 .ao_range_table = &range_ni_M_625x_ao,
983 .reg_type = ni_reg_625x,
986 .num_p0_dio_channels = 8,
987 .caldac = {caldac_none},
995 .ai_fifo_depth = 4095,
996 .gainlkup = ai_gain_628x,
1000 .ao_fifo_depth = 8191,
1001 .ao_range_table = &range_ni_M_625x_ao,
1002 .reg_type = ni_reg_625x,
1005 .num_p0_dio_channels = 8,
1006 .caldac = {caldac_none},
1010 .device_id = 0x70b7,
1014 .ai_fifo_depth = 4095,
1015 .gainlkup = ai_gain_628x,
1020 .reg_type = ni_reg_625x,
1022 .num_p0_dio_channels = 32,
1023 .caldac = {caldac_none},
1027 .device_id = 0x70ab,
1031 .ai_fifo_depth = 4095,
1032 .gainlkup = ai_gain_628x,
1036 .ao_fifo_depth = 8191,
1037 .ao_range_table = &range_ni_M_625x_ao,
1038 .reg_type = ni_reg_625x,
1041 .num_p0_dio_channels = 32,
1042 .caldac = {caldac_none},
1046 .device_id = 0x717f,
1047 .name = "pcie-6259",
1050 .ai_fifo_depth = 4095,
1051 .gainlkup = ai_gain_628x,
1055 .ao_fifo_depth = 8191,
1056 .ao_range_table = &range_ni_M_625x_ao,
1057 .reg_type = ni_reg_625x,
1060 .num_p0_dio_channels = 32,
1061 .caldac = {caldac_none},
1065 .device_id = 0x70b6,
1069 .ai_fifo_depth = 2047,
1070 .gainlkup = ai_gain_628x,
1074 .ao_fifo_depth = 8191,
1075 .reg_type = ni_reg_628x,
1077 .num_p0_dio_channels = 8,
1078 .caldac = {caldac_none},
1082 .device_id = 0x70bd,
1086 .ai_fifo_depth = 2047,
1087 .gainlkup = ai_gain_628x,
1091 .ao_fifo_depth = 8191,
1092 .ao_range_table = &range_ni_M_628x_ao,
1093 .reg_type = ni_reg_628x,
1096 .num_p0_dio_channels = 8,
1097 .caldac = {caldac_none},
1101 .device_id = 0x70bf,
1105 .ai_fifo_depth = 2047,
1106 .gainlkup = ai_gain_628x,
1110 .ao_fifo_depth = 8191,
1111 .ao_range_table = &range_ni_M_628x_ao,
1112 .reg_type = ni_reg_628x,
1115 .num_p0_dio_channels = 8,
1116 .caldac = {caldac_none},
1120 .device_id = 0x70bc,
1124 .ai_fifo_depth = 2047,
1125 .gainlkup = ai_gain_628x,
1130 .reg_type = ni_reg_628x,
1132 .num_p0_dio_channels = 32,
1133 .caldac = {caldac_none},
1137 .device_id = 0x70ac,
1141 .ai_fifo_depth = 2047,
1142 .gainlkup = ai_gain_628x,
1146 .ao_fifo_depth = 8191,
1147 .ao_range_table = &range_ni_M_628x_ao,
1148 .reg_type = ni_reg_628x,
1151 .num_p0_dio_channels = 32,
1152 .caldac = {caldac_none},
1156 .device_id = 0x70C0,
1160 .ai_fifo_depth = 1024,
1162 .gainlkup = ai_gain_6143,
1166 .reg_type = ni_reg_6143,
1169 .num_p0_dio_channels = 8,
1170 .caldac = {ad8804_debug, ad8804_debug},
1173 .device_id = 0x710D,
1177 .ai_fifo_depth = 1024,
1179 .gainlkup = ai_gain_6143,
1183 .reg_type = ni_reg_6143,
1186 .num_p0_dio_channels = 8,
1187 .caldac = {ad8804_debug, ad8804_debug},
1194 /* How we access registers */
1196 #define ni_writel(a, b) (writel((a), devpriv->mite->daq_io_addr + (b)))
1197 #define ni_readl(a) (readl(devpriv->mite->daq_io_addr + (a)))
1198 #define ni_writew(a, b) (writew((a), devpriv->mite->daq_io_addr + (b)))
1199 #define ni_readw(a) (readw(devpriv->mite->daq_io_addr + (a)))
1200 #define ni_writeb(a, b) (writeb((a), devpriv->mite->daq_io_addr + (b)))
1201 #define ni_readb(a) (readb(devpriv->mite->daq_io_addr + (a)))
1203 /* How we access STC registers */
1205 /* We automatically take advantage of STC registers that can be
1206 * read/written directly in the I/O space of the board. Most
1207 * PCIMIO devices map the low 8 STC registers to iobase+addr*2.
1208 * The 611x devices map the write registers to iobase+addr*2, and
1209 * the read registers to iobase+(addr-1)*2. */
1210 /* However, the 611x boards still aren't working, so I'm disabling
1211 * non-windowed STC access temporarily */
1213 static void e_series_win_out(struct comedi_device *dev, uint16_t data, int reg)
1215 struct ni_private *devpriv = dev->private;
1216 unsigned long flags;
1218 spin_lock_irqsave(&devpriv->window_lock, flags);
1219 ni_writew(reg, Window_Address);
1220 ni_writew(data, Window_Data);
1221 spin_unlock_irqrestore(&devpriv->window_lock, flags);
1224 static uint16_t e_series_win_in(struct comedi_device *dev, int reg)
1226 struct ni_private *devpriv = dev->private;
1227 unsigned long flags;
1230 spin_lock_irqsave(&devpriv->window_lock, flags);
1231 ni_writew(reg, Window_Address);
1232 ret = ni_readw(Window_Data);
1233 spin_unlock_irqrestore(&devpriv->window_lock, flags);
1238 static void m_series_stc_writew(struct comedi_device *dev, uint16_t data,
1241 struct ni_private *devpriv = dev->private;
1245 case ADC_FIFO_Clear:
1246 offset = M_Offset_AI_FIFO_Clear;
1248 case AI_Command_1_Register:
1249 offset = M_Offset_AI_Command_1;
1251 case AI_Command_2_Register:
1252 offset = M_Offset_AI_Command_2;
1254 case AI_Mode_1_Register:
1255 offset = M_Offset_AI_Mode_1;
1257 case AI_Mode_2_Register:
1258 offset = M_Offset_AI_Mode_2;
1260 case AI_Mode_3_Register:
1261 offset = M_Offset_AI_Mode_3;
1263 case AI_Output_Control_Register:
1264 offset = M_Offset_AI_Output_Control;
1266 case AI_Personal_Register:
1267 offset = M_Offset_AI_Personal;
1269 case AI_SI2_Load_A_Register:
1270 /* this is actually a 32 bit register on m series boards */
1271 ni_writel(data, M_Offset_AI_SI2_Load_A);
1274 case AI_SI2_Load_B_Register:
1275 /* this is actually a 32 bit register on m series boards */
1276 ni_writel(data, M_Offset_AI_SI2_Load_B);
1279 case AI_START_STOP_Select_Register:
1280 offset = M_Offset_AI_START_STOP_Select;
1282 case AI_Trigger_Select_Register:
1283 offset = M_Offset_AI_Trigger_Select;
1285 case Analog_Trigger_Etc_Register:
1286 offset = M_Offset_Analog_Trigger_Etc;
1288 case AO_Command_1_Register:
1289 offset = M_Offset_AO_Command_1;
1291 case AO_Command_2_Register:
1292 offset = M_Offset_AO_Command_2;
1294 case AO_Mode_1_Register:
1295 offset = M_Offset_AO_Mode_1;
1297 case AO_Mode_2_Register:
1298 offset = M_Offset_AO_Mode_2;
1300 case AO_Mode_3_Register:
1301 offset = M_Offset_AO_Mode_3;
1303 case AO_Output_Control_Register:
1304 offset = M_Offset_AO_Output_Control;
1306 case AO_Personal_Register:
1307 offset = M_Offset_AO_Personal;
1309 case AO_Start_Select_Register:
1310 offset = M_Offset_AO_Start_Select;
1312 case AO_Trigger_Select_Register:
1313 offset = M_Offset_AO_Trigger_Select;
1315 case Clock_and_FOUT_Register:
1316 offset = M_Offset_Clock_and_FOUT;
1318 case Configuration_Memory_Clear:
1319 offset = M_Offset_Configuration_Memory_Clear;
1321 case DAC_FIFO_Clear:
1322 offset = M_Offset_AO_FIFO_Clear;
1324 case DIO_Control_Register:
1326 ("%s: FIXME: register 0x%x does not map cleanly on to m-series boards.\n",
1330 case G_Autoincrement_Register(0):
1331 offset = M_Offset_G0_Autoincrement;
1333 case G_Autoincrement_Register(1):
1334 offset = M_Offset_G1_Autoincrement;
1336 case G_Command_Register(0):
1337 offset = M_Offset_G0_Command;
1339 case G_Command_Register(1):
1340 offset = M_Offset_G1_Command;
1342 case G_Input_Select_Register(0):
1343 offset = M_Offset_G0_Input_Select;
1345 case G_Input_Select_Register(1):
1346 offset = M_Offset_G1_Input_Select;
1348 case G_Mode_Register(0):
1349 offset = M_Offset_G0_Mode;
1351 case G_Mode_Register(1):
1352 offset = M_Offset_G1_Mode;
1354 case Interrupt_A_Ack_Register:
1355 offset = M_Offset_Interrupt_A_Ack;
1357 case Interrupt_A_Enable_Register:
1358 offset = M_Offset_Interrupt_A_Enable;
1360 case Interrupt_B_Ack_Register:
1361 offset = M_Offset_Interrupt_B_Ack;
1363 case Interrupt_B_Enable_Register:
1364 offset = M_Offset_Interrupt_B_Enable;
1366 case Interrupt_Control_Register:
1367 offset = M_Offset_Interrupt_Control;
1369 case IO_Bidirection_Pin_Register:
1370 offset = M_Offset_IO_Bidirection_Pin;
1372 case Joint_Reset_Register:
1373 offset = M_Offset_Joint_Reset;
1375 case RTSI_Trig_A_Output_Register:
1376 offset = M_Offset_RTSI_Trig_A_Output;
1378 case RTSI_Trig_B_Output_Register:
1379 offset = M_Offset_RTSI_Trig_B_Output;
1381 case RTSI_Trig_Direction_Register:
1382 offset = M_Offset_RTSI_Trig_Direction;
1384 /* FIXME: DIO_Output_Register (16 bit reg) is replaced by M_Offset_Static_Digital_Output (32 bit)
1385 and M_Offset_SCXI_Serial_Data_Out (8 bit) */
1387 dev_warn(dev->class_dev,
1388 "%s: bug! unhandled register=0x%x in switch.\n",
1394 ni_writew(data, offset);
1397 static uint16_t m_series_stc_readw(struct comedi_device *dev, int reg)
1399 struct ni_private *devpriv = dev->private;
1403 case AI_Status_1_Register:
1404 offset = M_Offset_AI_Status_1;
1406 case AO_Status_1_Register:
1407 offset = M_Offset_AO_Status_1;
1409 case AO_Status_2_Register:
1410 offset = M_Offset_AO_Status_2;
1412 case DIO_Serial_Input_Register:
1413 return ni_readb(M_Offset_SCXI_Serial_Data_In);
1415 case Joint_Status_1_Register:
1416 offset = M_Offset_Joint_Status_1;
1418 case Joint_Status_2_Register:
1419 offset = M_Offset_Joint_Status_2;
1421 case G_Status_Register:
1422 offset = M_Offset_G01_Status;
1425 dev_warn(dev->class_dev,
1426 "%s: bug! unhandled register=0x%x in switch.\n",
1432 return ni_readw(offset);
1435 static void m_series_stc_writel(struct comedi_device *dev, uint32_t data,
1438 struct ni_private *devpriv = dev->private;
1442 case AI_SC_Load_A_Registers:
1443 offset = M_Offset_AI_SC_Load_A;
1445 case AI_SI_Load_A_Registers:
1446 offset = M_Offset_AI_SI_Load_A;
1448 case AO_BC_Load_A_Register:
1449 offset = M_Offset_AO_BC_Load_A;
1451 case AO_UC_Load_A_Register:
1452 offset = M_Offset_AO_UC_Load_A;
1454 case AO_UI_Load_A_Register:
1455 offset = M_Offset_AO_UI_Load_A;
1457 case G_Load_A_Register(0):
1458 offset = M_Offset_G0_Load_A;
1460 case G_Load_A_Register(1):
1461 offset = M_Offset_G1_Load_A;
1463 case G_Load_B_Register(0):
1464 offset = M_Offset_G0_Load_B;
1466 case G_Load_B_Register(1):
1467 offset = M_Offset_G1_Load_B;
1470 dev_warn(dev->class_dev,
1471 "%s: bug! unhandled register=0x%x in switch.\n",
1477 ni_writel(data, offset);
1480 static uint32_t m_series_stc_readl(struct comedi_device *dev, int reg)
1482 struct ni_private *devpriv = dev->private;
1486 case G_HW_Save_Register(0):
1487 offset = M_Offset_G0_HW_Save;
1489 case G_HW_Save_Register(1):
1490 offset = M_Offset_G1_HW_Save;
1492 case G_Save_Register(0):
1493 offset = M_Offset_G0_Save;
1495 case G_Save_Register(1):
1496 offset = M_Offset_G1_Save;
1499 dev_warn(dev->class_dev,
1500 "%s: bug! unhandled register=0x%x in switch.\n",
1506 return ni_readl(offset);
1509 #define interrupt_pin(a) 0
1510 #define IRQ_POLARITY 1
1512 #define NI_E_IRQ_FLAGS IRQF_SHARED
1514 #include "ni_mio_common.c"
1516 static int pcimio_ai_change(struct comedi_device *dev,
1517 struct comedi_subdevice *s, unsigned long new_size);
1518 static int pcimio_ao_change(struct comedi_device *dev,
1519 struct comedi_subdevice *s, unsigned long new_size);
1520 static int pcimio_gpct0_change(struct comedi_device *dev,
1521 struct comedi_subdevice *s,
1522 unsigned long new_size);
1523 static int pcimio_gpct1_change(struct comedi_device *dev,
1524 struct comedi_subdevice *s,
1525 unsigned long new_size);
1526 static int pcimio_dio_change(struct comedi_device *dev,
1527 struct comedi_subdevice *s,
1528 unsigned long new_size);
1530 static void m_series_init_eeprom_buffer(struct comedi_device *dev)
1532 struct ni_private *devpriv = dev->private;
1533 static const int Start_Cal_EEPROM = 0x400;
1534 static const unsigned window_size = 10;
1535 static const int serial_number_eeprom_offset = 0x4;
1536 static const int serial_number_eeprom_length = 0x4;
1537 unsigned old_iodwbsr_bits;
1538 unsigned old_iodwbsr1_bits;
1539 unsigned old_iodwcr1_bits;
1542 old_iodwbsr_bits = readl(devpriv->mite->mite_io_addr + MITE_IODWBSR);
1543 old_iodwbsr1_bits = readl(devpriv->mite->mite_io_addr + MITE_IODWBSR_1);
1544 old_iodwcr1_bits = readl(devpriv->mite->mite_io_addr + MITE_IODWCR_1);
1545 writel(0x0, devpriv->mite->mite_io_addr + MITE_IODWBSR);
1546 writel(((0x80 | window_size) | devpriv->mite->daq_phys_addr),
1547 devpriv->mite->mite_io_addr + MITE_IODWBSR_1);
1548 writel(0x1 | old_iodwcr1_bits,
1549 devpriv->mite->mite_io_addr + MITE_IODWCR_1);
1550 writel(0xf, devpriv->mite->mite_io_addr + 0x30);
1552 BUG_ON(serial_number_eeprom_length > sizeof(devpriv->serial_number));
1553 for (i = 0; i < serial_number_eeprom_length; ++i) {
1554 char *byte_ptr = (char *)&devpriv->serial_number + i;
1555 *byte_ptr = ni_readb(serial_number_eeprom_offset + i);
1557 devpriv->serial_number = be32_to_cpu(devpriv->serial_number);
1559 for (i = 0; i < M_SERIES_EEPROM_SIZE; ++i)
1560 devpriv->eeprom_buffer[i] = ni_readb(Start_Cal_EEPROM + i);
1562 writel(old_iodwbsr1_bits, devpriv->mite->mite_io_addr + MITE_IODWBSR_1);
1563 writel(old_iodwbsr_bits, devpriv->mite->mite_io_addr + MITE_IODWBSR);
1564 writel(old_iodwcr1_bits, devpriv->mite->mite_io_addr + MITE_IODWCR_1);
1565 writel(0x0, devpriv->mite->mite_io_addr + 0x30);
1568 static void init_6143(struct comedi_device *dev)
1570 struct ni_private *devpriv = dev->private;
1572 /* Disable interrupts */
1573 devpriv->stc_writew(dev, 0, Interrupt_Control_Register);
1575 /* Initialise 6143 AI specific bits */
1576 ni_writeb(0x00, Magic_6143); /* Set G0,G1 DMA mode to E series version */
1577 ni_writeb(0x80, PipelineDelay_6143); /* Set EOCMode, ADCMode and pipelinedelay */
1578 ni_writeb(0x00, EOC_Set_6143); /* Set EOC Delay */
1580 ni_writel(boardtype.ai_fifo_depth / 2, AIFIFO_Flag_6143); /* Set the FIFO half full level */
1582 /* Strobe Relay disable bit */
1583 devpriv->ai_calib_source_enabled = 0;
1584 ni_writew(devpriv->ai_calib_source | Calibration_Channel_6143_RelayOff,
1585 Calibration_Channel_6143);
1586 ni_writew(devpriv->ai_calib_source, Calibration_Channel_6143);
1589 static void pcimio_detach(struct comedi_device *dev)
1591 struct ni_private *devpriv = dev->private;
1593 mio_common_detach(dev);
1595 free_irq(dev->irq, dev);
1597 mite_free_ring(devpriv->ai_mite_ring);
1598 mite_free_ring(devpriv->ao_mite_ring);
1599 mite_free_ring(devpriv->cdo_mite_ring);
1600 mite_free_ring(devpriv->gpct_mite_ring[0]);
1601 mite_free_ring(devpriv->gpct_mite_ring[1]);
1602 if (devpriv->mite) {
1603 mite_unsetup(devpriv->mite);
1604 mite_free(devpriv->mite);
1609 static const struct ni_board_struct *
1610 pcimio_find_boardinfo(struct pci_dev *pcidev)
1612 unsigned int device_id = pcidev->device;
1615 for (n = 0; n < ARRAY_SIZE(ni_boards); n++) {
1616 const struct ni_board_struct *board = &ni_boards[n];
1617 if (board->device_id == device_id)
1623 static int pcimio_auto_attach(struct comedi_device *dev,
1624 unsigned long context_unused)
1626 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1627 struct ni_private *devpriv;
1630 dev_info(dev->class_dev, "ni_pcimio: attach %s\n", pci_name(pcidev));
1632 ret = ni_alloc_private(dev);
1635 devpriv = dev->private;
1637 dev->board_ptr = pcimio_find_boardinfo(pcidev);
1638 if (!dev->board_ptr)
1641 devpriv->mite = mite_alloc(pcidev);
1645 dev_dbg(dev->class_dev, "%s\n", boardtype.name);
1646 dev->board_name = boardtype.name;
1648 if (boardtype.reg_type & ni_reg_m_series_mask) {
1649 devpriv->stc_writew = &m_series_stc_writew;
1650 devpriv->stc_readw = &m_series_stc_readw;
1651 devpriv->stc_writel = &m_series_stc_writel;
1652 devpriv->stc_readl = &m_series_stc_readl;
1654 devpriv->stc_writew = &e_series_win_out;
1655 devpriv->stc_readw = &e_series_win_in;
1656 devpriv->stc_writel = &win_out2;
1657 devpriv->stc_readl = &win_in2;
1660 ret = mite_setup(devpriv->mite);
1662 pr_warn("error setting up mite\n");
1666 devpriv->ai_mite_ring = mite_alloc_ring(devpriv->mite);
1667 if (devpriv->ai_mite_ring == NULL)
1669 devpriv->ao_mite_ring = mite_alloc_ring(devpriv->mite);
1670 if (devpriv->ao_mite_ring == NULL)
1672 devpriv->cdo_mite_ring = mite_alloc_ring(devpriv->mite);
1673 if (devpriv->cdo_mite_ring == NULL)
1675 devpriv->gpct_mite_ring[0] = mite_alloc_ring(devpriv->mite);
1676 if (devpriv->gpct_mite_ring[0] == NULL)
1678 devpriv->gpct_mite_ring[1] = mite_alloc_ring(devpriv->mite);
1679 if (devpriv->gpct_mite_ring[1] == NULL)
1682 if (boardtype.reg_type & ni_reg_m_series_mask)
1683 m_series_init_eeprom_buffer(dev);
1684 if (boardtype.reg_type == ni_reg_6143)
1687 dev->irq = mite_irq(devpriv->mite);
1689 if (dev->irq == 0) {
1690 pr_warn("unknown irq (bad)\n");
1692 pr_debug("( irq = %u )\n", dev->irq);
1693 ret = request_irq(dev->irq, ni_E_interrupt, NI_E_IRQ_FLAGS,
1696 pr_warn("irq not available\n");
1701 ret = ni_E_init(dev);
1705 dev->subdevices[NI_AI_SUBDEV].buf_change = &pcimio_ai_change;
1706 dev->subdevices[NI_AO_SUBDEV].buf_change = &pcimio_ao_change;
1707 dev->subdevices[NI_GPCT_SUBDEV(0)].buf_change = &pcimio_gpct0_change;
1708 dev->subdevices[NI_GPCT_SUBDEV(1)].buf_change = &pcimio_gpct1_change;
1709 dev->subdevices[NI_DIO_SUBDEV].buf_change = &pcimio_dio_change;
1714 static int pcimio_ai_change(struct comedi_device *dev,
1715 struct comedi_subdevice *s, unsigned long new_size)
1717 struct ni_private *devpriv = dev->private;
1720 ret = mite_buf_change(devpriv->ai_mite_ring, s->async);
1727 static int pcimio_ao_change(struct comedi_device *dev,
1728 struct comedi_subdevice *s, unsigned long new_size)
1730 struct ni_private *devpriv = dev->private;
1733 ret = mite_buf_change(devpriv->ao_mite_ring, s->async);
1740 static int pcimio_gpct0_change(struct comedi_device *dev,
1741 struct comedi_subdevice *s,
1742 unsigned long new_size)
1744 struct ni_private *devpriv = dev->private;
1747 ret = mite_buf_change(devpriv->gpct_mite_ring[0], s->async);
1754 static int pcimio_gpct1_change(struct comedi_device *dev,
1755 struct comedi_subdevice *s,
1756 unsigned long new_size)
1758 struct ni_private *devpriv = dev->private;
1761 ret = mite_buf_change(devpriv->gpct_mite_ring[1], s->async);
1768 static int pcimio_dio_change(struct comedi_device *dev,
1769 struct comedi_subdevice *s, unsigned long new_size)
1771 struct ni_private *devpriv = dev->private;
1774 ret = mite_buf_change(devpriv->cdo_mite_ring, s->async);
1781 static struct comedi_driver ni_pcimio_driver = {
1782 .driver_name = "ni_pcimio",
1783 .module = THIS_MODULE,
1784 .auto_attach = pcimio_auto_attach,
1785 .detach = pcimio_detach,
1788 static int ni_pcimio_pci_probe(struct pci_dev *dev,
1789 const struct pci_device_id *ent)
1791 return comedi_pci_auto_config(dev, &ni_pcimio_driver);
1794 static void ni_pcimio_pci_remove(struct pci_dev *dev)
1796 comedi_pci_auto_unconfig(dev);
1799 static DEFINE_PCI_DEVICE_TABLE(ni_pcimio_pci_table) = {
1800 { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x0162) },
1801 { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1170) },
1802 { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1180) },
1803 { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1190) },
1804 { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x11b0) },
1805 { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x11c0) },
1806 { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x11d0) },
1807 { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1270) },
1808 { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1330) },
1809 { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1340) },
1810 { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1350) },
1811 { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x14e0) },
1812 { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x14f0) },
1813 { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1580) },
1814 { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x15b0) },
1815 { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1880) },
1816 { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1870) },
1817 { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x18b0) },
1818 { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x18c0) },
1819 { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2410) },
1820 { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2420) },
1821 { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2430) },
1822 { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2890) },
1823 { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x28c0) },
1824 { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2a60) },
1825 { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2a70) },
1826 { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2a80) },
1827 { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2ab0) },
1828 { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2b80) },
1829 { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2b90) },
1830 { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2c80) },
1831 { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2ca0) },
1832 { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70aa) },
1833 { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70ab) },
1834 { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70ac) },
1835 { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70af) },
1836 { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70b0) },
1837 { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70b4) },
1838 { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70b6) },
1839 { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70b7) },
1840 { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70b8) },
1841 { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70bc) },
1842 { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70bd) },
1843 { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70bf) },
1844 { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70c0) },
1845 { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70f2) },
1846 { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x710d) },
1847 { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x716c) },
1848 { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x716d) },
1849 { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x717f) },
1850 { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x71bc) },
1851 { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x717d) },
1852 { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x72e8) },
1855 MODULE_DEVICE_TABLE(pci, ni_pcimio_pci_table);
1857 static struct pci_driver ni_pcimio_pci_driver = {
1858 .name = "ni_pcimio",
1859 .id_table = ni_pcimio_pci_table,
1860 .probe = ni_pcimio_pci_probe,
1861 .remove = ni_pcimio_pci_remove
1863 module_comedi_pci_driver(ni_pcimio_driver, ni_pcimio_pci_driver);
1865 MODULE_AUTHOR("Comedi http://www.comedi.org");
1866 MODULE_DESCRIPTION("Comedi low-level driver");
1867 MODULE_LICENSE("GPL");