3 * Comedi driver for Winsystems PC-104 based 48/96-channel DIO boards.
5 * COMEDI - Linux Control and Measurement Device Interface
6 * Copyright (C) 2006 Calin A. Culianu <calin@ajvar.org>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
21 * Description: Winsystems PC-104 based 48/96-channel DIO boards.
22 * Devices: (Winsystems) PCM-UIO48A [pcmuio48]
23 * (Winsystems) PCM-UIO96A [pcmuio96]
24 * Author: Calin Culianu <calin@ajvar.org>
25 * Updated: Fri, 13 Jan 2006 12:01:01 -0500
28 * A driver for the relatively straightforward-to-program PCM-UIO48A and
29 * PCM-UIO96A boards from Winsystems. These boards use either one or two
30 * (in the 96-DIO version) WS16C48 ASIC HighDensity I/O Chips (HDIO). This
31 * chip is interesting in that each I/O line is individually programmable
32 * for INPUT or OUTPUT (thus comedi_dio_config can be done on a per-channel
33 * basis). Also, each chip supports edge-triggered interrupts for the first
34 * 24 I/O lines. Of course, since the 96-channel version of the board has
35 * two ASICs, it can detect polarity changes on up to 48 I/O lines. Since
36 * this is essentially an (non-PnP) ISA board, I/O Address and IRQ selection
37 * are done through jumpers on the board. You need to pass that information
38 * to this driver as the first and second comedi_config option, respectively.
39 * Note that the 48-channel version uses 16 bytes of IO memory and the 96-
40 * channel version uses 32-bytes (in case you are worried about conflicts).
41 * The 48-channel board is split into two 24-channel comedi subdevices. The
42 * 96-channel board is split into 4 24-channel DIO subdevices.
44 * Note that IRQ support has been added, but it is untested.
46 * To use edge-detection IRQ support, pass the IRQs of both ASICS (for the
47 * 96 channel version) or just 1 ASIC (for 48-channel version). Then, use
48 * comedi_commands with TRIG_NOW. Your callback will be called each time an
49 * edge is triggered, and the data values will be two sample_t's, which
50 * should be concatenated to form one 32-bit unsigned int. This value is
51 * the mask of channels that had edges detected from your channel list. Note
52 * that the bits positions in the mask correspond to positions in your
53 * chanlist when you specified the command and *not* channel id's!
55 * To set the polarity of the edge-detection interrupts pass a nonzero value
56 * for either CR_RANGE or CR_AREF for edge-up polarity, or a zero value for
57 * both CR_RANGE and CR_AREF if you want edge-down polarity.
59 * In the 48-channel version:
61 * On subdev 0, the first 24 channels channels are edge-detect channels.
63 * In the 96-channel board you have the following channels that can do edge
66 * subdev 0, channels 0-24 (first 24 channels of 1st ASIC)
67 * subdev 2, channels 0-24 (first 24 channels of 2nd ASIC)
69 * Configuration Options:
70 * [0] - I/O port base address
71 * [1] - IRQ (for first ASIC, or first 24 channels)
72 * [2] - IRQ (for second ASIC, pcmuio96 only - IRQ for chans 48-72
73 * can be the same as first irq!)
76 #include <linux/interrupt.h>
77 #include <linux/slab.h>
79 #include "../comedidev.h"
81 #include "comedi_fc.h"
83 #define CHANS_PER_PORT 8
84 #define PORTS_PER_ASIC 6
85 #define INTR_PORTS_PER_ASIC 3
86 #define MAX_CHANS_PER_SUBDEV 24 /* number of channels per comedi subdevice */
87 #define PORTS_PER_SUBDEV (MAX_CHANS_PER_SUBDEV/CHANS_PER_PORT)
88 #define CHANS_PER_ASIC (CHANS_PER_PORT*PORTS_PER_ASIC)
89 #define INTR_CHANS_PER_ASIC 24
90 #define INTR_PORTS_PER_SUBDEV (INTR_CHANS_PER_ASIC/CHANS_PER_PORT)
91 #define MAX_DIO_CHANS (PORTS_PER_ASIC*2*CHANS_PER_PORT)
92 #define MAX_ASICS (MAX_DIO_CHANS/CHANS_PER_ASIC)
94 #define ASIC_IOSIZE (0x10)
95 #define PCMUIO48_IOSIZE ASIC_IOSIZE
96 #define PCMUIO96_IOSIZE (ASIC_IOSIZE*2)
98 /* Some offsets - these are all in the 16byte IO memory offset from
99 the base address. Note that there is a paging scheme to swap out
100 offsets 0x8-0xA using the PAGELOCK register. See the table below.
102 Register(s) Pages R/W? Description
103 --------------------------------------------------------------
104 REG_PORTx All R/W Read/Write/Configure IO
105 REG_INT_PENDING All ReadOnly Quickly see which INT_IDx has int.
106 REG_PAGELOCK All WriteOnly Select a page
107 REG_POLx Pg. 1 only WriteOnly Select edge-detection polarity
108 REG_ENABx Pg. 2 only WriteOnly Enable/Disable edge-detect. int.
109 REG_INT_IDx Pg. 3 only R/W See which ports/bits have ints.
111 #define REG_PORT0 0x0
112 #define REG_PORT1 0x1
113 #define REG_PORT2 0x2
114 #define REG_PORT3 0x3
115 #define REG_PORT4 0x4
116 #define REG_PORT5 0x5
117 #define REG_INT_PENDING 0x6
118 #define REG_PAGELOCK 0x7 /* page selector register, upper 2 bits select a page
119 and bits 0-5 are used to 'lock down' a particular
120 port above to make it readonly. */
124 #define REG_ENAB0 0x8
125 #define REG_ENAB1 0x9
126 #define REG_ENAB2 0xA
127 #define REG_INT_ID0 0x8
128 #define REG_INT_ID1 0x9
129 #define REG_INT_ID2 0xA
131 #define NUM_PAGED_REGS 3
133 #define FIRST_PAGED_REG 0x8
134 #define REG_PAGE_BITOFFSET 6
135 #define REG_LOCK_BITOFFSET 0
136 #define REG_PAGE_MASK (~((0x1<<REG_PAGE_BITOFFSET)-1))
137 #define REG_LOCK_MASK ~(REG_PAGE_MASK)
140 #define PAGE_INT_ID 3
143 * Board descriptions for two imaginary boards. Describing the
144 * boards in this way is optional, and completely driver-dependent.
145 * Some drivers use arrays such as this, other do not.
147 struct pcmuio_board {
150 const int num_channels_per_port;
154 /* this structure is for data unique to this subdevice. */
155 struct pcmuio_subdev_private {
156 /* mapping of halfwords (bytes) in port/chanarray to iobase */
157 unsigned long iobases[PORTS_PER_SUBDEV];
159 /* The below is only used for intr subdevices */
161 int asic; /* if non-negative, this subdev has an interrupt asic */
162 int first_chan; /* if nonnegative, the first channel id for
164 int num_asic_chans; /* the number of asic channels in this subdev
165 that have interrutps */
166 int asic_chan; /* if nonnegative, the first channel id with
167 respect to the asic that has interrupts */
168 int enabled_mask; /* subdev-relative channel mask for channels
169 we are interested in */
177 /* this structure is for data unique to this hardware driver. If
178 several hardware drivers keep similar information in this structure,
179 feel free to suggest moving the variable to the struct comedi_device struct. */
180 struct pcmuio_private {
182 unsigned char pagelock; /* current page and lock */
183 unsigned char pol[NUM_PAGED_REGS]; /* shadow of POLx registers */
184 unsigned char enab[NUM_PAGED_REGS]; /* shadow of ENABx registers */
186 unsigned long iobase;
190 struct pcmuio_subdev_private *sprivs;
193 /* DIO devices are slightly special. Although it is possible to
194 * implement the insn_read/insn_write interface, it is much more
195 * useful to applications if you implement the insn_bits interface.
196 * This allows packed reading/writing of the DIO channels. The
197 * comedi core can convert between insn_bits and insn_read/write */
198 static int pcmuio_dio_insn_bits(struct comedi_device *dev,
199 struct comedi_subdevice *s,
200 struct comedi_insn *insn, unsigned int *data)
202 struct pcmuio_subdev_private *subpriv = s->private;
206 reading a 0 means this channel was high
207 writine a 0 sets the channel high
208 reading a 1 means this channel was low
209 writing a 1 means set this channel low
211 Therefore everything is always inverted. */
213 /* The insn data is a mask in data[0] and the new data
214 * in data[1], each channel cooresponding to a bit. */
216 #ifdef DAMMIT_ITS_BROKEN
218 dev_dbg(dev->class_dev, "write mask: %08x data: %08x\n", data[0],
224 for (byte_no = 0; byte_no < s->n_chan / CHANS_PER_PORT; ++byte_no) {
225 /* address of 8-bit port */
226 unsigned long ioaddr = subpriv->iobases[byte_no],
227 /* bit offset of port in 32-bit doubleword */
228 offset = byte_no * 8;
229 /* this 8-bit port's data */
230 unsigned char byte = 0,
231 /* The write mask for this port (if any) */
232 write_mask_byte = (data[0] >> offset) & 0xff,
233 /* The data byte for this port */
234 data_byte = (data[1] >> offset) & 0xff;
236 byte = inb(ioaddr); /* read all 8-bits for this port */
238 #ifdef DAMMIT_ITS_BROKEN
241 ("byte %d wmb %02x db %02x offset %02d io %04x, data_in %02x ",
242 byte_no, (unsigned)write_mask_byte, (unsigned)data_byte,
243 offset, ioaddr, (unsigned)byte);
246 if (write_mask_byte) {
247 /* this byte has some write_bits -- so set the output lines */
248 byte &= ~write_mask_byte; /* clear bits for write mask */
249 byte |= ~data_byte & write_mask_byte; /* set to inverted data_byte */
250 /* Write out the new digital output state */
253 #ifdef DAMMIT_ITS_BROKEN
255 dev_dbg(dev->class_dev, "data_out_byte %02x\n", (unsigned)byte);
257 /* save the digital input lines for this byte.. */
258 s->state |= ((unsigned int)byte) << offset;
261 /* now return the DIO lines to data[1] - note they came inverted! */
264 #ifdef DAMMIT_ITS_BROKEN
266 dev_dbg(dev->class_dev, "s->state %08x data_out %08x\n", s->state,
273 /* The input or output configuration of each digital line is
274 * configured by a special insn_config instruction. chanspec
275 * contains the channel to be changed, and data[0] contains the
276 * value COMEDI_INPUT or COMEDI_OUTPUT. */
277 static int pcmuio_dio_insn_config(struct comedi_device *dev,
278 struct comedi_subdevice *s,
279 struct comedi_insn *insn, unsigned int *data)
281 struct pcmuio_subdev_private *subpriv = s->private;
282 int chan = CR_CHAN(insn->chanspec), byte_no = chan / 8, bit_no =
284 unsigned long ioaddr;
287 /* Compute ioaddr for this channel */
288 ioaddr = subpriv->iobases[byte_no];
291 writing a 0 an IO channel's bit sets the channel to INPUT
292 and pulls the line high as well
294 writing a 1 to an IO channel's bit pulls the line low
296 All channels are implicitly always in OUTPUT mode -- but when
297 they are high they can be considered to be in INPUT mode..
299 Thus, we only force channels low if the config request was INPUT,
300 otherwise we do nothing to the hardware. */
303 case INSN_CONFIG_DIO_OUTPUT:
304 /* save to io_bits -- don't actually do anything since
305 all input channels are also output channels... */
306 s->io_bits |= 1 << chan;
308 case INSN_CONFIG_DIO_INPUT:
309 /* write a 0 to the actual register representing the channel
310 to set it to 'input'. 0 means "float high". */
312 byte &= ~(1 << bit_no);
313 /**< set input channel to '0' */
315 /* write out byte -- this is the only time we actually affect the
316 hardware as all channels are implicitly output -- but input
317 channels are set to float-high */
320 /* save to io_bits */
321 s->io_bits &= ~(1 << chan);
324 case INSN_CONFIG_DIO_QUERY:
325 /* retrieve from shadow register */
327 (s->io_bits & (1 << chan)) ? COMEDI_OUTPUT : COMEDI_INPUT;
339 static void switch_page(struct comedi_device *dev, int asic, int page)
341 const struct pcmuio_board *board = comedi_board(dev);
342 struct pcmuio_private *devpriv = dev->private;
344 if (asic < 0 || asic >= board->num_asics)
345 return; /* paranoia */
346 if (page < 0 || page >= NUM_PAGES)
347 return; /* more paranoia */
349 devpriv->asics[asic].pagelock &= ~REG_PAGE_MASK;
350 devpriv->asics[asic].pagelock |= page << REG_PAGE_BITOFFSET;
352 /* now write out the shadow register */
353 outb(devpriv->asics[asic].pagelock,
354 dev->iobase + ASIC_IOSIZE * asic + REG_PAGELOCK);
357 static void init_asics(struct comedi_device *dev)
359 ASIC chip to defaults */
360 const struct pcmuio_board *board = comedi_board(dev);
363 for (asic = 0; asic < board->num_asics; ++asic) {
365 unsigned long baseaddr = dev->iobase + asic * ASIC_IOSIZE;
367 switch_page(dev, asic, 0); /* switch back to page 0 */
369 /* first, clear all the DIO port bits */
370 for (port = 0; port < PORTS_PER_ASIC; ++port)
371 outb(0, baseaddr + REG_PORT0 + port);
373 /* Next, clear all the paged registers for each page */
374 for (page = 1; page < NUM_PAGES; ++page) {
376 /* now clear all the paged registers */
377 switch_page(dev, asic, page);
378 for (reg = FIRST_PAGED_REG;
379 reg < FIRST_PAGED_REG + NUM_PAGED_REGS; ++reg)
380 outb(0, baseaddr + reg);
383 /* DEBUG set rising edge interrupts on port0 of both asics */
384 /*switch_page(dev, asic, PAGE_POL);
385 outb(0xff, baseaddr + REG_POL0);
386 switch_page(dev, asic, PAGE_ENAB);
387 outb(0xff, baseaddr + REG_ENAB0); */
390 switch_page(dev, asic, 0); /* switch back to default page 0 */
396 static void lock_port(struct comedi_device *dev, int asic, int port)
398 const struct pcmuio_board *board = comedi_board(dev);
399 struct pcmuio_private *devpriv = dev->private;
401 if (asic < 0 || asic >= board->num_asics)
402 return; /* paranoia */
403 if (port < 0 || port >= PORTS_PER_ASIC)
404 return; /* more paranoia */
406 devpriv->asics[asic].pagelock |= 0x1 << port;
407 /* now write out the shadow register */
408 outb(devpriv->asics[asic].pagelock,
409 dev->iobase + ASIC_IOSIZE * asic + REG_PAGELOCK);
412 static void unlock_port(struct comedi_device *dev, int asic, int port)
414 const struct pcmuio_board *board = comedi_board(dev);
415 struct pcmuio_private *devpriv = dev->private;
417 if (asic < 0 || asic >= board->num_asics)
418 return; /* paranoia */
419 if (port < 0 || port >= PORTS_PER_ASIC)
420 return; /* more paranoia */
421 devpriv->asics[asic].pagelock &= ~(0x1 << port) | REG_LOCK_MASK;
422 /* now write out the shadow register */
423 outb(devpriv->asics[asic].pagelock,
424 dev->iobase + ASIC_IOSIZE * asic + REG_PAGELOCK);
428 static void pcmuio_stop_intr(struct comedi_device *dev,
429 struct comedi_subdevice *s)
431 struct pcmuio_private *devpriv = dev->private;
432 struct pcmuio_subdev_private *subpriv = s->private;
433 int nports, firstport, asic, port;
435 asic = subpriv->intr.asic;
437 return; /* not an interrupt subdev */
439 subpriv->intr.enabled_mask = 0;
440 subpriv->intr.active = 0;
441 s->async->inttrig = NULL;
442 nports = subpriv->intr.num_asic_chans / CHANS_PER_PORT;
443 firstport = subpriv->intr.asic_chan / CHANS_PER_PORT;
444 switch_page(dev, asic, PAGE_ENAB);
445 for (port = firstport; port < firstport + nports; ++port) {
446 /* disable all intrs for this subdev.. */
447 outb(0, devpriv->asics[asic].iobase + REG_ENAB0 + port);
451 static void pcmuio_handle_intr_subdev(struct comedi_device *dev,
452 struct comedi_subdevice *s,
455 struct pcmuio_subdev_private *subpriv = s->private;
456 unsigned int len = s->async->cmd.chanlist_len;
457 unsigned oldevents = s->async->events;
458 unsigned int val = 0;
463 spin_lock_irqsave(&subpriv->intr.spinlock, flags);
465 if (!subpriv->intr.active)
468 mytrig = triggered >> subpriv->intr.asic_chan;
469 mytrig &= ((0x1 << subpriv->intr.num_asic_chans) - 1);
470 mytrig <<= subpriv->intr.first_chan;
472 if (!(mytrig & subpriv->intr.enabled_mask))
475 for (i = 0; i < len; i++) {
476 unsigned int chan = CR_CHAN(s->async->cmd.chanlist[i]);
477 if (mytrig & (1U << chan))
481 /* Write the scan to the buffer. */
482 if (comedi_buf_put(s->async, ((short *)&val)[0]) &&
483 comedi_buf_put(s->async, ((short *)&val)[1])) {
484 s->async->events |= (COMEDI_CB_BLOCK | COMEDI_CB_EOS);
486 /* Overflow! Stop acquisition!! */
487 /* TODO: STOP_ACQUISITION_CALL_HERE!! */
488 pcmuio_stop_intr(dev, s);
491 /* Check for end of acquisition. */
492 if (!subpriv->intr.continuous) {
493 /* stop_src == TRIG_COUNT */
494 if (subpriv->intr.stop_count > 0) {
495 subpriv->intr.stop_count--;
496 if (subpriv->intr.stop_count == 0) {
497 s->async->events |= COMEDI_CB_EOA;
498 /* TODO: STOP_ACQUISITION_CALL_HERE!! */
499 pcmuio_stop_intr(dev, s);
505 spin_unlock_irqrestore(&subpriv->intr.spinlock, flags);
507 if (oldevents != s->async->events)
508 comedi_event(dev, s);
511 static int pcmuio_handle_asic_interrupt(struct comedi_device *dev, int asic)
513 struct pcmuio_private *devpriv = dev->private;
514 struct pcmuio_subdev_private *subpriv;
515 unsigned long iobase = devpriv->asics[asic].iobase;
516 unsigned triggered = 0;
519 unsigned char int_pend;
522 spin_lock_irqsave(&devpriv->asics[asic].spinlock, flags);
524 int_pend = inb(iobase + REG_INT_PENDING) & 0x07;
526 for (i = 0; i < INTR_PORTS_PER_ASIC; ++i) {
527 if (int_pend & (0x1 << i)) {
530 switch_page(dev, asic, PAGE_INT_ID);
531 val = inb(iobase + REG_INT_ID0 + i);
533 /* clear pending interrupt */
534 outb(0, iobase + REG_INT_ID0 + i);
536 triggered |= (val << (i * 8));
543 spin_unlock_irqrestore(&devpriv->asics[asic].spinlock, flags);
546 struct comedi_subdevice *s;
547 /* TODO here: dispatch io lines to subdevs with commands.. */
548 for (i = 0; i < dev->n_subdevices; i++) {
549 s = &dev->subdevices[i];
550 subpriv = s->private;
551 if (subpriv->intr.asic == asic) {
553 * This is an interrupt subdev, and it
556 pcmuio_handle_intr_subdev(dev, s,
564 static irqreturn_t interrupt_pcmuio(int irq, void *d)
566 struct comedi_device *dev = d;
567 struct pcmuio_private *devpriv = dev->private;
571 for (asic = 0; asic < MAX_ASICS; ++asic) {
572 if (irq == devpriv->asics[asic].irq) {
573 /* it is an interrupt for ASIC #asic */
574 if (pcmuio_handle_asic_interrupt(dev, asic))
579 return IRQ_NONE; /* interrupt from other source */
583 static int pcmuio_start_intr(struct comedi_device *dev,
584 struct comedi_subdevice *s)
586 struct pcmuio_private *devpriv = dev->private;
587 struct pcmuio_subdev_private *subpriv = s->private;
589 if (!subpriv->intr.continuous && subpriv->intr.stop_count == 0) {
590 /* An empty acquisition! */
591 s->async->events |= COMEDI_CB_EOA;
592 subpriv->intr.active = 0;
595 unsigned bits = 0, pol_bits = 0, n;
596 int nports, firstport, asic, port;
597 struct comedi_cmd *cmd = &s->async->cmd;
599 asic = subpriv->intr.asic;
601 return 1; /* not an interrupt
603 subpriv->intr.enabled_mask = 0;
604 subpriv->intr.active = 1;
605 nports = subpriv->intr.num_asic_chans / CHANS_PER_PORT;
606 firstport = subpriv->intr.asic_chan / CHANS_PER_PORT;
608 for (n = 0; n < cmd->chanlist_len; n++) {
609 bits |= (1U << CR_CHAN(cmd->chanlist[n]));
610 pol_bits |= (CR_AREF(cmd->chanlist[n])
612 chanlist[n]) ? 1U : 0U)
613 << CR_CHAN(cmd->chanlist[n]);
616 bits &= ((0x1 << subpriv->intr.num_asic_chans) -
617 1) << subpriv->intr.first_chan;
618 subpriv->intr.enabled_mask = bits;
620 switch_page(dev, asic, PAGE_ENAB);
621 for (port = firstport; port < firstport + nports; ++port) {
623 bits >> (subpriv->intr.first_chan + (port -
626 pol_bits >> (subpriv->intr.first_chan +
627 (port - firstport) * 8) & 0xff;
628 /* set enab intrs for this subdev.. */
630 devpriv->asics[asic].iobase + REG_ENAB0 + port);
631 switch_page(dev, asic, PAGE_POL);
633 devpriv->asics[asic].iobase + REG_ENAB0 + port);
639 static int pcmuio_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
641 struct pcmuio_subdev_private *subpriv = s->private;
644 spin_lock_irqsave(&subpriv->intr.spinlock, flags);
645 if (subpriv->intr.active)
646 pcmuio_stop_intr(dev, s);
647 spin_unlock_irqrestore(&subpriv->intr.spinlock, flags);
653 * Internal trigger function to start acquisition for an 'INTERRUPT' subdevice.
656 pcmuio_inttrig_start_intr(struct comedi_device *dev, struct comedi_subdevice *s,
657 unsigned int trignum)
659 struct pcmuio_subdev_private *subpriv = s->private;
666 spin_lock_irqsave(&subpriv->intr.spinlock, flags);
667 s->async->inttrig = NULL;
668 if (subpriv->intr.active)
669 event = pcmuio_start_intr(dev, s);
671 spin_unlock_irqrestore(&subpriv->intr.spinlock, flags);
674 comedi_event(dev, s);
680 * 'do_cmd' function for an 'INTERRUPT' subdevice.
682 static int pcmuio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
684 struct pcmuio_subdev_private *subpriv = s->private;
685 struct comedi_cmd *cmd = &s->async->cmd;
689 spin_lock_irqsave(&subpriv->intr.spinlock, flags);
690 subpriv->intr.active = 1;
692 /* Set up end of acquisition. */
693 switch (cmd->stop_src) {
695 subpriv->intr.continuous = 0;
696 subpriv->intr.stop_count = cmd->stop_arg;
700 subpriv->intr.continuous = 1;
701 subpriv->intr.stop_count = 0;
705 /* Set up start of acquisition. */
706 switch (cmd->start_src) {
708 s->async->inttrig = pcmuio_inttrig_start_intr;
712 event = pcmuio_start_intr(dev, s);
715 spin_unlock_irqrestore(&subpriv->intr.spinlock, flags);
718 comedi_event(dev, s);
723 static int pcmuio_cmdtest(struct comedi_device *dev,
724 struct comedi_subdevice *s,
725 struct comedi_cmd *cmd)
729 /* Step 1 : check if triggers are trivially valid */
731 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_INT);
732 err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
733 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
734 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
735 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
740 /* Step 2a : make sure trigger sources are unique */
742 err |= cfc_check_trigger_is_unique(cmd->start_src);
743 err |= cfc_check_trigger_is_unique(cmd->stop_src);
745 /* Step 2b : and mutually compatible */
750 /* Step 3: check if arguments are trivially valid */
752 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
753 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
754 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
755 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
757 switch (cmd->stop_src) {
759 /* any count allowed */
762 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
771 /* step 4: fix up any arguments */
773 /* if (err) return 4; */
778 static int pcmuio_attach(struct comedi_device *dev, struct comedi_devconfig *it)
780 const struct pcmuio_board *board = comedi_board(dev);
781 struct comedi_subdevice *s;
782 struct pcmuio_private *devpriv;
783 struct pcmuio_subdev_private *subpriv;
784 int sdev_no, chans_left, n_subdevs, port, asic, thisasic_chanct = 0;
785 unsigned int irq[MAX_ASICS];
788 irq[0] = it->options[1];
789 irq[1] = it->options[2];
791 ret = comedi_request_region(dev, it->options[0],
792 board->num_asics * ASIC_IOSIZE);
796 devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
799 dev->private = devpriv;
801 for (asic = 0; asic < MAX_ASICS; ++asic) {
802 devpriv->asics[asic].num = asic;
803 devpriv->asics[asic].iobase = dev->iobase + asic * ASIC_IOSIZE;
804 devpriv->asics[asic].irq = 0; /* this gets actually set at the end of
805 this function when we
807 spin_lock_init(&devpriv->asics[asic].spinlock);
810 chans_left = CHANS_PER_ASIC * board->num_asics;
811 n_subdevs = (chans_left / MAX_CHANS_PER_SUBDEV) +
812 (!!(chans_left % MAX_CHANS_PER_SUBDEV));
813 devpriv->sprivs = kcalloc(n_subdevs,
814 sizeof(struct pcmuio_subdev_private),
816 if (!devpriv->sprivs)
819 ret = comedi_alloc_subdevices(dev, n_subdevs);
825 for (sdev_no = 0; sdev_no < (int)dev->n_subdevices; ++sdev_no) {
828 s = &dev->subdevices[sdev_no];
829 subpriv = &devpriv->sprivs[sdev_no];
830 s->private = subpriv;
832 s->range_table = &range_digital;
833 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
834 s->type = COMEDI_SUBD_DIO;
835 s->insn_bits = pcmuio_dio_insn_bits;
836 s->insn_config = pcmuio_dio_insn_config;
837 s->n_chan = min(chans_left, MAX_CHANS_PER_SUBDEV);
838 subpriv->intr.asic = -1;
839 subpriv->intr.first_chan = -1;
840 subpriv->intr.asic_chan = -1;
841 subpriv->intr.num_asic_chans = -1;
842 subpriv->intr.active = 0;
845 /* save the ioport address for each 'port' of 8 channels in the
847 for (byte_no = 0; byte_no < PORTS_PER_SUBDEV; ++byte_no, ++port) {
848 if (port >= PORTS_PER_ASIC) {
853 subpriv->iobases[byte_no] =
854 devpriv->asics[asic].iobase + port;
856 if (thisasic_chanct <
857 CHANS_PER_PORT * INTR_PORTS_PER_ASIC
858 && subpriv->intr.asic < 0) {
859 /* this is an interrupt subdevice, so setup the struct */
860 subpriv->intr.asic = asic;
861 subpriv->intr.active = 0;
862 subpriv->intr.stop_count = 0;
863 subpriv->intr.first_chan = byte_no * 8;
864 subpriv->intr.asic_chan = thisasic_chanct;
865 subpriv->intr.num_asic_chans =
866 s->n_chan - subpriv->intr.first_chan;
867 dev->read_subdev = s;
868 s->subdev_flags |= SDF_CMD_READ;
869 s->cancel = pcmuio_cancel;
870 s->do_cmd = pcmuio_cmd;
871 s->do_cmdtest = pcmuio_cmdtest;
872 s->len_chanlist = subpriv->intr.num_asic_chans;
874 thisasic_chanct += CHANS_PER_PORT;
876 spin_lock_init(&subpriv->intr.spinlock);
878 chans_left -= s->n_chan;
881 asic = 0; /* reset the asic to our first asic, to do intr subdevs */
887 init_asics(dev); /* clear out all the registers, basically */
889 for (asic = 0; irq[0] && asic < MAX_ASICS; ++asic) {
891 && request_irq(irq[asic], interrupt_pcmuio,
892 IRQF_SHARED, board->name, dev)) {
894 /* unroll the allocated irqs.. */
895 for (i = asic - 1; i >= 0; --i) {
896 free_irq(irq[i], dev);
897 devpriv->asics[i].irq = irq[i] = 0;
901 devpriv->asics[asic].irq = irq[asic];
905 dev_dbg(dev->class_dev, "irq: %u\n", irq[0]);
906 if (irq[1] && board->num_asics == 2)
907 dev_dbg(dev->class_dev, "second ASIC irq: %u\n",
910 dev_dbg(dev->class_dev, "(IRQ mode disabled)\n");
917 static void pcmuio_detach(struct comedi_device *dev)
919 struct pcmuio_private *devpriv = dev->private;
922 for (i = 0; i < MAX_ASICS; ++i) {
923 if (devpriv->asics[i].irq)
924 free_irq(devpriv->asics[i].irq, dev);
926 if (devpriv && devpriv->sprivs)
927 kfree(devpriv->sprivs);
928 comedi_legacy_detach(dev);
931 static const struct pcmuio_board pcmuio_boards[] = {
943 static struct comedi_driver pcmuio_driver = {
944 .driver_name = "pcmuio",
945 .module = THIS_MODULE,
946 .attach = pcmuio_attach,
947 .detach = pcmuio_detach,
948 .board_name = &pcmuio_boards[0].name,
949 .offset = sizeof(struct pcmuio_board),
950 .num_names = ARRAY_SIZE(pcmuio_boards),
952 module_comedi_driver(pcmuio_driver);
954 MODULE_AUTHOR("Comedi http://www.comedi.org");
955 MODULE_DESCRIPTION("Comedi low-level driver");
956 MODULE_LICENSE("GPL");