1 unsigned int max_intcnt = 0;
2 unsigned int max_bh = 0;
4 /*-----------------------------------------------------------------------------
7 * Copyright (C) 2007 One Stop Systems, Inc.
8 * Copyright (C) 2003-2006 SBE, Inc.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * For further information, contact via email: support@onestopsystems.com
21 * One Stop Systems, Inc. Escondido, California U.S.A.
22 *-----------------------------------------------------------------------------
25 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
27 #include <linux/types.h>
28 #include "pmcc4_sysdep.h"
29 #include <linux/kernel.h>
30 #include <linux/errno.h>
31 #include <linux/init.h>
32 #include "sbecom_inline_linux.h"
34 #include "pmcc4_private.h"
38 #ifdef SBE_INCLUDE_SYMBOLS
44 #define sd_find_chan(ci,ch) c4_find_chan(ch)
47 /*******************************************************************/
48 /* global driver variables */
50 extern int drvr_state;
51 extern int cxt1e1_log_level;
53 extern int cxt1e1_max_mru;
54 extern int cxt1e1_max_mtu;
55 extern int max_rxdesc_used;
56 extern int max_txdesc_used;
57 extern ci_t *CI; /* dummy pointr to board ZEROE's data - DEBUG
61 /*******************************************************************/
62 /* forward references */
63 void c4_fifo_free (mpi_t *, int);
64 void c4_wk_chan_restart (mch_t *);
65 void musycc_bh_tx_eom (mpi_t *, int);
66 int musycc_chan_up (ci_t *, int);
67 status_t __init musycc_init (ci_t *);
68 STATIC void __init musycc_init_port (mpi_t *);
69 void musycc_intr_bh_tasklet (ci_t *);
70 void musycc_serv_req (mpi_t *, u_int32_t);
71 void musycc_update_timeslots (mpi_t *);
73 /*******************************************************************/
77 musycc_dump_rxbuffer_ring (mch_t * ch, int lockit)
80 unsigned long flags = 0;
87 spin_lock_irqsave (&ch->ch_rxlock, flags);
91 pr_info(" ZERO receive buffers allocated for this channel.");
95 m = &ch->mdr[ch->rxix_irq_srv];
96 for (n = ch->rxd_num; n; n--)
98 status = le32_to_cpu (m->status);
100 pr_info("%c %08lx[%2d]: sts %08x (%c%c%c%c:%d.) Data [%08x] Next [%08x]\n",
101 (m == &ch->mdr[ch->rxix_irq_srv]) ? 'F' : ' ',
102 (unsigned long) m, n,
104 m->data ? (status & HOST_RX_OWNED ? 'H' : 'M') : '-',
105 status & POLL_DISABLED ? 'P' : '-',
106 status & EOBIRQ_ENABLE ? 'b' : '-',
107 status & EOMIRQ_ENABLE ? 'm' : '-',
108 status & LENGTH_MASK,
109 le32_to_cpu (m->data), le32_to_cpu (m->next));
110 #ifdef RLD_DUMP_BUFDATA
113 int len = status & LENGTH_MASK;
116 if (m->data && (status & HOST_RX_OWNED))
118 if (m->data) /* always dump regardless of valid RX
122 dp = (u_int32_t *) OS_phystov ((void *) (le32_to_cpu (m->data)));
124 pr_info(" %x[%x]: %08X %08X %08X %08x\n", (u_int32_t) dp, len,
125 *dp, *(dp + 1), *(dp + 2), *(dp + 3));
126 else if (len >= 0x08)
127 pr_info(" %x[%x]: %08X %08X\n", (u_int32_t) dp, len,
130 pr_info(" %x[%x]: %08X\n", (u_int32_t) dp, len, *dp);
142 spin_unlock_irqrestore (&ch->ch_rxlock, flags);
150 musycc_dump_txbuffer_ring (mch_t * ch, int lockit)
153 unsigned long flags = 0;
159 spin_lock_irqsave (&ch->ch_txlock, flags);
161 if (ch->txd_num == 0)
163 pr_info(" ZERO transmit buffers allocated for this channel.");
168 for (n = ch->txd_num; n; n--)
170 status = le32_to_cpu (m->status);
172 pr_info("%c%c %08lx[%2d]: sts %08x (%c%c%c%c:%d.) Data [%08x] Next [%08x]\n",
173 (m == ch->txd_usr_add) ? 'F' : ' ',
174 (m == ch->txd_irq_srv) ? 'L' : ' ',
175 (unsigned long) m, n,
177 m->data ? (status & MUSYCC_TX_OWNED ? 'M' : 'H') : '-',
178 status & POLL_DISABLED ? 'P' : '-',
179 status & EOBIRQ_ENABLE ? 'b' : '-',
180 status & EOMIRQ_ENABLE ? 'm' : '-',
181 status & LENGTH_MASK,
182 le32_to_cpu (m->data), le32_to_cpu (m->next));
183 #ifdef RLD_DUMP_BUFDATA
186 int len = status & LENGTH_MASK;
190 dp = (u_int32_t *) OS_phystov ((void *) (le32_to_cpu (m->data)));
192 pr_info(" %x[%x]: %08X %08X %08X %08x\n", (u_int32_t) dp, len,
193 *dp, *(dp + 1), *(dp + 2), *(dp + 3));
194 else if (len >= 0x08)
195 pr_info(" %x[%x]: %08X %08X\n", (u_int32_t) dp, len,
198 pr_info(" %x[%x]: %08X\n", (u_int32_t) dp, len, *dp);
210 spin_unlock_irqrestore (&ch->ch_txlock, flags);
218 * The following supports a backdoor debug facility which can be used to
219 * display the state of a board's channel.
223 musycc_dump_ring (ci_t * ci, unsigned int chan)
227 if (chan >= MAX_CHANS_USED)
229 return SBE_DRVR_FAIL; /* E2BIG */
234 bh = atomic_read (&ci->bh_pending);
235 pr_info(">> bh_pend %d [%d] ihead %d itail %d [%d] th_cnt %d bh_cnt %d wdcnt %d note %d\n",
236 bh, max_bh, ci->iqp_headx, ci->iqp_tailx, max_intcnt,
237 ci->intlog.drvr_intr_thcount,
238 ci->intlog.drvr_intr_bhcount,
239 ci->wdcount, ci->wd_notify);
240 max_bh = 0; /* reset counter */
241 max_intcnt = 0; /* reset counter */
244 if (!(ch = sd_find_chan (dummy, chan)))
246 pr_info(">> musycc_dump_ring: channel %d not up.\n", chan);
249 pr_info(">> CI %p CHANNEL %3d @ %p: state %x status/p %x/%x\n", ci, chan, ch, ch->state,
250 ch->status, ch->p.status);
251 pr_info("--------------------------------\nTX Buffer Ring - Channel %d, txd_num %d. (bd/ch pend %d %d), TXD required %d, txpkt %lu\n",
253 (u_int32_t) atomic_read (&ci->tx_pending), (u_int32_t) atomic_read (&ch->tx_pending), ch->txd_required, ch->s.tx_packets);
254 pr_info("++ User 0x%p IRQ_SRV 0x%p USR_ADD 0x%p QStopped %x, start_tx %x tx_full %d txd_free %d mode %x\n",
255 ch->user, ch->txd_irq_srv, ch->txd_usr_add,
256 sd_queue_stopped (ch->user),
257 ch->ch_start_tx, ch->tx_full, ch->txd_free, ch->p.chan_mode);
258 musycc_dump_txbuffer_ring (ch, 1);
259 pr_info("RX Buffer Ring - Channel %d, rxd_num %d. IRQ_SRV[%d] 0x%p, start_rx %x rxpkt %lu\n",
260 chan, ch->rxd_num, ch->rxix_irq_srv,
261 &ch->mdr[ch->rxix_irq_srv], ch->ch_start_rx, ch->s.rx_packets);
262 musycc_dump_rxbuffer_ring (ch, 1);
264 return SBE_DRVR_SUCCESS;
269 musycc_dump_rings (ci_t * ci, unsigned int start_chan)
273 for (chan = start_chan; chan < (start_chan + 5); chan++)
274 musycc_dump_ring (ci, chan);
275 return SBE_DRVR_SUCCESS;
280 * NOTE on musycc_init_mdt(): These MUSYCC writes are only operational after
281 * a MUSYCC GROUP_INIT command has been issued.
285 musycc_init_mdt (mpi_t * pi)
287 u_int32_t *addr, cfg;
291 * This Idle Code insertion takes effect prior to channel's first
292 * transmitted message. After that, each message contains its own Idle
293 * Code information which is to be issued after the message is
294 * transmitted (Ref.MUSYCC 5.2.2.3: MCENBL bit in Group Configuration
298 addr = (u_int32_t *) ((u_long) pi->reg + MUSYCC_MDT_BASE03_ADDR);
299 cfg = CFG_CH_FLAG_7E << IDLE_CODE;
301 for (i = 0; i < 32; addr++, i++)
303 pci_write_32 (addr, cfg);
308 /* Set TX thp to the next unprocessed md */
311 musycc_update_tx_thp (mch_t * ch)
316 spin_lock_irqsave (&ch->ch_txlock, flags);
319 md = ch->txd_irq_srv;
323 /* No MDs with buffers to process */
324 spin_unlock_irqrestore (&ch->ch_txlock, flags);
327 if ((le32_to_cpu (md->status)) & MUSYCC_TX_OWNED)
329 /* this is the MD to restart TX with */
333 * Otherwise, we have a valid, host-owned message descriptor which
334 * has been successfully transmitted and whose buffer can be freed,
335 * so... process this MD, it's owned by the host. (This might give
336 * as a new, updated txd_irq_srv.)
338 musycc_bh_tx_eom (ch->up, ch->gchan);
340 md = ch->txd_irq_srv;
341 ch->up->regram->thp[ch->gchan] = cpu_to_le32 (OS_vtophys (md));
347 ch->txd_required = 0;
348 sd_enable_xmit (ch->user); /* re-enable to catch flow controlled
351 spin_unlock_irqrestore (&ch->ch_txlock, flags);
353 #ifdef RLD_TRANS_DEBUG
354 pr_info("++ musycc_update_tx_thp[%d]: setting thp = %p, sts %x\n", ch->channum, md, md->status);
360 * This is the workq task executed by the OS when our queue_work() is
361 * scheduled and run. It can fire off either RX or TX ACTIVATION depending
362 * upon the channel's ch_start_tx and ch_start_rx variables. This routine
363 * is implemented as a work queue so that the call to the service request is
364 * able to sleep, awaiting an interrupt acknowledgment response (SACK) from
369 musycc_wq_chan_restart (void *arg) /* channel private structure */
378 ch = container_of(arg, struct c4_chan_info, ch_work);
381 #ifdef RLD_TRANS_DEBUG
382 pr_info("wq_chan_restart[%d]: start_RT[%d/%d] status %x\n",
383 ch->channum, ch->ch_start_rx, ch->ch_start_tx, ch->status);
387 /**********************************/
388 /** check for RX restart request **/
389 /**********************************/
391 if ((ch->ch_start_rx) && (ch->status & RX_ENABLED))
395 #if defined(RLD_TRANS_DEBUG) || defined(RLD_RXACT_DEBUG)
397 static int hereb4 = 7;
399 if (hereb4) /* RLD DEBUG */
402 #ifdef RLD_TRANS_DEBUG
403 md = &ch->mdr[ch->rxix_irq_srv];
404 pr_info("++ musycc_wq_chan_restart[%d] CHAN RX ACTIVATE: rxix_irq_srv %d, md %p sts %x, rxpkt %lu\n",
405 ch->channum, ch->rxix_irq_srv, md, le32_to_cpu (md->status),
407 #elif defined(RLD_RXACT_DEBUG)
408 md = &ch->mdr[ch->rxix_irq_srv];
409 pr_info("++ musycc_wq_chan_restart[%d] CHAN RX ACTIVATE: rxix_irq_srv %d, md %p sts %x, rxpkt %lu\n",
410 ch->channum, ch->rxix_irq_srv, md, le32_to_cpu (md->status),
412 musycc_dump_rxbuffer_ring (ch, 1); /* RLD DEBUG */
417 musycc_serv_req (pi, SR_CHANNEL_ACTIVATE | SR_RX_DIRECTION | ch->gchan);
419 /**********************************/
420 /** check for TX restart request **/
421 /**********************************/
423 if ((ch->ch_start_tx) && (ch->status & TX_ENABLED))
425 /* find next unprocessed message, then set TX thp to it */
426 musycc_update_tx_thp (ch);
429 spin_lock_irqsave (&ch->ch_txlock, flags);
431 md = ch->txd_irq_srv;
434 #ifdef RLD_TRANS_DEBUG
435 pr_info("-- musycc_wq_chan_restart[%d]: WARNING, starting NULL md\n", ch->channum);
438 spin_unlock_irqrestore (&ch->ch_txlock, flags);
440 } else if (md->data && ((le32_to_cpu (md->status)) & MUSYCC_TX_OWNED))
444 spin_unlock_irqrestore (&ch->ch_txlock, flags); /* allow interrupts for service request */
446 #ifdef RLD_TRANS_DEBUG
447 pr_info("++ musycc_wq_chan_restart() CHAN TX ACTIVATE: chan %d txd_irq_srv %p = sts %x, txpkt %lu\n",
448 ch->channum, ch->txd_irq_srv, ch->txd_irq_srv->status, ch->s.tx_packets);
450 musycc_serv_req (pi, SR_CHANNEL_ACTIVATE | SR_TX_DIRECTION | ch->gchan);
452 #ifdef RLD_RESTART_DEBUG
455 /* retain request to start until retried and we have data to xmit */
456 pr_info("-- musycc_wq_chan_restart[%d]: DELAYED due to md %p sts %x data %x, start_tx %x\n",
458 le32_to_cpu (md->status),
459 le32_to_cpu (md->data), ch->ch_start_tx);
460 musycc_dump_txbuffer_ring (ch, 0);
462 spin_unlock_irqrestore (&ch->ch_txlock, flags); /* allow interrupts for service request */
471 * Channel restart either fires of a workqueue request (2.6) or lodges a
472 * watchdog activation sequence (2.4).
476 musycc_chan_restart (mch_t * ch)
478 #ifdef RLD_RESTART_DEBUG
479 pr_info("++ musycc_chan_restart[%d]: txd_irq_srv @ %p = sts %x\n",
480 ch->channum, ch->txd_irq_srv, ch->txd_irq_srv->status);
483 /* 2.6 - find next unprocessed message, then set TX thp to it */
484 #ifdef RLD_RESTART_DEBUG
485 pr_info(">> musycc_chan_restart: scheduling Chan %x workQ @ %p\n", ch->channum, &ch->ch_work);
487 c4_wk_chan_restart (ch); /* work queue mechanism fires off: Ref:
488 * musycc_wq_chan_restart () */
494 rld_put_led (mpi_t * pi, u_int32_t ledval)
496 static u_int32_t led = 0;
503 pci_write_32 ((u_int32_t *) &pi->up->cpldbase->leds, led); /* RLD DEBUG TRANHANG */
507 #define MUSYCC_SR_RETRY_CNT 9
510 musycc_serv_req (mpi_t * pi, u_int32_t req)
512 volatile u_int32_t r;
516 * PORT NOTE: Semaphore protect service loop guarantees only a single
517 * operation at a time. Per MUSYCC Manual - "Issuing service requests to
518 * the same channel group without first receiving ACK from each request
519 * may cause the host to lose track of which service request has been
523 SD_SEM_TAKE (&pi->sr_sem_busy, "serv"); /* only 1 thru here, per
526 if (pi->sr_last == req)
528 #ifdef RLD_TRANS_DEBUG
529 pr_info(">> same SR, Port %d Req %x\n", pi->portnum, req);
533 * The most likely repeated request is the channel activation command
534 * which follows the occurrence of a Transparent mode TX ONR or a
535 * BUFF error. If the previous command was a CHANNEL ACTIVATE,
536 * precede it with a NOOP command in order maintain coherent control
537 * of this current (re)ACTIVATE.
540 r = (pi->sr_last & ~SR_GCHANNEL_MASK);
541 if ((r == (SR_CHANNEL_ACTIVATE | SR_TX_DIRECTION)) ||
542 (r == (SR_CHANNEL_ACTIVATE | SR_RX_DIRECTION)))
544 #ifdef RLD_TRANS_DEBUG
545 pr_info(">> same CHAN ACT SR, Port %d Req %x => issue SR_NOOP CMD\n", pi->portnum, req);
547 SD_SEM_GIVE (&pi->sr_sem_busy); /* allow this next request */
548 musycc_serv_req (pi, SR_NOOP);
549 SD_SEM_TAKE (&pi->sr_sem_busy, "serv"); /* relock & continue w/
551 } else if (req == SR_NOOP)
553 /* no need to issue back-to-back SR_NOOP commands at this time */
554 #ifdef RLD_TRANS_DEBUG
555 pr_info(">> same Port SR_NOOP skipped, Port %d\n", pi->portnum);
557 SD_SEM_GIVE (&pi->sr_sem_busy); /* allow this next request */
564 pci_write_32 ((u_int32_t *) &pi->reg->srd, req);
568 * Per MUSYCC Manual, Section 6.1,2 - "When writing an SCR service
569 * request, the host must ensure at least one PCI bus clock cycle has
570 * elapsed before writing another service request. To meet this minimum
571 * elapsed service request write timing interval, it is recommended that
572 * the host follow any SCR write with another operation which reads from
575 r = pci_read_32 ((u_int32_t *) &pi->reg->srd); /* adhere to write
576 * timing imposition */
579 if ((r != req) && (req != SR_CHIP_RESET) && (++rcnt <= MUSYCC_SR_RETRY_CNT))
581 if (cxt1e1_log_level >= LOG_MONITOR)
582 pr_info("%s: %d - reissue srv req/last %x/%x (hdw reads %x), Chan %d.\n",
583 pi->up->devname, rcnt, req, pi->sr_last, r,
584 (pi->portnum * MUSYCC_NCHANS) + (req & 0x1f));
585 OS_uwait_dummy (); /* this delay helps reduce reissue counts
586 * (reason not yet researched) */
589 if (rcnt > MUSYCC_SR_RETRY_CNT)
591 pr_warning("%s: failed service request (#%d)= %x, group %d.\n",
592 pi->up->devname, MUSYCC_SR_RETRY_CNT, req, pi->portnum);
593 SD_SEM_GIVE (&pi->sr_sem_busy); /* allow any next request */
596 if (req == SR_CHIP_RESET)
599 * PORT NOTE: the CHIP_RESET command is NOT ack'd by the MUSYCC, thus
600 * the upcoming delay is used. Though the MUSYCC documentation
601 * suggests a read-after-write would supply the required delay, it's
602 * unclear what CPU/BUS clock speeds might have been assumed when
603 * suggesting this 'lack of ACK' workaround. Thus the use of uwait.
605 OS_uwait (100000, "icard"); /* 100ms */
609 SD_SEM_TAKE (&pi->sr_sem_wait, "sakack"); /* sleep until SACK
610 * interrupt occurs */
612 SD_SEM_GIVE (&pi->sr_sem_busy); /* allow any next request */
616 #ifdef SBE_PMCC4_ENABLE
618 musycc_update_timeslots (mpi_t * pi)
621 char e1mode = IS_FRAME_ANY_E1 (pi->p.port_mode);
623 for (i = 0; i < 32; i++)
625 int usedby = 0, last = 0, ts, j, bits[8];
627 u_int8_t lastval = 0;
629 if (((i == 0) && e1mode) || /* disable if E1 mode */
630 ((i == 16) && ((pi->p.port_mode == CFG_FRAME_E1CRC_CAS) || (pi->p.port_mode == CFG_FRAME_E1CRC_CAS_AMI)))
631 || ((i > 23) && (!e1mode))) /* disable if T1 mode */
633 pi->tsm[i] = 0xff; /* make tslot unavailable for this mode */
636 pi->tsm[i] = 0x00; /* make tslot available for assignment */
638 for (j = 0; j < 8; j++)
640 for (ch = 0; ch < MUSYCC_NCHANS; ch++)
642 if ((pi->chan[ch]->state == UP) && (pi->chan[ch]->p.bitmask[i]))
646 lastval = pi->chan[ch]->p.bitmask[i];
647 for (j = 0; j < 8; j++)
648 if (lastval & (1 << j))
650 pi->tsm[i] |= lastval;
655 else if ((usedby == 1) && (lastval == 0xff))
656 ts = (4 << 5) | last;
657 else if ((usedby == 1) && (lastval == 0x7f))
658 ts = (5 << 5) | last;
664 ts = (6 << 5) | (idx = last);
666 ts = (7 << 5) | (idx = bits[0]);
667 for (j = 1; j < 8; j++)
669 pi->regram->rscm[idx * 8 + j] = (bits[j] < 0) ? 0 : (0x80 | bits[j]);
670 pi->regram->tscm[idx * 8 + j] = (bits[j] < 0) ? 0 : (0x80 | bits[j]);
673 pi->regram->rtsm[i] = ts;
674 pi->regram->ttsm[i] = ts;
678 musycc_serv_req (pi, SR_TIMESLOT_MAP | SR_RX_DIRECTION);
679 musycc_serv_req (pi, SR_TIMESLOT_MAP | SR_TX_DIRECTION);
680 musycc_serv_req (pi, SR_SUBCHANNEL_MAP | SR_RX_DIRECTION);
681 musycc_serv_req (pi, SR_SUBCHANNEL_MAP | SR_TX_DIRECTION);
686 #ifdef SBE_WAN256T3_ENABLE
688 musycc_update_timeslots (mpi_t * pi)
692 u_int8_t ts, hmask, tsen;
696 #ifdef SBE_PMCC4_ENABLE
697 hmask = (0x1f << pi->up->p.hypersize) & 0x1f;
699 #ifdef SBE_WAN256T3_ENABLE
700 hmask = (0x1f << hyperdummy) & 0x1f;
702 for (i = 0; i < 128; i++)
704 gchan = ((pi->portnum * MUSYCC_NCHANS) + (i & hmask)) % MUSYCC_NCHANS;
705 ch = pi->chan[gchan];
709 tsen = MODE_64KBPS; /* also the default */
710 ts = ((pi->portnum % 4) == (i / 32)) ? (tsen << 5) | (i & hmask) : 0;
711 pi->regram->rtsm[i] = ts;
712 pi->regram->ttsm[i] = ts;
715 musycc_serv_req (pi, SR_TIMESLOT_MAP | SR_RX_DIRECTION);
716 musycc_serv_req (pi, SR_TIMESLOT_MAP | SR_TX_DIRECTION);
722 * This routine converts a generic library channel configuration parameter
723 * into a hardware specific register value (IE. MUSYCC CCD Register).
726 musycc_chan_proto (int proto)
732 case CFG_CH_PROTO_TRANS: /* 0 */
733 reg = MUSYCC_CCD_TRANS;
735 case CFG_CH_PROTO_SS7: /* 1 */
736 reg = MUSYCC_CCD_SS7;
739 case CFG_CH_PROTO_ISLP_MODE: /* 4 */
740 case CFG_CH_PROTO_HDLC_FCS16: /* 2 */
741 reg = MUSYCC_CCD_HDLC_FCS16;
743 case CFG_CH_PROTO_HDLC_FCS32: /* 3 */
744 reg = MUSYCC_CCD_HDLC_FCS32;
751 #ifdef SBE_WAN256T3_ENABLE
753 musycc_init_port (mpi_t * pi)
755 pci_write_32 ((u_int32_t *) &pi->reg->gbp, OS_vtophys (pi->regram));
758 __constant_cpu_to_le32 (MUSYCC_GRCD_RX_ENABLE |
759 MUSYCC_GRCD_TX_ENABLE |
760 MUSYCC_GRCD_SF_ALIGN |
761 MUSYCC_GRCD_SUBCHAN_DISABLE |
762 MUSYCC_GRCD_OOFMP_DISABLE |
763 MUSYCC_GRCD_COFAIRQ_DISABLE |
764 MUSYCC_GRCD_MC_ENABLE |
765 (MUSYCC_GRCD_POLLTH_32 << MUSYCC_GRCD_POLLTH_SHIFT));
768 __constant_cpu_to_le32 (MUSYCC_PCD_E1X4_MODE |
769 MUSYCC_PCD_TXDATA_RISING |
770 MUSYCC_PCD_TX_DRIVEN);
772 /* Message length descriptor */
773 pi->regram->mld = __constant_cpu_to_le32 (cxt1e1_max_mru | (cxt1e1_max_mru << 16));
776 musycc_serv_req (pi, SR_GROUP_INIT | SR_RX_DIRECTION);
777 musycc_serv_req (pi, SR_GROUP_INIT | SR_TX_DIRECTION);
779 musycc_init_mdt (pi);
781 musycc_update_timeslots (pi);
787 musycc_init (ci_t * ci)
789 char *regaddr; /* temp for address boundary calculations */
792 OS_sem_init (&ci->sem_wdbusy, SEM_AVAILABLE); /* watchdog exclusion */
795 * Per MUSYCC manual, Section 6.3.4 - "The host must allocate a dword
796 * aligned memory segment for interrupt queue pointers."
799 #define INT_QUEUE_BOUNDARY 4
801 regaddr = OS_kmalloc ((INT_QUEUE_SIZE + 1) * sizeof (u_int32_t));
804 ci->iqd_p_saved = regaddr; /* save orig value for free's usage */
805 ci->iqd_p = (u_int32_t *) ((unsigned long) (regaddr + INT_QUEUE_BOUNDARY - 1) &
806 (~(INT_QUEUE_BOUNDARY - 1))); /* this calculates
807 * closest boundary */
809 for (i = 0; i < INT_QUEUE_SIZE; i++)
811 ci->iqd_p[i] = __constant_cpu_to_le32 (INT_EMPTY_ENTRY);
814 for (i = 0; i < ci->max_port; i++)
816 mpi_t *pi = &ci->port[i];
819 * Per MUSYCC manual, Section 6.3.2 - "The host must allocate a 2KB
820 * bound memory segment for Channel Group 0."
823 #define GROUP_BOUNDARY 0x800
825 regaddr = OS_kmalloc (sizeof (struct musycc_groupr) + GROUP_BOUNDARY);
828 for (gchan = 0; gchan < i; gchan++)
830 pi = &ci->port[gchan];
836 pi->regram_saved = regaddr; /* save orig value for free's usage */
837 pi->regram = (struct musycc_groupr *) ((unsigned long) (regaddr + GROUP_BOUNDARY - 1) &
838 (~(GROUP_BOUNDARY - 1))); /* this calculates
839 * closest boundary */
842 /* any board centric MUSYCC commands will use group ZERO as its "home" */
843 ci->regram = ci->port[0].regram;
844 musycc_serv_req (&ci->port[0], SR_CHIP_RESET);
846 pci_write_32 ((u_int32_t *) &ci->reg->gbp, OS_vtophys (ci->regram));
847 pci_flush_write (ci);
848 #ifdef CONFIG_SBE_PMCC4_NCOMM
849 ci->regram->__glcd = __constant_cpu_to_le32 (GCD_MAGIC);
851 /* standard driver POLLS for INTB via CPLD register */
852 ci->regram->__glcd = __constant_cpu_to_le32 (GCD_MAGIC | MUSYCC_GCD_INTB_DISABLE);
855 ci->regram->__iqp = cpu_to_le32 (OS_vtophys (&ci->iqd_p[0]));
856 ci->regram->__iql = __constant_cpu_to_le32 (INT_QUEUE_SIZE - 1);
857 pci_write_32 ((u_int32_t *) &ci->reg->dacbp, 0);
860 ci->state = C_RUNNING; /* mark as full interrupt processing
863 musycc_serv_req (&ci->port[0], SR_GLOBAL_INIT); /* FIRST INTERRUPT ! */
865 /* sanity check settable parameters */
867 if (cxt1e1_max_mru > 0xffe)
869 pr_warning("Maximum allowed MRU exceeded, resetting %d to %d.\n",
870 cxt1e1_max_mru, 0xffe);
871 cxt1e1_max_mru = 0xffe;
873 if (cxt1e1_max_mtu > 0xffe)
875 pr_warning("Maximum allowed MTU exceeded, resetting %d to %d.\n",
876 cxt1e1_max_mtu, 0xffe);
877 cxt1e1_max_mtu = 0xffe;
879 #ifdef SBE_WAN256T3_ENABLE
880 for (i = 0; i < MUSYCC_NPORTS; i++)
881 musycc_init_port (&ci->port[i]);
884 return SBE_DRVR_SUCCESS; /* no error */
889 musycc_bh_tx_eom (mpi_t * pi, int gchan)
895 #ifndef SBE_ISR_INLINE
900 volatile u_int32_t status;
902 ch = pi->chan[gchan];
903 if (ch == 0 || ch->state != UP)
905 if (cxt1e1_log_level >= LOG_ERROR)
906 pr_info("%s: intr: xmit EOM on uninitialized channel %d\n",
907 pi->up->devname, gchan);
909 if (ch == 0 || ch->mdt == 0)
910 return; /* note: mdt==0 implies a malloc()
911 * failure w/in chan_up() routine */
914 #ifdef SBE_ISR_INLINE
915 spin_lock_irq (&ch->ch_txlock);
917 spin_lock_irqsave (&ch->ch_txlock, flags);
923 md = ch->txd_irq_srv;
924 status = le32_to_cpu (md->status);
927 * Note: Per MUSYCC Ref 6.4.9, the host does not poll a host-owned
928 * Transmit Buffer Descriptor during Transparent Mode.
930 if (status & MUSYCC_TX_OWNED)
932 int readCount, loopCount;
934 /***********************************************************/
937 /* Under certain PCI Bus loading conditions, the data */
938 /* associated with an update of Shared Memory is delayed */
939 /* relative to its PCI Interrupt. This is caught when */
940 /* the host determines it does not yet OWN the descriptor. */
941 /***********************************************************/
944 while (status & MUSYCC_TX_OWNED)
946 for (loopCount = 0; loopCount < 0x30; loopCount++)
947 OS_uwait_dummy (); /* use call to avoid optimization
948 * removal of dummy delay */
950 status = le32_to_cpu (md->status);
951 if (readCount++ > 40)
952 break; /* don't wait any longer */
954 if (status & MUSYCC_TX_OWNED)
956 if (cxt1e1_log_level >= LOG_MONITOR)
958 pr_info("%s: Port %d Chan %2d - unexpected TX msg ownership intr (md %p sts %x)\n",
959 pi->up->devname, pi->portnum, ch->channum,
961 pr_info("++ User 0x%p IRQ_SRV 0x%p USR_ADD 0x%p QStopped %x, start_tx %x tx_full %d txd_free %d mode %x\n",
962 ch->user, ch->txd_irq_srv, ch->txd_usr_add,
963 sd_queue_stopped (ch->user),
964 ch->ch_start_tx, ch->tx_full, ch->txd_free, ch->p.chan_mode);
965 musycc_dump_txbuffer_ring (ch, 0);
967 break; /* Not our mdesc, done */
970 if (cxt1e1_log_level >= LOG_MONITOR)
971 pr_info("%s: Port %d Chan %2d - recovered TX msg ownership [%d] (md %p sts %x)\n",
972 pi->up->devname, pi->portnum, ch->channum, readCount, md, status);
975 ch->txd_irq_srv = md->snext;
978 if (md->mem_token != 0)
980 /* upcount channel */
981 atomic_sub (OS_mem_token_tlen (md->mem_token), &ch->tx_pending);
983 atomic_sub (OS_mem_token_tlen (md->mem_token), &pi->up->tx_pending);
984 #ifdef SBE_WAN256T3_ENABLE
985 if (!atomic_read (&pi->up->tx_pending))
986 wan256t3_led (pi->up, LED_TX, 0);
989 #ifdef CONFIG_SBE_WAN256T3_NCOMM
990 /* callback that our packet was sent */
992 int hdlcnum = (pi->portnum * 32 + gchan);
996 if (nciProcess_TX_complete)
997 (*nciProcess_TX_complete) (hdlcnum,
998 getuserbychan (gchan));
1001 #endif /*** CONFIG_SBE_WAN256T3_NCOMM ***/
1003 OS_mem_token_free_irq (md->mem_token);
1007 #ifdef RLD_TXFULL_DEBUG
1008 if (cxt1e1_log_level >= LOG_MONITOR2)
1009 pr_info("~~ tx_eom: tx_full %x txd_free %d -> %d\n",
1010 ch->tx_full, ch->txd_free, ch->txd_free + 1);
1015 if ((ch->p.chan_mode != CFG_CH_PROTO_TRANS) && (status & EOBIRQ_ENABLE))
1017 if (cxt1e1_log_level >= LOG_MONITOR)
1018 pr_info("%s: Mode (%x) incorrect EOB status (%x)\n",
1019 pi->up->devname, ch->p.chan_mode, status);
1020 if ((status & EOMIRQ_ENABLE) == 0)
1024 while ((ch->p.chan_mode != CFG_CH_PROTO_TRANS) && ((status & EOMIRQ_ENABLE) == 0));
1026 * NOTE: (The above 'while' is coupled w/ previous 'do', way above.) Each
1027 * Transparent data buffer has the EOB bit, and NOT the EOM bit, set and
1028 * will furthermore have a separate IQD associated with each messages
1034 * Smooth flow control hysterisis by maintaining task stoppage until half
1035 * the available write buffers are available.
1037 if (ch->tx_full && (ch->txd_free >= (ch->txd_num / 2)))
1040 * Then, only releave task stoppage if we actually have enough
1041 * buffers to service the last requested packet. It may require MORE
1042 * than half the available!
1044 if (ch->txd_free >= ch->txd_required)
1047 #ifdef RLD_TXFULL_DEBUG
1048 if (cxt1e1_log_level >= LOG_MONITOR2)
1049 pr_info("tx_eom[%d]: enable xmit tx_full no more, txd_free %d txd_num/2 %d\n",
1051 ch->txd_free, ch->txd_num / 2);
1054 ch->txd_required = 0;
1055 sd_enable_xmit (ch->user); /* re-enable to catch flow controlled
1059 #ifdef RLD_TXFULL_DEBUG
1060 else if (ch->tx_full)
1062 if (cxt1e1_log_level >= LOG_MONITOR2)
1063 pr_info("tx_eom[%d]: bypass TX enable though room available? (txd_free %d txd_num/2 %d)\n",
1065 ch->txd_free, ch->txd_num / 2);
1071 #ifdef SBE_ISR_INLINE
1072 spin_unlock_irq (&ch->ch_txlock);
1074 spin_unlock_irqrestore (&ch->ch_txlock, flags);
1081 musycc_bh_rx_eom (mpi_t * pi, int gchan)
1086 volatile u_int32_t status;
1089 ch = pi->chan[gchan];
1090 if (ch == 0 || ch->state != UP)
1092 if (cxt1e1_log_level > LOG_ERROR)
1093 pr_info("%s: intr: receive EOM on uninitialized channel %d\n",
1094 pi->up->devname, gchan);
1098 return; /* can this happen ? */
1103 md = &ch->mdr[ch->rxix_irq_srv];
1104 status = le32_to_cpu (md->status);
1105 if (!(status & HOST_RX_OWNED))
1106 break; /* Not our mdesc, done */
1108 error = (status >> 16) & 0xf;
1111 #ifdef CONFIG_SBE_WAN256T3_NCOMM
1112 int hdlcnum = (pi->portnum * 32 + gchan);
1115 * if the packet number belongs to NCOMM, then send it to the TMS
1120 if (nciProcess_RX_packet)
1121 (*nciProcess_RX_packet) (hdlcnum, status & 0x3fff, m, ch->user);
1123 #endif /*** CONFIG_SBE_WAN256T3_NCOMM ***/
1126 if ((m2 = OS_mem_token_alloc (cxt1e1_max_mru)))
1128 /* substitute the mbuf+cluster */
1130 md->data = cpu_to_le32 (OS_vtophys (OS_mem_token_data (m2)));
1132 /* pass the received mbuf upward */
1133 sd_recv_consume (m, status & LENGTH_MASK, ch->user);
1135 ch->s.rx_bytes += status & LENGTH_MASK;
1141 } else if (error == ERR_FCS)
1143 ch->s.rx_crc_errors++;
1144 } else if (error == ERR_ALIGN)
1146 ch->s.rx_missed_errors++;
1147 } else if (error == ERR_ABT)
1149 ch->s.rx_missed_errors++;
1150 } else if (error == ERR_LNG)
1152 ch->s.rx_length_errors++;
1153 } else if (error == ERR_SHT)
1155 ch->s.rx_length_errors++;
1158 status = cxt1e1_max_mru;
1159 if (ch->p.chan_mode == CFG_CH_PROTO_TRANS)
1160 status |= EOBIRQ_ENABLE;
1161 md->status = cpu_to_le32 (status);
1163 /* Check next mdesc in the ring */
1164 if (++ch->rxix_irq_srv >= ch->rxd_num)
1165 ch->rxix_irq_srv = 0;
1172 musycc_intr_th_handler (void *devp)
1174 ci_t *ci = (ci_t *) devp;
1175 volatile u_int32_t status, currInt = 0;
1176 u_int32_t nextInt, intCnt;
1179 * Hardware not available, potential interrupt hang. But since interrupt
1180 * might be shared, just return.
1182 if (ci->state == C_INIT)
1187 * Marked as hardware available. Don't service interrupts, just clear the
1191 if (ci->state == C_IDLE)
1193 status = pci_read_32 ((u_int32_t *) &ci->reg->isd);
1195 /* clear the interrupt but process nothing else */
1196 pci_write_32 ((u_int32_t *) &ci->reg->isd, status);
1202 status = pci_read_32 ((u_int32_t *) &ci->reg->isd);
1203 nextInt = INTRPTS_NEXTINT (status);
1204 intCnt = INTRPTS_INTCNT (status);
1205 ci->intlog.drvr_intr_thcount++;
1207 /*********************************************************/
1210 /* Under certain PCI Bus loading conditions, the */
1211 /* MUSYCC looses the data associated with an update */
1212 /* of its ISD and erroneously returns the immediately */
1213 /* preceding 'nextInt' value. However, the 'intCnt' */
1214 /* value appears to be correct. By not starting service */
1215 /* where the 'missing' 'nextInt' SHOULD point causes */
1216 /* the IQD not to be serviced - the 'not serviced' */
1217 /* entries then remain and continue to increase as more */
1218 /* incorrect ISD's are encountered. */
1219 /*********************************************************/
1221 if (nextInt != INTRPTS_NEXTINT (ci->intlog.this_status_new))
1223 if (cxt1e1_log_level >= LOG_MONITOR)
1225 pr_info("%s: note - updated ISD from %08x to %08x\n",
1226 ci->devname, status,
1227 (status & (~INTRPTS_NEXTINT_M)) | ci->intlog.this_status_new);
1230 * Replace bogus status with software corrected value.
1232 * It's not known whether, during this problem occurrence, if the
1233 * INTFULL bit is correctly reported or not.
1235 status = (status & (~INTRPTS_NEXTINT_M)) | (ci->intlog.this_status_new);
1236 nextInt = INTRPTS_NEXTINT (status);
1238 /**********************************************/
1239 /* Cn847x Bug Fix */
1240 /* -------------- */
1241 /* Fix for inability to write back same index */
1242 /* as read for a full interrupt queue. */
1243 /**********************************************/
1245 if (intCnt == INT_QUEUE_SIZE)
1247 currInt = ((intCnt - 1) + nextInt) & (INT_QUEUE_SIZE - 1);
1249 /************************************************/
1250 /* Interrupt Write Location Issues */
1251 /* ------------------------------- */
1252 /* When the interrupt status descriptor is */
1253 /* written, the interrupt line is de-asserted */
1254 /* by the Cn847x. In the case of MIPS */
1255 /* microprocessors, this must occur at the */
1256 /* beginning of the interrupt handler so that */
1257 /* the interrupt handle is not re-entered due */
1258 /* to interrupt dis-assertion latency. */
1259 /* In the case of all other processors, this */
1260 /* action should occur at the end of the */
1261 /* interrupt handler to avoid overwriting the */
1262 /* interrupt queue. */
1263 /************************************************/
1267 currInt = (intCnt + nextInt) & (INT_QUEUE_SIZE - 1);
1271 * NOTE: Servicing an interrupt whose ISD contains a count of ZERO
1272 * can be indicative of a Shared Interrupt chain. Our driver can be
1273 * called from the system's interrupt handler as a matter of the OS
1274 * walking the chain. As the chain is walked, the interrupt will
1275 * eventually be serviced by the correct driver/handler.
1278 /* chained interrupt = not ours */
1279 pr_info(">> %s: intCnt NULL, sts %x, possibly a chained interrupt!\n",
1280 ci->devname, status);
1285 ci->iqp_tailx = currInt;
1287 currInt <<= INTRPTS_NEXTINT_S;
1288 ci->intlog.last_status_new = ci->intlog.this_status_new;
1289 ci->intlog.this_status_new = currInt;
1291 if ((cxt1e1_log_level >= LOG_WARN) && (status & INTRPTS_INTFULL_M))
1293 pr_info("%s: Interrupt queue full condition occurred\n", ci->devname);
1295 if (cxt1e1_log_level >= LOG_DEBUG)
1296 pr_info("%s: interrupts pending, isd @ 0x%p: %x curr %d cnt %d NEXT %d\n",
1297 ci->devname, &ci->reg->isd,
1298 status, nextInt, intCnt, (intCnt + nextInt) & (INT_QUEUE_SIZE - 1));
1301 #if defined(SBE_ISR_TASKLET)
1302 pci_write_32 ((u_int32_t *) &ci->reg->isd, currInt);
1303 atomic_inc (&ci->bh_pending);
1304 tasklet_schedule (&ci->ci_musycc_isr_tasklet);
1305 #elif defined(SBE_ISR_IMMEDIATE)
1306 pci_write_32 ((u_int32_t *) &ci->reg->isd, currInt);
1307 atomic_inc (&ci->bh_pending);
1308 queue_task (&ci->ci_musycc_isr_tq, &tq_immediate);
1309 mark_bh (IMMEDIATE_BH);
1310 #elif defined(SBE_ISR_INLINE)
1311 (void) musycc_intr_bh_tasklet (ci);
1312 pci_write_32 ((u_int32_t *) &ci->reg->isd, currInt);
1318 #if defined(SBE_ISR_IMMEDIATE)
1323 musycc_intr_bh_tasklet (ci_t * ci)
1327 unsigned int intCnt;
1328 volatile u_int32_t currInt = 0;
1329 volatile unsigned int headx, tailx;
1330 int readCount, loopCount;
1331 int group, gchan, event, err, tx;
1332 u_int32_t badInt = INT_EMPTY_ENTRY;
1333 u_int32_t badInt2 = INT_EMPTY_ENTRY2;
1336 * Hardware not available, potential interrupt hang. But since interrupt
1337 * might be shared, just return.
1339 if ((drvr_state != SBE_DRVR_AVAILABLE) || (ci->state == C_INIT))
1341 #if defined(SBE_ISR_IMMEDIATE)
1347 #if defined(SBE_ISR_TASKLET) || defined(SBE_ISR_IMMEDIATE)
1348 if (drvr_state != SBE_DRVR_AVAILABLE)
1350 #if defined(SBE_ISR_TASKLET)
1352 #elif defined(SBE_ISR_IMMEDIATE)
1356 #elif defined(SBE_ISR_INLINE)
1357 /* no semaphore taken, no double checks */
1360 ci->intlog.drvr_intr_bhcount++;
1363 unsigned int bh = atomic_read (&ci->bh_pending);
1365 max_bh = max (bh, max_bh);
1367 atomic_set (&ci->bh_pending, 0);/* if here, no longer pending */
1368 while ((headx = ci->iqp_headx) != (tailx = ci->iqp_tailx))
1370 intCnt = (tailx >= headx) ? (tailx - headx) : (tailx - headx + INT_QUEUE_SIZE);
1371 currInt = le32_to_cpu (ci->iqd_p[headx]);
1373 max_intcnt = max (intCnt, max_intcnt); /* RLD DEBUG */
1375 /**************************************************/
1378 /* The following code checks for the condition */
1379 /* of interrupt assertion before interrupt */
1380 /* queue update. This is a problem on several */
1381 /* PCI-Local bridge chips found on some products. */
1382 /**************************************************/
1385 if ((currInt == badInt) || (currInt == badInt2))
1386 ci->intlog.drvr_int_failure++;
1388 while ((currInt == badInt) || (currInt == badInt2))
1390 for (loopCount = 0; loopCount < 0x30; loopCount++)
1391 OS_uwait_dummy (); /* use call to avoid optimization removal
1394 currInt = le32_to_cpu (ci->iqd_p[headx]);
1395 if (readCount++ > 20)
1399 if ((currInt == badInt) || (currInt == badInt2)) /* catch failure of Bug
1402 if (cxt1e1_log_level >= LOG_WARN)
1403 pr_info("%s: Illegal Interrupt Detected @ 0x%p, mod %d.)\n",
1404 ci->devname, &ci->iqd_p[headx], headx);
1407 * If the descriptor has not recovered, then leaving the EMPTY
1408 * entry set will not signal to the MUSYCC that this descriptor
1409 * has been serviced. The Interrupt Queue can then start losing
1410 * available descriptors and MUSYCC eventually encounters and
1411 * reports the INTFULL condition. Per manual, changing any bit
1412 * marks descriptor as available, thus the use of different
1413 * EMPTY_ENTRY values.
1416 if (currInt == badInt)
1418 ci->iqd_p[headx] = __constant_cpu_to_le32 (INT_EMPTY_ENTRY2);
1421 ci->iqd_p[headx] = __constant_cpu_to_le32 (INT_EMPTY_ENTRY);
1423 ci->iqp_headx = (headx + 1) & (INT_QUEUE_SIZE - 1); /* insure wrapness */
1428 group = INTRPT_GRP (currInt);
1429 gchan = INTRPT_CH (currInt);
1430 event = INTRPT_EVENT (currInt);
1431 err = INTRPT_ERROR (currInt);
1432 tx = currInt & INTRPT_DIR_M;
1434 ci->iqd_p[headx] = __constant_cpu_to_le32 (INT_EMPTY_ENTRY);
1437 if (cxt1e1_log_level >= LOG_DEBUG)
1440 pr_info(" %08x -> err: %2d,", currInt, err);
1442 pr_info("+ interrupt event: %d, grp: %d, chan: %2d, side: %cX\n",
1443 event, group, gchan, tx ? 'T' : 'R');
1445 pi = &ci->port[group]; /* notice that here we assume 1-1 group -
1447 ch = pi->chan[gchan];
1450 case EVE_SACK: /* Service Request Acknowledge */
1451 if (cxt1e1_log_level >= LOG_DEBUG)
1453 volatile u_int32_t r;
1455 r = pci_read_32 ((u_int32_t *) &pi->reg->srd);
1456 pr_info("- SACK cmd: %08x (hdw= %08x)\n", pi->sr_last, r);
1458 SD_SEM_GIVE (&pi->sr_sem_wait); /* wake up waiting process */
1460 case EVE_CHABT: /* Change To Abort Code (0x7e -> 0xff) */
1461 case EVE_CHIC: /* Change To Idle Code (0xff -> 0x7e) */
1463 case EVE_EOM: /* End Of Message */
1464 case EVE_EOB: /* End Of Buffer (Transparent mode) */
1467 musycc_bh_tx_eom (pi, gchan);
1470 musycc_bh_rx_eom (pi, gchan);
1476 * MUSYCC Interrupt Descriptor section states that EOB and EOM
1477 * can be combined with the NONE error (as well as others). So
1478 * drop thru to catch this...
1484 ch->s.rx_length_errors++;
1488 if (cxt1e1_log_level >= LOG_WARN)
1489 pr_info("%s: unexpected interrupt event: %d, iqd[%d]: %08x, port: %d\n", ci->devname,
1490 event, headx, currInt, group);
1492 } /* switch on event */
1496 * Per MUSYCC Manual, Section 6.4.8.3 [Transmit Errors], TX errors
1497 * are service-affecting and require action to resume normal
1498 * bit-level processing.
1505 * Per MUSYCC manual, Section 6.4.8.3 [Transmit Errors], this
1506 * error requires Transmit channel reactivation.
1508 * Per MUSYCC manual, Section 6.4.8.4 [Receive Errors], this error
1509 * requires Receive channel reactivation.
1515 * TX ONR Error only occurs when channel is configured for
1516 * Transparent Mode. However, this code will catch and
1517 * re-activate on ANY TX ONR error.
1521 * Set flag to re-enable on any next transmit attempt.
1523 ch->ch_start_tx = CH_START_TX_ONR;
1526 #ifdef RLD_TRANS_DEBUG
1527 if (1 || cxt1e1_log_level >= LOG_MONITOR)
1529 if (cxt1e1_log_level >= LOG_MONITOR)
1532 pr_info("%s: TX buffer underflow [ONR] on channel %d, mode %x QStopped %x free %d\n",
1533 ci->devname, ch->channum, ch->p.chan_mode, sd_queue_stopped (ch->user), ch->txd_free);
1535 if (ch->p.chan_mode == 2) /* problem = ONR on HDLC
1538 pr_info("++ Failed Last %x Next %x QStopped %x, start_tx %x tx_full %d txd_free %d mode %x\n",
1539 (u_int32_t) ch->txd_irq_srv, (u_int32_t) ch->txd_usr_add,
1540 sd_queue_stopped (ch->user),
1541 ch->ch_start_tx, ch->tx_full, ch->txd_free, ch->p.chan_mode);
1542 musycc_dump_txbuffer_ring (ch, 0);
1547 } else /* RX buffer overrun */
1550 * Per MUSYCC manual, Section 6.4.8.4 [Receive Errors],
1551 * channel recovery for this RX ONR error IS required. It is
1552 * also suggested to increase the number of receive buffers
1553 * for this channel. Receive channel reactivation IS
1554 * required, and data has been lost.
1556 ch->s.rx_over_errors++;
1557 ch->ch_start_rx = CH_START_RX_ONR;
1559 if (cxt1e1_log_level >= LOG_WARN)
1561 pr_info("%s: RX buffer overflow [ONR] on channel %d, mode %x\n",
1562 ci->devname, ch->channum, ch->p.chan_mode);
1563 //musycc_dump_rxbuffer_ring (ch, 0); /* RLD DEBUG */
1566 musycc_chan_restart (ch);
1571 ch->s.tx_fifo_errors++;
1572 ch->ch_start_tx = CH_START_TX_BUF;
1574 * Per MUSYCC manual, Section 6.4.8.3 [Transmit Errors],
1575 * this BUFF error requires Transmit channel reactivation.
1577 if (cxt1e1_log_level >= LOG_MONITOR)
1578 pr_info("%s: TX buffer underrun [BUFF] on channel %d, mode %x\n",
1579 ci->devname, ch->channum, ch->p.chan_mode);
1580 } else /* RX buffer overrun */
1582 ch->s.rx_over_errors++;
1584 * Per MUSYCC manual, Section 6.4.8.4 [Receive Errors], HDLC
1585 * mode requires NO recovery for this RX BUFF error is
1586 * required. It is suggested to increase the FIFO buffer
1587 * space for this channel. Receive channel reactivation is
1588 * not required, but data has been lost.
1590 if (cxt1e1_log_level >= LOG_WARN)
1591 pr_info("%s: RX buffer overrun [BUFF] on channel %d, mode %x\n",
1592 ci->devname, ch->channum, ch->p.chan_mode);
1594 * Per MUSYCC manual, Section 6.4.9.4 [Receive Errors],
1595 * Transparent mode DOES require recovery for the RX BUFF
1596 * error. It is suggested to increase the FIFO buffer space
1597 * for this channel. Receive channel reactivation IS
1598 * required and data has been lost.
1600 if (ch->p.chan_mode == CFG_CH_PROTO_TRANS)
1601 ch->ch_start_rx = CH_START_RX_BUF;
1604 if (tx || (ch->p.chan_mode == CFG_CH_PROTO_TRANS))
1605 musycc_chan_restart (ch);
1609 } /* switch on err */
1611 /* Check for interrupt lost condition */
1612 if ((currInt & INTRPT_ILOST_M) && (cxt1e1_log_level >= LOG_ERROR))
1614 pr_info("%s: Interrupt queue overflow - ILOST asserted\n",
1617 ci->iqp_headx = (headx + 1) & (INT_QUEUE_SIZE - 1); /* insure wrapness */
1621 if ((cxt1e1_log_level >= LOG_MONITOR2) && (ci->iqp_headx != ci->iqp_tailx))
1625 bh = atomic_read (&CI->bh_pending);
1626 pr_info("_bh_: late arrivals, head %d != tail %d, pending %d\n",
1627 ci->iqp_headx, ci->iqp_tailx, bh);
1629 #if defined(SBE_ISR_IMMEDIATE)
1632 /* else, nothing returned */
1637 musycc_new_chan (ci_t * ci, int channum, void *user)
1641 ch = ci->port[channum / MUSYCC_NCHANS].chan[channum % MUSYCC_NCHANS];
1643 if (ch->state != UNASSIGNED)
1645 /* NOTE: mch_t already cleared during OS_kmalloc() */
1651 ch->p.intr_mask = 0;
1653 ch->p.chan_mode = CFG_CH_PROTO_HDLC_FCS16;
1654 ch->p.idlecode = CFG_CH_FLAG_7E;
1655 ch->p.pad_fill_count = 2;
1656 spin_lock_init (&ch->ch_rxlock);
1657 spin_lock_init (&ch->ch_txlock);
1664 #ifdef SBE_PMCC4_ENABLE
1666 musycc_chan_down (ci_t * dummy, int channum)
1672 if (!(ch = sd_find_chan (dummy, channum)))
1677 /* Deactivate the channel */
1678 musycc_serv_req (pi, SR_CHANNEL_DEACTIVATE | SR_RX_DIRECTION | gchan);
1679 ch->ch_start_rx = 0;
1680 musycc_serv_req (pi, SR_CHANNEL_DEACTIVATE | SR_TX_DIRECTION | gchan);
1681 ch->ch_start_tx = 0;
1683 if (ch->state == DOWN)
1687 pi->regram->thp[gchan] = 0;
1688 pi->regram->tmp[gchan] = 0;
1689 pi->regram->rhp[gchan] = 0;
1690 pi->regram->rmp[gchan] = 0;
1692 for (i = 0; i < ch->txd_num; i++)
1694 if (ch->mdt[i].mem_token != 0)
1695 OS_mem_token_free (ch->mdt[i].mem_token);
1698 for (i = 0; i < ch->rxd_num; i++)
1700 if (ch->mdr[i].mem_token != 0)
1701 OS_mem_token_free (ch->mdr[i].mem_token);
1711 musycc_update_timeslots (pi);
1712 c4_fifo_free (pi, ch->gchan);
1721 musycc_del_chan (ci_t * ci, int channum)
1725 if ((channum < 0) || (channum >= (MUSYCC_NPORTS * MUSYCC_NCHANS))) /* sanity chk param */
1727 if (!(ch = sd_find_chan (ci, channum)))
1729 if (ch->state == UP)
1730 musycc_chan_down (ci, channum);
1731 ch->state = UNASSIGNED;
1737 musycc_del_chan_stats (ci_t * ci, int channum)
1741 if (channum < 0 || channum >= (MUSYCC_NPORTS * MUSYCC_NCHANS)) /* sanity chk param */
1743 if (!(ch = sd_find_chan (ci, channum)))
1746 memset (&ch->s, 0, sizeof (struct sbecom_chan_stats));
1752 musycc_start_xmit (ci_t * ci, int channum, void *mem_token)
1758 unsigned long flags;
1763 if (!(ch = sd_find_chan (ci, channum)))
1766 if (ci->state != C_RUNNING) /* full interrupt processing available */
1768 if (ch->state != UP)
1771 if (!(ch->status & TX_ENABLED))
1772 return EROFS; /* how else to flag unwritable state ? */
1774 #ifdef RLD_TRANS_DEBUGx
1775 if (1 || cxt1e1_log_level >= LOG_MONITOR2)
1777 if (cxt1e1_log_level >= LOG_MONITOR2)
1780 pr_info("++ start_xmt[%d]: state %x start %x full %d free %d required %d stopped %x\n",
1781 channum, ch->state, ch->ch_start_tx, ch->tx_full,
1782 ch->txd_free, ch->txd_required, sd_queue_stopped (ch->user));
1784 /***********************************************/
1785 /** Determine total amount of data to be sent **/
1786 /***********************************************/
1789 for (len = OS_mem_token_tlen (m2); len > 0;
1790 m2 = (void *) OS_mem_token_next (m2))
1792 if (!OS_mem_token_len (m2))
1795 len -= OS_mem_token_len (m2);
1798 if (txd_need_cnt == 0)
1800 if (cxt1e1_log_level >= LOG_MONITOR2)
1801 pr_info("%s channel %d: no TX data in User buffer\n", ci->devname, channum);
1802 OS_mem_token_free (mem_token);
1803 return 0; /* no data to send */
1805 /*************************************************/
1806 /** Are there sufficient descriptors available? **/
1807 /*************************************************/
1808 if (txd_need_cnt > ch->txd_num) /* never enough descriptors for this
1811 if (cxt1e1_log_level >= LOG_DEBUG)
1813 pr_info("start_xmit: discarding buffer, insufficient descriptor cnt %d, need %d.\n",
1814 ch->txd_num, txd_need_cnt + 1);
1817 OS_mem_token_free (mem_token);
1821 spin_lock_irqsave (&ch->ch_txlock, flags);
1823 /************************************************************/
1824 /** flow control the line if not enough descriptors remain **/
1825 /************************************************************/
1826 if (txd_need_cnt > ch->txd_free)
1828 if (cxt1e1_log_level >= LOG_MONITOR2)
1830 pr_info("start_xmit[%d]: EBUSY - need more descriptors, have %d of %d need %d\n",
1831 channum, ch->txd_free, ch->txd_num, txd_need_cnt);
1834 ch->txd_required = txd_need_cnt;
1835 sd_disable_xmit (ch->user);
1837 spin_unlock_irqrestore (&ch->ch_txlock, flags);
1839 return EBUSY; /* tell user to try again later */
1841 /**************************************************/
1842 /** Put the user data into MUSYCC data buffer(s) **/
1843 /**************************************************/
1845 md = ch->txd_usr_add; /* get current available descriptor */
1847 for (len = OS_mem_token_tlen (m2); len > 0; m2 = OS_mem_token_next (m2))
1849 int u = OS_mem_token_len (m2);
1856 * Enable following chunks, yet wait to enable the FIRST chunk until
1857 * after ALL subsequent chunks are setup.
1859 if (md != ch->txd_usr_add) /* not first chunk */
1860 u |= MUSYCC_TX_OWNED; /* transfer ownership from HOST to MUSYCC */
1862 if (len) /* not last chunk */
1864 else if (ch->p.chan_mode == CFG_CH_PROTO_TRANS)
1867 * Per MUSYCC Ref 6.4.9 for Transparent Mode, the host must
1868 * always clear EOMIRQ_ENABLE in every Transmit Buffer Descriptor
1869 * (IE. don't set herein).
1873 u |= EOMIRQ_ENABLE; /* EOM, last HDLC chunk */
1876 /* last chunk in hdlc mode */
1877 u |= (ch->p.idlecode << IDLE_CODE);
1878 if (ch->p.pad_fill_count)
1881 /* NOOP NOTE: u_int8_t cannot be > 0xFF */
1882 /* sanitize pad_fill_count for maximums allowed by hardware */
1883 if (ch->p.pad_fill_count > EXTRA_FLAGS_MASK)
1884 ch->p.pad_fill_count = EXTRA_FLAGS_MASK;
1886 u |= (PADFILL_ENABLE | (ch->p.pad_fill_count << EXTRA_FLAGS));
1888 md->mem_token = len ? 0 : mem_token; /* Fill in mds on last
1889 * segment, others set ZERO
1890 * so that entire token is
1891 * removed ONLY when ALL
1892 * segments have been
1895 md->data = cpu_to_le32 (OS_vtophys (OS_mem_token_data (m2)));
1897 md->status = cpu_to_le32 (u);
1905 * Now transfer ownership of first chunk from HOST to MUSYCC in order to
1906 * fire-off this XMIT.
1908 ch->txd_usr_add->status |= __constant_cpu_to_le32 (MUSYCC_TX_OWNED);
1910 ch->txd_usr_add = md;
1912 len = OS_mem_token_tlen (mem_token);
1913 atomic_add (len, &ch->tx_pending);
1914 atomic_add (len, &ci->tx_pending);
1916 ch->s.tx_bytes += len;
1918 * If an ONR was seen, then channel requires poking to restart
1921 if (ch->ch_start_tx)
1923 musycc_chan_restart (ch);
1925 #ifdef SBE_WAN256T3_ENABLE
1926 wan256t3_led (ci, LED_TX, LEDV_G);
1932 /*** End-of-File ***/