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29 * This is a special protocol for configuring communication over the
30 * I2S bus between the DSP on the MSM8994 and APBridgeA. Therefore,
31 * we can predefine several low-level attributes of the communication
32 * because we know that they are supported. In particular, the following
33 * assumptions are made:
34 * - there are two channels (i.e., stereo)
35 * - the low-level protocol is I2S as defined by Philips/NXP
36 * - the DSP on the MSM8994 is the clock master for MCLK, BCLK, and WCLK
37 * - WCLK changes on the falling edge of BCLK
38 * - WCLK low for left channel; high for right channel
39 * - TX data is sent on the falling edge of BCLK
40 * - RX data is received/latched on the rising edge of BCLK
43 #ifndef __AUDIO_APBRIDGEA_H
44 #define __AUDIO_APBRIDGEA_H
46 #define AUDIO_APBRIDGEA_TYPE_SET_CONFIG 0x01
47 #define AUDIO_APBRIDGEA_TYPE_REGISTER_CPORT 0x02
48 #define AUDIO_APBRIDGEA_TYPE_UNREGISTER_CPORT 0x03
49 #define AUDIO_APBRIDGEA_TYPE_SET_TX_DATA_SIZE 0x04
51 #define AUDIO_APBRIDGEA_TYPE_PREPARE_TX 0x06
52 #define AUDIO_APBRIDGEA_TYPE_START_TX 0x07
53 #define AUDIO_APBRIDGEA_TYPE_STOP_TX 0x08
54 #define AUDIO_APBRIDGEA_TYPE_SHUTDOWN_TX 0x09
55 #define AUDIO_APBRIDGEA_TYPE_SET_RX_DATA_SIZE 0x0a
57 #define AUDIO_APBRIDGEA_TYPE_PREPARE_RX 0x0c
58 #define AUDIO_APBRIDGEA_TYPE_START_RX 0x0d
59 #define AUDIO_APBRIDGEA_TYPE_STOP_RX 0x0e
60 #define AUDIO_APBRIDGEA_TYPE_SHUTDOWN_RX 0x0f
62 #define AUDIO_APBRIDGEA_PCM_FMT_8 BIT(0)
63 #define AUDIO_APBRIDGEA_PCM_FMT_16 BIT(1)
64 #define AUDIO_APBRIDGEA_PCM_FMT_24 BIT(2)
65 #define AUDIO_APBRIDGEA_PCM_FMT_32 BIT(3)
66 #define AUDIO_APBRIDGEA_PCM_FMT_64 BIT(4)
68 #define AUDIO_APBRIDGEA_PCM_RATE_5512 BIT(0)
69 #define AUDIO_APBRIDGEA_PCM_RATE_8000 BIT(1)
70 #define AUDIO_APBRIDGEA_PCM_RATE_11025 BIT(2)
71 #define AUDIO_APBRIDGEA_PCM_RATE_16000 BIT(3)
72 #define AUDIO_APBRIDGEA_PCM_RATE_22050 BIT(4)
73 #define AUDIO_APBRIDGEA_PCM_RATE_32000 BIT(5)
74 #define AUDIO_APBRIDGEA_PCM_RATE_44100 BIT(6)
75 #define AUDIO_APBRIDGEA_PCM_RATE_48000 BIT(7)
76 #define AUDIO_APBRIDGEA_PCM_RATE_64000 BIT(8)
77 #define AUDIO_APBRIDGEA_PCM_RATE_88200 BIT(9)
78 #define AUDIO_APBRIDGEA_PCM_RATE_96000 BIT(10)
79 #define AUDIO_APBRIDGEA_PCM_RATE_176400 BIT(11)
80 #define AUDIO_APBRIDGEA_PCM_RATE_192000 BIT(12)
82 #define AUDIO_APBRIDGEA_DIRECTION_TX BIT(0)
83 #define AUDIO_APBRIDGEA_DIRECTION_RX BIT(1)
85 /* The I2S port is passed in the 'index' parameter of the USB request */
86 /* The CPort is passed in the 'value' parameter of the USB request */
88 struct audio_apbridgea_hdr {
94 struct audio_apbridgea_set_config_request {
95 struct audio_apbridgea_hdr hdr;
96 __le32 format; /* AUDIO_APBRIDGEA_PCM_FMT_* */
97 __le32 rate; /* AUDIO_APBRIDGEA_PCM_RATE_* */
98 __le32 mclk_freq; /* XXX Remove? */
101 struct audio_apbridgea_register_cport_request {
102 struct audio_apbridgea_hdr hdr;
107 struct audio_apbridgea_unregister_cport_request {
108 struct audio_apbridgea_hdr hdr;
113 struct audio_apbridgea_set_tx_data_size_request {
114 struct audio_apbridgea_hdr hdr;
118 struct audio_apbridgea_prepare_tx_request {
119 struct audio_apbridgea_hdr hdr;
122 struct audio_apbridgea_start_tx_request {
123 struct audio_apbridgea_hdr hdr;
127 struct audio_apbridgea_stop_tx_request {
128 struct audio_apbridgea_hdr hdr;
131 struct audio_apbridgea_shutdown_tx_request {
132 struct audio_apbridgea_hdr hdr;
135 struct audio_apbridgea_set_rx_data_size_request {
136 struct audio_apbridgea_hdr hdr;
140 struct audio_apbridgea_prepare_rx_request {
141 struct audio_apbridgea_hdr hdr;
144 struct audio_apbridgea_start_rx_request {
145 struct audio_apbridgea_hdr hdr;
148 struct audio_apbridgea_stop_rx_request {
149 struct audio_apbridgea_hdr hdr;
152 struct audio_apbridgea_shutdown_rx_request {
153 struct audio_apbridgea_hdr hdr;
156 #endif /*__AUDIO_APBRIDGEA_H */