drivers/staging/media/omap4iss/iss_csi2.c

   1 /*
   2  * TI OMAP4 ISS V4L2 Driver - CSI PHY module
   3  *
   4  * Copyright (C) 2012 Texas Instruments, Inc.
   5  *
   6  * Author: Sergio Aguirre <sergio.a.aguirre@gmail.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 #include <linux/delay.h>
  15 #include <media/v4l2-common.h>
  16 #include <linux/v4l2-mediabus.h>
  17 #include <linux/mm.h>
  18
  19 #include "iss.h"
  20 #include "iss_regs.h"
  21 #include "iss_csi2.h"
  22
  23 /*
  24  * csi2_if_enable - Enable CSI2 Receiver interface.
  25  * @enable: enable flag
  26  *
  27  */
  28 static void csi2_if_enable(struct iss_csi2_device *csi2, u8 enable)
  29 {
  30         struct iss_csi2_ctrl_cfg *currctrl = &csi2->ctrl;
  31
  32         iss_reg_update(csi2->iss, csi2->regs1, CSI2_CTRL, CSI2_CTRL_IF_EN,
  33                        enable ? CSI2_CTRL_IF_EN : 0);
  34
  35         currctrl->if_enable = enable;
  36 }
  37
  38 /*
  39  * csi2_recv_config - CSI2 receiver module configuration.
  40  * @currctrl: iss_csi2_ctrl_cfg structure
  41  *
  42  */
  43 static void csi2_recv_config(struct iss_csi2_device *csi2,
  44                              struct iss_csi2_ctrl_cfg *currctrl)
  45 {
  46         u32 reg = 0;
  47
  48         if (currctrl->frame_mode)
  49                 reg |= CSI2_CTRL_FRAME;
  50         else
  51                 reg &= ~CSI2_CTRL_FRAME;
  52
  53         if (currctrl->vp_clk_enable)
  54                 reg |= CSI2_CTRL_VP_CLK_EN;
  55         else
  56                 reg &= ~CSI2_CTRL_VP_CLK_EN;
  57
  58         if (currctrl->vp_only_enable)
  59                 reg |= CSI2_CTRL_VP_ONLY_EN;
  60         else
  61                 reg &= ~CSI2_CTRL_VP_ONLY_EN;
  62
  63         reg &= ~CSI2_CTRL_VP_OUT_CTRL_MASK;
  64         reg |= currctrl->vp_out_ctrl << CSI2_CTRL_VP_OUT_CTRL_SHIFT;
  65
  66         if (currctrl->ecc_enable)
  67                 reg |= CSI2_CTRL_ECC_EN;
  68         else
  69                 reg &= ~CSI2_CTRL_ECC_EN;
  70
  71         /*
  72          * Set MFlag assertion boundaries to:
  73          * Low: 4/8 of FIFO size
  74          * High: 6/8 of FIFO size
  75          */
  76         reg &= ~(CSI2_CTRL_MFLAG_LEVH_MASK | CSI2_CTRL_MFLAG_LEVL_MASK);
  77         reg |= (2 << CSI2_CTRL_MFLAG_LEVH_SHIFT) |
  78                (4 << CSI2_CTRL_MFLAG_LEVL_SHIFT);
  79
  80         /* Generation of 16x64-bit bursts (Recommended) */
  81         reg |= CSI2_CTRL_BURST_SIZE_EXPAND;
  82
  83         /* Do Non-Posted writes (Recommended) */
  84         reg |= CSI2_CTRL_NON_POSTED_WRITE;
  85
  86         /*
  87          * Enforce Little endian for all formats, including:
  88          * YUV4:2:2 8-bit and YUV4:2:0 Legacy
  89          */
  90         reg |= CSI2_CTRL_ENDIANNESS;
  91
  92         iss_reg_write(csi2->iss, csi2->regs1, CSI2_CTRL, reg);
  93 }
  94
  95 static const unsigned int csi2_input_fmts[] = {
  96         V4L2_MBUS_FMT_SGRBG10_1X10,
  97         V4L2_MBUS_FMT_SGRBG10_DPCM8_1X8,
  98         V4L2_MBUS_FMT_SRGGB10_1X10,
  99         V4L2_MBUS_FMT_SRGGB10_DPCM8_1X8,
 100         V4L2_MBUS_FMT_SBGGR10_1X10,
 101         V4L2_MBUS_FMT_SBGGR10_DPCM8_1X8,
 102         V4L2_MBUS_FMT_SGBRG10_1X10,
 103         V4L2_MBUS_FMT_SGBRG10_DPCM8_1X8,
 104         V4L2_MBUS_FMT_SBGGR8_1X8,
 105         V4L2_MBUS_FMT_SGBRG8_1X8,
 106         V4L2_MBUS_FMT_SGRBG8_1X8,
 107         V4L2_MBUS_FMT_SRGGB8_1X8,
 108         V4L2_MBUS_FMT_UYVY8_1X16,
 109         V4L2_MBUS_FMT_YUYV8_1X16,
 110 };
 111
 112 /* To set the format on the CSI2 requires a mapping function that takes
 113  * the following inputs:
 114  * - 3 different formats (at this time)
 115  * - 2 destinations (mem, vp+mem) (vp only handled separately)
 116  * - 2 decompression options (on, off)
 117  * Output should be CSI2 frame format code
 118  * Array indices as follows: [format][dest][decompr]
 119  * Not all combinations are valid. 0 means invalid.
 120  */
 121 static const u16 __csi2_fmt_map[][2][2] = {
 122         /* RAW10 formats */
 123         {
 124                 /* Output to memory */
 125                 {
 126                         /* No DPCM decompression */
 127                         CSI2_PIX_FMT_RAW10_EXP16,
 128                         /* DPCM decompression */
 129                         0,
 130                 },
 131                 /* Output to both */
 132                 {
 133                         /* No DPCM decompression */
 134                         CSI2_PIX_FMT_RAW10_EXP16_VP,
 135                         /* DPCM decompression */
 136                         0,
 137                 },
 138         },
 139         /* RAW10 DPCM8 formats */
 140         {
 141                 /* Output to memory */
 142                 {
 143                         /* No DPCM decompression */
 144                         CSI2_USERDEF_8BIT_DATA1,
 145                         /* DPCM decompression */
 146                         CSI2_USERDEF_8BIT_DATA1_DPCM10,
 147                 },
 148                 /* Output to both */
 149                 {
 150                         /* No DPCM decompression */
 151                         CSI2_PIX_FMT_RAW8_VP,
 152                         /* DPCM decompression */
 153                         CSI2_USERDEF_8BIT_DATA1_DPCM10_VP,
 154                 },
 155         },
 156         /* RAW8 formats */
 157         {
 158                 /* Output to memory */
 159                 {
 160                         /* No DPCM decompression */
 161                         CSI2_PIX_FMT_RAW8,
 162                         /* DPCM decompression */
 163                         0,
 164                 },
 165                 /* Output to both */
 166                 {
 167                         /* No DPCM decompression */
 168                         CSI2_PIX_FMT_RAW8_VP,
 169                         /* DPCM decompression */
 170                         0,
 171                 },
 172         },
 173         /* YUV422 formats */
 174         {
 175                 /* Output to memory */
 176                 {
 177                         /* No DPCM decompression */
 178                         CSI2_PIX_FMT_YUV422_8BIT,
 179                         /* DPCM decompression */
 180                         0,
 181                 },
 182                 /* Output to both */
 183                 {
 184                         /* No DPCM decompression */
 185                         CSI2_PIX_FMT_YUV422_8BIT_VP16,
 186                         /* DPCM decompression */
 187                         0,
 188                 },
 189         },
 190 };
 191
 192 /*
 193  * csi2_ctx_map_format - Map CSI2 sink media bus format to CSI2 format ID
 194  * @csi2: ISS CSI2 device
 195  *
 196  * Returns CSI2 physical format id
 197  */
 198 static u16 csi2_ctx_map_format(struct iss_csi2_device *csi2)
 199 {
 200         const struct v4l2_mbus_framefmt *fmt = &csi2->formats[CSI2_PAD_SINK];
 201         int fmtidx, destidx;
 202
 203         switch (fmt->code) {
 204         case V4L2_MBUS_FMT_SGRBG10_1X10:
 205         case V4L2_MBUS_FMT_SRGGB10_1X10:
 206         case V4L2_MBUS_FMT_SBGGR10_1X10:
 207         case V4L2_MBUS_FMT_SGBRG10_1X10:
 208                 fmtidx = 0;
 209                 break;
 210         case V4L2_MBUS_FMT_SGRBG10_DPCM8_1X8:
 211         case V4L2_MBUS_FMT_SRGGB10_DPCM8_1X8:
 212         case V4L2_MBUS_FMT_SBGGR10_DPCM8_1X8:
 213         case V4L2_MBUS_FMT_SGBRG10_DPCM8_1X8:
 214                 fmtidx = 1;
 215                 break;
 216         case V4L2_MBUS_FMT_SBGGR8_1X8:
 217         case V4L2_MBUS_FMT_SGBRG8_1X8:
 218         case V4L2_MBUS_FMT_SGRBG8_1X8:
 219         case V4L2_MBUS_FMT_SRGGB8_1X8:
 220                 fmtidx = 2;
 221                 break;
 222         case V4L2_MBUS_FMT_UYVY8_1X16:
 223         case V4L2_MBUS_FMT_YUYV8_1X16:
 224                 fmtidx = 3;
 225                 break;
 226         default:
 227                 WARN(1, KERN_ERR "CSI2: pixel format %08x unsupported!\n",
 228                      fmt->code);
 229                 return 0;
 230         }
 231
 232         if (!(csi2->output & CSI2_OUTPUT_IPIPEIF) &&
 233             !(csi2->output & CSI2_OUTPUT_MEMORY)) {
 234                 /* Neither output enabled is a valid combination */
 235                 return CSI2_PIX_FMT_OTHERS;
 236         }
 237
 238         /* If we need to skip frames at the beginning of the stream disable the
 239          * video port to avoid sending the skipped frames to the IPIPEIF.
 240          */
 241         destidx = csi2->frame_skip ? 0 : !!(csi2->output & CSI2_OUTPUT_IPIPEIF);
 242
 243         return __csi2_fmt_map[fmtidx][destidx][csi2->dpcm_decompress];
 244 }
 245
 246 /*
 247  * csi2_set_outaddr - Set memory address to save output image
 248  * @csi2: Pointer to ISS CSI2a device.
 249  * @addr: 32-bit memory address aligned on 32 byte boundary.
 250  *
 251  * Sets the memory address where the output will be saved.
 252  *
 253  * Returns 0 if successful, or -EINVAL if the address is not in the 32 byte
 254  * boundary.
 255  */
 256 static void csi2_set_outaddr(struct iss_csi2_device *csi2, u32 addr)
 257 {
 258         struct iss_csi2_ctx_cfg *ctx = &csi2->contexts[0];
 259
 260         ctx->ping_addr = addr;
 261         ctx->pong_addr = addr;
 262         iss_reg_write(csi2->iss, csi2->regs1, CSI2_CTX_PING_ADDR(ctx->ctxnum),
 263                       ctx->ping_addr);
 264         iss_reg_write(csi2->iss, csi2->regs1, CSI2_CTX_PONG_ADDR(ctx->ctxnum),
 265                       ctx->pong_addr);
 266 }
 267
 268 /*
 269  * is_usr_def_mapping - Checks whether USER_DEF_MAPPING should
 270  *                      be enabled by CSI2.
 271  * @format_id: mapped format id
 272  *
 273  */
 274 static inline int is_usr_def_mapping(u32 format_id)
 275 {
 276         return (format_id & 0xf0) == 0x40 ? 1 : 0;
 277 }
 278
 279 /*
 280  * csi2_ctx_enable - Enable specified CSI2 context
 281  * @ctxnum: Context number, valid between 0 and 7 values.
 282  * @enable: enable
 283  *
 284  */
 285 static void csi2_ctx_enable(struct iss_csi2_device *csi2, u8 ctxnum, u8 enable)
 286 {
 287         struct iss_csi2_ctx_cfg *ctx = &csi2->contexts[ctxnum];
 288         u32 reg;
 289
 290         reg = iss_reg_read(csi2->iss, csi2->regs1, CSI2_CTX_CTRL1(ctxnum));
 291
 292         if (enable) {
 293                 unsigned int skip = 0;
 294
 295                 if (csi2->frame_skip)
 296                         skip = csi2->frame_skip;
 297                 else if (csi2->output & CSI2_OUTPUT_MEMORY)
 298                         skip = 1;
 299
 300                 reg &= ~CSI2_CTX_CTRL1_COUNT_MASK;
 301                 reg |= CSI2_CTX_CTRL1_COUNT_UNLOCK
 302                     |  (skip << CSI2_CTX_CTRL1_COUNT_SHIFT)
 303                     |  CSI2_CTX_CTRL1_CTX_EN;
 304         } else {
 305                 reg &= ~CSI2_CTX_CTRL1_CTX_EN;
 306         }
 307
 308         iss_reg_write(csi2->iss, csi2->regs1, CSI2_CTX_CTRL1(ctxnum), reg);
 309         ctx->enabled = enable;
 310 }
 311
 312 /*
 313  * csi2_ctx_config - CSI2 context configuration.
 314  * @ctx: context configuration
 315  *
 316  */
 317 static void csi2_ctx_config(struct iss_csi2_device *csi2,
 318                             struct iss_csi2_ctx_cfg *ctx)
 319 {
 320         u32 reg;
 321
 322         /* Set up CSI2_CTx_CTRL1 */
 323         if (ctx->eof_enabled)
 324                 reg = CSI2_CTX_CTRL1_EOF_EN;
 325
 326         if (ctx->eol_enabled)
 327                 reg |= CSI2_CTX_CTRL1_EOL_EN;
 328
 329         if (ctx->checksum_enabled)
 330                 reg |= CSI2_CTX_CTRL1_CS_EN;
 331
 332         iss_reg_write(csi2->iss, csi2->regs1, CSI2_CTX_CTRL1(ctx->ctxnum), reg);
 333
 334         /* Set up CSI2_CTx_CTRL2 */
 335         reg = ctx->virtual_id << CSI2_CTX_CTRL2_VIRTUAL_ID_SHIFT;
 336         reg |= ctx->format_id << CSI2_CTX_CTRL2_FORMAT_SHIFT;
 337
 338         if (ctx->dpcm_decompress && ctx->dpcm_predictor)
 339                 reg |= CSI2_CTX_CTRL2_DPCM_PRED;
 340
 341         if (is_usr_def_mapping(ctx->format_id))
 342                 reg |= 2 << CSI2_CTX_CTRL2_USER_DEF_MAP_SHIFT;
 343
 344         iss_reg_write(csi2->iss, csi2->regs1, CSI2_CTX_CTRL2(ctx->ctxnum), reg);
 345
 346         /* Set up CSI2_CTx_CTRL3 */
 347         iss_reg_write(csi2->iss, csi2->regs1, CSI2_CTX_CTRL3(ctx->ctxnum),
 348                       ctx->alpha << CSI2_CTX_CTRL3_ALPHA_SHIFT);
 349
 350         /* Set up CSI2_CTx_DAT_OFST */
 351         iss_reg_update(csi2->iss, csi2->regs1, CSI2_CTX_DAT_OFST(ctx->ctxnum),
 352                        CSI2_CTX_DAT_OFST_MASK, ctx->data_offset);
 353
 354         iss_reg_write(csi2->iss, csi2->regs1, CSI2_CTX_PING_ADDR(ctx->ctxnum),
 355                       ctx->ping_addr);
 356         iss_reg_write(csi2->iss, csi2->regs1, CSI2_CTX_PONG_ADDR(ctx->ctxnum),
 357                       ctx->pong_addr);
 358 }
 359
 360 /*
 361  * csi2_timing_config - CSI2 timing configuration.
 362  * @timing: csi2_timing_cfg structure
 363  */
 364 static void csi2_timing_config(struct iss_csi2_device *csi2,
 365                                struct iss_csi2_timing_cfg *timing)
 366 {
 367         u32 reg;
 368
 369         reg = iss_reg_read(csi2->iss, csi2->regs1, CSI2_TIMING);
 370
 371         if (timing->force_rx_mode)
 372                 reg |= CSI2_TIMING_FORCE_RX_MODE_IO1;
 373         else
 374                 reg &= ~CSI2_TIMING_FORCE_RX_MODE_IO1;
 375
 376         if (timing->stop_state_16x)
 377                 reg |= CSI2_TIMING_STOP_STATE_X16_IO1;
 378         else
 379                 reg &= ~CSI2_TIMING_STOP_STATE_X16_IO1;
 380
 381         if (timing->stop_state_4x)
 382                 reg |= CSI2_TIMING_STOP_STATE_X4_IO1;
 383         else
 384                 reg &= ~CSI2_TIMING_STOP_STATE_X4_IO1;
 385
 386         reg &= ~CSI2_TIMING_STOP_STATE_COUNTER_IO1_MASK;
 387         reg |= timing->stop_state_counter <<
 388                CSI2_TIMING_STOP_STATE_COUNTER_IO1_SHIFT;
 389
 390         iss_reg_write(csi2->iss, csi2->regs1, CSI2_TIMING, reg);
 391 }
 392
 393 /*
 394  * csi2_irq_ctx_set - Enables CSI2 Context IRQs.
 395  * @enable: Enable/disable CSI2 Context interrupts
 396  */
 397 static void csi2_irq_ctx_set(struct iss_csi2_device *csi2, int enable)
 398 {
 399         u32 reg = CSI2_CTX_IRQ_FE;
 400         int i;
 401
 402         if (csi2->use_fs_irq)
 403                 reg |= CSI2_CTX_IRQ_FS;
 404
 405         for (i = 0; i < 8; i++) {
 406                 iss_reg_write(csi2->iss, csi2->regs1, CSI2_CTX_IRQSTATUS(i),
 407                               reg);
 408                 if (enable)
 409                         iss_reg_set(csi2->iss, csi2->regs1,
 410                                     CSI2_CTX_IRQENABLE(i), reg);
 411                 else
 412                         iss_reg_clr(csi2->iss, csi2->regs1,
 413                                     CSI2_CTX_IRQENABLE(i), reg);
 414         }
 415 }
 416
 417 /*
 418  * csi2_irq_complexio1_set - Enables CSI2 ComplexIO IRQs.
 419  * @enable: Enable/disable CSI2 ComplexIO #1 interrupts
 420  */
 421 static void csi2_irq_complexio1_set(struct iss_csi2_device *csi2, int enable)
 422 {
 423         u32 reg;
 424         reg = CSI2_COMPLEXIO_IRQ_STATEALLULPMEXIT |
 425                 CSI2_COMPLEXIO_IRQ_STATEALLULPMENTER |
 426                 CSI2_COMPLEXIO_IRQ_STATEULPM5 |
 427                 CSI2_COMPLEXIO_IRQ_ERRCONTROL5 |
 428                 CSI2_COMPLEXIO_IRQ_ERRESC5 |
 429                 CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS5 |
 430                 CSI2_COMPLEXIO_IRQ_ERRSOTHS5 |
 431                 CSI2_COMPLEXIO_IRQ_STATEULPM4 |
 432                 CSI2_COMPLEXIO_IRQ_ERRCONTROL4 |
 433                 CSI2_COMPLEXIO_IRQ_ERRESC4 |
 434                 CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS4 |
 435                 CSI2_COMPLEXIO_IRQ_ERRSOTHS4 |
 436                 CSI2_COMPLEXIO_IRQ_STATEULPM3 |
 437                 CSI2_COMPLEXIO_IRQ_ERRCONTROL3 |
 438                 CSI2_COMPLEXIO_IRQ_ERRESC3 |
 439                 CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS3 |
 440                 CSI2_COMPLEXIO_IRQ_ERRSOTHS3 |
 441                 CSI2_COMPLEXIO_IRQ_STATEULPM2 |
 442                 CSI2_COMPLEXIO_IRQ_ERRCONTROL2 |
 443                 CSI2_COMPLEXIO_IRQ_ERRESC2 |
 444                 CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS2 |
 445                 CSI2_COMPLEXIO_IRQ_ERRSOTHS2 |
 446                 CSI2_COMPLEXIO_IRQ_STATEULPM1 |
 447                 CSI2_COMPLEXIO_IRQ_ERRCONTROL1 |
 448                 CSI2_COMPLEXIO_IRQ_ERRESC1 |
 449                 CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS1 |
 450                 CSI2_COMPLEXIO_IRQ_ERRSOTHS1;
 451         iss_reg_write(csi2->iss, csi2->regs1, CSI2_COMPLEXIO_IRQSTATUS, reg);
 452         if (enable)
 453                 iss_reg_set(csi2->iss, csi2->regs1, CSI2_COMPLEXIO_IRQENABLE,
 454                             reg);
 455         else
 456                 iss_reg_write(csi2->iss, csi2->regs1, CSI2_COMPLEXIO_IRQENABLE,
 457                               0);
 458 }
 459
 460 /*
 461  * csi2_irq_status_set - Enables CSI2 Status IRQs.
 462  * @enable: Enable/disable CSI2 Status interrupts
 463  */
 464 static void csi2_irq_status_set(struct iss_csi2_device *csi2, int enable)
 465 {
 466         u32 reg;
 467         reg = CSI2_IRQ_OCP_ERR |
 468                 CSI2_IRQ_SHORT_PACKET |
 469                 CSI2_IRQ_ECC_CORRECTION |
 470                 CSI2_IRQ_ECC_NO_CORRECTION |
 471                 CSI2_IRQ_COMPLEXIO_ERR |
 472                 CSI2_IRQ_FIFO_OVF |
 473                 CSI2_IRQ_CONTEXT0;
 474         iss_reg_write(csi2->iss, csi2->regs1, CSI2_IRQSTATUS, reg);
 475         if (enable)
 476                 iss_reg_set(csi2->iss, csi2->regs1, CSI2_IRQENABLE, reg);
 477         else
 478                 iss_reg_write(csi2->iss, csi2->regs1, CSI2_IRQENABLE, 0);
 479 }
 480
 481 /*
 482  * omap4iss_csi2_reset - Resets the CSI2 module.
 483  *
 484  * Must be called with the phy lock held.
 485  *
 486  * Returns 0 if successful, or -EBUSY if power command didn't respond.
 487  */
 488 int omap4iss_csi2_reset(struct iss_csi2_device *csi2)
 489 {
 490         u8 soft_reset_retries = 0;
 491         u32 reg;
 492         int i;
 493
 494         if (!csi2->available)
 495                 return -ENODEV;
 496
 497         if (csi2->phy->phy_in_use)
 498                 return -EBUSY;
 499
 500         iss_reg_set(csi2->iss, csi2->regs1, CSI2_SYSCONFIG,
 501                     CSI2_SYSCONFIG_SOFT_RESET);
 502
 503         do {
 504                 reg = iss_reg_read(csi2->iss, csi2->regs1, CSI2_SYSSTATUS)
 505                     & CSI2_SYSSTATUS_RESET_DONE;
 506                 if (reg == CSI2_SYSSTATUS_RESET_DONE)
 507                         break;
 508                 soft_reset_retries++;
 509                 if (soft_reset_retries < 5)
 510                         usleep_range(100, 100);
 511         } while (soft_reset_retries < 5);
 512
 513         if (soft_reset_retries == 5) {
 514                 dev_err(csi2->iss->dev,
 515                         "CSI2: Soft reset try count exceeded!\n");
 516                 return -EBUSY;
 517         }
 518
 519         iss_reg_set(csi2->iss, csi2->regs1, CSI2_COMPLEXIO_CFG,
 520                     CSI2_COMPLEXIO_CFG_RESET_CTRL);
 521
 522         i = 100;
 523         do {
 524                 reg = iss_reg_read(csi2->iss, csi2->phy->phy_regs, REGISTER1)
 525                     & REGISTER1_RESET_DONE_CTRLCLK;
 526                 if (reg == REGISTER1_RESET_DONE_CTRLCLK)
 527                         break;
 528                 usleep_range(100, 100);
 529         } while (--i > 0);
 530
 531         if (i == 0) {
 532                 dev_err(csi2->iss->dev,
 533                         "CSI2: Reset for CSI2_96M_FCLK domain Failed!\n");
 534                 return -EBUSY;
 535         }
 536
 537         iss_reg_update(csi2->iss, csi2->regs1, CSI2_SYSCONFIG,
 538                        CSI2_SYSCONFIG_MSTANDBY_MODE_MASK |
 539                        CSI2_SYSCONFIG_AUTO_IDLE,
 540                        CSI2_SYSCONFIG_MSTANDBY_MODE_NO);
 541
 542         return 0;
 543 }
 544
 545 static int csi2_configure(struct iss_csi2_device *csi2)
 546 {
 547         const struct iss_v4l2_subdevs_group *pdata;
 548         struct iss_csi2_timing_cfg *timing = &csi2->timing[0];
 549         struct v4l2_subdev *sensor;
 550         struct media_pad *pad;
 551
 552         /*
 553          * CSI2 fields that can be updated while the context has
 554          * been enabled or the interface has been enabled are not
 555          * updated dynamically currently. So we do not allow to
 556          * reconfigure if either has been enabled
 557          */
 558         if (csi2->contexts[0].enabled || csi2->ctrl.if_enable)
 559                 return -EBUSY;
 560
 561         pad = media_entity_remote_pad(&csi2->pads[CSI2_PAD_SINK]);
 562         sensor = media_entity_to_v4l2_subdev(pad->entity);
 563         pdata = sensor->host_priv;
 564
 565         csi2->frame_skip = 0;
 566         v4l2_subdev_call(sensor, sensor, g_skip_frames, &csi2->frame_skip);
 567
 568         csi2->ctrl.vp_out_ctrl = pdata->bus.csi2.vpclk_div;
 569         csi2->ctrl.frame_mode = ISS_CSI2_FRAME_IMMEDIATE;
 570         csi2->ctrl.ecc_enable = pdata->bus.csi2.crc;
 571
 572         timing->force_rx_mode = 1;
 573         timing->stop_state_16x = 1;
 574         timing->stop_state_4x = 1;
 575         timing->stop_state_counter = 0x1ff;
 576
 577         /*
 578          * The CSI2 receiver can't do any format conversion except DPCM
 579          * decompression, so every set_format call configures both pads
 580          * and enables DPCM decompression as a special case:
 581          */
 582         if (csi2->formats[CSI2_PAD_SINK].code !=
 583             csi2->formats[CSI2_PAD_SOURCE].code)
 584                 csi2->dpcm_decompress = true;
 585         else
 586                 csi2->dpcm_decompress = false;
 587
 588         csi2->contexts[0].format_id = csi2_ctx_map_format(csi2);
 589
 590         if (csi2->video_out.bpl_padding == 0)
 591                 csi2->contexts[0].data_offset = 0;
 592         else
 593                 csi2->contexts[0].data_offset = csi2->video_out.bpl_value;
 594
 595         /*
 596          * Enable end of frame and end of line signals generation for
 597          * context 0. These signals are generated from CSI2 receiver to
 598          * qualify the last pixel of a frame and the last pixel of a line.
 599          * Without enabling the signals CSI2 receiver writes data to memory
 600          * beyond buffer size and/or data line offset is not handled correctly.
 601          */
 602         csi2->contexts[0].eof_enabled = 1;
 603         csi2->contexts[0].eol_enabled = 1;
 604
 605         csi2_irq_complexio1_set(csi2, 1);
 606         csi2_irq_ctx_set(csi2, 1);
 607         csi2_irq_status_set(csi2, 1);
 608
 609         /* Set configuration (timings, format and links) */
 610         csi2_timing_config(csi2, timing);
 611         csi2_recv_config(csi2, &csi2->ctrl);
 612         csi2_ctx_config(csi2, &csi2->contexts[0]);
 613
 614         return 0;
 615 }
 616
 617 /*
 618  * csi2_print_status - Prints CSI2 debug information.
 619  */
 620 #define CSI2_PRINT_REGISTER(iss, regs, name)\
 621         dev_dbg(iss->dev, "###CSI2 " #name "=0x%08x\n", \
 622                 iss_reg_read(iss, regs, CSI2_##name))
 623
 624 static void csi2_print_status(struct iss_csi2_device *csi2)
 625 {
 626         struct iss_device *iss = csi2->iss;
 627
 628         if (!csi2->available)
 629                 return;
 630
 631         dev_dbg(iss->dev, "-------------CSI2 Register dump-------------\n");
 632
 633         CSI2_PRINT_REGISTER(iss, csi2->regs1, SYSCONFIG);
 634         CSI2_PRINT_REGISTER(iss, csi2->regs1, SYSSTATUS);
 635         CSI2_PRINT_REGISTER(iss, csi2->regs1, IRQENABLE);
 636         CSI2_PRINT_REGISTER(iss, csi2->regs1, IRQSTATUS);
 637         CSI2_PRINT_REGISTER(iss, csi2->regs1, CTRL);
 638         CSI2_PRINT_REGISTER(iss, csi2->regs1, DBG_H);
 639         CSI2_PRINT_REGISTER(iss, csi2->regs1, COMPLEXIO_CFG);
 640         CSI2_PRINT_REGISTER(iss, csi2->regs1, COMPLEXIO_IRQSTATUS);
 641         CSI2_PRINT_REGISTER(iss, csi2->regs1, SHORT_PACKET);
 642         CSI2_PRINT_REGISTER(iss, csi2->regs1, COMPLEXIO_IRQENABLE);
 643         CSI2_PRINT_REGISTER(iss, csi2->regs1, DBG_P);
 644         CSI2_PRINT_REGISTER(iss, csi2->regs1, TIMING);
 645         CSI2_PRINT_REGISTER(iss, csi2->regs1, CTX_CTRL1(0));
 646         CSI2_PRINT_REGISTER(iss, csi2->regs1, CTX_CTRL2(0));
 647         CSI2_PRINT_REGISTER(iss, csi2->regs1, CTX_DAT_OFST(0));
 648         CSI2_PRINT_REGISTER(iss, csi2->regs1, CTX_PING_ADDR(0));
 649         CSI2_PRINT_REGISTER(iss, csi2->regs1, CTX_PONG_ADDR(0));
 650         CSI2_PRINT_REGISTER(iss, csi2->regs1, CTX_IRQENABLE(0));
 651         CSI2_PRINT_REGISTER(iss, csi2->regs1, CTX_IRQSTATUS(0));
 652         CSI2_PRINT_REGISTER(iss, csi2->regs1, CTX_CTRL3(0));
 653
 654         dev_dbg(iss->dev, "--------------------------------------------\n");
 655 }
 656
 657 /* -----------------------------------------------------------------------------
 658  * Interrupt handling
 659  */
 660
 661 /*
 662  * csi2_isr_buffer - Does buffer handling at end-of-frame
 663  * when writing to memory.
 664  */
 665 static void csi2_isr_buffer(struct iss_csi2_device *csi2)
 666 {
 667         struct iss_buffer *buffer;
 668
 669         csi2_ctx_enable(csi2, 0, 0);
 670
 671         buffer = omap4iss_video_buffer_next(&csi2->video_out);
 672
 673         /*
 674          * Let video queue operation restart engine if there is an underrun
 675          * condition.
 676          */
 677         if (buffer == NULL)
 678                 return;
 679
 680         csi2_set_outaddr(csi2, buffer->iss_addr);
 681         csi2_ctx_enable(csi2, 0, 1);
 682 }
 683
 684 static void csi2_isr_ctx(struct iss_csi2_device *csi2,
 685                          struct iss_csi2_ctx_cfg *ctx)
 686 {
 687         unsigned int n = ctx->ctxnum;
 688         u32 status;
 689
 690         status = iss_reg_read(csi2->iss, csi2->regs1, CSI2_CTX_IRQSTATUS(n));
 691         iss_reg_write(csi2->iss, csi2->regs1, CSI2_CTX_IRQSTATUS(n), status);
 692
 693         /* Propagate frame number */
 694         if (status & CSI2_CTX_IRQ_FS) {
 695                 struct iss_pipeline *pipe =
 696                                      to_iss_pipeline(&csi2->subdev.entity);
 697                 if (pipe->do_propagation)
 698                         atomic_inc(&pipe->frame_number);
 699         }
 700
 701         if (!(status & CSI2_CTX_IRQ_FE))
 702                 return;
 703
 704         /* Skip interrupts until we reach the frame skip count. The CSI2 will be
 705          * automatically disabled, as the frame skip count has been programmed
 706          * in the CSI2_CTx_CTRL1::COUNT field, so reenable it.
 707          *
 708          * It would have been nice to rely on the FRAME_NUMBER interrupt instead
 709          * but it turned out that the interrupt is only generated when the CSI2
 710          * writes to memory (the CSI2_CTx_CTRL1::COUNT field is decreased
 711          * correctly and reaches 0 when data is forwarded to the video port only
 712          * but no interrupt arrives). Maybe a CSI2 hardware bug.
 713          */
 714         if (csi2->frame_skip) {
 715                 csi2->frame_skip--;
 716                 if (csi2->frame_skip == 0) {
 717                         ctx->format_id = csi2_ctx_map_format(csi2);
 718                         csi2_ctx_config(csi2, ctx);
 719                         csi2_ctx_enable(csi2, n, 1);
 720                 }
 721                 return;
 722         }
 723
 724         if (csi2->output & CSI2_OUTPUT_MEMORY)
 725                 csi2_isr_buffer(csi2);
 726 }
 727
 728 /*
 729  * omap4iss_csi2_isr - CSI2 interrupt handling.
 730  */
 731 void omap4iss_csi2_isr(struct iss_csi2_device *csi2)
 732 {
 733         struct iss_pipeline *pipe = to_iss_pipeline(&csi2->subdev.entity);
 734         u32 csi2_irqstatus, cpxio1_irqstatus;
 735         struct iss_device *iss = csi2->iss;
 736
 737         if (!csi2->available)
 738                 return;
 739
 740         csi2_irqstatus = iss_reg_read(csi2->iss, csi2->regs1, CSI2_IRQSTATUS);
 741         iss_reg_write(csi2->iss, csi2->regs1, CSI2_IRQSTATUS, csi2_irqstatus);
 742
 743         /* Failure Cases */
 744         if (csi2_irqstatus & CSI2_IRQ_COMPLEXIO_ERR) {
 745                 cpxio1_irqstatus = iss_reg_read(csi2->iss, csi2->regs1,
 746                                                 CSI2_COMPLEXIO_IRQSTATUS);
 747                 iss_reg_write(csi2->iss, csi2->regs1, CSI2_COMPLEXIO_IRQSTATUS,
 748                               cpxio1_irqstatus);
 749                 dev_dbg(iss->dev, "CSI2: ComplexIO Error IRQ %x\n",
 750                         cpxio1_irqstatus);
 751                 pipe->error = true;
 752         }
 753
 754         if (csi2_irqstatus & (CSI2_IRQ_OCP_ERR |
 755                               CSI2_IRQ_SHORT_PACKET |
 756                               CSI2_IRQ_ECC_NO_CORRECTION |
 757                               CSI2_IRQ_COMPLEXIO_ERR |
 758                               CSI2_IRQ_FIFO_OVF)) {
 759                 dev_dbg(iss->dev,
 760                         "CSI2 Err: OCP:%d SHORT:%d ECC:%d CPXIO:%d OVF:%d\n",
 761                         csi2_irqstatus & CSI2_IRQ_OCP_ERR ? 1 : 0,
 762                         csi2_irqstatus & CSI2_IRQ_SHORT_PACKET ? 1 : 0,
 763                         csi2_irqstatus & CSI2_IRQ_ECC_NO_CORRECTION ? 1 : 0,
 764                         csi2_irqstatus & CSI2_IRQ_COMPLEXIO_ERR ? 1 : 0,
 765                         csi2_irqstatus & CSI2_IRQ_FIFO_OVF ? 1 : 0);
 766                 pipe->error = true;
 767         }
 768
 769         if (omap4iss_module_sync_is_stopping(&csi2->wait, &csi2->stopping))
 770                 return;
 771
 772         /* Successful cases */
 773         if (csi2_irqstatus & CSI2_IRQ_CONTEXT0)
 774                 csi2_isr_ctx(csi2, &csi2->contexts[0]);
 775
 776         if (csi2_irqstatus & CSI2_IRQ_ECC_CORRECTION)
 777                 dev_dbg(iss->dev, "CSI2: ECC correction done\n");
 778 }
 779
 780 /* -----------------------------------------------------------------------------
 781  * ISS video operations
 782  */
 783
 784 /*
 785  * csi2_queue - Queues the first buffer when using memory output
 786  * @video: The video node
 787  * @buffer: buffer to queue
 788  */
 789 static int csi2_queue(struct iss_video *video, struct iss_buffer *buffer)
 790 {
 791         struct iss_csi2_device *csi2 = container_of(video,
 792                                 struct iss_csi2_device, video_out);
 793
 794         csi2_set_outaddr(csi2, buffer->iss_addr);
 795
 796         /*
 797          * If streaming was enabled before there was a buffer queued
 798          * or underrun happened in the ISR, the hardware was not enabled
 799          * and DMA queue flag ISS_VIDEO_DMAQUEUE_UNDERRUN is still set.
 800          * Enable it now.
 801          */
 802         if (csi2->video_out.dmaqueue_flags & ISS_VIDEO_DMAQUEUE_UNDERRUN) {
 803                 /* Enable / disable context 0 and IRQs */
 804                 csi2_if_enable(csi2, 1);
 805                 csi2_ctx_enable(csi2, 0, 1);
 806                 iss_video_dmaqueue_flags_clr(&csi2->video_out);
 807         }
 808
 809         return 0;
 810 }
 811
 812 static const struct iss_video_operations csi2_issvideo_ops = {
 813         .queue = csi2_queue,
 814 };
 815
 816 /* -----------------------------------------------------------------------------
 817  * V4L2 subdev operations
 818  */
 819
 820 static struct v4l2_mbus_framefmt *
 821 __csi2_get_format(struct iss_csi2_device *csi2, struct v4l2_subdev_fh *fh,
 822                   unsigned int pad, enum v4l2_subdev_format_whence which)
 823 {
 824         if (which == V4L2_SUBDEV_FORMAT_TRY)
 825                 return v4l2_subdev_get_try_format(fh, pad);
 826         else
 827                 return &csi2->formats[pad];
 828 }
 829
 830 static void
 831 csi2_try_format(struct iss_csi2_device *csi2, struct v4l2_subdev_fh *fh,
 832                 unsigned int pad, struct v4l2_mbus_framefmt *fmt,
 833                 enum v4l2_subdev_format_whence which)
 834 {
 835         enum v4l2_mbus_pixelcode pixelcode;
 836         struct v4l2_mbus_framefmt *format;
 837         const struct iss_format_info *info;
 838         unsigned int i;
 839
 840         switch (pad) {
 841         case CSI2_PAD_SINK:
 842                 /* Clamp the width and height to valid range (1-8191). */
 843                 for (i = 0; i < ARRAY_SIZE(csi2_input_fmts); i++) {
 844                         if (fmt->code == csi2_input_fmts[i])
 845                                 break;
 846                 }
 847
 848                 /* If not found, use SGRBG10 as default */
 849                 if (i >= ARRAY_SIZE(csi2_input_fmts))
 850                         fmt->code = V4L2_MBUS_FMT_SGRBG10_1X10;
 851
 852                 fmt->width = clamp_t(u32, fmt->width, 1, 8191);
 853                 fmt->height = clamp_t(u32, fmt->height, 1, 8191);
 854                 break;
 855
 856         case CSI2_PAD_SOURCE:
 857                 /* Source format same as sink format, except for DPCM
 858                  * compression.
 859                  */
 860                 pixelcode = fmt->code;
 861                 format = __csi2_get_format(csi2, fh, CSI2_PAD_SINK, which);
 862                 memcpy(fmt, format, sizeof(*fmt));
 863
 864                 /*
 865                  * Only Allow DPCM decompression, and check that the
 866                  * pattern is preserved
 867                  */
 868                 info = omap4iss_video_format_info(fmt->code);
 869                 if (info->uncompressed == pixelcode)
 870                         fmt->code = pixelcode;
 871                 break;
 872         }
 873
 874         /* RGB, non-interlaced */
 875         fmt->colorspace = V4L2_COLORSPACE_SRGB;
 876         fmt->field = V4L2_FIELD_NONE;
 877 }
 878
 879 /*
 880  * csi2_enum_mbus_code - Handle pixel format enumeration
 881  * @sd     : pointer to v4l2 subdev structure
 882  * @fh     : V4L2 subdev file handle
 883  * @code   : pointer to v4l2_subdev_mbus_code_enum structure
 884  * return -EINVAL or zero on success
 885  */
 886 static int csi2_enum_mbus_code(struct v4l2_subdev *sd,
 887                                struct v4l2_subdev_fh *fh,
 888                                struct v4l2_subdev_mbus_code_enum *code)
 889 {
 890         struct iss_csi2_device *csi2 = v4l2_get_subdevdata(sd);
 891         struct v4l2_mbus_framefmt *format;
 892         const struct iss_format_info *info;
 893
 894         if (code->pad == CSI2_PAD_SINK) {
 895                 if (code->index >= ARRAY_SIZE(csi2_input_fmts))
 896                         return -EINVAL;
 897
 898                 code->code = csi2_input_fmts[code->index];
 899         } else {
 900                 format = __csi2_get_format(csi2, fh, CSI2_PAD_SINK,
 901                                            V4L2_SUBDEV_FORMAT_TRY);
 902                 switch (code->index) {
 903                 case 0:
 904                         /* Passthrough sink pad code */
 905                         code->code = format->code;
 906                         break;
 907                 case 1:
 908                         /* Uncompressed code */
 909                         info = omap4iss_video_format_info(format->code);
 910                         if (info->uncompressed == format->code)
 911                                 return -EINVAL;
 912
 913                         code->code = info->uncompressed;
 914                         break;
 915                 default:
 916                         return -EINVAL;
 917                 }
 918         }
 919
 920         return 0;
 921 }
 922
 923 static int csi2_enum_frame_size(struct v4l2_subdev *sd,
 924                                 struct v4l2_subdev_fh *fh,
 925                                 struct v4l2_subdev_frame_size_enum *fse)
 926 {
 927         struct iss_csi2_device *csi2 = v4l2_get_subdevdata(sd);
 928         struct v4l2_mbus_framefmt format;
 929
 930         if (fse->index != 0)
 931                 return -EINVAL;
 932
 933         format.code = fse->code;
 934         format.width = 1;
 935         format.height = 1;
 936         csi2_try_format(csi2, fh, fse->pad, &format, V4L2_SUBDEV_FORMAT_TRY);
 937         fse->min_width = format.width;
 938         fse->min_height = format.height;
 939
 940         if (format.code != fse->code)
 941                 return -EINVAL;
 942
 943         format.code = fse->code;
 944         format.width = -1;
 945         format.height = -1;
 946         csi2_try_format(csi2, fh, fse->pad, &format, V4L2_SUBDEV_FORMAT_TRY);
 947         fse->max_width = format.width;
 948         fse->max_height = format.height;
 949
 950         return 0;
 951 }
 952
 953 /*
 954  * csi2_get_format - Handle get format by pads subdev method
 955  * @sd : pointer to v4l2 subdev structure
 956  * @fh : V4L2 subdev file handle
 957  * @fmt: pointer to v4l2 subdev format structure
 958  * return -EINVAL or zero on success
 959  */
 960 static int csi2_get_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
 961                            struct v4l2_subdev_format *fmt)
 962 {
 963         struct iss_csi2_device *csi2 = v4l2_get_subdevdata(sd);
 964         struct v4l2_mbus_framefmt *format;
 965
 966         format = __csi2_get_format(csi2, fh, fmt->pad, fmt->which);
 967         if (format == NULL)
 968                 return -EINVAL;
 969
 970         fmt->format = *format;
 971         return 0;
 972 }
 973
 974 /*
 975  * csi2_set_format - Handle set format by pads subdev method
 976  * @sd : pointer to v4l2 subdev structure
 977  * @fh : V4L2 subdev file handle
 978  * @fmt: pointer to v4l2 subdev format structure
 979  * return -EINVAL or zero on success
 980  */
 981 static int csi2_set_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
 982                            struct v4l2_subdev_format *fmt)
 983 {
 984         struct iss_csi2_device *csi2 = v4l2_get_subdevdata(sd);
 985         struct v4l2_mbus_framefmt *format;
 986
 987         format = __csi2_get_format(csi2, fh, fmt->pad, fmt->which);
 988         if (format == NULL)
 989                 return -EINVAL;
 990
 991         csi2_try_format(csi2, fh, fmt->pad, &fmt->format, fmt->which);
 992         *format = fmt->format;
 993
 994         /* Propagate the format from sink to source */
 995         if (fmt->pad == CSI2_PAD_SINK) {
 996                 format = __csi2_get_format(csi2, fh, CSI2_PAD_SOURCE,
 997                                            fmt->which);
 998                 *format = fmt->format;
 999                 csi2_try_format(csi2, fh, CSI2_PAD_SOURCE, format, fmt->which);
1000         }
1001
1002         return 0;
1003 }
1004
1005 static int csi2_link_validate(struct v4l2_subdev *sd, struct media_link *link,
1006                               struct v4l2_subdev_format *source_fmt,
1007                               struct v4l2_subdev_format *sink_fmt)
1008 {
1009         struct iss_csi2_device *csi2 = v4l2_get_subdevdata(sd);
1010         struct iss_pipeline *pipe = to_iss_pipeline(&csi2->subdev.entity);
1011         int rval;
1012
1013         pipe->external = media_entity_to_v4l2_subdev(link->source->entity);
1014         rval = omap4iss_get_external_info(pipe, link);
1015         if (rval < 0)
1016                 return rval;
1017
1018         return v4l2_subdev_link_validate_default(sd, link, source_fmt,
1019                                                  sink_fmt);
1020 }
1021
1022 /*
1023  * csi2_init_formats - Initialize formats on all pads
1024  * @sd: ISS CSI2 V4L2 subdevice
1025  * @fh: V4L2 subdev file handle
1026  *
1027  * Initialize all pad formats with default values. If fh is not NULL, try
1028  * formats are initialized on the file handle. Otherwise active formats are
1029  * initialized on the device.
1030  */
1031 static int csi2_init_formats(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1032 {
1033         struct v4l2_subdev_format format;
1034
1035         memset(&format, 0, sizeof(format));
1036         format.pad = CSI2_PAD_SINK;
1037         format.which = fh ? V4L2_SUBDEV_FORMAT_TRY : V4L2_SUBDEV_FORMAT_ACTIVE;
1038         format.format.code = V4L2_MBUS_FMT_SGRBG10_1X10;
1039         format.format.width = 4096;
1040         format.format.height = 4096;
1041         csi2_set_format(sd, fh, &format);
1042
1043         return 0;
1044 }
1045
1046 /*
1047  * csi2_set_stream - Enable/Disable streaming on the CSI2 module
1048  * @sd: ISS CSI2 V4L2 subdevice
1049  * @enable: ISS pipeline stream state
1050  *
1051  * Return 0 on success or a negative error code otherwise.
1052  */
1053 static int csi2_set_stream(struct v4l2_subdev *sd, int enable)
1054 {
1055         struct iss_csi2_device *csi2 = v4l2_get_subdevdata(sd);
1056         struct iss_device *iss = csi2->iss;
1057         struct iss_pipeline *pipe = to_iss_pipeline(&csi2->subdev.entity);
1058         struct iss_video *video_out = &csi2->video_out;
1059         int ret = 0;
1060
1061         if (csi2->state == ISS_PIPELINE_STREAM_STOPPED) {
1062                 if (enable == ISS_PIPELINE_STREAM_STOPPED)
1063                         return 0;
1064
1065                 omap4iss_subclk_enable(iss, csi2->subclk);
1066         }
1067
1068         switch (enable) {
1069         case ISS_PIPELINE_STREAM_CONTINUOUS: {
1070                 ret = omap4iss_csiphy_config(iss, sd);
1071                 if (ret < 0)
1072                         return ret;
1073
1074                 if (omap4iss_csiphy_acquire(csi2->phy) < 0)
1075                         return -ENODEV;
1076                 csi2->use_fs_irq = pipe->do_propagation;
1077                 csi2_configure(csi2);
1078                 csi2_print_status(csi2);
1079
1080                 /*
1081                  * When outputting to memory with no buffer available, let the
1082                  * buffer queue handler start the hardware. A DMA queue flag
1083                  * ISS_VIDEO_DMAQUEUE_QUEUED will be set as soon as there is
1084                  * a buffer available.
1085                  */
1086                 if (csi2->output & CSI2_OUTPUT_MEMORY &&
1087                     !(video_out->dmaqueue_flags & ISS_VIDEO_DMAQUEUE_QUEUED))
1088                         break;
1089                 /* Enable context 0 and IRQs */
1090                 atomic_set(&csi2->stopping, 0);
1091                 csi2_ctx_enable(csi2, 0, 1);
1092                 csi2_if_enable(csi2, 1);
1093                 iss_video_dmaqueue_flags_clr(video_out);
1094                 break;
1095         }
1096         case ISS_PIPELINE_STREAM_STOPPED:
1097                 if (csi2->state == ISS_PIPELINE_STREAM_STOPPED)
1098                         return 0;
1099                 if (omap4iss_module_sync_idle(&sd->entity, &csi2->wait,
1100                                               &csi2->stopping))
1101                         ret = -ETIMEDOUT;
1102                 csi2_ctx_enable(csi2, 0, 0);
1103                 csi2_if_enable(csi2, 0);
1104                 csi2_irq_ctx_set(csi2, 0);
1105                 omap4iss_csiphy_release(csi2->phy);
1106                 omap4iss_subclk_disable(iss, csi2->subclk);
1107                 iss_video_dmaqueue_flags_clr(video_out);
1108                 break;
1109         }
1110
1111         csi2->state = enable;
1112         return ret;
1113 }
1114
1115 /* subdev video operations */
1116 static const struct v4l2_subdev_video_ops csi2_video_ops = {
1117         .s_stream = csi2_set_stream,
1118 };
1119
1120 /* subdev pad operations */
1121 static const struct v4l2_subdev_pad_ops csi2_pad_ops = {
1122         .enum_mbus_code = csi2_enum_mbus_code,
1123         .enum_frame_size = csi2_enum_frame_size,
1124         .get_fmt = csi2_get_format,
1125         .set_fmt = csi2_set_format,
1126         .link_validate = csi2_link_validate,
1127 };
1128
1129 /* subdev operations */
1130 static const struct v4l2_subdev_ops csi2_ops = {
1131         .video = &csi2_video_ops,
1132         .pad = &csi2_pad_ops,
1133 };
1134
1135 /* subdev internal operations */
1136 static const struct v4l2_subdev_internal_ops csi2_internal_ops = {
1137         .open = csi2_init_formats,
1138 };
1139
1140 /* -----------------------------------------------------------------------------
1141  * Media entity operations
1142  */
1143
1144 /*
1145  * csi2_link_setup - Setup CSI2 connections.
1146  * @entity : Pointer to media entity structure
1147  * @local  : Pointer to local pad array
1148  * @remote : Pointer to remote pad array
1149  * @flags  : Link flags
1150  * return -EINVAL or zero on success
1151  */
1152 static int csi2_link_setup(struct media_entity *entity,
1153                            const struct media_pad *local,
1154                            const struct media_pad *remote, u32 flags)
1155 {
1156         struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
1157         struct iss_csi2_device *csi2 = v4l2_get_subdevdata(sd);
1158         struct iss_csi2_ctrl_cfg *ctrl = &csi2->ctrl;
1159
1160         /*
1161          * The ISS core doesn't support pipelines with multiple video outputs.
1162          * Revisit this when it will be implemented, and return -EBUSY for now.
1163          */
1164
1165         switch (local->index | media_entity_type(remote->entity)) {
1166         case CSI2_PAD_SOURCE | MEDIA_ENT_T_DEVNODE:
1167                 if (flags & MEDIA_LNK_FL_ENABLED) {
1168                         if (csi2->output & ~CSI2_OUTPUT_MEMORY)
1169                                 return -EBUSY;
1170                         csi2->output |= CSI2_OUTPUT_MEMORY;
1171                 } else {
1172                         csi2->output &= ~CSI2_OUTPUT_MEMORY;
1173                 }
1174                 break;
1175
1176         case CSI2_PAD_SOURCE | MEDIA_ENT_T_V4L2_SUBDEV:
1177                 if (flags & MEDIA_LNK_FL_ENABLED) {
1178                         if (csi2->output & ~CSI2_OUTPUT_IPIPEIF)
1179                                 return -EBUSY;
1180                         csi2->output |= CSI2_OUTPUT_IPIPEIF;
1181                 } else {
1182                         csi2->output &= ~CSI2_OUTPUT_IPIPEIF;
1183                 }
1184                 break;
1185
1186         default:
1187                 /* Link from camera to CSI2 is fixed... */
1188                 return -EINVAL;
1189         }
1190
1191         ctrl->vp_only_enable = csi2->output & CSI2_OUTPUT_MEMORY ? false : true;
1192         ctrl->vp_clk_enable = !!(csi2->output & CSI2_OUTPUT_IPIPEIF);
1193
1194         return 0;
1195 }
1196
1197 /* media operations */
1198 static const struct media_entity_operations csi2_media_ops = {
1199         .link_setup = csi2_link_setup,
1200         .link_validate = v4l2_subdev_link_validate,
1201 };
1202
1203 void omap4iss_csi2_unregister_entities(struct iss_csi2_device *csi2)
1204 {
1205         v4l2_device_unregister_subdev(&csi2->subdev);
1206         omap4iss_video_unregister(&csi2->video_out);
1207 }
1208
1209 int omap4iss_csi2_register_entities(struct iss_csi2_device *csi2,
1210                                     struct v4l2_device *vdev)
1211 {
1212         int ret;
1213
1214         /* Register the subdev and video nodes. */
1215         ret = v4l2_device_register_subdev(vdev, &csi2->subdev);
1216         if (ret < 0)
1217                 goto error;
1218
1219         ret = omap4iss_video_register(&csi2->video_out, vdev);
1220         if (ret < 0)
1221                 goto error;
1222
1223         return 0;
1224
1225 error:
1226         omap4iss_csi2_unregister_entities(csi2);
1227         return ret;
1228 }
1229
1230 /* -----------------------------------------------------------------------------
1231  * ISS CSI2 initialisation and cleanup
1232  */
1233
1234 /*
1235  * csi2_init_entities - Initialize subdev and media entity.
1236  * @csi2: Pointer to csi2 structure.
1237  * return -ENOMEM or zero on success
1238  */
1239 static int csi2_init_entities(struct iss_csi2_device *csi2, const char *subname)
1240 {
1241         struct v4l2_subdev *sd = &csi2->subdev;
1242         struct media_pad *pads = csi2->pads;
1243         struct media_entity *me = &sd->entity;
1244         int ret;
1245         char name[V4L2_SUBDEV_NAME_SIZE];
1246
1247         v4l2_subdev_init(sd, &csi2_ops);
1248         sd->internal_ops = &csi2_internal_ops;
1249         sprintf(name, "CSI2%s", subname);
1250         snprintf(sd->name, sizeof(sd->name), "OMAP4 ISS %s", name);
1251
1252         sd->grp_id = 1 << 16;   /* group ID for iss subdevs */
1253         v4l2_set_subdevdata(sd, csi2);
1254         sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1255
1256         pads[CSI2_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
1257         pads[CSI2_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
1258
1259         me->ops = &csi2_media_ops;
1260         ret = media_entity_init(me, CSI2_PADS_NUM, pads, 0);
1261         if (ret < 0)
1262                 return ret;
1263
1264         csi2_init_formats(sd, NULL);
1265
1266         /* Video device node */
1267         csi2->video_out.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1268         csi2->video_out.ops = &csi2_issvideo_ops;
1269         csi2->video_out.bpl_alignment = 32;
1270         csi2->video_out.bpl_zero_padding = 1;
1271         csi2->video_out.bpl_max = 0x1ffe0;
1272         csi2->video_out.iss = csi2->iss;
1273         csi2->video_out.capture_mem = PAGE_ALIGN(4096 * 4096) * 3;
1274
1275         ret = omap4iss_video_init(&csi2->video_out, name);
1276         if (ret < 0)
1277                 goto error_video;
1278
1279         /* Connect the CSI2 subdev to the video node. */
1280         ret = media_entity_create_link(&csi2->subdev.entity, CSI2_PAD_SOURCE,
1281                                        &csi2->video_out.video.entity, 0, 0);
1282         if (ret < 0)
1283                 goto error_link;
1284
1285         return 0;
1286
1287 error_link:
1288         omap4iss_video_cleanup(&csi2->video_out);
1289 error_video:
1290         media_entity_cleanup(&csi2->subdev.entity);
1291         return ret;
1292 }
1293
1294 /*
1295  * omap4iss_csi2_init - Routine for module driver init
1296  */
1297 int omap4iss_csi2_init(struct iss_device *iss)
1298 {
1299         struct iss_csi2_device *csi2a = &iss->csi2a;
1300         struct iss_csi2_device *csi2b = &iss->csi2b;
1301         int ret;
1302
1303         csi2a->iss = iss;
1304         csi2a->available = 1;
1305         csi2a->regs1 = OMAP4_ISS_MEM_CSI2_A_REGS1;
1306         csi2a->phy = &iss->csiphy1;
1307         csi2a->subclk = OMAP4_ISS_SUBCLK_CSI2_A;
1308         csi2a->state = ISS_PIPELINE_STREAM_STOPPED;
1309         init_waitqueue_head(&csi2a->wait);
1310
1311         ret = csi2_init_entities(csi2a, "a");
1312         if (ret < 0)
1313                 return ret;
1314
1315         csi2b->iss = iss;
1316         csi2b->available = 1;
1317         csi2b->regs1 = OMAP4_ISS_MEM_CSI2_B_REGS1;
1318         csi2b->phy = &iss->csiphy2;
1319         csi2b->subclk = OMAP4_ISS_SUBCLK_CSI2_B;
1320         csi2b->state = ISS_PIPELINE_STREAM_STOPPED;
1321         init_waitqueue_head(&csi2b->wait);
1322
1323         ret = csi2_init_entities(csi2b, "b");
1324         if (ret < 0)
1325                 return ret;
1326
1327         return 0;
1328 }
1329
1330 /*
1331  * omap4iss_csi2_cleanup - Routine for module driver cleanup
1332  */
1333 void omap4iss_csi2_cleanup(struct iss_device *iss)
1334 {
1335         struct iss_csi2_device *csi2a = &iss->csi2a;
1336         struct iss_csi2_device *csi2b = &iss->csi2b;
1337
1338         omap4iss_video_cleanup(&csi2a->video_out);
1339         media_entity_cleanup(&csi2a->subdev.entity);
1340
1341         omap4iss_video_cleanup(&csi2b->video_out);
1342         media_entity_cleanup(&csi2b->subdev.entity);
1343 }