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44 * Configuration and status register (CSR) type definitions for
47 * This file is auto generated. Do not edit.
52 #ifndef __CVMX_USBCX_TYPEDEFS_H__
53 #define __CVMX_USBCX_TYPEDEFS_H__
55 #define CVMX_USBCX_DAINT(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000818ull) + ((block_id) & 1) * 0x100000000000ull)
56 #define CVMX_USBCX_DAINTMSK(block_id) (CVMX_ADD_IO_SEG(0x00016F001000081Cull) + ((block_id) & 1) * 0x100000000000ull)
57 #define CVMX_USBCX_DCFG(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000800ull) + ((block_id) & 1) * 0x100000000000ull)
58 #define CVMX_USBCX_DCTL(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000804ull) + ((block_id) & 1) * 0x100000000000ull)
59 #define CVMX_USBCX_DIEPCTLX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000900ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32)
60 #define CVMX_USBCX_DIEPINTX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000908ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32)
61 #define CVMX_USBCX_DIEPMSK(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000810ull) + ((block_id) & 1) * 0x100000000000ull)
62 #define CVMX_USBCX_DIEPTSIZX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000910ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32)
63 #define CVMX_USBCX_DOEPCTLX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000B00ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32)
64 #define CVMX_USBCX_DOEPINTX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000B08ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32)
65 #define CVMX_USBCX_DOEPMSK(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000814ull) + ((block_id) & 1) * 0x100000000000ull)
66 #define CVMX_USBCX_DOEPTSIZX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000B10ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32)
67 #define CVMX_USBCX_DPTXFSIZX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000100ull) + (((offset) & 7) + ((block_id) & 1) * 0x40000000000ull) * 4)
68 #define CVMX_USBCX_DSTS(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000808ull) + ((block_id) & 1) * 0x100000000000ull)
69 #define CVMX_USBCX_DTKNQR1(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000820ull) + ((block_id) & 1) * 0x100000000000ull)
70 #define CVMX_USBCX_DTKNQR2(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000824ull) + ((block_id) & 1) * 0x100000000000ull)
71 #define CVMX_USBCX_DTKNQR3(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000830ull) + ((block_id) & 1) * 0x100000000000ull)
72 #define CVMX_USBCX_DTKNQR4(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000834ull) + ((block_id) & 1) * 0x100000000000ull)
73 #define CVMX_USBCX_GAHBCFG(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000008ull) + ((block_id) & 1) * 0x100000000000ull)
74 #define CVMX_USBCX_GHWCFG1(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000044ull) + ((block_id) & 1) * 0x100000000000ull)
75 #define CVMX_USBCX_GHWCFG2(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000048ull) + ((block_id) & 1) * 0x100000000000ull)
76 #define CVMX_USBCX_GHWCFG3(block_id) (CVMX_ADD_IO_SEG(0x00016F001000004Cull) + ((block_id) & 1) * 0x100000000000ull)
77 #define CVMX_USBCX_GHWCFG4(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000050ull) + ((block_id) & 1) * 0x100000000000ull)
78 #define CVMX_USBCX_GINTMSK(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000018ull) + ((block_id) & 1) * 0x100000000000ull)
79 #define CVMX_USBCX_GINTSTS(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000014ull) + ((block_id) & 1) * 0x100000000000ull)
80 #define CVMX_USBCX_GNPTXFSIZ(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000028ull) + ((block_id) & 1) * 0x100000000000ull)
81 #define CVMX_USBCX_GNPTXSTS(block_id) (CVMX_ADD_IO_SEG(0x00016F001000002Cull) + ((block_id) & 1) * 0x100000000000ull)
82 #define CVMX_USBCX_GOTGCTL(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000000ull) + ((block_id) & 1) * 0x100000000000ull)
83 #define CVMX_USBCX_GOTGINT(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000004ull) + ((block_id) & 1) * 0x100000000000ull)
84 #define CVMX_USBCX_GRSTCTL(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000010ull) + ((block_id) & 1) * 0x100000000000ull)
85 #define CVMX_USBCX_GRXFSIZ(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000024ull) + ((block_id) & 1) * 0x100000000000ull)
86 #define CVMX_USBCX_GRXSTSPD(block_id) (CVMX_ADD_IO_SEG(0x00016F0010040020ull) + ((block_id) & 1) * 0x100000000000ull)
87 #define CVMX_USBCX_GRXSTSPH(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000020ull) + ((block_id) & 1) * 0x100000000000ull)
88 #define CVMX_USBCX_GRXSTSRD(block_id) (CVMX_ADD_IO_SEG(0x00016F001004001Cull) + ((block_id) & 1) * 0x100000000000ull)
89 #define CVMX_USBCX_GRXSTSRH(block_id) (CVMX_ADD_IO_SEG(0x00016F001000001Cull) + ((block_id) & 1) * 0x100000000000ull)
90 #define CVMX_USBCX_GSNPSID(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000040ull) + ((block_id) & 1) * 0x100000000000ull)
91 #define CVMX_USBCX_GUSBCFG(block_id) (CVMX_ADD_IO_SEG(0x00016F001000000Cull) + ((block_id) & 1) * 0x100000000000ull)
92 #define CVMX_USBCX_HAINT(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000414ull) + ((block_id) & 1) * 0x100000000000ull)
93 #define CVMX_USBCX_HAINTMSK(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000418ull) + ((block_id) & 1) * 0x100000000000ull)
94 #define CVMX_USBCX_HCCHARX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000500ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32)
95 #define CVMX_USBCX_HCFG(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000400ull) + ((block_id) & 1) * 0x100000000000ull)
96 #define CVMX_USBCX_HCINTMSKX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F001000050Cull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32)
97 #define CVMX_USBCX_HCINTX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000508ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32)
98 #define CVMX_USBCX_HCSPLTX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000504ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32)
99 #define CVMX_USBCX_HCTSIZX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000510ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32)
100 #define CVMX_USBCX_HFIR(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000404ull) + ((block_id) & 1) * 0x100000000000ull)
101 #define CVMX_USBCX_HFNUM(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000408ull) + ((block_id) & 1) * 0x100000000000ull)
102 #define CVMX_USBCX_HPRT(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000440ull) + ((block_id) & 1) * 0x100000000000ull)
103 #define CVMX_USBCX_HPTXFSIZ(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000100ull) + ((block_id) & 1) * 0x100000000000ull)
104 #define CVMX_USBCX_HPTXSTS(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000410ull) + ((block_id) & 1) * 0x100000000000ull)
105 #define CVMX_USBCX_NPTXDFIFOX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010001000ull) + (((offset) & 7) + ((block_id) & 1) * 0x100000000ull) * 4096)
106 #define CVMX_USBCX_PCGCCTL(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000E00ull) + ((block_id) & 1) * 0x100000000000ull)
111 * Device All Endpoints Interrupt Register (DAINT)
113 * When a significant event occurs on an endpoint, a Device All Endpoints Interrupt register
114 * interrupts the application using the Device OUT Endpoints Interrupt bit or Device IN Endpoints
115 * Interrupt bit of the Core Interrupt register (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively).
116 * There is one interrupt bit per endpoint, up to a maximum of 16 bits for OUT endpoints and 16
117 * bits for IN endpoints. For a bidirectional endpoint, the corresponding IN and OUT interrupt
118 * bits are used. Bits in this register are set and cleared when the application sets and clears
119 * bits in the corresponding Device Endpoint-n Interrupt register (DIEPINTn/DOEPINTn).
121 union cvmx_usbcx_daint
124 struct cvmx_usbcx_daint_s
126 uint32_t outepint : 16; /**< OUT Endpoint Interrupt Bits (OutEPInt)
127 One bit per OUT endpoint:
128 Bit 16 for OUT endpoint 0, bit 31 for OUT endpoint 15 */
129 uint32_t inepint : 16; /**< IN Endpoint Interrupt Bits (InEpInt)
130 One bit per IN Endpoint:
131 Bit 0 for IN endpoint 0, bit 15 for endpoint 15 */
133 struct cvmx_usbcx_daint_s cn30xx;
134 struct cvmx_usbcx_daint_s cn31xx;
135 struct cvmx_usbcx_daint_s cn50xx;
136 struct cvmx_usbcx_daint_s cn52xx;
137 struct cvmx_usbcx_daint_s cn52xxp1;
138 struct cvmx_usbcx_daint_s cn56xx;
139 struct cvmx_usbcx_daint_s cn56xxp1;
141 typedef union cvmx_usbcx_daint cvmx_usbcx_daint_t;
144 * cvmx_usbc#_daintmsk
146 * Device All Endpoints Interrupt Mask Register (DAINTMSK)
148 * The Device Endpoint Interrupt Mask register works with the Device Endpoint Interrupt register
149 * to interrupt the application when an event occurs on a device endpoint. However, the Device
150 * All Endpoints Interrupt (DAINT) register bit corresponding to that interrupt will still be set.
151 * Mask Interrupt: 1'b0 Unmask Interrupt: 1'b1
153 union cvmx_usbcx_daintmsk
156 struct cvmx_usbcx_daintmsk_s
158 uint32_t outepmsk : 16; /**< OUT EP Interrupt Mask Bits (OutEpMsk)
159 One per OUT Endpoint:
160 Bit 16 for OUT EP 0, bit 31 for OUT EP 15 */
161 uint32_t inepmsk : 16; /**< IN EP Interrupt Mask Bits (InEpMsk)
162 One bit per IN Endpoint:
163 Bit 0 for IN EP 0, bit 15 for IN EP 15 */
165 struct cvmx_usbcx_daintmsk_s cn30xx;
166 struct cvmx_usbcx_daintmsk_s cn31xx;
167 struct cvmx_usbcx_daintmsk_s cn50xx;
168 struct cvmx_usbcx_daintmsk_s cn52xx;
169 struct cvmx_usbcx_daintmsk_s cn52xxp1;
170 struct cvmx_usbcx_daintmsk_s cn56xx;
171 struct cvmx_usbcx_daintmsk_s cn56xxp1;
173 typedef union cvmx_usbcx_daintmsk cvmx_usbcx_daintmsk_t;
178 * Device Configuration Register (DCFG)
180 * This register configures the core in Device mode after power-on or after certain control
181 * commands or enumeration. Do not make changes to this register after initial programming.
183 union cvmx_usbcx_dcfg
186 struct cvmx_usbcx_dcfg_s
188 uint32_t reserved_23_31 : 9;
189 uint32_t epmiscnt : 5; /**< IN Endpoint Mismatch Count (EPMisCnt)
190 The application programs this filed with a count that determines
191 when the core generates an Endpoint Mismatch interrupt
192 (GINTSTS.EPMis). The core loads this value into an internal
193 counter and decrements it. The counter is reloaded whenever
194 there is a match or when the counter expires. The width of this
195 counter depends on the depth of the Token Queue. */
196 uint32_t reserved_13_17 : 5;
197 uint32_t perfrint : 2; /**< Periodic Frame Interval (PerFrInt)
198 Indicates the time within a (micro)frame at which the application
199 must be notified using the End Of Periodic Frame Interrupt. This
200 can be used to determine if all the isochronous traffic for that
201 (micro)frame is complete.
202 * 2'b00: 80% of the (micro)frame interval
206 uint32_t devaddr : 7; /**< Device Address (DevAddr)
207 The application must program this field after every SetAddress
209 uint32_t reserved_3_3 : 1;
210 uint32_t nzstsouthshk : 1; /**< Non-Zero-Length Status OUT Handshake (NZStsOUTHShk)
211 The application can use this field to select the handshake the
212 core sends on receiving a nonzero-length data packet during
213 the OUT transaction of a control transfer's Status stage.
214 * 1'b1: Send a STALL handshake on a nonzero-length status
215 OUT transaction and do not send the received OUT packet to
217 * 1'b0: Send the received OUT packet to the application (zero-
218 length or nonzero-length) and send a handshake based on
219 the NAK and STALL bits for the endpoint in the Device
220 Endpoint Control register. */
221 uint32_t devspd : 2; /**< Device Speed (DevSpd)
222 Indicates the speed at which the application requires the core to
223 enumerate, or the maximum speed the application can support.
224 However, the actual bus speed is determined only after the
225 chirp sequence is completed, and is based on the speed of the
226 USB host to which the core is connected. See "Device
227 Initialization" on page 249 for details.
228 * 2'b00: High speed (USB 2.0 PHY clock is 30 MHz or 60 MHz)
229 * 2'b01: Full speed (USB 2.0 PHY clock is 30 MHz or 60 MHz)
230 * 2'b10: Low speed (USB 1.1 transceiver clock is 6 MHz). If
231 you select 6 MHz LS mode, you must do a soft reset.
232 * 2'b11: Full speed (USB 1.1 transceiver clock is 48 MHz) */
234 struct cvmx_usbcx_dcfg_s cn30xx;
235 struct cvmx_usbcx_dcfg_s cn31xx;
236 struct cvmx_usbcx_dcfg_s cn50xx;
237 struct cvmx_usbcx_dcfg_s cn52xx;
238 struct cvmx_usbcx_dcfg_s cn52xxp1;
239 struct cvmx_usbcx_dcfg_s cn56xx;
240 struct cvmx_usbcx_dcfg_s cn56xxp1;
242 typedef union cvmx_usbcx_dcfg cvmx_usbcx_dcfg_t;
247 * Device Control Register (DCTL)
250 union cvmx_usbcx_dctl
253 struct cvmx_usbcx_dctl_s
255 uint32_t reserved_12_31 : 20;
256 uint32_t pwronprgdone : 1; /**< Power-On Programming Done (PWROnPrgDone)
257 The application uses this bit to indicate that register
258 programming is completed after a wake-up from Power Down
259 mode. For more information, see "Device Mode Suspend and
260 Resume With Partial Power-Down" on page 357. */
261 uint32_t cgoutnak : 1; /**< Clear Global OUT NAK (CGOUTNak)
262 A write to this field clears the Global OUT NAK. */
263 uint32_t sgoutnak : 1; /**< Set Global OUT NAK (SGOUTNak)
264 A write to this field sets the Global OUT NAK.
265 The application uses this bit to send a NAK handshake on all
267 The application should set the this bit only after making sure
268 that the Global OUT NAK Effective bit in the Core Interrupt
269 Register (GINTSTS.GOUTNakEff) is cleared. */
270 uint32_t cgnpinnak : 1; /**< Clear Global Non-Periodic IN NAK (CGNPInNak)
271 A write to this field clears the Global Non-Periodic IN NAK. */
272 uint32_t sgnpinnak : 1; /**< Set Global Non-Periodic IN NAK (SGNPInNak)
273 A write to this field sets the Global Non-Periodic IN NAK.The
274 application uses this bit to send a NAK handshake on all non-
275 periodic IN endpoints. The core can also set this bit when a
276 timeout condition is detected on a non-periodic endpoint.
277 The application should set this bit only after making sure that
278 the Global IN NAK Effective bit in the Core Interrupt Register
279 (GINTSTS.GINNakEff) is cleared. */
280 uint32_t tstctl : 3; /**< Test Control (TstCtl)
281 * 3'b000: Test mode disabled
282 * 3'b001: Test_J mode
283 * 3'b010: Test_K mode
284 * 3'b011: Test_SE0_NAK mode
285 * 3'b100: Test_Packet mode
286 * 3'b101: Test_Force_Enable
287 * Others: Reserved */
288 uint32_t goutnaksts : 1; /**< Global OUT NAK Status (GOUTNakSts)
289 * 1'b0: A handshake is sent based on the FIFO Status and the
290 NAK and STALL bit settings.
291 * 1'b1: No data is written to the RxFIFO, irrespective of space
292 availability. Sends a NAK handshake on all packets, except
293 on SETUP transactions. All isochronous OUT packets are
295 uint32_t gnpinnaksts : 1; /**< Global Non-Periodic IN NAK Status (GNPINNakSts)
296 * 1'b0: A handshake is sent out based on the data availability
297 in the transmit FIFO.
298 * 1'b1: A NAK handshake is sent out on all non-periodic IN
299 endpoints, irrespective of the data availability in the transmit
301 uint32_t sftdiscon : 1; /**< Soft Disconnect (SftDiscon)
302 The application uses this bit to signal the O2P USB core to do a
303 soft disconnect. As long as this bit is set, the host will not see
304 that the device is connected, and the device will not receive
305 signals on the USB. The core stays in the disconnected state
306 until the application clears this bit.
307 The minimum duration for which the core must keep this bit set
308 is specified in Minimum Duration for Soft Disconnect .
309 * 1'b0: Normal operation. When this bit is cleared after a soft
310 disconnect, the core drives the phy_opmode_o signal on the
311 UTMI+ to 2'b00, which generates a device connect event to
312 the USB host. When the device is reconnected, the USB host
313 restarts device enumeration.
314 * 1'b1: The core drives the phy_opmode_o signal on the
315 UTMI+ to 2'b01, which generates a device disconnect event
317 uint32_t rmtwkupsig : 1; /**< Remote Wakeup Signaling (RmtWkUpSig)
318 When the application sets this bit, the core initiates remote
319 signaling to wake up the USB host.The application must set this
320 bit to get the core out of Suspended state and must clear this bit
321 after the core comes out of Suspended state. */
323 struct cvmx_usbcx_dctl_s cn30xx;
324 struct cvmx_usbcx_dctl_s cn31xx;
325 struct cvmx_usbcx_dctl_s cn50xx;
326 struct cvmx_usbcx_dctl_s cn52xx;
327 struct cvmx_usbcx_dctl_s cn52xxp1;
328 struct cvmx_usbcx_dctl_s cn56xx;
329 struct cvmx_usbcx_dctl_s cn56xxp1;
331 typedef union cvmx_usbcx_dctl cvmx_usbcx_dctl_t;
334 * cvmx_usbc#_diepctl#
336 * Device IN Endpoint-n Control Register (DIEPCTLn)
338 * The application uses the register to control the behaviour of each logical endpoint other than endpoint 0.
340 union cvmx_usbcx_diepctlx
343 struct cvmx_usbcx_diepctlx_s
345 uint32_t epena : 1; /**< Endpoint Enable (EPEna)
346 Indicates that data is ready to be transmitted on the endpoint.
347 The core clears this bit before setting any of the following
348 interrupts on this endpoint:
350 * Transfer Completed */
351 uint32_t epdis : 1; /**< Endpoint Disable (EPDis)
352 The application sets this bit to stop transmitting data on an
353 endpoint, even before the transfer for that endpoint is complete.
354 The application must wait for the Endpoint Disabled interrupt
355 before treating the endpoint as disabled. The core clears this bit
356 before setting the Endpoint Disabled Interrupt. The application
357 should set this bit only if Endpoint Enable is already set for this
359 uint32_t setd1pid : 1; /**< For Interrupt/BULK enpoints:
360 Set DATA1 PID (SetD1PID)
361 Writing to this field sets the Endpoint Data Pid (DPID) field in
362 this register to DATA1.
363 For Isochronous endpoints:
364 Set Odd (micro)frame (SetOddFr)
365 Writing to this field sets the Even/Odd (micro)frame (EO_FrNum)
366 field to odd (micro)frame. */
367 uint32_t setd0pid : 1; /**< For Interrupt/BULK enpoints:
368 Writing to this field sets the Endpoint Data Pid (DPID) field in
369 this register to DATA0.
370 For Isochronous endpoints:
371 Set Odd (micro)frame (SetEvenFr)
372 Writing to this field sets the Even/Odd (micro)frame (EO_FrNum)
373 field to even (micro)frame. */
374 uint32_t snak : 1; /**< Set NAK (SNAK)
375 A write to this bit sets the NAK bit for the endpoint.
376 Using this bit, the application can control the transmission of
377 NAK handshakes on an endpoint. The core can also set this bit
378 for an endpoint after a SETUP packet is received on the
380 uint32_t cnak : 1; /**< Clear NAK (CNAK)
381 A write to this bit clears the NAK bit for the endpoint. */
382 uint32_t txfnum : 4; /**< TxFIFO Number (TxFNum)
383 Non-periodic endpoints must set this bit to zero. Periodic
384 endpoints must map this to the corresponding Periodic TxFIFO
386 * 4'h0: Non-Periodic TxFIFO
387 * Others: Specified Periodic TxFIFO number */
388 uint32_t stall : 1; /**< STALL Handshake (Stall)
389 For non-control, non-isochronous endpoints:
390 The application sets this bit to stall all tokens from the USB host
391 to this endpoint. If a NAK bit, Global Non-Periodic IN NAK, or
392 Global OUT NAK is set along with this bit, the STALL bit takes
393 priority. Only the application can clear this bit, never the core.
394 For control endpoints:
395 The application can only set this bit, and the core clears it, when
396 a SETUP token i received for this endpoint. If a NAK bit, Global
397 Non-Periodic IN NAK, or Global OUT NAK is set along with this
398 bit, the STALL bit takes priority. Irrespective of this bit's setting,
399 the core always responds to SETUP data packets with an ACK handshake. */
400 uint32_t reserved_20_20 : 1;
401 uint32_t eptype : 2; /**< Endpoint Type (EPType)
402 This is the transfer type supported by this logical endpoint.
406 * 2'b11: Interrupt */
407 uint32_t naksts : 1; /**< NAK Status (NAKSts)
408 Indicates the following:
409 * 1'b0: The core is transmitting non-NAK handshakes based
411 * 1'b1: The core is transmitting NAK handshakes on this
413 When either the application or the core sets this bit:
414 * For non-isochronous IN endpoints: The core stops
415 transmitting any data on an IN endpoint, even if data is
416 available in the TxFIFO.
417 * For isochronous IN endpoints: The core sends out a zero-
418 length data packet, even if data is available in the TxFIFO.
419 Irrespective of this bit's setting, the core always responds to
420 SETUP data packets with an ACK handshake. */
421 uint32_t dpid : 1; /**< For interrupt/bulk IN and OUT endpoints:
422 Endpoint Data PID (DPID)
423 Contains the PID of the packet to be received or transmitted on
424 this endpoint. The application should program the PID of the first
425 packet to be received or transmitted on this endpoint, after the
426 endpoint is activated. Applications use the SetD1PID and
427 SetD0PID fields of this register to program either DATA0 or
431 For isochronous IN and OUT endpoints:
432 Even/Odd (Micro)Frame (EO_FrNum)
433 Indicates the (micro)frame number in which the core transmits/
434 receives isochronous data for this endpoint. The application
435 should program the even/odd (micro) frame number in which it
436 intends to transmit/receive isochronous data for this endpoint
437 using the SetEvnFr and SetOddFr fields in this register.
438 * 1'b0: Even (micro)frame
439 * 1'b1: Odd (micro)frame */
440 uint32_t usbactep : 1; /**< USB Active Endpoint (USBActEP)
441 Indicates whether this endpoint is active in the current
442 configuration and interface. The core clears this bit for all
443 endpoints (other than EP 0) after detecting a USB reset. After
444 receiving the SetConfiguration and SetInterface commands, the
445 application must program endpoint registers accordingly and set
447 uint32_t nextep : 4; /**< Next Endpoint (NextEp)
448 Applies to non-periodic IN endpoints only.
449 Indicates the endpoint number to be fetched after the data for
450 the current endpoint is fetched. The core can access this field,
451 even when the Endpoint Enable (EPEna) bit is not set. This
452 field is not valid in Slave mode. */
453 uint32_t mps : 11; /**< Maximum Packet Size (MPS)
454 Applies to IN and OUT endpoints.
455 The application must program this field with the maximum
456 packet size for the current logical endpoint. This value is in
459 struct cvmx_usbcx_diepctlx_s cn30xx;
460 struct cvmx_usbcx_diepctlx_s cn31xx;
461 struct cvmx_usbcx_diepctlx_s cn50xx;
462 struct cvmx_usbcx_diepctlx_s cn52xx;
463 struct cvmx_usbcx_diepctlx_s cn52xxp1;
464 struct cvmx_usbcx_diepctlx_s cn56xx;
465 struct cvmx_usbcx_diepctlx_s cn56xxp1;
467 typedef union cvmx_usbcx_diepctlx cvmx_usbcx_diepctlx_t;
470 * cvmx_usbc#_diepint#
472 * Device Endpoint-n Interrupt Register (DIEPINTn)
474 * This register indicates the status of an endpoint with respect to
475 * USB- and AHB-related events. The application must read this register
476 * when the OUT Endpoints Interrupt bit or IN Endpoints Interrupt bit of
477 * the Core Interrupt register (GINTSTS.OEPInt or GINTSTS.IEPInt,
478 * respectively) is set. Before the application can read this register,
479 * it must first read the Device All Endpoints Interrupt (DAINT) register
480 * to get the exact endpoint number for the Device Endpoint-n Interrupt
481 * register. The application must clear the appropriate bit in this register
482 * to clear the corresponding bits in the DAINT and GINTSTS registers.
484 union cvmx_usbcx_diepintx
487 struct cvmx_usbcx_diepintx_s
489 uint32_t reserved_7_31 : 25;
490 uint32_t inepnakeff : 1; /**< IN Endpoint NAK Effective (INEPNakEff)
491 Applies to periodic IN endpoints only.
492 Indicates that the IN endpoint NAK bit set by the application has
493 taken effect in the core. This bit can be cleared when the
494 application clears the IN endpoint NAK by writing to
496 This interrupt indicates that the core has sampled the NAK bit
497 set (either by the application or by the core).
498 This interrupt does not necessarily mean that a NAK handshake
499 is sent on the USB. A STALL bit takes priority over a NAK bit. */
500 uint32_t intknepmis : 1; /**< IN Token Received with EP Mismatch (INTknEPMis)
501 Applies to non-periodic IN endpoints only.
502 Indicates that the data in the top of the non-periodic TxFIFO
503 belongs to an endpoint other than the one for which the IN
504 token was received. This interrupt is asserted on the endpoint
505 for which the IN token was received. */
506 uint32_t intkntxfemp : 1; /**< IN Token Received When TxFIFO is Empty (INTknTXFEmp)
507 Applies only to non-periodic IN endpoints.
508 Indicates that an IN token was received when the associated
509 TxFIFO (periodic/non-periodic) was empty. This interrupt is
510 asserted on the endpoint for which the IN token was received. */
511 uint32_t timeout : 1; /**< Timeout Condition (TimeOUT)
512 Applies to non-isochronous IN endpoints only.
513 Indicates that the core has detected a timeout condition on the
514 USB for the last IN token on this endpoint. */
515 uint32_t ahberr : 1; /**< AHB Error (AHBErr)
516 This is generated only in Internal DMA mode when there is an
517 AHB error during an AHB read/write. The application can read
518 the corresponding endpoint DMA address register to get the
520 uint32_t epdisbld : 1; /**< Endpoint Disabled Interrupt (EPDisbld)
521 This bit indicates that the endpoint is disabled per the
522 application's request. */
523 uint32_t xfercompl : 1; /**< Transfer Completed Interrupt (XferCompl)
524 Indicates that the programmed transfer is complete on the AHB
525 as well as on the USB, for this endpoint. */
527 struct cvmx_usbcx_diepintx_s cn30xx;
528 struct cvmx_usbcx_diepintx_s cn31xx;
529 struct cvmx_usbcx_diepintx_s cn50xx;
530 struct cvmx_usbcx_diepintx_s cn52xx;
531 struct cvmx_usbcx_diepintx_s cn52xxp1;
532 struct cvmx_usbcx_diepintx_s cn56xx;
533 struct cvmx_usbcx_diepintx_s cn56xxp1;
535 typedef union cvmx_usbcx_diepintx cvmx_usbcx_diepintx_t;
540 * Device IN Endpoint Common Interrupt Mask Register (DIEPMSK)
542 * This register works with each of the Device IN Endpoint Interrupt (DIEPINTn) registers
543 * for all endpoints to generate an interrupt per IN endpoint. The IN endpoint interrupt
544 * for a specific status in the DIEPINTn register can be masked by writing to the corresponding
545 * bit in this register. Status bits are masked by default.
546 * Mask interrupt: 1'b0 Unmask interrupt: 1'b1
548 union cvmx_usbcx_diepmsk
551 struct cvmx_usbcx_diepmsk_s
553 uint32_t reserved_7_31 : 25;
554 uint32_t inepnakeffmsk : 1; /**< IN Endpoint NAK Effective Mask (INEPNakEffMsk) */
555 uint32_t intknepmismsk : 1; /**< IN Token received with EP Mismatch Mask (INTknEPMisMsk) */
556 uint32_t intkntxfempmsk : 1; /**< IN Token Received When TxFIFO Empty Mask
558 uint32_t timeoutmsk : 1; /**< Timeout Condition Mask (TimeOUTMsk)
559 (Non-isochronous endpoints) */
560 uint32_t ahberrmsk : 1; /**< AHB Error Mask (AHBErrMsk) */
561 uint32_t epdisbldmsk : 1; /**< Endpoint Disabled Interrupt Mask (EPDisbldMsk) */
562 uint32_t xfercomplmsk : 1; /**< Transfer Completed Interrupt Mask (XferComplMsk) */
564 struct cvmx_usbcx_diepmsk_s cn30xx;
565 struct cvmx_usbcx_diepmsk_s cn31xx;
566 struct cvmx_usbcx_diepmsk_s cn50xx;
567 struct cvmx_usbcx_diepmsk_s cn52xx;
568 struct cvmx_usbcx_diepmsk_s cn52xxp1;
569 struct cvmx_usbcx_diepmsk_s cn56xx;
570 struct cvmx_usbcx_diepmsk_s cn56xxp1;
572 typedef union cvmx_usbcx_diepmsk cvmx_usbcx_diepmsk_t;
575 * cvmx_usbc#_dieptsiz#
577 * Device Endpoint-n Transfer Size Register (DIEPTSIZn)
579 * The application must modify this register before enabling the endpoint.
580 * Once the endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control registers (DIEPCTLn.EPEna/DOEPCTLn.EPEna),
581 * the core modifies this register. The application can only read this register once the core has cleared the Endpoint Enable bit.
582 * This register is used only for endpoints other than Endpoint 0.
584 union cvmx_usbcx_dieptsizx
587 struct cvmx_usbcx_dieptsizx_s
589 uint32_t reserved_31_31 : 1;
590 uint32_t mc : 2; /**< Multi Count (MC)
591 Applies to IN endpoints only.
592 For periodic IN endpoints, this field indicates the number of
593 packets that must be transmitted per microframe on the USB.
594 The core uses this field to calculate the data PID for
595 isochronous IN endpoints.
599 For non-periodic IN endpoints, this field is valid only in Internal
600 DMA mode. It specifies the number of packets the core should
601 fetch for an IN endpoint before it switches to the endpoint
602 pointed to by the Next Endpoint field of the Device Endpoint-n
603 Control register (DIEPCTLn.NextEp) */
604 uint32_t pktcnt : 10; /**< Packet Count (PktCnt)
605 Indicates the total number of USB packets that constitute the
606 Transfer Size amount of data for this endpoint.
607 IN Endpoints: This field is decremented every time a packet
608 (maximum size or short packet) is read from the TxFIFO. */
609 uint32_t xfersize : 19; /**< Transfer Size (XferSize)
610 This field contains the transfer size in bytes for the current
612 The core only interrupts the application after it has exhausted
613 the transfer size amount of data. The transfer size can be set to
614 the maximum packet size of the endpoint, to be interrupted at
615 the end of each packet.
616 IN Endpoints: The core decrements this field every time a
617 packet from the external memory is written to the TxFIFO. */
619 struct cvmx_usbcx_dieptsizx_s cn30xx;
620 struct cvmx_usbcx_dieptsizx_s cn31xx;
621 struct cvmx_usbcx_dieptsizx_s cn50xx;
622 struct cvmx_usbcx_dieptsizx_s cn52xx;
623 struct cvmx_usbcx_dieptsizx_s cn52xxp1;
624 struct cvmx_usbcx_dieptsizx_s cn56xx;
625 struct cvmx_usbcx_dieptsizx_s cn56xxp1;
627 typedef union cvmx_usbcx_dieptsizx cvmx_usbcx_dieptsizx_t;
630 * cvmx_usbc#_doepctl#
632 * Device OUT Endpoint-n Control Register (DOEPCTLn)
634 * The application uses the register to control the behaviour of each logical endpoint other than endpoint 0.
636 union cvmx_usbcx_doepctlx
639 struct cvmx_usbcx_doepctlx_s
641 uint32_t epena : 1; /**< Endpoint Enable (EPEna)
642 Indicates that the application has allocated the memory tp start
643 receiving data from the USB.
644 The core clears this bit before setting any of the following
645 interrupts on this endpoint:
649 For control OUT endpoints in DMA mode, this bit must be set
650 to be able to transfer SETUP data packets in memory. */
651 uint32_t epdis : 1; /**< Endpoint Disable (EPDis)
652 The application sets this bit to stop transmitting data on an
653 endpoint, even before the transfer for that endpoint is complete.
654 The application must wait for the Endpoint Disabled interrupt
655 before treating the endpoint as disabled. The core clears this bit
656 before setting the Endpoint Disabled Interrupt. The application
657 should set this bit only if Endpoint Enable is already set for this
659 uint32_t setd1pid : 1; /**< For Interrupt/BULK enpoints:
660 Set DATA1 PID (SetD1PID)
661 Writing to this field sets the Endpoint Data Pid (DPID) field in
662 this register to DATA1.
663 For Isochronous endpoints:
664 Set Odd (micro)frame (SetOddFr)
665 Writing to this field sets the Even/Odd (micro)frame (EO_FrNum)
666 field to odd (micro)frame. */
667 uint32_t setd0pid : 1; /**< For Interrupt/BULK enpoints:
668 Writing to this field sets the Endpoint Data Pid (DPID) field in
669 this register to DATA0.
670 For Isochronous endpoints:
671 Set Odd (micro)frame (SetEvenFr)
672 Writing to this field sets the Even/Odd (micro)frame (EO_FrNum)
673 field to even (micro)frame. */
674 uint32_t snak : 1; /**< Set NAK (SNAK)
675 A write to this bit sets the NAK bit for the endpoint.
676 Using this bit, the application can control the transmission of
677 NAK handshakes on an endpoint. The core can also set this bit
678 for an endpoint after a SETUP packet is received on the
680 uint32_t cnak : 1; /**< Clear NAK (CNAK)
681 A write to this bit clears the NAK bit for the endpoint. */
682 uint32_t reserved_22_25 : 4;
683 uint32_t stall : 1; /**< STALL Handshake (Stall)
684 For non-control, non-isochronous endpoints:
685 The application sets this bit to stall all tokens from the USB host
686 to this endpoint. If a NAK bit, Global Non-Periodic IN NAK, or
687 Global OUT NAK is set along with this bit, the STALL bit takes
688 priority. Only the application can clear this bit, never the core.
689 For control endpoints:
690 The application can only set this bit, and the core clears it, when
691 a SETUP token i received for this endpoint. If a NAK bit, Global
692 Non-Periodic IN NAK, or Global OUT NAK is set along with this
693 bit, the STALL bit takes priority. Irrespective of this bit's setting,
694 the core always responds to SETUP data packets with an ACK handshake. */
695 uint32_t snp : 1; /**< Snoop Mode (Snp)
696 This bit configures the endpoint to Snoop mode. In Snoop mode,
697 the core does not check the correctness of OUT packets before
698 transferring them to application memory. */
699 uint32_t eptype : 2; /**< Endpoint Type (EPType)
700 This is the transfer type supported by this logical endpoint.
704 * 2'b11: Interrupt */
705 uint32_t naksts : 1; /**< NAK Status (NAKSts)
706 Indicates the following:
707 * 1'b0: The core is transmitting non-NAK handshakes based
709 * 1'b1: The core is transmitting NAK handshakes on this
711 When either the application or the core sets this bit:
712 * The core stops receiving any data on an OUT endpoint, even
713 if there is space in the RxFIFO to accomodate the incoming
715 uint32_t dpid : 1; /**< For interrupt/bulk IN and OUT endpoints:
716 Endpoint Data PID (DPID)
717 Contains the PID of the packet to be received or transmitted on
718 this endpoint. The application should program the PID of the first
719 packet to be received or transmitted on this endpoint, after the
720 endpoint is activated. Applications use the SetD1PID and
721 SetD0PID fields of this register to program either DATA0 or
725 For isochronous IN and OUT endpoints:
726 Even/Odd (Micro)Frame (EO_FrNum)
727 Indicates the (micro)frame number in which the core transmits/
728 receives isochronous data for this endpoint. The application
729 should program the even/odd (micro) frame number in which it
730 intends to transmit/receive isochronous data for this endpoint
731 using the SetEvnFr and SetOddFr fields in this register.
732 * 1'b0: Even (micro)frame
733 * 1'b1: Odd (micro)frame */
734 uint32_t usbactep : 1; /**< USB Active Endpoint (USBActEP)
735 Indicates whether this endpoint is active in the current
736 configuration and interface. The core clears this bit for all
737 endpoints (other than EP 0) after detecting a USB reset. After
738 receiving the SetConfiguration and SetInterface commands, the
739 application must program endpoint registers accordingly and set
741 uint32_t reserved_11_14 : 4;
742 uint32_t mps : 11; /**< Maximum Packet Size (MPS)
743 Applies to IN and OUT endpoints.
744 The application must program this field with the maximum
745 packet size for the current logical endpoint. This value is in
748 struct cvmx_usbcx_doepctlx_s cn30xx;
749 struct cvmx_usbcx_doepctlx_s cn31xx;
750 struct cvmx_usbcx_doepctlx_s cn50xx;
751 struct cvmx_usbcx_doepctlx_s cn52xx;
752 struct cvmx_usbcx_doepctlx_s cn52xxp1;
753 struct cvmx_usbcx_doepctlx_s cn56xx;
754 struct cvmx_usbcx_doepctlx_s cn56xxp1;
756 typedef union cvmx_usbcx_doepctlx cvmx_usbcx_doepctlx_t;
759 * cvmx_usbc#_doepint#
761 * Device Endpoint-n Interrupt Register (DOEPINTn)
763 * This register indicates the status of an endpoint with respect to USB- and AHB-related events.
764 * The application must read this register when the OUT Endpoints Interrupt bit or IN Endpoints
765 * Interrupt bit of the Core Interrupt register (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively)
766 * is set. Before the application can read this register, it must first read the Device All
767 * Endpoints Interrupt (DAINT) register to get the exact endpoint number for the Device Endpoint-n
768 * Interrupt register. The application must clear the appropriate bit in this register to clear the
769 * corresponding bits in the DAINT and GINTSTS registers.
771 union cvmx_usbcx_doepintx
774 struct cvmx_usbcx_doepintx_s
776 uint32_t reserved_5_31 : 27;
777 uint32_t outtknepdis : 1; /**< OUT Token Received When Endpoint Disabled (OUTTknEPdis)
778 Applies only to control OUT endpoints.
779 Indicates that an OUT token was received when the endpoint
780 was not yet enabled. This interrupt is asserted on the endpoint
781 for which the OUT token was received. */
782 uint32_t setup : 1; /**< SETUP Phase Done (SetUp)
783 Applies to control OUT endpoints only.
784 Indicates that the SETUP phase for the control endpoint is
785 complete and no more back-to-back SETUP packets were
786 received for the current control transfer. On this interrupt, the
787 application can decode the received SETUP data packet. */
788 uint32_t ahberr : 1; /**< AHB Error (AHBErr)
789 This is generated only in Internal DMA mode when there is an
790 AHB error during an AHB read/write. The application can read
791 the corresponding endpoint DMA address register to get the
793 uint32_t epdisbld : 1; /**< Endpoint Disabled Interrupt (EPDisbld)
794 This bit indicates that the endpoint is disabled per the
795 application's request. */
796 uint32_t xfercompl : 1; /**< Transfer Completed Interrupt (XferCompl)
797 Indicates that the programmed transfer is complete on the AHB
798 as well as on the USB, for this endpoint. */
800 struct cvmx_usbcx_doepintx_s cn30xx;
801 struct cvmx_usbcx_doepintx_s cn31xx;
802 struct cvmx_usbcx_doepintx_s cn50xx;
803 struct cvmx_usbcx_doepintx_s cn52xx;
804 struct cvmx_usbcx_doepintx_s cn52xxp1;
805 struct cvmx_usbcx_doepintx_s cn56xx;
806 struct cvmx_usbcx_doepintx_s cn56xxp1;
808 typedef union cvmx_usbcx_doepintx cvmx_usbcx_doepintx_t;
813 * Device OUT Endpoint Common Interrupt Mask Register (DOEPMSK)
815 * This register works with each of the Device OUT Endpoint Interrupt (DOEPINTn) registers
816 * for all endpoints to generate an interrupt per OUT endpoint. The OUT endpoint interrupt
817 * for a specific status in the DOEPINTn register can be masked by writing into the
818 * corresponding bit in this register. Status bits are masked by default.
819 * Mask interrupt: 1'b0 Unmask interrupt: 1'b1
821 union cvmx_usbcx_doepmsk
824 struct cvmx_usbcx_doepmsk_s
826 uint32_t reserved_5_31 : 27;
827 uint32_t outtknepdismsk : 1; /**< OUT Token Received when Endpoint Disabled Mask
829 Applies to control OUT endpoints only. */
830 uint32_t setupmsk : 1; /**< SETUP Phase Done Mask (SetUPMsk)
831 Applies to control endpoints only. */
832 uint32_t ahberrmsk : 1; /**< AHB Error (AHBErrMsk) */
833 uint32_t epdisbldmsk : 1; /**< Endpoint Disabled Interrupt Mask (EPDisbldMsk) */
834 uint32_t xfercomplmsk : 1; /**< Transfer Completed Interrupt Mask (XferComplMsk) */
836 struct cvmx_usbcx_doepmsk_s cn30xx;
837 struct cvmx_usbcx_doepmsk_s cn31xx;
838 struct cvmx_usbcx_doepmsk_s cn50xx;
839 struct cvmx_usbcx_doepmsk_s cn52xx;
840 struct cvmx_usbcx_doepmsk_s cn52xxp1;
841 struct cvmx_usbcx_doepmsk_s cn56xx;
842 struct cvmx_usbcx_doepmsk_s cn56xxp1;
844 typedef union cvmx_usbcx_doepmsk cvmx_usbcx_doepmsk_t;
847 * cvmx_usbc#_doeptsiz#
849 * Device Endpoint-n Transfer Size Register (DOEPTSIZn)
851 * The application must modify this register before enabling the endpoint.
852 * Once the endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control
853 * registers (DOEPCTLn.EPEna/DOEPCTLn.EPEna), the core modifies this register. The application
854 * can only read this register once the core has cleared the Endpoint Enable bit.
855 * This register is used only for endpoints other than Endpoint 0.
857 union cvmx_usbcx_doeptsizx
860 struct cvmx_usbcx_doeptsizx_s
862 uint32_t reserved_31_31 : 1;
863 uint32_t mc : 2; /**< Multi Count (MC)
864 Received Data PID (RxDPID)
865 Applies to isochronous OUT endpoints only.
866 This is the data PID received in the last packet for this endpoint.
871 SETUP Packet Count (SUPCnt)
872 Applies to control OUT Endpoints only.
873 This field specifies the number of back-to-back SETUP data
874 packets the endpoint can receive.
878 uint32_t pktcnt : 10; /**< Packet Count (PktCnt)
879 Indicates the total number of USB packets that constitute the
880 Transfer Size amount of data for this endpoint.
881 OUT Endpoints: This field is decremented every time a
882 packet (maximum size or short packet) is written to the
884 uint32_t xfersize : 19; /**< Transfer Size (XferSize)
885 This field contains the transfer size in bytes for the current
887 The core only interrupts the application after it has exhausted
888 the transfer size amount of data. The transfer size can be set to
889 the maximum packet size of the endpoint, to be interrupted at
890 the end of each packet.
891 OUT Endpoints: The core decrements this field every time a
892 packet is read from the RxFIFO and written to the external
895 struct cvmx_usbcx_doeptsizx_s cn30xx;
896 struct cvmx_usbcx_doeptsizx_s cn31xx;
897 struct cvmx_usbcx_doeptsizx_s cn50xx;
898 struct cvmx_usbcx_doeptsizx_s cn52xx;
899 struct cvmx_usbcx_doeptsizx_s cn52xxp1;
900 struct cvmx_usbcx_doeptsizx_s cn56xx;
901 struct cvmx_usbcx_doeptsizx_s cn56xxp1;
903 typedef union cvmx_usbcx_doeptsizx cvmx_usbcx_doeptsizx_t;
906 * cvmx_usbc#_dptxfsiz#
908 * Device Periodic Transmit FIFO-n Size Register (DPTXFSIZ)
910 * This register holds the memory start address of each periodic TxFIFO to implemented
911 * in Device mode. Each periodic FIFO holds the data for one periodic IN endpoint.
912 * This register is repeated for each periodic FIFO instantiated.
914 union cvmx_usbcx_dptxfsizx
917 struct cvmx_usbcx_dptxfsizx_s
919 uint32_t dptxfsize : 16; /**< Device Periodic TxFIFO Size (DPTxFSize)
920 This value is in terms of 32-bit words.
922 * Maximum value is 768 */
923 uint32_t dptxfstaddr : 16; /**< Device Periodic TxFIFO RAM Start Address (DPTxFStAddr)
924 Holds the start address in the RAM for this periodic FIFO. */
926 struct cvmx_usbcx_dptxfsizx_s cn30xx;
927 struct cvmx_usbcx_dptxfsizx_s cn31xx;
928 struct cvmx_usbcx_dptxfsizx_s cn50xx;
929 struct cvmx_usbcx_dptxfsizx_s cn52xx;
930 struct cvmx_usbcx_dptxfsizx_s cn52xxp1;
931 struct cvmx_usbcx_dptxfsizx_s cn56xx;
932 struct cvmx_usbcx_dptxfsizx_s cn56xxp1;
934 typedef union cvmx_usbcx_dptxfsizx cvmx_usbcx_dptxfsizx_t;
939 * Device Status Register (DSTS)
941 * This register indicates the status of the core with respect to USB-related events.
942 * It must be read on interrupts from Device All Interrupts (DAINT) register.
944 union cvmx_usbcx_dsts
947 struct cvmx_usbcx_dsts_s
949 uint32_t reserved_22_31 : 10;
950 uint32_t soffn : 14; /**< Frame or Microframe Number of the Received SOF (SOFFN)
951 When the core is operating at high speed, this field contains a
952 microframe number. When the core is operating at full or low
953 speed, this field contains a frame number. */
954 uint32_t reserved_4_7 : 4;
955 uint32_t errticerr : 1; /**< Erratic Error (ErrticErr)
956 The core sets this bit to report any erratic errors
957 (phy_rxvalid_i/phy_rxvldh_i or phy_rxactive_i is asserted for at
958 least 2 ms, due to PHY error) seen on the UTMI+.
959 Due to erratic errors, the O2P USB core goes into Suspended
960 state and an interrupt is generated to the application with Early
961 Suspend bit of the Core Interrupt register (GINTSTS.ErlySusp).
962 If the early suspend is asserted due to an erratic error, the
963 application can only perform a soft disconnect recover. */
964 uint32_t enumspd : 2; /**< Enumerated Speed (EnumSpd)
965 Indicates the speed at which the O2P USB core has come up
966 after speed detection through a chirp sequence.
967 * 2'b00: High speed (PHY clock is running at 30 or 60 MHz)
968 * 2'b01: Full speed (PHY clock is running at 30 or 60 MHz)
969 * 2'b10: Low speed (PHY clock is running at 6 MHz)
970 * 2'b11: Full speed (PHY clock is running at 48 MHz)
971 Low speed is not supported for devices using a UTMI+ PHY. */
972 uint32_t suspsts : 1; /**< Suspend Status (SuspSts)
973 In Device mode, this bit is set as long as a Suspend condition is
974 detected on the USB. The core enters the Suspended state
975 when there is no activity on the phy_line_state_i signal for an
976 extended period of time. The core comes out of the suspend:
977 * When there is any activity on the phy_line_state_i signal
978 * When the application writes to the Remote Wakeup Signaling
979 bit in the Device Control register (DCTL.RmtWkUpSig). */
981 struct cvmx_usbcx_dsts_s cn30xx;
982 struct cvmx_usbcx_dsts_s cn31xx;
983 struct cvmx_usbcx_dsts_s cn50xx;
984 struct cvmx_usbcx_dsts_s cn52xx;
985 struct cvmx_usbcx_dsts_s cn52xxp1;
986 struct cvmx_usbcx_dsts_s cn56xx;
987 struct cvmx_usbcx_dsts_s cn56xxp1;
989 typedef union cvmx_usbcx_dsts cvmx_usbcx_dsts_t;
994 * Device IN Token Sequence Learning Queue Read Register 1 (DTKNQR1)
996 * The depth of the IN Token Sequence Learning Queue is specified for Device Mode IN Token
997 * Sequence Learning Queue Depth. The queue is 4 bits wide to store the endpoint number.
998 * A read from this register returns the first 5 endpoint entries of the IN Token Sequence
999 * Learning Queue. When the queue is full, the new token is pushed into the queue and oldest
1000 * token is discarded.
1002 union cvmx_usbcx_dtknqr1
1005 struct cvmx_usbcx_dtknqr1_s
1007 uint32_t eptkn : 24; /**< Endpoint Token (EPTkn)
1008 Four bits per token represent the endpoint number of the token:
1009 * Bits [31:28]: Endpoint number of Token 5
1010 * Bits [27:24]: Endpoint number of Token 4
1012 * Bits [15:12]: Endpoint number of Token 1
1013 * Bits [11:8]: Endpoint number of Token 0 */
1014 uint32_t wrapbit : 1; /**< Wrap Bit (WrapBit)
1015 This bit is set when the write pointer wraps. It is cleared when
1016 the learning queue is cleared. */
1017 uint32_t reserved_5_6 : 2;
1018 uint32_t intknwptr : 5; /**< IN Token Queue Write Pointer (INTknWPtr) */
1020 struct cvmx_usbcx_dtknqr1_s cn30xx;
1021 struct cvmx_usbcx_dtknqr1_s cn31xx;
1022 struct cvmx_usbcx_dtknqr1_s cn50xx;
1023 struct cvmx_usbcx_dtknqr1_s cn52xx;
1024 struct cvmx_usbcx_dtknqr1_s cn52xxp1;
1025 struct cvmx_usbcx_dtknqr1_s cn56xx;
1026 struct cvmx_usbcx_dtknqr1_s cn56xxp1;
1028 typedef union cvmx_usbcx_dtknqr1 cvmx_usbcx_dtknqr1_t;
1031 * cvmx_usbc#_dtknqr2
1033 * Device IN Token Sequence Learning Queue Read Register 2 (DTKNQR2)
1035 * A read from this register returns the next 8 endpoint entries of the learning queue.
1037 union cvmx_usbcx_dtknqr2
1040 struct cvmx_usbcx_dtknqr2_s
1042 uint32_t eptkn : 32; /**< Endpoint Token (EPTkn)
1043 Four bits per token represent the endpoint number of the token:
1044 * Bits [31:28]: Endpoint number of Token 13
1045 * Bits [27:24]: Endpoint number of Token 12
1047 * Bits [7:4]: Endpoint number of Token 7
1048 * Bits [3:0]: Endpoint number of Token 6 */
1050 struct cvmx_usbcx_dtknqr2_s cn30xx;
1051 struct cvmx_usbcx_dtknqr2_s cn31xx;
1052 struct cvmx_usbcx_dtknqr2_s cn50xx;
1053 struct cvmx_usbcx_dtknqr2_s cn52xx;
1054 struct cvmx_usbcx_dtknqr2_s cn52xxp1;
1055 struct cvmx_usbcx_dtknqr2_s cn56xx;
1056 struct cvmx_usbcx_dtknqr2_s cn56xxp1;
1058 typedef union cvmx_usbcx_dtknqr2 cvmx_usbcx_dtknqr2_t;
1061 * cvmx_usbc#_dtknqr3
1063 * Device IN Token Sequence Learning Queue Read Register 3 (DTKNQR3)
1065 * A read from this register returns the next 8 endpoint entries of the learning queue.
1067 union cvmx_usbcx_dtknqr3
1070 struct cvmx_usbcx_dtknqr3_s
1072 uint32_t eptkn : 32; /**< Endpoint Token (EPTkn)
1073 Four bits per token represent the endpoint number of the token:
1074 * Bits [31:28]: Endpoint number of Token 21
1075 * Bits [27:24]: Endpoint number of Token 20
1077 * Bits [7:4]: Endpoint number of Token 15
1078 * Bits [3:0]: Endpoint number of Token 14 */
1080 struct cvmx_usbcx_dtknqr3_s cn30xx;
1081 struct cvmx_usbcx_dtknqr3_s cn31xx;
1082 struct cvmx_usbcx_dtknqr3_s cn50xx;
1083 struct cvmx_usbcx_dtknqr3_s cn52xx;
1084 struct cvmx_usbcx_dtknqr3_s cn52xxp1;
1085 struct cvmx_usbcx_dtknqr3_s cn56xx;
1086 struct cvmx_usbcx_dtknqr3_s cn56xxp1;
1088 typedef union cvmx_usbcx_dtknqr3 cvmx_usbcx_dtknqr3_t;
1091 * cvmx_usbc#_dtknqr4
1093 * Device IN Token Sequence Learning Queue Read Register 4 (DTKNQR4)
1095 * A read from this register returns the last 8 endpoint entries of the learning queue.
1097 union cvmx_usbcx_dtknqr4
1100 struct cvmx_usbcx_dtknqr4_s
1102 uint32_t eptkn : 32; /**< Endpoint Token (EPTkn)
1103 Four bits per token represent the endpoint number of the token:
1104 * Bits [31:28]: Endpoint number of Token 29
1105 * Bits [27:24]: Endpoint number of Token 28
1107 * Bits [7:4]: Endpoint number of Token 23
1108 * Bits [3:0]: Endpoint number of Token 22 */
1110 struct cvmx_usbcx_dtknqr4_s cn30xx;
1111 struct cvmx_usbcx_dtknqr4_s cn31xx;
1112 struct cvmx_usbcx_dtknqr4_s cn50xx;
1113 struct cvmx_usbcx_dtknqr4_s cn52xx;
1114 struct cvmx_usbcx_dtknqr4_s cn52xxp1;
1115 struct cvmx_usbcx_dtknqr4_s cn56xx;
1116 struct cvmx_usbcx_dtknqr4_s cn56xxp1;
1118 typedef union cvmx_usbcx_dtknqr4 cvmx_usbcx_dtknqr4_t;
1121 * cvmx_usbc#_gahbcfg
1123 * Core AHB Configuration Register (GAHBCFG)
1125 * This register can be used to configure the core after power-on or a change in mode of operation.
1126 * This register mainly contains AHB system-related configuration parameters. The AHB is the processor
1127 * interface to the O2P USB core. In general, software need not know about this interface except to
1128 * program the values as specified.
1130 * The application must program this register as part of the O2P USB core initialization.
1131 * Do not change this register after the initial programming.
1133 union cvmx_usbcx_gahbcfg
1136 struct cvmx_usbcx_gahbcfg_s
1138 uint32_t reserved_9_31 : 23;
1139 uint32_t ptxfemplvl : 1; /**< Periodic TxFIFO Empty Level (PTxFEmpLvl)
1140 Software should set this bit to 0x1.
1141 Indicates when the Periodic TxFIFO Empty Interrupt bit in the
1142 Core Interrupt register (GINTSTS.PTxFEmp) is triggered. This
1143 bit is used only in Slave mode.
1144 * 1'b0: GINTSTS.PTxFEmp interrupt indicates that the Periodic
1145 TxFIFO is half empty
1146 * 1'b1: GINTSTS.PTxFEmp interrupt indicates that the Periodic
1147 TxFIFO is completely empty */
1148 uint32_t nptxfemplvl : 1; /**< Non-Periodic TxFIFO Empty Level (NPTxFEmpLvl)
1149 Software should set this bit to 0x1.
1150 Indicates when the Non-Periodic TxFIFO Empty Interrupt bit in
1151 the Core Interrupt register (GINTSTS.NPTxFEmp) is triggered.
1152 This bit is used only in Slave mode.
1153 * 1'b0: GINTSTS.NPTxFEmp interrupt indicates that the Non-
1154 Periodic TxFIFO is half empty
1155 * 1'b1: GINTSTS.NPTxFEmp interrupt indicates that the Non-
1156 Periodic TxFIFO is completely empty */
1157 uint32_t reserved_6_6 : 1;
1158 uint32_t dmaen : 1; /**< DMA Enable (DMAEn)
1159 * 1'b0: Core operates in Slave mode
1160 * 1'b1: Core operates in a DMA mode */
1161 uint32_t hbstlen : 4; /**< Burst Length/Type (HBstLen)
1162 This field has not effect and should be left as 0x0. */
1163 uint32_t glblintrmsk : 1; /**< Global Interrupt Mask (GlblIntrMsk)
1164 Software should set this field to 0x1.
1165 The application uses this bit to mask or unmask the interrupt
1166 line assertion to itself. Irrespective of this bit's setting, the
1167 interrupt status registers are updated by the core.
1168 * 1'b0: Mask the interrupt assertion to the application.
1169 * 1'b1: Unmask the interrupt assertion to the application. */
1171 struct cvmx_usbcx_gahbcfg_s cn30xx;
1172 struct cvmx_usbcx_gahbcfg_s cn31xx;
1173 struct cvmx_usbcx_gahbcfg_s cn50xx;
1174 struct cvmx_usbcx_gahbcfg_s cn52xx;
1175 struct cvmx_usbcx_gahbcfg_s cn52xxp1;
1176 struct cvmx_usbcx_gahbcfg_s cn56xx;
1177 struct cvmx_usbcx_gahbcfg_s cn56xxp1;
1179 typedef union cvmx_usbcx_gahbcfg cvmx_usbcx_gahbcfg_t;
1182 * cvmx_usbc#_ghwcfg1
1184 * User HW Config1 Register (GHWCFG1)
1186 * This register contains the logical endpoint direction(s) of the O2P USB core.
1188 union cvmx_usbcx_ghwcfg1
1191 struct cvmx_usbcx_ghwcfg1_s
1193 uint32_t epdir : 32; /**< Endpoint Direction (epdir)
1194 Two bits per endpoint represent the direction.
1195 * 2'b00: BIDIR (IN and OUT) endpoint
1196 * 2'b01: IN endpoint
1197 * 2'b10: OUT endpoint
1199 Bits [31:30]: Endpoint 15 direction
1200 Bits [29:28]: Endpoint 14 direction
1202 Bits [3:2]: Endpoint 1 direction
1203 Bits[1:0]: Endpoint 0 direction (always BIDIR) */
1205 struct cvmx_usbcx_ghwcfg1_s cn30xx;
1206 struct cvmx_usbcx_ghwcfg1_s cn31xx;
1207 struct cvmx_usbcx_ghwcfg1_s cn50xx;
1208 struct cvmx_usbcx_ghwcfg1_s cn52xx;
1209 struct cvmx_usbcx_ghwcfg1_s cn52xxp1;
1210 struct cvmx_usbcx_ghwcfg1_s cn56xx;
1211 struct cvmx_usbcx_ghwcfg1_s cn56xxp1;
1213 typedef union cvmx_usbcx_ghwcfg1 cvmx_usbcx_ghwcfg1_t;
1216 * cvmx_usbc#_ghwcfg2
1218 * User HW Config2 Register (GHWCFG2)
1220 * This register contains configuration options of the O2P USB core.
1222 union cvmx_usbcx_ghwcfg2
1225 struct cvmx_usbcx_ghwcfg2_s
1227 uint32_t reserved_31_31 : 1;
1228 uint32_t tknqdepth : 5; /**< Device Mode IN Token Sequence Learning Queue Depth
1231 uint32_t ptxqdepth : 2; /**< Host Mode Periodic Request Queue Depth (PTxQDepth)
1235 * Others: Reserved */
1236 uint32_t nptxqdepth : 2; /**< Non-Periodic Request Queue Depth (NPTxQDepth)
1240 * Others: Reserved */
1241 uint32_t reserved_20_21 : 2;
1242 uint32_t dynfifosizing : 1; /**< Dynamic FIFO Sizing Enabled (DynFifoSizing)
1245 uint32_t periosupport : 1; /**< Periodic OUT Channels Supported in Host Mode
1249 uint32_t numhstchnl : 4; /**< Number of Host Channels (NumHstChnl)
1250 Indicates the number of host channels supported by the core in
1251 Host mode. The range of this field is 0-15: 0 specifies 1
1252 channel, 15 specifies 16 channels. */
1253 uint32_t numdeveps : 4; /**< Number of Device Endpoints (NumDevEps)
1254 Indicates the number of device endpoints supported by the core
1255 in Device mode in addition to control endpoint 0. The range of
1256 this field is 1-15. */
1257 uint32_t fsphytype : 2; /**< Full-Speed PHY Interface Type (FSPhyType)
1258 * 2'b00: Full-speed interface not supported
1259 * 2'b01: Dedicated full-speed interface
1260 * 2'b10: FS pins shared with UTMI+ pins
1261 * 2'b11: FS pins shared with ULPI pins */
1262 uint32_t hsphytype : 2; /**< High-Speed PHY Interface Type (HSPhyType)
1263 * 2'b00: High-Speed interface not supported
1266 * 2'b11: UTMI+ and ULPI */
1267 uint32_t singpnt : 1; /**< Point-to-Point (SingPnt)
1268 * 1'b0: Multi-point application
1269 * 1'b1: Single-point application */
1270 uint32_t otgarch : 2; /**< Architecture (OtgArch)
1272 * 2'b01: External DMA
1273 * 2'b10: Internal DMA
1274 * Others: Reserved */
1275 uint32_t otgmode : 3; /**< Mode of Operation (OtgMode)
1276 * 3'b000: HNP- and SRP-Capable OTG (Host & Device)
1277 * 3'b001: SRP-Capable OTG (Host & Device)
1278 * 3'b010: Non-HNP and Non-SRP Capable OTG (Host &
1280 * 3'b011: SRP-Capable Device
1281 * 3'b100: Non-OTG Device
1282 * 3'b101: SRP-Capable Host
1283 * 3'b110: Non-OTG Host
1284 * Others: Reserved */
1286 struct cvmx_usbcx_ghwcfg2_s cn30xx;
1287 struct cvmx_usbcx_ghwcfg2_s cn31xx;
1288 struct cvmx_usbcx_ghwcfg2_s cn50xx;
1289 struct cvmx_usbcx_ghwcfg2_s cn52xx;
1290 struct cvmx_usbcx_ghwcfg2_s cn52xxp1;
1291 struct cvmx_usbcx_ghwcfg2_s cn56xx;
1292 struct cvmx_usbcx_ghwcfg2_s cn56xxp1;
1294 typedef union cvmx_usbcx_ghwcfg2 cvmx_usbcx_ghwcfg2_t;
1297 * cvmx_usbc#_ghwcfg3
1299 * User HW Config3 Register (GHWCFG3)
1301 * This register contains the configuration options of the O2P USB core.
1303 union cvmx_usbcx_ghwcfg3
1306 struct cvmx_usbcx_ghwcfg3_s
1308 uint32_t dfifodepth : 16; /**< DFIFO Depth (DfifoDepth)
1309 This value is in terms of 32-bit words.
1310 * Minimum value is 32
1311 * Maximum value is 32768 */
1312 uint32_t reserved_13_15 : 3;
1313 uint32_t ahbphysync : 1; /**< AHB and PHY Synchronous (AhbPhySync)
1314 Indicates whether AHB and PHY clocks are synchronous to
1318 This bit is tied to 1. */
1319 uint32_t rsttype : 1; /**< Reset Style for Clocked always Blocks in RTL (RstType)
1320 * 1'b0: Asynchronous reset is used in the core
1321 * 1'b1: Synchronous reset is used in the core */
1322 uint32_t optfeature : 1; /**< Optional Features Removed (OptFeature)
1323 Indicates whether the User ID register, GPIO interface ports,
1324 and SOF toggle and counter ports were removed for gate count
1326 uint32_t vendor_control_interface_support : 1;/**< Vendor Control Interface Support
1327 * 1'b0: Vendor Control Interface is not available on the core.
1328 * 1'b1: Vendor Control Interface is available. */
1329 uint32_t i2c_selection : 1; /**< I2C Selection
1330 * 1'b0: I2C Interface is not available on the core.
1331 * 1'b1: I2C Interface is available on the core. */
1332 uint32_t otgen : 1; /**< OTG Function Enabled (OtgEn)
1333 The application uses this bit to indicate the O2P USB core's
1335 * 1'b0: Not OTG capable
1336 * 1'b1: OTG Capable */
1337 uint32_t pktsizewidth : 3; /**< Width of Packet Size Counters (PktSizeWidth)
1345 * Others: Reserved */
1346 uint32_t xfersizewidth : 4; /**< Width of Transfer Size Counters (XferSizeWidth)
1351 * Others: Reserved */
1353 struct cvmx_usbcx_ghwcfg3_s cn30xx;
1354 struct cvmx_usbcx_ghwcfg3_s cn31xx;
1355 struct cvmx_usbcx_ghwcfg3_s cn50xx;
1356 struct cvmx_usbcx_ghwcfg3_s cn52xx;
1357 struct cvmx_usbcx_ghwcfg3_s cn52xxp1;
1358 struct cvmx_usbcx_ghwcfg3_s cn56xx;
1359 struct cvmx_usbcx_ghwcfg3_s cn56xxp1;
1361 typedef union cvmx_usbcx_ghwcfg3 cvmx_usbcx_ghwcfg3_t;
1364 * cvmx_usbc#_ghwcfg4
1366 * User HW Config4 Register (GHWCFG4)
1368 * This register contains the configuration options of the O2P USB core.
1370 union cvmx_usbcx_ghwcfg4
1373 struct cvmx_usbcx_ghwcfg4_s
1375 uint32_t reserved_30_31 : 2;
1376 uint32_t numdevmodinend : 4; /**< Enable dedicatd transmit FIFO for device IN endpoints. */
1377 uint32_t endedtrfifo : 1; /**< Enable dedicatd transmit FIFO for device IN endpoints. */
1378 uint32_t sessendfltr : 1; /**< "session_end" Filter Enabled (SessEndFltr)
1381 uint32_t bvalidfltr : 1; /**< "b_valid" Filter Enabled (BValidFltr)
1384 uint32_t avalidfltr : 1; /**< "a_valid" Filter Enabled (AValidFltr)
1387 uint32_t vbusvalidfltr : 1; /**< "vbus_valid" Filter Enabled (VBusValidFltr)
1390 uint32_t iddgfltr : 1; /**< "iddig" Filter Enable (IddgFltr)
1393 uint32_t numctleps : 4; /**< Number of Device Mode Control Endpoints in Addition to
1394 Endpoint 0 (NumCtlEps)
1396 uint32_t phydatawidth : 2; /**< UTMI+ PHY/ULPI-to-Internal UTMI+ Wrapper Data Width
1398 When a ULPI PHY is used, an internal wrapper converts ULPI
1402 * 2'b10: 8/16 bits, software selectable
1403 * Others: Reserved */
1404 uint32_t reserved_6_13 : 8;
1405 uint32_t ahbfreq : 1; /**< Minimum AHB Frequency Less Than 60 MHz (AhbFreq)
1408 uint32_t enablepwropt : 1; /**< Enable Power Optimization? (EnablePwrOpt)
1411 uint32_t numdevperioeps : 4; /**< Number of Device Mode Periodic IN Endpoints
1415 struct cvmx_usbcx_ghwcfg4_cn30xx
1417 uint32_t reserved_25_31 : 7;
1418 uint32_t sessendfltr : 1; /**< "session_end" Filter Enabled (SessEndFltr)
1421 uint32_t bvalidfltr : 1; /**< "b_valid" Filter Enabled (BValidFltr)
1424 uint32_t avalidfltr : 1; /**< "a_valid" Filter Enabled (AValidFltr)
1427 uint32_t vbusvalidfltr : 1; /**< "vbus_valid" Filter Enabled (VBusValidFltr)
1430 uint32_t iddgfltr : 1; /**< "iddig" Filter Enable (IddgFltr)
1433 uint32_t numctleps : 4; /**< Number of Device Mode Control Endpoints in Addition to
1434 Endpoint 0 (NumCtlEps)
1436 uint32_t phydatawidth : 2; /**< UTMI+ PHY/ULPI-to-Internal UTMI+ Wrapper Data Width
1438 When a ULPI PHY is used, an internal wrapper converts ULPI
1442 * 2'b10: 8/16 bits, software selectable
1443 * Others: Reserved */
1444 uint32_t reserved_6_13 : 8;
1445 uint32_t ahbfreq : 1; /**< Minimum AHB Frequency Less Than 60 MHz (AhbFreq)
1448 uint32_t enablepwropt : 1; /**< Enable Power Optimization? (EnablePwrOpt)
1451 uint32_t numdevperioeps : 4; /**< Number of Device Mode Periodic IN Endpoints
1455 struct cvmx_usbcx_ghwcfg4_cn30xx cn31xx;
1456 struct cvmx_usbcx_ghwcfg4_s cn50xx;
1457 struct cvmx_usbcx_ghwcfg4_s cn52xx;
1458 struct cvmx_usbcx_ghwcfg4_s cn52xxp1;
1459 struct cvmx_usbcx_ghwcfg4_s cn56xx;
1460 struct cvmx_usbcx_ghwcfg4_s cn56xxp1;
1462 typedef union cvmx_usbcx_ghwcfg4 cvmx_usbcx_ghwcfg4_t;
1465 * cvmx_usbc#_gintmsk
1467 * Core Interrupt Mask Register (GINTMSK)
1469 * This register works with the Core Interrupt register to interrupt the application.
1470 * When an interrupt bit is masked, the interrupt associated with that bit will not be generated.
1471 * However, the Core Interrupt (GINTSTS) register bit corresponding to that interrupt will still be set.
1472 * Mask interrupt: 1'b0, Unmask interrupt: 1'b1
1474 union cvmx_usbcx_gintmsk
1477 struct cvmx_usbcx_gintmsk_s
1479 uint32_t wkupintmsk : 1; /**< Resume/Remote Wakeup Detected Interrupt Mask
1481 uint32_t sessreqintmsk : 1; /**< Session Request/New Session Detected Interrupt Mask
1483 uint32_t disconnintmsk : 1; /**< Disconnect Detected Interrupt Mask (DisconnIntMsk) */
1484 uint32_t conidstschngmsk : 1; /**< Connector ID Status Change Mask (ConIDStsChngMsk) */
1485 uint32_t reserved_27_27 : 1;
1486 uint32_t ptxfempmsk : 1; /**< Periodic TxFIFO Empty Mask (PTxFEmpMsk) */
1487 uint32_t hchintmsk : 1; /**< Host Channels Interrupt Mask (HChIntMsk) */
1488 uint32_t prtintmsk : 1; /**< Host Port Interrupt Mask (PrtIntMsk) */
1489 uint32_t reserved_23_23 : 1;
1490 uint32_t fetsuspmsk : 1; /**< Data Fetch Suspended Mask (FetSuspMsk) */
1491 uint32_t incomplpmsk : 1; /**< Incomplete Periodic Transfer Mask (incomplPMsk)
1492 Incomplete Isochronous OUT Transfer Mask
1493 (incompISOOUTMsk) */
1494 uint32_t incompisoinmsk : 1; /**< Incomplete Isochronous IN Transfer Mask (incompISOINMsk) */
1495 uint32_t oepintmsk : 1; /**< OUT Endpoints Interrupt Mask (OEPIntMsk) */
1496 uint32_t inepintmsk : 1; /**< IN Endpoints Interrupt Mask (INEPIntMsk) */
1497 uint32_t epmismsk : 1; /**< Endpoint Mismatch Interrupt Mask (EPMisMsk) */
1498 uint32_t reserved_16_16 : 1;
1499 uint32_t eopfmsk : 1; /**< End of Periodic Frame Interrupt Mask (EOPFMsk) */
1500 uint32_t isooutdropmsk : 1; /**< Isochronous OUT Packet Dropped Interrupt Mask
1502 uint32_t enumdonemsk : 1; /**< Enumeration Done Mask (EnumDoneMsk) */
1503 uint32_t usbrstmsk : 1; /**< USB Reset Mask (USBRstMsk) */
1504 uint32_t usbsuspmsk : 1; /**< USB Suspend Mask (USBSuspMsk) */
1505 uint32_t erlysuspmsk : 1; /**< Early Suspend Mask (ErlySuspMsk) */
1506 uint32_t i2cint : 1; /**< I2C Interrupt Mask (I2CINT) */
1507 uint32_t ulpickintmsk : 1; /**< ULPI Carkit Interrupt Mask (ULPICKINTMsk)
1508 I2C Carkit Interrupt Mask (I2CCKINTMsk) */
1509 uint32_t goutnakeffmsk : 1; /**< Global OUT NAK Effective Mask (GOUTNakEffMsk) */
1510 uint32_t ginnakeffmsk : 1; /**< Global Non-Periodic IN NAK Effective Mask (GINNakEffMsk) */
1511 uint32_t nptxfempmsk : 1; /**< Non-Periodic TxFIFO Empty Mask (NPTxFEmpMsk) */
1512 uint32_t rxflvlmsk : 1; /**< Receive FIFO Non-Empty Mask (RxFLvlMsk) */
1513 uint32_t sofmsk : 1; /**< Start of (micro)Frame Mask (SofMsk) */
1514 uint32_t otgintmsk : 1; /**< OTG Interrupt Mask (OTGIntMsk) */
1515 uint32_t modemismsk : 1; /**< Mode Mismatch Interrupt Mask (ModeMisMsk) */
1516 uint32_t reserved_0_0 : 1;
1518 struct cvmx_usbcx_gintmsk_s cn30xx;
1519 struct cvmx_usbcx_gintmsk_s cn31xx;
1520 struct cvmx_usbcx_gintmsk_s cn50xx;
1521 struct cvmx_usbcx_gintmsk_s cn52xx;
1522 struct cvmx_usbcx_gintmsk_s cn52xxp1;
1523 struct cvmx_usbcx_gintmsk_s cn56xx;
1524 struct cvmx_usbcx_gintmsk_s cn56xxp1;
1526 typedef union cvmx_usbcx_gintmsk cvmx_usbcx_gintmsk_t;
1529 * cvmx_usbc#_gintsts
1531 * Core Interrupt Register (GINTSTS)
1533 * This register interrupts the application for system-level events in the current mode of operation
1534 * (Device mode or Host mode). It is shown in Interrupt. Some of the bits in this register are valid only in Host mode,
1535 * while others are valid in Device mode only. This register also indicates the current mode of operation.
1536 * In order to clear the interrupt status bits of type R_SS_WC, the application must write 1'b1 into the bit.
1537 * The FIFO status interrupts are read only; once software reads from or writes to the FIFO while servicing these
1538 * interrupts, FIFO interrupt conditions are cleared automatically.
1540 union cvmx_usbcx_gintsts
1543 struct cvmx_usbcx_gintsts_s
1545 uint32_t wkupint : 1; /**< Resume/Remote Wakeup Detected Interrupt (WkUpInt)
1546 In Device mode, this interrupt is asserted when a resume is
1547 detected on the USB. In Host mode, this interrupt is asserted
1548 when a remote wakeup is detected on the USB.
1549 For more information on how to use this interrupt, see "Partial
1550 Power-Down and Clock Gating Programming Model" on
1552 uint32_t sessreqint : 1; /**< Session Request/New Session Detected Interrupt (SessReqInt)
1553 In Host mode, this interrupt is asserted when a session request
1554 is detected from the device. In Device mode, this interrupt is
1555 asserted when the utmiotg_bvalid signal goes high.
1556 For more information on how to use this interrupt, see "Partial
1557 Power-Down and Clock Gating Programming Model" on
1559 uint32_t disconnint : 1; /**< Disconnect Detected Interrupt (DisconnInt)
1560 Asserted when a device disconnect is detected. */
1561 uint32_t conidstschng : 1; /**< Connector ID Status Change (ConIDStsChng)
1562 The core sets this bit when there is a change in connector ID
1564 uint32_t reserved_27_27 : 1;
1565 uint32_t ptxfemp : 1; /**< Periodic TxFIFO Empty (PTxFEmp)
1566 Asserted when the Periodic Transmit FIFO is either half or
1567 completely empty and there is space for at least one entry to be
1568 written in the Periodic Request Queue. The half or completely
1569 empty status is determined by the Periodic TxFIFO Empty Level
1570 bit in the Core AHB Configuration register
1571 (GAHBCFG.PTxFEmpLvl). */
1572 uint32_t hchint : 1; /**< Host Channels Interrupt (HChInt)
1573 The core sets this bit to indicate that an interrupt is pending on
1574 one of the channels of the core (in Host mode). The application
1575 must read the Host All Channels Interrupt (HAINT) register to
1576 determine the exact number of the channel on which the
1577 interrupt occurred, and then read the corresponding Host
1578 Channel-n Interrupt (HCINTn) register to determine the exact
1579 cause of the interrupt. The application must clear the
1580 appropriate status bit in the HCINTn register to clear this bit. */
1581 uint32_t prtint : 1; /**< Host Port Interrupt (PrtInt)
1582 The core sets this bit to indicate a change in port status of one
1583 of the O2P USB core ports in Host mode. The application must
1584 read the Host Port Control and Status (HPRT) register to
1585 determine the exact event that caused this interrupt. The
1586 application must clear the appropriate status bit in the Host Port
1587 Control and Status register to clear this bit. */
1588 uint32_t reserved_23_23 : 1;
1589 uint32_t fetsusp : 1; /**< Data Fetch Suspended (FetSusp)
1590 This interrupt is valid only in DMA mode. This interrupt indicates
1591 that the core has stopped fetching data for IN endpoints due to
1592 the unavailability of TxFIFO space or Request Queue space.
1593 This interrupt is used by the application for an endpoint
1594 mismatch algorithm. */
1595 uint32_t incomplp : 1; /**< Incomplete Periodic Transfer (incomplP)
1596 In Host mode, the core sets this interrupt bit when there are
1597 incomplete periodic transactions still pending which are
1598 scheduled for the current microframe.
1599 Incomplete Isochronous OUT Transfer (incompISOOUT)
1600 The Device mode, the core sets this interrupt to indicate that
1601 there is at least one isochronous OUT endpoint on which the
1602 transfer is not completed in the current microframe. This
1603 interrupt is asserted along with the End of Periodic Frame
1604 Interrupt (EOPF) bit in this register. */
1605 uint32_t incompisoin : 1; /**< Incomplete Isochronous IN Transfer (incompISOIN)
1606 The core sets this interrupt to indicate that there is at least one
1607 isochronous IN endpoint on which the transfer is not completed
1608 in the current microframe. This interrupt is asserted along with
1609 the End of Periodic Frame Interrupt (EOPF) bit in this register. */
1610 uint32_t oepint : 1; /**< OUT Endpoints Interrupt (OEPInt)
1611 The core sets this bit to indicate that an interrupt is pending on
1612 one of the OUT endpoints of the core (in Device mode). The
1613 application must read the Device All Endpoints Interrupt
1614 (DAINT) register to determine the exact number of the OUT
1615 endpoint on which the interrupt occurred, and then read the
1616 corresponding Device OUT Endpoint-n Interrupt (DOEPINTn)
1617 register to determine the exact cause of the interrupt. The
1618 application must clear the appropriate status bit in the
1619 corresponding DOEPINTn register to clear this bit. */
1620 uint32_t iepint : 1; /**< IN Endpoints Interrupt (IEPInt)
1621 The core sets this bit to indicate that an interrupt is pending on
1622 one of the IN endpoints of the core (in Device mode). The
1623 application must read the Device All Endpoints Interrupt
1624 (DAINT) register to determine the exact number of the IN
1625 endpoint on which the interrupt occurred, and then read the
1626 corresponding Device IN Endpoint-n Interrupt (DIEPINTn)
1627 register to determine the exact cause of the interrupt. The
1628 application must clear the appropriate status bit in the
1629 corresponding DIEPINTn register to clear this bit. */
1630 uint32_t epmis : 1; /**< Endpoint Mismatch Interrupt (EPMis)
1631 Indicates that an IN token has been received for a non-periodic
1632 endpoint, but the data for another endpoint is present in the top
1633 of the Non-Periodic Transmit FIFO and the IN endpoint
1634 mismatch count programmed by the application has expired. */
1635 uint32_t reserved_16_16 : 1;
1636 uint32_t eopf : 1; /**< End of Periodic Frame Interrupt (EOPF)
1637 Indicates that the period specified in the Periodic Frame Interval
1638 field of the Device Configuration register (DCFG.PerFrInt) has
1639 been reached in the current microframe. */
1640 uint32_t isooutdrop : 1; /**< Isochronous OUT Packet Dropped Interrupt (ISOOutDrop)
1641 The core sets this bit when it fails to write an isochronous OUT
1642 packet into the RxFIFO because the RxFIFO doesn't have
1643 enough space to accommodate a maximum packet size packet
1644 for the isochronous OUT endpoint. */
1645 uint32_t enumdone : 1; /**< Enumeration Done (EnumDone)
1646 The core sets this bit to indicate that speed enumeration is
1647 complete. The application must read the Device Status (DSTS)
1648 register to obtain the enumerated speed. */
1649 uint32_t usbrst : 1; /**< USB Reset (USBRst)
1650 The core sets this bit to indicate that a reset is detected on the
1652 uint32_t usbsusp : 1; /**< USB Suspend (USBSusp)
1653 The core sets this bit to indicate that a suspend was detected
1654 on the USB. The core enters the Suspended state when there
1655 is no activity on the phy_line_state_i signal for an extended
1657 uint32_t erlysusp : 1; /**< Early Suspend (ErlySusp)
1658 The core sets this bit to indicate that an Idle state has been
1659 detected on the USB for 3 ms. */
1660 uint32_t i2cint : 1; /**< I2C Interrupt (I2CINT)
1661 This bit is always 0x0. */
1662 uint32_t ulpickint : 1; /**< ULPI Carkit Interrupt (ULPICKINT)
1663 This bit is always 0x0. */
1664 uint32_t goutnakeff : 1; /**< Global OUT NAK Effective (GOUTNakEff)
1665 Indicates that the Set Global OUT NAK bit in the Device Control
1666 register (DCTL.SGOUTNak), set by the application, has taken
1667 effect in the core. This bit can be cleared by writing the Clear
1668 Global OUT NAK bit in the Device Control register
1670 uint32_t ginnakeff : 1; /**< Global IN Non-Periodic NAK Effective (GINNakEff)
1671 Indicates that the Set Global Non-Periodic IN NAK bit in the
1672 Device Control register (DCTL.SGNPInNak), set by the
1673 application, has taken effect in the core. That is, the core has
1674 sampled the Global IN NAK bit set by the application. This bit
1675 can be cleared by clearing the Clear Global Non-Periodic IN
1676 NAK bit in the Device Control register (DCTL.CGNPInNak).
1677 This interrupt does not necessarily mean that a NAK handshake
1678 is sent out on the USB. The STALL bit takes precedence over
1680 uint32_t nptxfemp : 1; /**< Non-Periodic TxFIFO Empty (NPTxFEmp)
1681 This interrupt is asserted when the Non-Periodic TxFIFO is
1682 either half or completely empty, and there is space for at least
1683 one entry to be written to the Non-Periodic Transmit Request
1684 Queue. The half or completely empty status is determined by
1685 the Non-Periodic TxFIFO Empty Level bit in the Core AHB
1686 Configuration register (GAHBCFG.NPTxFEmpLvl). */
1687 uint32_t rxflvl : 1; /**< RxFIFO Non-Empty (RxFLvl)
1688 Indicates that there is at least one packet pending to be read
1690 uint32_t sof : 1; /**< Start of (micro)Frame (Sof)
1691 In Host mode, the core sets this bit to indicate that an SOF
1692 (FS), micro-SOF (HS), or Keep-Alive (LS) is transmitted on the
1693 USB. The application must write a 1 to this bit to clear the
1695 In Device mode, in the core sets this bit to indicate that an SOF
1696 token has been received on the USB. The application can read
1697 the Device Status register to get the current (micro)frame
1698 number. This interrupt is seen only when the core is operating
1699 at either HS or FS. */
1700 uint32_t otgint : 1; /**< OTG Interrupt (OTGInt)
1701 The core sets this bit to indicate an OTG protocol event. The
1702 application must read the OTG Interrupt Status (GOTGINT)
1703 register to determine the exact event that caused this interrupt.
1704 The application must clear the appropriate status bit in the
1705 GOTGINT register to clear this bit. */
1706 uint32_t modemis : 1; /**< Mode Mismatch Interrupt (ModeMis)
1707 The core sets this bit when the application is trying to access:
1708 * A Host mode register, when the core is operating in Device
1710 * A Device mode register, when the core is operating in Host
1712 The register access is completed on the AHB with an OKAY
1713 response, but is ignored by the core internally and doesn't
1714 affect the operation of the core. */
1715 uint32_t curmod : 1; /**< Current Mode of Operation (CurMod)
1716 Indicates the current mode of operation.
1718 * 1'b1: Host mode */
1720 struct cvmx_usbcx_gintsts_s cn30xx;
1721 struct cvmx_usbcx_gintsts_s cn31xx;
1722 struct cvmx_usbcx_gintsts_s cn50xx;
1723 struct cvmx_usbcx_gintsts_s cn52xx;
1724 struct cvmx_usbcx_gintsts_s cn52xxp1;
1725 struct cvmx_usbcx_gintsts_s cn56xx;
1726 struct cvmx_usbcx_gintsts_s cn56xxp1;
1728 typedef union cvmx_usbcx_gintsts cvmx_usbcx_gintsts_t;
1731 * cvmx_usbc#_gnptxfsiz
1733 * Non-Periodic Transmit FIFO Size Register (GNPTXFSIZ)
1735 * The application can program the RAM size and the memory start address for the Non-Periodic TxFIFO.
1737 union cvmx_usbcx_gnptxfsiz
1740 struct cvmx_usbcx_gnptxfsiz_s
1742 uint32_t nptxfdep : 16; /**< Non-Periodic TxFIFO Depth (NPTxFDep)
1743 This value is in terms of 32-bit words.
1745 Maximum value is 32768 */
1746 uint32_t nptxfstaddr : 16; /**< Non-Periodic Transmit RAM Start Address (NPTxFStAddr)
1747 This field contains the memory start address for Non-Periodic
1748 Transmit FIFO RAM. */
1750 struct cvmx_usbcx_gnptxfsiz_s cn30xx;
1751 struct cvmx_usbcx_gnptxfsiz_s cn31xx;
1752 struct cvmx_usbcx_gnptxfsiz_s cn50xx;
1753 struct cvmx_usbcx_gnptxfsiz_s cn52xx;
1754 struct cvmx_usbcx_gnptxfsiz_s cn52xxp1;
1755 struct cvmx_usbcx_gnptxfsiz_s cn56xx;
1756 struct cvmx_usbcx_gnptxfsiz_s cn56xxp1;
1758 typedef union cvmx_usbcx_gnptxfsiz cvmx_usbcx_gnptxfsiz_t;
1761 * cvmx_usbc#_gnptxsts
1763 * Non-Periodic Transmit FIFO/Queue Status Register (GNPTXSTS)
1765 * This read-only register contains the free space information for the Non-Periodic TxFIFO and
1766 * the Non-Periodic Transmit Request Queue
1768 union cvmx_usbcx_gnptxsts
1771 struct cvmx_usbcx_gnptxsts_s
1773 uint32_t reserved_31_31 : 1;
1774 uint32_t nptxqtop : 7; /**< Top of the Non-Periodic Transmit Request Queue (NPTxQTop)
1775 Entry in the Non-Periodic Tx Request Queue that is currently
1776 being processed by the MAC.
1777 * Bits [30:27]: Channel/endpoint number
1779 - 2'b00: IN/OUT token
1780 - 2'b01: Zero-length transmit packet (device IN/host OUT)
1781 - 2'b10: PING/CSPLIT token
1782 - 2'b11: Channel halt command
1783 * Bit [24]: Terminate (last entry for selected channel/endpoint) */
1784 uint32_t nptxqspcavail : 8; /**< Non-Periodic Transmit Request Queue Space Available
1786 Indicates the amount of free space available in the Non-
1787 Periodic Transmit Request Queue. This queue holds both IN
1788 and OUT requests in Host mode. Device mode has only IN
1790 * 8'h0: Non-Periodic Transmit Request Queue is full
1791 * 8'h1: 1 location available
1792 * 8'h2: 2 locations available
1793 * n: n locations available (0..8)
1794 * Others: Reserved */
1795 uint32_t nptxfspcavail : 16; /**< Non-Periodic TxFIFO Space Avail (NPTxFSpcAvail)
1796 Indicates the amount of free space available in the Non-
1798 Values are in terms of 32-bit words.
1799 * 16'h0: Non-Periodic TxFIFO is full
1800 * 16'h1: 1 word available
1801 * 16'h2: 2 words available
1802 * 16'hn: n words available (where 0..32768)
1803 * 16'h8000: 32768 words available
1804 * Others: Reserved */
1806 struct cvmx_usbcx_gnptxsts_s cn30xx;
1807 struct cvmx_usbcx_gnptxsts_s cn31xx;
1808 struct cvmx_usbcx_gnptxsts_s cn50xx;
1809 struct cvmx_usbcx_gnptxsts_s cn52xx;
1810 struct cvmx_usbcx_gnptxsts_s cn52xxp1;
1811 struct cvmx_usbcx_gnptxsts_s cn56xx;
1812 struct cvmx_usbcx_gnptxsts_s cn56xxp1;
1814 typedef union cvmx_usbcx_gnptxsts cvmx_usbcx_gnptxsts_t;
1817 * cvmx_usbc#_gotgctl
1819 * OTG Control and Status Register (GOTGCTL)
1821 * The OTG Control and Status register controls the behavior and reflects the status of the OTG function of the core.:
1823 union cvmx_usbcx_gotgctl
1826 struct cvmx_usbcx_gotgctl_s
1828 uint32_t reserved_20_31 : 12;
1829 uint32_t bsesvld : 1; /**< B-Session Valid (BSesVld)
1830 Valid only when O2P USB core is configured as a USB device.
1831 Indicates the Device mode transceiver status.
1832 * 1'b0: B-session is not valid.
1833 * 1'b1: B-session is valid. */
1834 uint32_t asesvld : 1; /**< A-Session Valid (ASesVld)
1835 Valid only when O2P USB core is configured as a USB host.
1836 Indicates the Host mode transceiver status.
1837 * 1'b0: A-session is not valid
1838 * 1'b1: A-session is valid */
1839 uint32_t dbnctime : 1; /**< Long/Short Debounce Time (DbncTime)
1840 In the present version of the core this bit will only read as '0'. */
1841 uint32_t conidsts : 1; /**< Connector ID Status (ConIDSts)
1842 Indicates the connector ID status on a connect event.
1843 * 1'b0: The O2P USB core is in A-device mode
1844 * 1'b1: The O2P USB core is in B-device mode */
1845 uint32_t reserved_12_15 : 4;
1846 uint32_t devhnpen : 1; /**< Device HNP Enabled (DevHNPEn)
1847 Since O2P USB core is not HNP capable this bit is 0x0. */
1848 uint32_t hstsethnpen : 1; /**< Host Set HNP Enable (HstSetHNPEn)
1849 Since O2P USB core is not HNP capable this bit is 0x0. */
1850 uint32_t hnpreq : 1; /**< HNP Request (HNPReq)
1851 Since O2P USB core is not HNP capable this bit is 0x0. */
1852 uint32_t hstnegscs : 1; /**< Host Negotiation Success (HstNegScs)
1853 Since O2P USB core is not HNP capable this bit is 0x0. */
1854 uint32_t reserved_2_7 : 6;
1855 uint32_t sesreq : 1; /**< Session Request (SesReq)
1856 Since O2P USB core is not SRP capable this bit is 0x0. */
1857 uint32_t sesreqscs : 1; /**< Session Request Success (SesReqScs)
1858 Since O2P USB core is not SRP capable this bit is 0x0. */
1860 struct cvmx_usbcx_gotgctl_s cn30xx;
1861 struct cvmx_usbcx_gotgctl_s cn31xx;
1862 struct cvmx_usbcx_gotgctl_s cn50xx;
1863 struct cvmx_usbcx_gotgctl_s cn52xx;
1864 struct cvmx_usbcx_gotgctl_s cn52xxp1;
1865 struct cvmx_usbcx_gotgctl_s cn56xx;
1866 struct cvmx_usbcx_gotgctl_s cn56xxp1;
1868 typedef union cvmx_usbcx_gotgctl cvmx_usbcx_gotgctl_t;
1871 * cvmx_usbc#_gotgint
1873 * OTG Interrupt Register (GOTGINT)
1875 * The application reads this register whenever there is an OTG interrupt and clears the bits in this register
1876 * to clear the OTG interrupt. It is shown in Interrupt .:
1878 union cvmx_usbcx_gotgint
1881 struct cvmx_usbcx_gotgint_s
1883 uint32_t reserved_20_31 : 12;
1884 uint32_t dbncedone : 1; /**< Debounce Done (DbnceDone)
1885 In the present version of the code this bit is tied to '0'. */
1886 uint32_t adevtoutchg : 1; /**< A-Device Timeout Change (ADevTOUTChg)
1887 Since O2P USB core is not HNP or SRP capable this bit is always 0x0. */
1888 uint32_t hstnegdet : 1; /**< Host Negotiation Detected (HstNegDet)
1889 Since O2P USB core is not HNP or SRP capable this bit is always 0x0. */
1890 uint32_t reserved_10_16 : 7;
1891 uint32_t hstnegsucstschng : 1; /**< Host Negotiation Success Status Change (HstNegSucStsChng)
1892 Since O2P USB core is not HNP or SRP capable this bit is always 0x0. */
1893 uint32_t sesreqsucstschng : 1; /**< Session Request Success Status Change
1894 Since O2P USB core is not HNP or SRP capable this bit is always 0x0. */
1895 uint32_t reserved_3_7 : 5;
1896 uint32_t sesenddet : 1; /**< Session End Detected (SesEndDet)
1897 Since O2P USB core is not HNP or SRP capable this bit is always 0x0. */
1898 uint32_t reserved_0_1 : 2;
1900 struct cvmx_usbcx_gotgint_s cn30xx;
1901 struct cvmx_usbcx_gotgint_s cn31xx;
1902 struct cvmx_usbcx_gotgint_s cn50xx;
1903 struct cvmx_usbcx_gotgint_s cn52xx;
1904 struct cvmx_usbcx_gotgint_s cn52xxp1;
1905 struct cvmx_usbcx_gotgint_s cn56xx;
1906 struct cvmx_usbcx_gotgint_s cn56xxp1;
1908 typedef union cvmx_usbcx_gotgint cvmx_usbcx_gotgint_t;
1911 * cvmx_usbc#_grstctl
1913 * Core Reset Register (GRSTCTL)
1915 * The application uses this register to reset various hardware features inside the core.
1917 union cvmx_usbcx_grstctl
1920 struct cvmx_usbcx_grstctl_s
1922 uint32_t ahbidle : 1; /**< AHB Master Idle (AHBIdle)
1923 Indicates that the AHB Master State Machine is in the IDLE
1925 uint32_t dmareq : 1; /**< DMA Request Signal (DMAReq)
1926 Indicates that the DMA request is in progress. Used for debug. */
1927 uint32_t reserved_11_29 : 19;
1928 uint32_t txfnum : 5; /**< TxFIFO Number (TxFNum)
1929 This is the FIFO number that must be flushed using the TxFIFO
1930 Flush bit. This field must not be changed until the core clears
1931 the TxFIFO Flush bit.
1932 * 5'h0: Non-Periodic TxFIFO flush
1933 * 5'h1: Periodic TxFIFO 1 flush in Device mode or Periodic
1934 TxFIFO flush in Host mode
1935 * 5'h2: Periodic TxFIFO 2 flush in Device mode
1937 * 5'hF: Periodic TxFIFO 15 flush in Device mode
1938 * 5'h10: Flush all the Periodic and Non-Periodic TxFIFOs in the
1940 uint32_t txfflsh : 1; /**< TxFIFO Flush (TxFFlsh)
1941 This bit selectively flushes a single or all transmit FIFOs, but
1942 cannot do so if the core is in the midst of a transaction.
1943 The application must only write this bit after checking that the
1944 core is neither writing to the TxFIFO nor reading from the
1946 The application must wait until the core clears this bit before
1947 performing any operations. This bit takes 8 clocks (of phy_clk or
1948 hclk, whichever is slower) to clear. */
1949 uint32_t rxfflsh : 1; /**< RxFIFO Flush (RxFFlsh)
1950 The application can flush the entire RxFIFO using this bit, but
1951 must first ensure that the core is not in the middle of a
1953 The application must only write to this bit after checking that the
1954 core is neither reading from the RxFIFO nor writing to the
1956 The application must wait until the bit is cleared before
1957 performing any other operations. This bit will take 8 clocks
1958 (slowest of PHY or AHB clock) to clear. */
1959 uint32_t intknqflsh : 1; /**< IN Token Sequence Learning Queue Flush (INTknQFlsh)
1960 The application writes this bit to flush the IN Token Sequence
1962 uint32_t frmcntrrst : 1; /**< Host Frame Counter Reset (FrmCntrRst)
1963 The application writes this bit to reset the (micro)frame number
1964 counter inside the core. When the (micro)frame counter is reset,
1965 the subsequent SOF sent out by the core will have a
1966 (micro)frame number of 0. */
1967 uint32_t hsftrst : 1; /**< HClk Soft Reset (HSftRst)
1968 The application uses this bit to flush the control logic in the AHB
1969 Clock domain. Only AHB Clock Domain pipelines are reset.
1970 * FIFOs are not flushed with this bit.
1971 * All state machines in the AHB clock domain are reset to the
1972 Idle state after terminating the transactions on the AHB,
1973 following the protocol.
1974 * CSR control bits used by the AHB clock domain state
1975 machines are cleared.
1976 * To clear this interrupt, status mask bits that control the
1977 interrupt status and are generated by the AHB clock domain
1978 state machine are cleared.
1979 * Because interrupt status bits are not cleared, the application
1980 can get the status of any core events that occurred after it set
1982 This is a self-clearing bit that the core clears after all necessary
1983 logic is reset in the core. This may take several clocks,
1984 depending on the core's current state. */
1985 uint32_t csftrst : 1; /**< Core Soft Reset (CSftRst)
1986 Resets the hclk and phy_clock domains as follows:
1987 * Clears the interrupts and all the CSR registers except the
1988 following register bits:
1989 - PCGCCTL.RstPdwnModule
1992 - PCGCCTL.StopPPhyLPwrClkSelclk
1993 - GUSBCFG.PhyLPwrClkSel
1997 - GUSBCFG.ULPI_UTMI_Sel
2001 * All module state machines (except the AHB Slave Unit) are
2002 reset to the IDLE state, and all the transmit FIFOs and the
2003 receive FIFO are flushed.
2004 * Any transactions on the AHB Master are terminated as soon
2005 as possible, after gracefully completing the last data phase of
2006 an AHB transfer. Any transactions on the USB are terminated
2008 The application can write to this bit any time it wants to reset
2009 the core. This is a self-clearing bit and the core clears this bit
2010 after all the necessary logic is reset in the core, which may take
2011 several clocks, depending on the current state of the core.
2012 Once this bit is cleared software should wait at least 3 PHY
2013 clocks before doing any access to the PHY domain
2014 (synchronization delay). Software should also should check that
2015 bit 31 of this register is 1 (AHB Master is IDLE) before starting
2017 Typically software reset is used during software development
2018 and also when you dynamically change the PHY selection bits
2019 in the USB configuration registers listed above. When you
2020 change the PHY, the corresponding clock for the PHY is
2021 selected and used in the PHY domain. Once a new clock is
2022 selected, the PHY domain has to be reset for proper operation. */
2024 struct cvmx_usbcx_grstctl_s cn30xx;
2025 struct cvmx_usbcx_grstctl_s cn31xx;
2026 struct cvmx_usbcx_grstctl_s cn50xx;
2027 struct cvmx_usbcx_grstctl_s cn52xx;
2028 struct cvmx_usbcx_grstctl_s cn52xxp1;
2029 struct cvmx_usbcx_grstctl_s cn56xx;
2030 struct cvmx_usbcx_grstctl_s cn56xxp1;
2032 typedef union cvmx_usbcx_grstctl cvmx_usbcx_grstctl_t;
2035 * cvmx_usbc#_grxfsiz
2037 * Receive FIFO Size Register (GRXFSIZ)
2039 * The application can program the RAM size that must be allocated to the RxFIFO.
2041 union cvmx_usbcx_grxfsiz
2044 struct cvmx_usbcx_grxfsiz_s
2046 uint32_t reserved_16_31 : 16;
2047 uint32_t rxfdep : 16; /**< RxFIFO Depth (RxFDep)
2048 This value is in terms of 32-bit words.
2049 * Minimum value is 16
2050 * Maximum value is 32768 */
2052 struct cvmx_usbcx_grxfsiz_s cn30xx;
2053 struct cvmx_usbcx_grxfsiz_s cn31xx;
2054 struct cvmx_usbcx_grxfsiz_s cn50xx;
2055 struct cvmx_usbcx_grxfsiz_s cn52xx;
2056 struct cvmx_usbcx_grxfsiz_s cn52xxp1;
2057 struct cvmx_usbcx_grxfsiz_s cn56xx;
2058 struct cvmx_usbcx_grxfsiz_s cn56xxp1;
2060 typedef union cvmx_usbcx_grxfsiz cvmx_usbcx_grxfsiz_t;
2063 * cvmx_usbc#_grxstspd
2065 * Receive Status Debug Read Register, Device Mode (GRXSTSPD)
2067 * A read to the Receive Status Read and Pop register returns and additionally pops the top data entry out of the RxFIFO.
2068 * This Description is only valid when the core is in Device Mode. For Host Mode use USBC_GRXSTSPH instead.
2069 * NOTE: GRXSTSPH and GRXSTSPD are physically the same register and share the same offset in the O2P USB core.
2070 * The offset difference shown in this document is for software clarity and is actually ignored by the
2073 union cvmx_usbcx_grxstspd
2076 struct cvmx_usbcx_grxstspd_s
2078 uint32_t reserved_25_31 : 7;
2079 uint32_t fn : 4; /**< Frame Number (FN)
2080 This is the least significant 4 bits of the (micro)frame number in
2081 which the packet is received on the USB. This field is supported
2082 only when the isochronous OUT endpoints are supported. */
2083 uint32_t pktsts : 4; /**< Packet Status (PktSts)
2084 Indicates the status of the received packet
2085 * 4'b0001: Glogal OUT NAK (triggers an interrupt)
2086 * 4'b0010: OUT data packet received
2087 * 4'b0100: SETUP transaction completed (triggers an interrupt)
2088 * 4'b0110: SETUP data packet received
2089 * Others: Reserved */
2090 uint32_t dpid : 2; /**< Data PID (DPID)
2095 uint32_t bcnt : 11; /**< Byte Count (BCnt)
2096 Indicates the byte count of the received data packet */
2097 uint32_t epnum : 4; /**< Endpoint Number (EPNum)
2098 Indicates the endpoint number to which the current received
2101 struct cvmx_usbcx_grxstspd_s cn30xx;
2102 struct cvmx_usbcx_grxstspd_s cn31xx;
2103 struct cvmx_usbcx_grxstspd_s cn50xx;
2104 struct cvmx_usbcx_grxstspd_s cn52xx;
2105 struct cvmx_usbcx_grxstspd_s cn52xxp1;
2106 struct cvmx_usbcx_grxstspd_s cn56xx;
2107 struct cvmx_usbcx_grxstspd_s cn56xxp1;
2109 typedef union cvmx_usbcx_grxstspd cvmx_usbcx_grxstspd_t;
2112 * cvmx_usbc#_grxstsph
2114 * Receive Status Read and Pop Register, Host Mode (GRXSTSPH)
2116 * A read to the Receive Status Read and Pop register returns and additionally pops the top data entry out of the RxFIFO.
2117 * This Description is only valid when the core is in Host Mode. For Device Mode use USBC_GRXSTSPD instead.
2118 * NOTE: GRXSTSPH and GRXSTSPD are physically the same register and share the same offset in the O2P USB core.
2119 * The offset difference shown in this document is for software clarity and is actually ignored by the
2122 union cvmx_usbcx_grxstsph
2125 struct cvmx_usbcx_grxstsph_s
2127 uint32_t reserved_21_31 : 11;
2128 uint32_t pktsts : 4; /**< Packet Status (PktSts)
2129 Indicates the status of the received packet
2130 * 4'b0010: IN data packet received
2131 * 4'b0011: IN transfer completed (triggers an interrupt)
2132 * 4'b0101: Data toggle error (triggers an interrupt)
2133 * 4'b0111: Channel halted (triggers an interrupt)
2134 * Others: Reserved */
2135 uint32_t dpid : 2; /**< Data PID (DPID)
2140 uint32_t bcnt : 11; /**< Byte Count (BCnt)
2141 Indicates the byte count of the received IN data packet */
2142 uint32_t chnum : 4; /**< Channel Number (ChNum)
2143 Indicates the channel number to which the current received
2146 struct cvmx_usbcx_grxstsph_s cn30xx;
2147 struct cvmx_usbcx_grxstsph_s cn31xx;
2148 struct cvmx_usbcx_grxstsph_s cn50xx;
2149 struct cvmx_usbcx_grxstsph_s cn52xx;
2150 struct cvmx_usbcx_grxstsph_s cn52xxp1;
2151 struct cvmx_usbcx_grxstsph_s cn56xx;
2152 struct cvmx_usbcx_grxstsph_s cn56xxp1;
2154 typedef union cvmx_usbcx_grxstsph cvmx_usbcx_grxstsph_t;
2157 * cvmx_usbc#_grxstsrd
2159 * Receive Status Debug Read Register, Device Mode (GRXSTSRD)
2161 * A read to the Receive Status Debug Read register returns the contents of the top of the Receive FIFO.
2162 * This Description is only valid when the core is in Device Mode. For Host Mode use USBC_GRXSTSRH instead.
2163 * NOTE: GRXSTSRH and GRXSTSRD are physically the same register and share the same offset in the O2P USB core.
2164 * The offset difference shown in this document is for software clarity and is actually ignored by the
2167 union cvmx_usbcx_grxstsrd
2170 struct cvmx_usbcx_grxstsrd_s
2172 uint32_t reserved_25_31 : 7;
2173 uint32_t fn : 4; /**< Frame Number (FN)
2174 This is the least significant 4 bits of the (micro)frame number in
2175 which the packet is received on the USB. This field is supported
2176 only when the isochronous OUT endpoints are supported. */
2177 uint32_t pktsts : 4; /**< Packet Status (PktSts)
2178 Indicates the status of the received packet
2179 * 4'b0001: Glogal OUT NAK (triggers an interrupt)
2180 * 4'b0010: OUT data packet received
2181 * 4'b0100: SETUP transaction completed (triggers an interrupt)
2182 * 4'b0110: SETUP data packet received
2183 * Others: Reserved */
2184 uint32_t dpid : 2; /**< Data PID (DPID)
2189 uint32_t bcnt : 11; /**< Byte Count (BCnt)
2190 Indicates the byte count of the received data packet */
2191 uint32_t epnum : 4; /**< Endpoint Number (EPNum)
2192 Indicates the endpoint number to which the current received
2195 struct cvmx_usbcx_grxstsrd_s cn30xx;
2196 struct cvmx_usbcx_grxstsrd_s cn31xx;
2197 struct cvmx_usbcx_grxstsrd_s cn50xx;
2198 struct cvmx_usbcx_grxstsrd_s cn52xx;
2199 struct cvmx_usbcx_grxstsrd_s cn52xxp1;
2200 struct cvmx_usbcx_grxstsrd_s cn56xx;
2201 struct cvmx_usbcx_grxstsrd_s cn56xxp1;
2203 typedef union cvmx_usbcx_grxstsrd cvmx_usbcx_grxstsrd_t;
2206 * cvmx_usbc#_grxstsrh
2208 * Receive Status Debug Read Register, Host Mode (GRXSTSRH)
2210 * A read to the Receive Status Debug Read register returns the contents of the top of the Receive FIFO.
2211 * This Description is only valid when the core is in Host Mode. For Device Mode use USBC_GRXSTSRD instead.
2212 * NOTE: GRXSTSRH and GRXSTSRD are physically the same register and share the same offset in the O2P USB core.
2213 * The offset difference shown in this document is for software clarity and is actually ignored by the
2216 union cvmx_usbcx_grxstsrh
2219 struct cvmx_usbcx_grxstsrh_s
2221 uint32_t reserved_21_31 : 11;
2222 uint32_t pktsts : 4; /**< Packet Status (PktSts)
2223 Indicates the status of the received packet
2224 * 4'b0010: IN data packet received
2225 * 4'b0011: IN transfer completed (triggers an interrupt)
2226 * 4'b0101: Data toggle error (triggers an interrupt)
2227 * 4'b0111: Channel halted (triggers an interrupt)
2228 * Others: Reserved */
2229 uint32_t dpid : 2; /**< Data PID (DPID)
2234 uint32_t bcnt : 11; /**< Byte Count (BCnt)
2235 Indicates the byte count of the received IN data packet */
2236 uint32_t chnum : 4; /**< Channel Number (ChNum)
2237 Indicates the channel number to which the current received
2240 struct cvmx_usbcx_grxstsrh_s cn30xx;
2241 struct cvmx_usbcx_grxstsrh_s cn31xx;
2242 struct cvmx_usbcx_grxstsrh_s cn50xx;
2243 struct cvmx_usbcx_grxstsrh_s cn52xx;
2244 struct cvmx_usbcx_grxstsrh_s cn52xxp1;
2245 struct cvmx_usbcx_grxstsrh_s cn56xx;
2246 struct cvmx_usbcx_grxstsrh_s cn56xxp1;
2248 typedef union cvmx_usbcx_grxstsrh cvmx_usbcx_grxstsrh_t;
2251 * cvmx_usbc#_gsnpsid
2253 * Synopsys ID Register (GSNPSID)
2255 * This is a read-only register that contains the release number of the core being used.
2257 union cvmx_usbcx_gsnpsid
2260 struct cvmx_usbcx_gsnpsid_s
2262 uint32_t synopsysid : 32; /**< 0x4F54\<version\>A, release number of the core being used.
2263 0x4F54220A => pass1.x, 0x4F54240A => pass2.x */
2265 struct cvmx_usbcx_gsnpsid_s cn30xx;
2266 struct cvmx_usbcx_gsnpsid_s cn31xx;
2267 struct cvmx_usbcx_gsnpsid_s cn50xx;
2268 struct cvmx_usbcx_gsnpsid_s cn52xx;
2269 struct cvmx_usbcx_gsnpsid_s cn52xxp1;
2270 struct cvmx_usbcx_gsnpsid_s cn56xx;
2271 struct cvmx_usbcx_gsnpsid_s cn56xxp1;
2273 typedef union cvmx_usbcx_gsnpsid cvmx_usbcx_gsnpsid_t;
2276 * cvmx_usbc#_gusbcfg
2278 * Core USB Configuration Register (GUSBCFG)
2280 * This register can be used to configure the core after power-on or a changing to Host mode or Device mode.
2281 * It contains USB and USB-PHY related configuration parameters. The application must program this register
2282 * before starting any transactions on either the AHB or the USB.
2283 * Do not make changes to this register after the initial programming.
2285 union cvmx_usbcx_gusbcfg
2288 struct cvmx_usbcx_gusbcfg_s
2290 uint32_t reserved_17_31 : 15;
2291 uint32_t otgi2csel : 1; /**< UTMIFS or I2C Interface Select (OtgI2CSel)
2292 This bit is always 0x0. */
2293 uint32_t phylpwrclksel : 1; /**< PHY Low-Power Clock Select (PhyLPwrClkSel)
2294 Software should set this bit to 0x0.
2295 Selects either 480-MHz or 48-MHz (low-power) PHY mode. In
2296 FS and LS modes, the PHY can usually operate on a 48-MHz
2297 clock to save power.
2298 * 1'b0: 480-MHz Internal PLL clock
2299 * 1'b1: 48-MHz External Clock
2300 In 480 MHz mode, the UTMI interface operates at either 60 or
2301 30-MHz, depending upon whether 8- or 16-bit data width is
2302 selected. In 48-MHz mode, the UTMI interface operates at 48
2303 MHz in FS mode and at either 48 or 6 MHz in LS mode
2304 (depending on the PHY vendor).
2305 This bit drives the utmi_fsls_low_power core output signal, and
2306 is valid only for UTMI+ PHYs. */
2307 uint32_t reserved_14_14 : 1;
2308 uint32_t usbtrdtim : 4; /**< USB Turnaround Time (USBTrdTim)
2309 Sets the turnaround time in PHY clocks.
2310 Specifies the response time for a MAC request to the Packet
2311 FIFO Controller (PFC) to fetch data from the DFIFO (SPRAM).
2312 This must be programmed to 0x5. */
2313 uint32_t hnpcap : 1; /**< HNP-Capable (HNPCap)
2314 This bit is always 0x0. */
2315 uint32_t srpcap : 1; /**< SRP-Capable (SRPCap)
2316 This bit is always 0x0. */
2317 uint32_t ddrsel : 1; /**< ULPI DDR Select (DDRSel)
2318 Software should set this bit to 0x0. */
2319 uint32_t physel : 1; /**< USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial
2320 Software should set this bit to 0x0. */
2321 uint32_t fsintf : 1; /**< Full-Speed Serial Interface Select (FSIntf)
2322 Software should set this bit to 0x0. */
2323 uint32_t ulpi_utmi_sel : 1; /**< ULPI or UTMI+ Select (ULPI_UTMI_Sel)
2324 This bit is always 0x0. */
2325 uint32_t phyif : 1; /**< PHY Interface (PHYIf)
2326 This bit is always 0x1. */
2327 uint32_t toutcal : 3; /**< HS/FS Timeout Calibration (TOutCal)
2328 The number of PHY clocks that the application programs in this
2329 field is added to the high-speed/full-speed interpacket timeout
2330 duration in the core to account for any additional delays
2331 introduced by the PHY. This may be required, since the delay
2332 introduced by the PHY in generating the linestate condition may
2333 vary from one PHY to another.
2334 The USB standard timeout value for high-speed operation is
2335 736 to 816 (inclusive) bit times. The USB standard timeout
2336 value for full-speed operation is 16 to 18 (inclusive) bit times.
2337 The application must program this field based on the speed of
2338 enumeration. The number of bit times added per PHY clock are:
2339 High-speed operation:
2340 * One 30-MHz PHY clock = 16 bit times
2341 * One 60-MHz PHY clock = 8 bit times
2342 Full-speed operation:
2343 * One 30-MHz PHY clock = 0.4 bit times
2344 * One 60-MHz PHY clock = 0.2 bit times
2345 * One 48-MHz PHY clock = 0.25 bit times */
2347 struct cvmx_usbcx_gusbcfg_s cn30xx;
2348 struct cvmx_usbcx_gusbcfg_s cn31xx;
2349 struct cvmx_usbcx_gusbcfg_s cn50xx;
2350 struct cvmx_usbcx_gusbcfg_s cn52xx;
2351 struct cvmx_usbcx_gusbcfg_s cn52xxp1;
2352 struct cvmx_usbcx_gusbcfg_s cn56xx;
2353 struct cvmx_usbcx_gusbcfg_s cn56xxp1;
2355 typedef union cvmx_usbcx_gusbcfg cvmx_usbcx_gusbcfg_t;
2360 * Host All Channels Interrupt Register (HAINT)
2362 * When a significant event occurs on a channel, the Host All Channels Interrupt register
2363 * interrupts the application using the Host Channels Interrupt bit of the Core Interrupt
2364 * register (GINTSTS.HChInt). This is shown in Interrupt . There is one interrupt bit per
2365 * channel, up to a maximum of 16 bits. Bits in this register are set and cleared when the
2366 * application sets and clears bits in the corresponding Host Channel-n Interrupt register.
2368 union cvmx_usbcx_haint
2371 struct cvmx_usbcx_haint_s
2373 uint32_t reserved_16_31 : 16;
2374 uint32_t haint : 16; /**< Channel Interrupts (HAINT)
2375 One bit per channel: Bit 0 for Channel 0, bit 15 for Channel 15 */
2377 struct cvmx_usbcx_haint_s cn30xx;
2378 struct cvmx_usbcx_haint_s cn31xx;
2379 struct cvmx_usbcx_haint_s cn50xx;
2380 struct cvmx_usbcx_haint_s cn52xx;
2381 struct cvmx_usbcx_haint_s cn52xxp1;
2382 struct cvmx_usbcx_haint_s cn56xx;
2383 struct cvmx_usbcx_haint_s cn56xxp1;
2385 typedef union cvmx_usbcx_haint cvmx_usbcx_haint_t;
2388 * cvmx_usbc#_haintmsk
2390 * Host All Channels Interrupt Mask Register (HAINTMSK)
2392 * The Host All Channel Interrupt Mask register works with the Host All Channel Interrupt
2393 * register to interrupt the application when an event occurs on a channel. There is one
2394 * interrupt mask bit per channel, up to a maximum of 16 bits.
2395 * Mask interrupt: 1'b0 Unmask interrupt: 1'b1
2397 union cvmx_usbcx_haintmsk
2400 struct cvmx_usbcx_haintmsk_s
2402 uint32_t reserved_16_31 : 16;
2403 uint32_t haintmsk : 16; /**< Channel Interrupt Mask (HAINTMsk)
2404 One bit per channel: Bit 0 for channel 0, bit 15 for channel 15 */
2406 struct cvmx_usbcx_haintmsk_s cn30xx;
2407 struct cvmx_usbcx_haintmsk_s cn31xx;
2408 struct cvmx_usbcx_haintmsk_s cn50xx;
2409 struct cvmx_usbcx_haintmsk_s cn52xx;
2410 struct cvmx_usbcx_haintmsk_s cn52xxp1;
2411 struct cvmx_usbcx_haintmsk_s cn56xx;
2412 struct cvmx_usbcx_haintmsk_s cn56xxp1;
2414 typedef union cvmx_usbcx_haintmsk cvmx_usbcx_haintmsk_t;
2417 * cvmx_usbc#_hcchar#
2419 * Host Channel-n Characteristics Register (HCCHAR)
2422 union cvmx_usbcx_hccharx
2425 struct cvmx_usbcx_hccharx_s
2427 uint32_t chena : 1; /**< Channel Enable (ChEna)
2428 This field is set by the application and cleared by the OTG host.
2429 * 1'b0: Channel disabled
2430 * 1'b1: Channel enabled */
2431 uint32_t chdis : 1; /**< Channel Disable (ChDis)
2432 The application sets this bit to stop transmitting/receiving data
2433 on a channel, even before the transfer for that channel is
2434 complete. The application must wait for the Channel Disabled
2435 interrupt before treating the channel as disabled. */
2436 uint32_t oddfrm : 1; /**< Odd Frame (OddFrm)
2437 This field is set (reset) by the application to indicate that the
2438 OTG host must perform a transfer in an odd (micro)frame. This
2439 field is applicable for only periodic (isochronous and interrupt)
2441 * 1'b0: Even (micro)frame
2442 * 1'b1: Odd (micro)frame */
2443 uint32_t devaddr : 7; /**< Device Address (DevAddr)
2444 This field selects the specific device serving as the data source
2446 uint32_t ec : 2; /**< Multi Count (MC) / Error Count (EC)
2447 When the Split Enable bit of the Host Channel-n Split Control
2448 register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates
2449 to the host the number of transactions that should be executed
2450 per microframe for this endpoint.
2451 * 2'b00: Reserved. This field yields undefined results.
2452 * 2'b01: 1 transaction
2453 * 2'b10: 2 transactions to be issued for this endpoint per
2455 * 2'b11: 3 transactions to be issued for this endpoint per
2457 When HCSPLTn.SpltEna is set (1'b1), this field indicates the
2458 number of immediate retries to be performed for a periodic split
2459 transactions on transaction errors. This field must be set to at
2461 uint32_t eptype : 2; /**< Endpoint Type (EPType)
2462 Indicates the transfer type selected.
2464 * 2'b01: Isochronous
2466 * 2'b11: Interrupt */
2467 uint32_t lspddev : 1; /**< Low-Speed Device (LSpdDev)
2468 This field is set by the application to indicate that this channel is
2469 communicating to a low-speed device. */
2470 uint32_t reserved_16_16 : 1;
2471 uint32_t epdir : 1; /**< Endpoint Direction (EPDir)
2472 Indicates whether the transaction is IN or OUT.
2475 uint32_t epnum : 4; /**< Endpoint Number (EPNum)
2476 Indicates the endpoint number on the device serving as the
2477 data source or sink. */
2478 uint32_t mps : 11; /**< Maximum Packet Size (MPS)
2479 Indicates the maximum packet size of the associated endpoint. */
2481 struct cvmx_usbcx_hccharx_s cn30xx;
2482 struct cvmx_usbcx_hccharx_s cn31xx;
2483 struct cvmx_usbcx_hccharx_s cn50xx;
2484 struct cvmx_usbcx_hccharx_s cn52xx;
2485 struct cvmx_usbcx_hccharx_s cn52xxp1;
2486 struct cvmx_usbcx_hccharx_s cn56xx;
2487 struct cvmx_usbcx_hccharx_s cn56xxp1;
2489 typedef union cvmx_usbcx_hccharx cvmx_usbcx_hccharx_t;
2494 * Host Configuration Register (HCFG)
2496 * This register configures the core after power-on. Do not make changes to this register after initializing the host.
2498 union cvmx_usbcx_hcfg
2501 struct cvmx_usbcx_hcfg_s
2503 uint32_t reserved_3_31 : 29;
2504 uint32_t fslssupp : 1; /**< FS- and LS-Only Support (FSLSSupp)
2505 The application uses this bit to control the core's enumeration
2506 speed. Using this bit, the application can make the core
2507 enumerate as a FS host, even if the connected device supports
2508 HS traffic. Do not make changes to this field after initial
2510 * 1'b0: HS/FS/LS, based on the maximum speed supported by
2511 the connected device
2512 * 1'b1: FS/LS-only, even if the connected device can support HS */
2513 uint32_t fslspclksel : 2; /**< FS/LS PHY Clock Select (FSLSPclkSel)
2514 When the core is in FS Host mode
2515 * 2'b00: PHY clock is running at 30/60 MHz
2516 * 2'b01: PHY clock is running at 48 MHz
2518 When the core is in LS Host mode
2519 * 2'b00: PHY clock is running at 30/60 MHz. When the
2520 UTMI+/ULPI PHY Low Power mode is not selected, use
2522 * 2'b01: PHY clock is running at 48 MHz. When the UTMI+
2523 PHY Low Power mode is selected, use 48MHz if the PHY
2524 supplies a 48 MHz clock during LS mode.
2525 * 2'b10: PHY clock is running at 6 MHz. In USB 1.1 FS mode,
2526 use 6 MHz when the UTMI+ PHY Low Power mode is
2527 selected and the PHY supplies a 6 MHz clock during LS
2528 mode. If you select a 6 MHz clock during LS mode, you must
2530 * 2'b11: Reserved */
2532 struct cvmx_usbcx_hcfg_s cn30xx;
2533 struct cvmx_usbcx_hcfg_s cn31xx;
2534 struct cvmx_usbcx_hcfg_s cn50xx;
2535 struct cvmx_usbcx_hcfg_s cn52xx;
2536 struct cvmx_usbcx_hcfg_s cn52xxp1;
2537 struct cvmx_usbcx_hcfg_s cn56xx;
2538 struct cvmx_usbcx_hcfg_s cn56xxp1;
2540 typedef union cvmx_usbcx_hcfg cvmx_usbcx_hcfg_t;
2545 * Host Channel-n Interrupt Register (HCINT)
2547 * This register indicates the status of a channel with respect to USB- and AHB-related events.
2548 * The application must read this register when the Host Channels Interrupt bit of the Core Interrupt
2549 * register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read
2550 * the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n
2551 * Interrupt register. The application must clear the appropriate bit in this register to clear the
2552 * corresponding bits in the HAINT and GINTSTS registers.
2554 union cvmx_usbcx_hcintx
2557 struct cvmx_usbcx_hcintx_s
2559 uint32_t reserved_11_31 : 21;
2560 uint32_t datatglerr : 1; /**< Data Toggle Error (DataTglErr) */
2561 uint32_t frmovrun : 1; /**< Frame Overrun (FrmOvrun) */
2562 uint32_t bblerr : 1; /**< Babble Error (BblErr) */
2563 uint32_t xacterr : 1; /**< Transaction Error (XactErr) */
2564 uint32_t nyet : 1; /**< NYET Response Received Interrupt (NYET) */
2565 uint32_t ack : 1; /**< ACK Response Received Interrupt (ACK) */
2566 uint32_t nak : 1; /**< NAK Response Received Interrupt (NAK) */
2567 uint32_t stall : 1; /**< STALL Response Received Interrupt (STALL) */
2568 uint32_t ahberr : 1; /**< This bit is always 0x0. */
2569 uint32_t chhltd : 1; /**< Channel Halted (ChHltd)
2570 Indicates the transfer completed abnormally either because of
2571 any USB transaction error or in response to disable request by
2573 uint32_t xfercompl : 1; /**< Transfer Completed (XferCompl)
2574 Transfer completed normally without any errors. */
2576 struct cvmx_usbcx_hcintx_s cn30xx;
2577 struct cvmx_usbcx_hcintx_s cn31xx;
2578 struct cvmx_usbcx_hcintx_s cn50xx;
2579 struct cvmx_usbcx_hcintx_s cn52xx;
2580 struct cvmx_usbcx_hcintx_s cn52xxp1;
2581 struct cvmx_usbcx_hcintx_s cn56xx;
2582 struct cvmx_usbcx_hcintx_s cn56xxp1;
2584 typedef union cvmx_usbcx_hcintx cvmx_usbcx_hcintx_t;
2587 * cvmx_usbc#_hcintmsk#
2589 * Host Channel-n Interrupt Mask Register (HCINTMSKn)
2591 * This register reflects the mask for each channel status described in the previous section.
2592 * Mask interrupt: 1'b0 Unmask interrupt: 1'b1
2594 union cvmx_usbcx_hcintmskx
2597 struct cvmx_usbcx_hcintmskx_s
2599 uint32_t reserved_11_31 : 21;
2600 uint32_t datatglerrmsk : 1; /**< Data Toggle Error Mask (DataTglErrMsk) */
2601 uint32_t frmovrunmsk : 1; /**< Frame Overrun Mask (FrmOvrunMsk) */
2602 uint32_t bblerrmsk : 1; /**< Babble Error Mask (BblErrMsk) */
2603 uint32_t xacterrmsk : 1; /**< Transaction Error Mask (XactErrMsk) */
2604 uint32_t nyetmsk : 1; /**< NYET Response Received Interrupt Mask (NyetMsk) */
2605 uint32_t ackmsk : 1; /**< ACK Response Received Interrupt Mask (AckMsk) */
2606 uint32_t nakmsk : 1; /**< NAK Response Received Interrupt Mask (NakMsk) */
2607 uint32_t stallmsk : 1; /**< STALL Response Received Interrupt Mask (StallMsk) */
2608 uint32_t ahberrmsk : 1; /**< AHB Error Mask (AHBErrMsk) */
2609 uint32_t chhltdmsk : 1; /**< Channel Halted Mask (ChHltdMsk) */
2610 uint32_t xfercomplmsk : 1; /**< Transfer Completed Mask (XferComplMsk) */
2612 struct cvmx_usbcx_hcintmskx_s cn30xx;
2613 struct cvmx_usbcx_hcintmskx_s cn31xx;
2614 struct cvmx_usbcx_hcintmskx_s cn50xx;
2615 struct cvmx_usbcx_hcintmskx_s cn52xx;
2616 struct cvmx_usbcx_hcintmskx_s cn52xxp1;
2617 struct cvmx_usbcx_hcintmskx_s cn56xx;
2618 struct cvmx_usbcx_hcintmskx_s cn56xxp1;
2620 typedef union cvmx_usbcx_hcintmskx cvmx_usbcx_hcintmskx_t;
2623 * cvmx_usbc#_hcsplt#
2625 * Host Channel-n Split Control Register (HCSPLT)
2628 union cvmx_usbcx_hcspltx
2631 struct cvmx_usbcx_hcspltx_s
2633 uint32_t spltena : 1; /**< Split Enable (SpltEna)
2634 The application sets this field to indicate that this channel is
2635 enabled to perform split transactions. */
2636 uint32_t reserved_17_30 : 14;
2637 uint32_t compsplt : 1; /**< Do Complete Split (CompSplt)
2638 The application sets this field to request the OTG host to
2639 perform a complete split transaction. */
2640 uint32_t xactpos : 2; /**< Transaction Position (XactPos)
2641 This field is used to determine whether to send all, first, middle,
2642 or last payloads with each OUT transaction.
2643 * 2'b11: All. This is the entire data payload is of this transaction
2644 (which is less than or equal to 188 bytes).
2645 * 2'b10: Begin. This is the first data payload of this transaction
2646 (which is larger than 188 bytes).
2647 * 2'b00: Mid. This is the middle payload of this transaction
2648 (which is larger than 188 bytes).
2649 * 2'b01: End. This is the last payload of this transaction (which
2650 is larger than 188 bytes). */
2651 uint32_t hubaddr : 7; /**< Hub Address (HubAddr)
2652 This field holds the device address of the transaction
2653 translator's hub. */
2654 uint32_t prtaddr : 7; /**< Port Address (PrtAddr)
2655 This field is the port number of the recipient transaction
2658 struct cvmx_usbcx_hcspltx_s cn30xx;
2659 struct cvmx_usbcx_hcspltx_s cn31xx;
2660 struct cvmx_usbcx_hcspltx_s cn50xx;
2661 struct cvmx_usbcx_hcspltx_s cn52xx;
2662 struct cvmx_usbcx_hcspltx_s cn52xxp1;
2663 struct cvmx_usbcx_hcspltx_s cn56xx;
2664 struct cvmx_usbcx_hcspltx_s cn56xxp1;
2666 typedef union cvmx_usbcx_hcspltx cvmx_usbcx_hcspltx_t;
2669 * cvmx_usbc#_hctsiz#
2671 * Host Channel-n Transfer Size Register (HCTSIZ)
2674 union cvmx_usbcx_hctsizx
2677 struct cvmx_usbcx_hctsizx_s
2679 uint32_t dopng : 1; /**< Do Ping (DoPng)
2680 Setting this field to 1 directs the host to do PING protocol. */
2681 uint32_t pid : 2; /**< PID (Pid)
2682 The application programs this field with the type of PID to use
2683 for the initial transaction. The host will maintain this field for the
2684 rest of the transfer.
2688 * 2'b11: MDATA (non-control)/SETUP (control) */
2689 uint32_t pktcnt : 10; /**< Packet Count (PktCnt)
2690 This field is programmed by the application with the expected
2691 number of packets to be transmitted (OUT) or received (IN).
2692 The host decrements this count on every successful
2693 transmission or reception of an OUT/IN packet. Once this count
2694 reaches zero, the application is interrupted to indicate normal
2696 uint32_t xfersize : 19; /**< Transfer Size (XferSize)
2697 For an OUT, this field is the number of data bytes the host will
2698 send during the transfer.
2699 For an IN, this field is the buffer size that the application has
2700 reserved for the transfer. The application is expected to
2701 program this field as an integer multiple of the maximum packet
2702 size for IN transactions (periodic and non-periodic). */
2704 struct cvmx_usbcx_hctsizx_s cn30xx;
2705 struct cvmx_usbcx_hctsizx_s cn31xx;
2706 struct cvmx_usbcx_hctsizx_s cn50xx;
2707 struct cvmx_usbcx_hctsizx_s cn52xx;
2708 struct cvmx_usbcx_hctsizx_s cn52xxp1;
2709 struct cvmx_usbcx_hctsizx_s cn56xx;
2710 struct cvmx_usbcx_hctsizx_s cn56xxp1;
2712 typedef union cvmx_usbcx_hctsizx cvmx_usbcx_hctsizx_t;
2717 * Host Frame Interval Register (HFIR)
2719 * This register stores the frame interval information for the current speed to which the O2P USB core has enumerated.
2721 union cvmx_usbcx_hfir
2724 struct cvmx_usbcx_hfir_s
2726 uint32_t reserved_16_31 : 16;
2727 uint32_t frint : 16; /**< Frame Interval (FrInt)
2728 The value that the application programs to this field specifies
2729 the interval between two consecutive SOFs (FS) or micro-
2730 SOFs (HS) or Keep-Alive tokens (HS). This field contains the
2731 number of PHY clocks that constitute the required frame
2732 interval. The default value set in this field for a FS operation
2733 when the PHY clock frequency is 60 MHz. The application can
2734 write a value to this register only after the Port Enable bit of
2735 the Host Port Control and Status register (HPRT.PrtEnaPort)
2736 has been set. If no value is programmed, the core calculates
2737 the value based on the PHY clock specified in the FS/LS PHY
2738 Clock Select field of the Host Configuration register
2739 (HCFG.FSLSPclkSel). Do not change the value of this field
2740 after the initial configuration.
2741 * 125 us (PHY clock frequency for HS)
2742 * 1 ms (PHY clock frequency for FS/LS) */
2744 struct cvmx_usbcx_hfir_s cn30xx;
2745 struct cvmx_usbcx_hfir_s cn31xx;
2746 struct cvmx_usbcx_hfir_s cn50xx;
2747 struct cvmx_usbcx_hfir_s cn52xx;
2748 struct cvmx_usbcx_hfir_s cn52xxp1;
2749 struct cvmx_usbcx_hfir_s cn56xx;
2750 struct cvmx_usbcx_hfir_s cn56xxp1;
2752 typedef union cvmx_usbcx_hfir cvmx_usbcx_hfir_t;
2757 * Host Frame Number/Frame Time Remaining Register (HFNUM)
2759 * This register indicates the current frame number.
2760 * It also indicates the time remaining (in terms of the number of PHY clocks)
2761 * in the current (micro)frame.
2763 union cvmx_usbcx_hfnum
2766 struct cvmx_usbcx_hfnum_s
2768 uint32_t frrem : 16; /**< Frame Time Remaining (FrRem)
2769 Indicates the amount of time remaining in the current
2770 microframe (HS) or frame (FS/LS), in terms of PHY clocks.
2771 This field decrements on each PHY clock. When it reaches
2772 zero, this field is reloaded with the value in the Frame Interval
2773 register and a new SOF is transmitted on the USB. */
2774 uint32_t frnum : 16; /**< Frame Number (FrNum)
2775 This field increments when a new SOF is transmitted on the
2776 USB, and is reset to 0 when it reaches 16'h3FFF. */
2778 struct cvmx_usbcx_hfnum_s cn30xx;
2779 struct cvmx_usbcx_hfnum_s cn31xx;
2780 struct cvmx_usbcx_hfnum_s cn50xx;
2781 struct cvmx_usbcx_hfnum_s cn52xx;
2782 struct cvmx_usbcx_hfnum_s cn52xxp1;
2783 struct cvmx_usbcx_hfnum_s cn56xx;
2784 struct cvmx_usbcx_hfnum_s cn56xxp1;
2786 typedef union cvmx_usbcx_hfnum cvmx_usbcx_hfnum_t;
2791 * Host Port Control and Status Register (HPRT)
2793 * This register is available in both Host and Device modes.
2794 * Currently, the OTG Host supports only one port.
2795 * A single register holds USB port-related information such as USB reset, enable, suspend, resume,
2796 * connect status, and test mode for each port. The R_SS_WC bits in this register can trigger an
2797 * interrupt to the application through the Host Port Interrupt bit of the Core Interrupt
2798 * register (GINTSTS.PrtInt). On a Port Interrupt, the application must read this register and clear
2799 * the bit that caused the interrupt. For the R_SS_WC bits, the application must write a 1 to the bit
2800 * to clear the interrupt.
2802 union cvmx_usbcx_hprt
2805 struct cvmx_usbcx_hprt_s
2807 uint32_t reserved_19_31 : 13;
2808 uint32_t prtspd : 2; /**< Port Speed (PrtSpd)
2809 Indicates the speed of the device attached to this port.
2813 * 2'b11: Reserved */
2814 uint32_t prttstctl : 4; /**< Port Test Control (PrtTstCtl)
2815 The application writes a nonzero value to this field to put
2816 the port into a Test mode, and the corresponding pattern is
2817 signaled on the port.
2818 * 4'b0000: Test mode disabled
2819 * 4'b0001: Test_J mode
2820 * 4'b0010: Test_K mode
2821 * 4'b0011: Test_SE0_NAK mode
2822 * 4'b0100: Test_Packet mode
2823 * 4'b0101: Test_Force_Enable
2825 PrtSpd must be zero (i.e. the interface must be in high-speed
2826 mode) to use the PrtTstCtl test modes. */
2827 uint32_t prtpwr : 1; /**< Port Power (PrtPwr)
2828 The application uses this field to control power to this port,
2829 and the core clears this bit on an overcurrent condition.
2832 uint32_t prtlnsts : 2; /**< Port Line Status (PrtLnSts)
2833 Indicates the current logic level USB data lines
2834 * Bit [10]: Logic level of D-
2835 * Bit [11]: Logic level of D+ */
2836 uint32_t reserved_9_9 : 1;
2837 uint32_t prtrst : 1; /**< Port Reset (PrtRst)
2838 When the application sets this bit, a reset sequence is
2839 started on this port. The application must time the reset
2840 period and clear this bit after the reset sequence is
2842 * 1'b0: Port not in reset
2843 * 1'b1: Port in reset
2844 The application must leave this bit set for at least a
2845 minimum duration mentioned below to start a reset on the
2846 port. The application can leave it set for another 10 ms in
2847 addition to the required minimum duration, before clearing
2848 the bit, even though there is no maximum limit set by the
2851 * Full speed/Low speed: 10 ms */
2852 uint32_t prtsusp : 1; /**< Port Suspend (PrtSusp)
2853 The application sets this bit to put this port in Suspend
2854 mode. The core only stops sending SOFs when this is set.
2855 To stop the PHY clock, the application must set the Port
2856 Clock Stop bit, which will assert the suspend input pin of
2858 The read value of this bit reflects the current suspend
2859 status of the port. This bit is cleared by the core after a
2860 remote wakeup signal is detected or the application sets
2861 the Port Reset bit or Port Resume bit in this register or the
2862 Resume/Remote Wakeup Detected Interrupt bit or
2863 Disconnect Detected Interrupt bit in the Core Interrupt
2864 register (GINTSTS.WkUpInt or GINTSTS.DisconnInt,
2866 * 1'b0: Port not in Suspend mode
2867 * 1'b1: Port in Suspend mode */
2868 uint32_t prtres : 1; /**< Port Resume (PrtRes)
2869 The application sets this bit to drive resume signaling on
2870 the port. The core continues to drive the resume signal
2871 until the application clears this bit.
2872 If the core detects a USB remote wakeup sequence, as
2873 indicated by the Port Resume/Remote Wakeup Detected
2874 Interrupt bit of the Core Interrupt register
2875 (GINTSTS.WkUpInt), the core starts driving resume
2876 signaling without application intervention and clears this bit
2877 when it detects a disconnect condition. The read value of
2878 this bit indicates whether the core is currently driving
2880 * 1'b0: No resume driven
2881 * 1'b1: Resume driven */
2882 uint32_t prtovrcurrchng : 1; /**< Port Overcurrent Change (PrtOvrCurrChng)
2883 The core sets this bit when the status of the Port
2884 Overcurrent Active bit (bit 4) in this register changes. */
2885 uint32_t prtovrcurract : 1; /**< Port Overcurrent Active (PrtOvrCurrAct)
2886 Indicates the overcurrent condition of the port.
2887 * 1'b0: No overcurrent condition
2888 * 1'b1: Overcurrent condition */
2889 uint32_t prtenchng : 1; /**< Port Enable/Disable Change (PrtEnChng)
2890 The core sets this bit when the status of the Port Enable bit
2891 [2] of this register changes. */
2892 uint32_t prtena : 1; /**< Port Enable (PrtEna)
2893 A port is enabled only by the core after a reset sequence,
2894 and is disabled by an overcurrent condition, a disconnect
2895 condition, or by the application clearing this bit. The
2896 application cannot set this bit by a register write. It can only
2897 clear it to disable the port. This bit does not trigger any
2898 interrupt to the application.
2899 * 1'b0: Port disabled
2900 * 1'b1: Port enabled */
2901 uint32_t prtconndet : 1; /**< Port Connect Detected (PrtConnDet)
2902 The core sets this bit when a device connection is detected
2903 to trigger an interrupt to the application using the Host Port
2904 Interrupt bit of the Core Interrupt register (GINTSTS.PrtInt).
2905 The application must write a 1 to this bit to clear the
2907 uint32_t prtconnsts : 1; /**< Port Connect Status (PrtConnSts)
2908 * 0: No device is attached to the port.
2909 * 1: A device is attached to the port. */
2911 struct cvmx_usbcx_hprt_s cn30xx;
2912 struct cvmx_usbcx_hprt_s cn31xx;
2913 struct cvmx_usbcx_hprt_s cn50xx;
2914 struct cvmx_usbcx_hprt_s cn52xx;
2915 struct cvmx_usbcx_hprt_s cn52xxp1;
2916 struct cvmx_usbcx_hprt_s cn56xx;
2917 struct cvmx_usbcx_hprt_s cn56xxp1;
2919 typedef union cvmx_usbcx_hprt cvmx_usbcx_hprt_t;
2922 * cvmx_usbc#_hptxfsiz
2924 * Host Periodic Transmit FIFO Size Register (HPTXFSIZ)
2926 * This register holds the size and the memory start address of the Periodic TxFIFO, as shown in Figures 310 and 311.
2928 union cvmx_usbcx_hptxfsiz
2931 struct cvmx_usbcx_hptxfsiz_s
2933 uint32_t ptxfsize : 16; /**< Host Periodic TxFIFO Depth (PTxFSize)
2934 This value is in terms of 32-bit words.
2935 * Minimum value is 16
2936 * Maximum value is 32768 */
2937 uint32_t ptxfstaddr : 16; /**< Host Periodic TxFIFO Start Address (PTxFStAddr) */
2939 struct cvmx_usbcx_hptxfsiz_s cn30xx;
2940 struct cvmx_usbcx_hptxfsiz_s cn31xx;
2941 struct cvmx_usbcx_hptxfsiz_s cn50xx;
2942 struct cvmx_usbcx_hptxfsiz_s cn52xx;
2943 struct cvmx_usbcx_hptxfsiz_s cn52xxp1;
2944 struct cvmx_usbcx_hptxfsiz_s cn56xx;
2945 struct cvmx_usbcx_hptxfsiz_s cn56xxp1;
2947 typedef union cvmx_usbcx_hptxfsiz cvmx_usbcx_hptxfsiz_t;
2950 * cvmx_usbc#_hptxsts
2952 * Host Periodic Transmit FIFO/Queue Status Register (HPTXSTS)
2954 * This read-only register contains the free space information for the Periodic TxFIFO and
2955 * the Periodic Transmit Request Queue
2957 union cvmx_usbcx_hptxsts
2960 struct cvmx_usbcx_hptxsts_s
2962 uint32_t ptxqtop : 8; /**< Top of the Periodic Transmit Request Queue (PTxQTop)
2963 This indicates the entry in the Periodic Tx Request Queue that
2964 is currently being processes by the MAC.
2965 This register is used for debugging.
2966 * Bit [31]: Odd/Even (micro)frame
2967 - 1'b0: send in even (micro)frame
2968 - 1'b1: send in odd (micro)frame
2969 * Bits [30:27]: Channel/endpoint number
2970 * Bits [26:25]: Type
2972 - 2'b01: Zero-length packet
2974 - 2'b11: Disable channel command
2975 * Bit [24]: Terminate (last entry for the selected
2976 channel/endpoint) */
2977 uint32_t ptxqspcavail : 8; /**< Periodic Transmit Request Queue Space Available
2979 Indicates the number of free locations available to be written in
2980 the Periodic Transmit Request Queue. This queue holds both
2981 IN and OUT requests.
2982 * 8'h0: Periodic Transmit Request Queue is full
2983 * 8'h1: 1 location available
2984 * 8'h2: 2 locations available
2985 * n: n locations available (0..8)
2986 * Others: Reserved */
2987 uint32_t ptxfspcavail : 16; /**< Periodic Transmit Data FIFO Space Available (PTxFSpcAvail)
2988 Indicates the number of free locations available to be written to
2989 in the Periodic TxFIFO.
2990 Values are in terms of 32-bit words
2991 * 16'h0: Periodic TxFIFO is full
2992 * 16'h1: 1 word available
2993 * 16'h2: 2 words available
2994 * 16'hn: n words available (where 0..32768)
2995 * 16'h8000: 32768 words available
2996 * Others: Reserved */
2998 struct cvmx_usbcx_hptxsts_s cn30xx;
2999 struct cvmx_usbcx_hptxsts_s cn31xx;
3000 struct cvmx_usbcx_hptxsts_s cn50xx;
3001 struct cvmx_usbcx_hptxsts_s cn52xx;
3002 struct cvmx_usbcx_hptxsts_s cn52xxp1;
3003 struct cvmx_usbcx_hptxsts_s cn56xx;
3004 struct cvmx_usbcx_hptxsts_s cn56xxp1;
3006 typedef union cvmx_usbcx_hptxsts cvmx_usbcx_hptxsts_t;
3009 * cvmx_usbc#_nptxdfifo#
3011 * NPTX Data Fifo (NPTXDFIFO)
3013 * A slave mode application uses this register to access the Tx FIFO for channel n.
3015 union cvmx_usbcx_nptxdfifox
3018 struct cvmx_usbcx_nptxdfifox_s
3020 uint32_t data : 32; /**< Reserved */
3022 struct cvmx_usbcx_nptxdfifox_s cn30xx;
3023 struct cvmx_usbcx_nptxdfifox_s cn31xx;
3024 struct cvmx_usbcx_nptxdfifox_s cn50xx;
3025 struct cvmx_usbcx_nptxdfifox_s cn52xx;
3026 struct cvmx_usbcx_nptxdfifox_s cn52xxp1;
3027 struct cvmx_usbcx_nptxdfifox_s cn56xx;
3028 struct cvmx_usbcx_nptxdfifox_s cn56xxp1;
3030 typedef union cvmx_usbcx_nptxdfifox cvmx_usbcx_nptxdfifox_t;
3033 * cvmx_usbc#_pcgcctl
3035 * Power and Clock Gating Control Register (PCGCCTL)
3037 * The application can use this register to control the core's power-down and clock gating features.
3039 union cvmx_usbcx_pcgcctl
3042 struct cvmx_usbcx_pcgcctl_s
3044 uint32_t reserved_5_31 : 27;
3045 uint32_t physuspended : 1; /**< PHY Suspended. (PhySuspended)
3046 Indicates that the PHY has been suspended. After the
3047 application sets the Stop Pclk bit (bit 0), this bit is updated once
3048 the PHY is suspended.
3049 Since the UTMI+ PHY suspend is controlled through a port, the
3050 UTMI+ PHY is suspended immediately after Stop Pclk is set.
3051 However, the ULPI PHY takes a few clocks to suspend,
3052 because the suspend information is conveyed through the ULPI
3053 protocol to the ULPI PHY. */
3054 uint32_t rstpdwnmodule : 1; /**< Reset Power-Down Modules (RstPdwnModule)
3055 This bit is valid only in Partial Power-Down mode. The
3056 application sets this bit when the power is turned off. The
3057 application clears this bit after the power is turned on and the
3059 uint32_t pwrclmp : 1; /**< Power Clamp (PwrClmp)
3060 This bit is only valid in Partial Power-Down mode. The
3061 application sets this bit before the power is turned off to clamp
3062 the signals between the power-on modules and the power-off
3063 modules. The application clears the bit to disable the clamping
3064 before the power is turned on. */
3065 uint32_t gatehclk : 1; /**< Gate Hclk (GateHclk)
3066 The application sets this bit to gate hclk to modules other than
3067 the AHB Slave and Master and wakeup logic when the USB is
3068 suspended or the session is not valid. The application clears
3069 this bit when the USB is resumed or a new session starts. */
3070 uint32_t stoppclk : 1; /**< Stop Pclk (StopPclk)
3071 The application sets this bit to stop the PHY clock (phy_clk)
3072 when the USB is suspended, the session is not valid, or the
3073 device is disconnected. The application clears this bit when the
3074 USB is resumed or a new session starts. */
3076 struct cvmx_usbcx_pcgcctl_s cn30xx;
3077 struct cvmx_usbcx_pcgcctl_s cn31xx;
3078 struct cvmx_usbcx_pcgcctl_s cn50xx;
3079 struct cvmx_usbcx_pcgcctl_s cn52xx;
3080 struct cvmx_usbcx_pcgcctl_s cn52xxp1;
3081 struct cvmx_usbcx_pcgcctl_s cn56xx;
3082 struct cvmx_usbcx_pcgcctl_s cn56xxp1;
3084 typedef union cvmx_usbcx_pcgcctl cvmx_usbcx_pcgcctl_t;
projects / karo-tx-linux.git / blob