2 * Copyright (c) 2009,2010 One Laptop per Child
4 * This program is free software. You can redistribute it and/or
5 * modify it under the terms of version 2 of the GNU General Public
6 * License as published by the Free Software Foundation.
9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
11 #include <linux/acpi.h>
12 #include <linux/delay.h>
13 #include <linux/gpio.h>
16 /* TODO: this eventually belongs in linux/vx855.h */
17 #define NR_VX855_GPI 14
18 #define NR_VX855_GPO 13
19 #define NR_VX855_GPIO 15
21 #define VX855_GPI(n) (n)
22 #define VX855_GPO(n) (NR_VX855_GPI + (n))
23 #define VX855_GPIO(n) (NR_VX855_GPI + NR_VX855_GPO + (n))
25 #include "olpc_dcon.h"
27 /* Hardware setup on the XO 1.5:
28 * DCONLOAD connects to VX855_GPIO1 (not SMBCK2)
29 * DCONBLANK connects to VX855_GPIO8 (not SSPICLK) unused in driver
30 * DCONSTAT0 connects to VX855_GPI10 (not SSPISDI)
31 * DCONSTAT1 connects to VX855_GPI11 (not nSSPISS)
32 * DCONIRQ connects to VX855_GPIO12
33 * DCONSMBDATA connects to VX855 graphics CRTSPD
34 * DCONSMBCLK connects to VX855 graphics CRTSPCLK
37 #define VX855_GENL_PURPOSE_OUTPUT 0x44c /* PMIO_Rx4c-4f */
38 #define VX855_GPI_STATUS_CHG 0x450 /* PMIO_Rx50 */
39 #define VX855_GPI_SCI_SMI 0x452 /* PMIO_Rx52 */
40 #define BIT_GPIO12 0x40
42 #define PREFIX "OLPC DCON:"
44 static void dcon_clear_irq(void)
46 /* irq status will appear in PMIO_Rx50[6] (RW1C) on gpio12 */
47 outb(BIT_GPIO12, VX855_GPI_STATUS_CHG);
50 static int dcon_was_irq(void)
54 /* irq status will appear in PMIO_Rx50[6] on gpio12 */
55 tmp = inb(VX855_GPI_STATUS_CHG);
56 return !!(tmp & BIT_GPIO12);
61 static int dcon_init_xo_1_5(struct dcon_priv *dcon)
67 /* set PMIO_Rx52[6] to enable SCI/SMI on gpio12 */
68 outb(inb(VX855_GPI_SCI_SMI)|BIT_GPIO12, VX855_GPI_SCI_SMI);
70 /* Determine the current state of DCONLOAD, likely set by firmware */
72 dcon->curr_src = (inl(VX855_GENL_PURPOSE_OUTPUT) & 0x1000) ?
73 DCON_SOURCE_CPU : DCON_SOURCE_DCON;
74 dcon->pending_src = dcon->curr_src;
76 /* we're sharing the IRQ with ACPI */
77 irq = acpi_gbl_FADT.sci_interrupt;
78 if (request_irq(irq, &dcon_interrupt, IRQF_SHARED, "DCON", dcon)) {
79 pr_err("DCON (IRQ%d) allocation failed\n", irq);
86 static void set_i2c_line(int sda, int scl)
89 unsigned int port = 0x26;
91 /* FIXME: This directly accesses the CRT GPIO controller !!! */
112 static void dcon_wiggle_xo_1_5(void)
117 * According to HiMax, when powering the DCON up we should hold
118 * SMB_DATA high for 8 SMB_CLK cycles. This will force the DCON
119 * state machine to reset to a (sane) initial state. Mitch Bradley
120 * did some testing and discovered that holding for 16 SMB_CLK cycles
121 * worked a lot more reliably, so that's what we do here.
125 for (x = 0; x < 16; x++) {
133 /* set PMIO_Rx52[6] to enable SCI/SMI on gpio12 */
134 outb(inb(VX855_GPI_SCI_SMI)|BIT_GPIO12, VX855_GPI_SCI_SMI);
137 static void dcon_set_dconload_xo_1_5(int val)
139 gpio_set_value(VX855_GPIO(1), val);
142 static int dcon_read_status_xo_1_5(u8 *status)
147 /* i believe this is the same as "inb(0x44b) & 3" */
148 *status = gpio_get_value(VX855_GPI(10));
149 *status |= gpio_get_value(VX855_GPI(11)) << 1;
156 struct dcon_platform_data dcon_pdata_xo_1_5 = {
157 .init = dcon_init_xo_1_5,
158 .bus_stabilize_wiggle = dcon_wiggle_xo_1_5,
159 .set_dconload = dcon_set_dconload_xo_1_5,
160 .read_status = dcon_read_status_xo_1_5,