3 * This file is provided under a dual BSD/GPLv2 license. When using or
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8 * Copyright(c) 2015 Intel Corporation.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
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50 #include <linux/delay.h>
56 * The EPROM is logically divided into two partitions:
57 * partition 0: the first 128K, visible from PCI ROM BAR
58 * partition 1: the rest
60 #define P0_SIZE (128 * 1024)
61 #define P1_START P0_SIZE
63 /* largest erase size supported by the controller */
64 #define SIZE_32KB (32 * 1024)
65 #define MASK_32KB (SIZE_32KB - 1)
67 /* controller page size, in bytes */
68 #define EP_PAGE_SIZE 256
69 #define EEP_PAGE_MASK (EP_PAGE_SIZE - 1)
71 /* controller commands */
74 #define CMD_PAGE_PROGRAM(addr) ((0x02 << CMD_SHIFT) | addr)
75 #define CMD_READ_DATA(addr) ((0x03 << CMD_SHIFT) | addr)
76 #define CMD_READ_SR1 ((0x05 << CMD_SHIFT))
77 #define CMD_WRITE_ENABLE ((0x06 << CMD_SHIFT))
78 #define CMD_SECTOR_ERASE_32KB(addr) ((0x52 << CMD_SHIFT) | addr)
79 #define CMD_CHIP_ERASE ((0x60 << CMD_SHIFT))
80 #define CMD_READ_MANUF_DEV_ID ((0x90 << CMD_SHIFT))
81 #define CMD_RELEASE_POWERDOWN_NOID ((0xab << CMD_SHIFT))
83 /* controller interface speeds */
84 #define EP_SPEED_FULL 0x2 /* full speed */
86 /* controller status register 1 bits */
87 #define SR1_BUSY 0x1ull /* the BUSY bit in SR1 */
89 /* sleep length while waiting for controller */
90 #define WAIT_SLEEP_US 100 /* must be larger than 5 (see usage) */
91 #define COUNT_DELAY_SEC(n) ((n) * (1000000/WAIT_SLEEP_US))
94 #define EPROM_WP_N (1ull << 14) /* EPROM write line */
97 * Use the EP mutex to guard against other callers from within the driver.
98 * Also covers usage of eprom_available.
100 static DEFINE_MUTEX(eprom_mutex);
101 static int eprom_available; /* default: not available */
104 * Turn on external enable line that allows writing on the flash.
106 static void write_enable(struct hfi1_devdata *dd)
109 write_csr(dd, ASIC_GPIO_OUT,
110 read_csr(dd, ASIC_GPIO_OUT) | EPROM_WP_N);
112 write_csr(dd, ASIC_GPIO_OE,
113 read_csr(dd, ASIC_GPIO_OE) | EPROM_WP_N);
117 * Turn off external enable line that allows writing on the flash.
119 static void write_disable(struct hfi1_devdata *dd)
122 write_csr(dd, ASIC_GPIO_OUT,
123 read_csr(dd, ASIC_GPIO_OUT) & ~EPROM_WP_N);
125 write_csr(dd, ASIC_GPIO_OE,
126 read_csr(dd, ASIC_GPIO_OE) & ~EPROM_WP_N);
130 * Wait for the device to become not busy. Must be called after all
131 * write or erase operations.
133 static int wait_for_not_busy(struct hfi1_devdata *dd)
135 unsigned long count = 0;
139 /* starts page mode */
140 write_csr(dd, ASIC_EEP_ADDR_CMD, CMD_READ_SR1);
142 udelay(WAIT_SLEEP_US);
143 usleep_range(WAIT_SLEEP_US - 5, WAIT_SLEEP_US + 5);
145 reg = read_csr(dd, ASIC_EEP_DATA);
146 if ((reg & SR1_BUSY) == 0)
148 /* 200s is the largest time for a 128Mb device */
149 if (count > COUNT_DELAY_SEC(200)) {
150 dd_dev_err(dd, "waited too long for SPI FLASH busy to clear - failing\n");
152 break; /* break, not goto - must stop page mode */
156 /* stop page mode with a NOP */
157 write_csr(dd, ASIC_EEP_ADDR_CMD, CMD_NOP);
163 * Read the device ID from the SPI controller.
165 static u32 read_device_id(struct hfi1_devdata *dd)
167 /* read the Manufacture Device ID */
168 write_csr(dd, ASIC_EEP_ADDR_CMD, CMD_READ_MANUF_DEV_ID);
169 return (u32)read_csr(dd, ASIC_EEP_DATA);
173 * Erase the whole flash.
175 static int erase_chip(struct hfi1_devdata *dd)
181 write_csr(dd, ASIC_EEP_ADDR_CMD, CMD_WRITE_ENABLE);
182 write_csr(dd, ASIC_EEP_ADDR_CMD, CMD_CHIP_ERASE);
183 ret = wait_for_not_busy(dd);
191 * Erase a range using the 32KB erase command.
193 static int erase_32kb_range(struct hfi1_devdata *dd, u32 start, u32 end)
200 if ((start & MASK_32KB) || (end & MASK_32KB)) {
202 "%s: non-aligned range (0x%x,0x%x) for a 32KB erase\n",
203 __func__, start, end);
209 for (; start < end; start += SIZE_32KB) {
210 write_csr(dd, ASIC_EEP_ADDR_CMD, CMD_WRITE_ENABLE);
211 write_csr(dd, ASIC_EEP_ADDR_CMD,
212 CMD_SECTOR_ERASE_32KB(start));
213 ret = wait_for_not_busy(dd);
225 * Read a 256 byte (64 dword) EPROM page.
226 * All callers have verified the offset is at a page boundary.
228 static void read_page(struct hfi1_devdata *dd, u32 offset, u32 *result)
232 write_csr(dd, ASIC_EEP_ADDR_CMD, CMD_READ_DATA(offset));
233 for (i = 0; i < EP_PAGE_SIZE/sizeof(u32); i++)
234 result[i] = (u32)read_csr(dd, ASIC_EEP_DATA);
235 write_csr(dd, ASIC_EEP_ADDR_CMD, CMD_NOP); /* close open page */
239 * Read length bytes starting at offset. Copy to user address addr.
241 static int read_length(struct hfi1_devdata *dd, u32 start, u32 len, u64 addr)
244 u32 buffer[EP_PAGE_SIZE/sizeof(u32)];
247 /* reject anything not on an EPROM page boundary */
248 if ((start & EEP_PAGE_MASK) || (len & EEP_PAGE_MASK))
251 for (offset = 0; offset < len; offset += EP_PAGE_SIZE) {
252 read_page(dd, start + offset, buffer);
253 if (copy_to_user((void __user *)(addr + offset),
254 buffer, EP_PAGE_SIZE)) {
265 * Write a 256 byte (64 dword) EPROM page.
266 * All callers have verified the offset is at a page boundary.
268 static int write_page(struct hfi1_devdata *dd, u32 offset, u32 *data)
272 write_csr(dd, ASIC_EEP_ADDR_CMD, CMD_WRITE_ENABLE);
273 write_csr(dd, ASIC_EEP_DATA, data[0]);
274 write_csr(dd, ASIC_EEP_ADDR_CMD, CMD_PAGE_PROGRAM(offset));
275 for (i = 1; i < EP_PAGE_SIZE/sizeof(u32); i++)
276 write_csr(dd, ASIC_EEP_DATA, data[i]);
277 /* will close the open page */
278 return wait_for_not_busy(dd);
282 * Write length bytes starting at offset. Read from user address addr.
284 static int write_length(struct hfi1_devdata *dd, u32 start, u32 len, u64 addr)
287 u32 buffer[EP_PAGE_SIZE/sizeof(u32)];
290 /* reject anything not on an EPROM page boundary */
291 if ((start & EEP_PAGE_MASK) || (len & EEP_PAGE_MASK))
296 for (offset = 0; offset < len; offset += EP_PAGE_SIZE) {
297 if (copy_from_user(buffer, (void __user *)(addr + offset),
302 ret = write_page(dd, start + offset, buffer);
313 * Perform the given operation on the EPROM. Called from user space. The
314 * user credentials have already been checked.
316 * Return 0 on success, -ERRNO on error
318 int handle_eprom_command(const struct hfi1_cmd *cmd)
320 struct hfi1_devdata *dd;
325 * The EPROM is per-device, so use unit 0 as that will always
330 pr_err("%s: cannot find unit 0!\n", __func__);
334 /* lock against other callers touching the ASIC block */
335 mutex_lock(&eprom_mutex);
337 /* some platforms do not have an EPROM */
338 if (!eprom_available) {
343 /* lock against the other HFI on another OS */
344 ret = acquire_hw_mutex(dd);
347 "%s: unable to acquire hw mutex, no EPROM support\n",
352 dd_dev_info(dd, "%s: cmd: type %d, len 0x%x, addr 0x%016llx\n",
353 __func__, cmd->type, cmd->len, cmd->addr);
356 case HFI1_CMD_EP_INFO:
357 if (cmd->len != sizeof(u32)) {
361 dev_id = read_device_id(dd);
362 /* addr points to a u32 user buffer */
363 if (copy_to_user((void __user *)cmd->addr, &dev_id,
367 case HFI1_CMD_EP_ERASE_CHIP:
368 ret = erase_chip(dd);
370 case HFI1_CMD_EP_ERASE_P0:
371 if (cmd->len != P0_SIZE) {
375 ret = erase_32kb_range(dd, 0, cmd->len);
377 case HFI1_CMD_EP_ERASE_P1:
378 /* check for overflow */
379 if (P1_START + cmd->len > ASIC_EEP_ADDR_CMD_EP_ADDR_MASK) {
383 ret = erase_32kb_range(dd, P1_START, P1_START + cmd->len);
385 case HFI1_CMD_EP_READ_P0:
386 if (cmd->len != P0_SIZE) {
390 ret = read_length(dd, 0, cmd->len, cmd->addr);
392 case HFI1_CMD_EP_READ_P1:
393 /* check for overflow */
394 if (P1_START + cmd->len > ASIC_EEP_ADDR_CMD_EP_ADDR_MASK) {
398 ret = read_length(dd, P1_START, cmd->len, cmd->addr);
400 case HFI1_CMD_EP_WRITE_P0:
401 if (cmd->len > P0_SIZE) {
405 ret = write_length(dd, 0, cmd->len, cmd->addr);
407 case HFI1_CMD_EP_WRITE_P1:
408 /* check for overflow */
409 if (P1_START + cmd->len > ASIC_EEP_ADDR_CMD_EP_ADDR_MASK) {
413 ret = write_length(dd, P1_START, cmd->len, cmd->addr);
416 dd_dev_err(dd, "%s: unexpected command %d\n",
417 __func__, cmd->type);
422 release_hw_mutex(dd);
424 mutex_unlock(&eprom_mutex);
429 * Initialize the EPROM handler.
431 int eprom_init(struct hfi1_devdata *dd)
435 /* only the discrete chip has an EPROM, nothing to do */
436 if (dd->pcidev->device != PCI_DEVICE_ID_INTEL0)
439 /* lock against other callers */
440 mutex_lock(&eprom_mutex);
441 if (eprom_available) /* already initialized */
445 * Lock against the other HFI on another OS - the mutex above
446 * would have caught anything in this driver. It is OK if
447 * both OSes reset the EPROM - as long as they don't do it at
450 ret = acquire_hw_mutex(dd);
453 "%s: unable to acquire hw mutex, no EPROM support\n",
458 /* reset EPROM to be sure it is in a good state */
461 write_csr(dd, ASIC_EEP_CTL_STAT,
462 ASIC_EEP_CTL_STAT_EP_RESET_SMASK);
463 /* clear reset, set speed */
464 write_csr(dd, ASIC_EEP_CTL_STAT,
465 EP_SPEED_FULL << ASIC_EEP_CTL_STAT_RATE_SPI_SHIFT);
467 /* wake the device with command "release powerdown NoID" */
468 write_csr(dd, ASIC_EEP_ADDR_CMD, CMD_RELEASE_POWERDOWN_NOID);
471 release_hw_mutex(dd);
473 mutex_unlock(&eprom_mutex);