drivers/staging/rdma/hfi1/verbs.c

   1 /*
   2  *
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
   4  * redistributing this file, you may do so under either license.
   5  *
   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2015 Intel Corporation.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of version 2 of the GNU General Public License as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but
  15  * WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * General Public License for more details.
  18  *
  19  * BSD LICENSE
  20  *
  21  * Copyright(c) 2015 Intel Corporation.
  22  *
  23  * Redistribution and use in source and binary forms, with or without
  24  * modification, are permitted provided that the following conditions
  25  * are met:
  26  *
  27  *  - Redistributions of source code must retain the above copyright
  28  *    notice, this list of conditions and the following disclaimer.
  29  *  - Redistributions in binary form must reproduce the above copyright
  30  *    notice, this list of conditions and the following disclaimer in
  31  *    the documentation and/or other materials provided with the
  32  *    distribution.
  33  *  - Neither the name of Intel Corporation nor the names of its
  34  *    contributors may be used to endorse or promote products derived
  35  *    from this software without specific prior written permission.
  36  *
  37  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  38  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  39  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  40  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  41  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  42  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  43  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  44  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  45  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  46  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  47  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  48  *
  49  */
  50
  51 #include <rdma/ib_mad.h>
  52 #include <rdma/ib_user_verbs.h>
  53 #include <linux/io.h>
  54 #include <linux/module.h>
  55 #include <linux/utsname.h>
  56 #include <linux/rculist.h>
  57 #include <linux/mm.h>
  58 #include <linux/random.h>
  59 #include <linux/vmalloc.h>
  60
  61 #include "hfi.h"
  62 #include "common.h"
  63 #include "device.h"
  64 #include "trace.h"
  65 #include "qp.h"
  66 #include "sdma.h"
  67
  68 unsigned int hfi1_lkey_table_size = 16;
  69 module_param_named(lkey_table_size, hfi1_lkey_table_size, uint,
  70                    S_IRUGO);
  71 MODULE_PARM_DESC(lkey_table_size,
  72                  "LKEY table size in bits (2^n, 1 <= n <= 23)");
  73
  74 static unsigned int hfi1_max_pds = 0xFFFF;
  75 module_param_named(max_pds, hfi1_max_pds, uint, S_IRUGO);
  76 MODULE_PARM_DESC(max_pds,
  77                  "Maximum number of protection domains to support");
  78
  79 static unsigned int hfi1_max_ahs = 0xFFFF;
  80 module_param_named(max_ahs, hfi1_max_ahs, uint, S_IRUGO);
  81 MODULE_PARM_DESC(max_ahs, "Maximum number of address handles to support");
  82
  83 unsigned int hfi1_max_cqes = 0x2FFFF;
  84 module_param_named(max_cqes, hfi1_max_cqes, uint, S_IRUGO);
  85 MODULE_PARM_DESC(max_cqes,
  86                  "Maximum number of completion queue entries to support");
  87
  88 unsigned int hfi1_max_cqs = 0x1FFFF;
  89 module_param_named(max_cqs, hfi1_max_cqs, uint, S_IRUGO);
  90 MODULE_PARM_DESC(max_cqs, "Maximum number of completion queues to support");
  91
  92 unsigned int hfi1_max_qp_wrs = 0x3FFF;
  93 module_param_named(max_qp_wrs, hfi1_max_qp_wrs, uint, S_IRUGO);
  94 MODULE_PARM_DESC(max_qp_wrs, "Maximum number of QP WRs to support");
  95
  96 unsigned int hfi1_max_qps = 16384;
  97 module_param_named(max_qps, hfi1_max_qps, uint, S_IRUGO);
  98 MODULE_PARM_DESC(max_qps, "Maximum number of QPs to support");
  99
 100 unsigned int hfi1_max_sges = 0x60;
 101 module_param_named(max_sges, hfi1_max_sges, uint, S_IRUGO);
 102 MODULE_PARM_DESC(max_sges, "Maximum number of SGEs to support");
 103
 104 unsigned int hfi1_max_mcast_grps = 16384;
 105 module_param_named(max_mcast_grps, hfi1_max_mcast_grps, uint, S_IRUGO);
 106 MODULE_PARM_DESC(max_mcast_grps,
 107                  "Maximum number of multicast groups to support");
 108
 109 unsigned int hfi1_max_mcast_qp_attached = 16;
 110 module_param_named(max_mcast_qp_attached, hfi1_max_mcast_qp_attached,
 111                    uint, S_IRUGO);
 112 MODULE_PARM_DESC(max_mcast_qp_attached,
 113                  "Maximum number of attached QPs to support");
 114
 115 unsigned int hfi1_max_srqs = 1024;
 116 module_param_named(max_srqs, hfi1_max_srqs, uint, S_IRUGO);
 117 MODULE_PARM_DESC(max_srqs, "Maximum number of SRQs to support");
 118
 119 unsigned int hfi1_max_srq_sges = 128;
 120 module_param_named(max_srq_sges, hfi1_max_srq_sges, uint, S_IRUGO);
 121 MODULE_PARM_DESC(max_srq_sges, "Maximum number of SRQ SGEs to support");
 122
 123 unsigned int hfi1_max_srq_wrs = 0x1FFFF;
 124 module_param_named(max_srq_wrs, hfi1_max_srq_wrs, uint, S_IRUGO);
 125 MODULE_PARM_DESC(max_srq_wrs, "Maximum number of SRQ WRs support");
 126
 127 static void verbs_sdma_complete(
 128         struct sdma_txreq *cookie,
 129         int status,
 130         int drained);
 131
 132 /* Length of buffer to create verbs txreq cache name */
 133 #define TXREQ_NAME_LEN 24
 134
 135 /*
 136  * Note that it is OK to post send work requests in the SQE and ERR
 137  * states; hfi1_do_send() will process them and generate error
 138  * completions as per IB 1.2 C10-96.
 139  */
 140 const int ib_hfi1_state_ops[IB_QPS_ERR + 1] = {
 141         [IB_QPS_RESET] = 0,
 142         [IB_QPS_INIT] = HFI1_POST_RECV_OK,
 143         [IB_QPS_RTR] = HFI1_POST_RECV_OK | HFI1_PROCESS_RECV_OK,
 144         [IB_QPS_RTS] = HFI1_POST_RECV_OK | HFI1_PROCESS_RECV_OK |
 145             HFI1_POST_SEND_OK | HFI1_PROCESS_SEND_OK |
 146             HFI1_PROCESS_NEXT_SEND_OK,
 147         [IB_QPS_SQD] = HFI1_POST_RECV_OK | HFI1_PROCESS_RECV_OK |
 148             HFI1_POST_SEND_OK | HFI1_PROCESS_SEND_OK,
 149         [IB_QPS_SQE] = HFI1_POST_RECV_OK | HFI1_PROCESS_RECV_OK |
 150             HFI1_POST_SEND_OK | HFI1_FLUSH_SEND,
 151         [IB_QPS_ERR] = HFI1_POST_RECV_OK | HFI1_FLUSH_RECV |
 152             HFI1_POST_SEND_OK | HFI1_FLUSH_SEND,
 153 };
 154
 155 struct hfi1_ucontext {
 156         struct ib_ucontext ibucontext;
 157 };
 158
 159 static inline struct hfi1_ucontext *to_iucontext(struct ib_ucontext
 160                                                   *ibucontext)
 161 {
 162         return container_of(ibucontext, struct hfi1_ucontext, ibucontext);
 163 }
 164
 165 static inline void _hfi1_schedule_send(struct hfi1_qp *qp);
 166
 167 /*
 168  * Translate ib_wr_opcode into ib_wc_opcode.
 169  */
 170 const enum ib_wc_opcode ib_hfi1_wc_opcode[] = {
 171         [IB_WR_RDMA_WRITE] = IB_WC_RDMA_WRITE,
 172         [IB_WR_RDMA_WRITE_WITH_IMM] = IB_WC_RDMA_WRITE,
 173         [IB_WR_SEND] = IB_WC_SEND,
 174         [IB_WR_SEND_WITH_IMM] = IB_WC_SEND,
 175         [IB_WR_RDMA_READ] = IB_WC_RDMA_READ,
 176         [IB_WR_ATOMIC_CMP_AND_SWP] = IB_WC_COMP_SWAP,
 177         [IB_WR_ATOMIC_FETCH_AND_ADD] = IB_WC_FETCH_ADD
 178 };
 179
 180 /*
 181  * Length of header by opcode, 0 --> not supported
 182  */
 183 const u8 hdr_len_by_opcode[256] = {
 184         /* RC */
 185         [IB_OPCODE_RC_SEND_FIRST]                     = 12 + 8,
 186         [IB_OPCODE_RC_SEND_MIDDLE]                    = 12 + 8,
 187         [IB_OPCODE_RC_SEND_LAST]                      = 12 + 8,
 188         [IB_OPCODE_RC_SEND_LAST_WITH_IMMEDIATE]       = 12 + 8 + 4,
 189         [IB_OPCODE_RC_SEND_ONLY]                      = 12 + 8,
 190         [IB_OPCODE_RC_SEND_ONLY_WITH_IMMEDIATE]       = 12 + 8 + 4,
 191         [IB_OPCODE_RC_RDMA_WRITE_FIRST]               = 12 + 8 + 16,
 192         [IB_OPCODE_RC_RDMA_WRITE_MIDDLE]              = 12 + 8,
 193         [IB_OPCODE_RC_RDMA_WRITE_LAST]                = 12 + 8,
 194         [IB_OPCODE_RC_RDMA_WRITE_LAST_WITH_IMMEDIATE] = 12 + 8 + 4,
 195         [IB_OPCODE_RC_RDMA_WRITE_ONLY]                = 12 + 8 + 16,
 196         [IB_OPCODE_RC_RDMA_WRITE_ONLY_WITH_IMMEDIATE] = 12 + 8 + 20,
 197         [IB_OPCODE_RC_RDMA_READ_REQUEST]              = 12 + 8 + 16,
 198         [IB_OPCODE_RC_RDMA_READ_RESPONSE_FIRST]       = 12 + 8 + 4,
 199         [IB_OPCODE_RC_RDMA_READ_RESPONSE_MIDDLE]      = 12 + 8,
 200         [IB_OPCODE_RC_RDMA_READ_RESPONSE_LAST]        = 12 + 8 + 4,
 201         [IB_OPCODE_RC_RDMA_READ_RESPONSE_ONLY]        = 12 + 8 + 4,
 202         [IB_OPCODE_RC_ACKNOWLEDGE]                    = 12 + 8 + 4,
 203         [IB_OPCODE_RC_ATOMIC_ACKNOWLEDGE]             = 12 + 8 + 4,
 204         [IB_OPCODE_RC_COMPARE_SWAP]                   = 12 + 8 + 28,
 205         [IB_OPCODE_RC_FETCH_ADD]                      = 12 + 8 + 28,
 206         /* UC */
 207         [IB_OPCODE_UC_SEND_FIRST]                     = 12 + 8,
 208         [IB_OPCODE_UC_SEND_MIDDLE]                    = 12 + 8,
 209         [IB_OPCODE_UC_SEND_LAST]                      = 12 + 8,
 210         [IB_OPCODE_UC_SEND_LAST_WITH_IMMEDIATE]       = 12 + 8 + 4,
 211         [IB_OPCODE_UC_SEND_ONLY]                      = 12 + 8,
 212         [IB_OPCODE_UC_SEND_ONLY_WITH_IMMEDIATE]       = 12 + 8 + 4,
 213         [IB_OPCODE_UC_RDMA_WRITE_FIRST]               = 12 + 8 + 16,
 214         [IB_OPCODE_UC_RDMA_WRITE_MIDDLE]              = 12 + 8,
 215         [IB_OPCODE_UC_RDMA_WRITE_LAST]                = 12 + 8,
 216         [IB_OPCODE_UC_RDMA_WRITE_LAST_WITH_IMMEDIATE] = 12 + 8 + 4,
 217         [IB_OPCODE_UC_RDMA_WRITE_ONLY]                = 12 + 8 + 16,
 218         [IB_OPCODE_UC_RDMA_WRITE_ONLY_WITH_IMMEDIATE] = 12 + 8 + 20,
 219         /* UD */
 220         [IB_OPCODE_UD_SEND_ONLY]                      = 12 + 8 + 8,
 221         [IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE]       = 12 + 8 + 12
 222 };
 223
 224 static const opcode_handler opcode_handler_tbl[256] = {
 225         /* RC */
 226         [IB_OPCODE_RC_SEND_FIRST]                     = &hfi1_rc_rcv,
 227         [IB_OPCODE_RC_SEND_MIDDLE]                    = &hfi1_rc_rcv,
 228         [IB_OPCODE_RC_SEND_LAST]                      = &hfi1_rc_rcv,
 229         [IB_OPCODE_RC_SEND_LAST_WITH_IMMEDIATE]       = &hfi1_rc_rcv,
 230         [IB_OPCODE_RC_SEND_ONLY]                      = &hfi1_rc_rcv,
 231         [IB_OPCODE_RC_SEND_ONLY_WITH_IMMEDIATE]       = &hfi1_rc_rcv,
 232         [IB_OPCODE_RC_RDMA_WRITE_FIRST]               = &hfi1_rc_rcv,
 233         [IB_OPCODE_RC_RDMA_WRITE_MIDDLE]              = &hfi1_rc_rcv,
 234         [IB_OPCODE_RC_RDMA_WRITE_LAST]                = &hfi1_rc_rcv,
 235         [IB_OPCODE_RC_RDMA_WRITE_LAST_WITH_IMMEDIATE] = &hfi1_rc_rcv,
 236         [IB_OPCODE_RC_RDMA_WRITE_ONLY]                = &hfi1_rc_rcv,
 237         [IB_OPCODE_RC_RDMA_WRITE_ONLY_WITH_IMMEDIATE] = &hfi1_rc_rcv,
 238         [IB_OPCODE_RC_RDMA_READ_REQUEST]              = &hfi1_rc_rcv,
 239         [IB_OPCODE_RC_RDMA_READ_RESPONSE_FIRST]       = &hfi1_rc_rcv,
 240         [IB_OPCODE_RC_RDMA_READ_RESPONSE_MIDDLE]      = &hfi1_rc_rcv,
 241         [IB_OPCODE_RC_RDMA_READ_RESPONSE_LAST]        = &hfi1_rc_rcv,
 242         [IB_OPCODE_RC_RDMA_READ_RESPONSE_ONLY]        = &hfi1_rc_rcv,
 243         [IB_OPCODE_RC_ACKNOWLEDGE]                    = &hfi1_rc_rcv,
 244         [IB_OPCODE_RC_ATOMIC_ACKNOWLEDGE]             = &hfi1_rc_rcv,
 245         [IB_OPCODE_RC_COMPARE_SWAP]                   = &hfi1_rc_rcv,
 246         [IB_OPCODE_RC_FETCH_ADD]                      = &hfi1_rc_rcv,
 247         /* UC */
 248         [IB_OPCODE_UC_SEND_FIRST]                     = &hfi1_uc_rcv,
 249         [IB_OPCODE_UC_SEND_MIDDLE]                    = &hfi1_uc_rcv,
 250         [IB_OPCODE_UC_SEND_LAST]                      = &hfi1_uc_rcv,
 251         [IB_OPCODE_UC_SEND_LAST_WITH_IMMEDIATE]       = &hfi1_uc_rcv,
 252         [IB_OPCODE_UC_SEND_ONLY]                      = &hfi1_uc_rcv,
 253         [IB_OPCODE_UC_SEND_ONLY_WITH_IMMEDIATE]       = &hfi1_uc_rcv,
 254         [IB_OPCODE_UC_RDMA_WRITE_FIRST]               = &hfi1_uc_rcv,
 255         [IB_OPCODE_UC_RDMA_WRITE_MIDDLE]              = &hfi1_uc_rcv,
 256         [IB_OPCODE_UC_RDMA_WRITE_LAST]                = &hfi1_uc_rcv,
 257         [IB_OPCODE_UC_RDMA_WRITE_LAST_WITH_IMMEDIATE] = &hfi1_uc_rcv,
 258         [IB_OPCODE_UC_RDMA_WRITE_ONLY]                = &hfi1_uc_rcv,
 259         [IB_OPCODE_UC_RDMA_WRITE_ONLY_WITH_IMMEDIATE] = &hfi1_uc_rcv,
 260         /* UD */
 261         [IB_OPCODE_UD_SEND_ONLY]                      = &hfi1_ud_rcv,
 262         [IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE]       = &hfi1_ud_rcv,
 263         /* CNP */
 264         [IB_OPCODE_CNP]                               = &hfi1_cnp_rcv
 265 };
 266
 267 /*
 268  * System image GUID.
 269  */
 270 __be64 ib_hfi1_sys_image_guid;
 271
 272 /**
 273  * hfi1_copy_sge - copy data to SGE memory
 274  * @ss: the SGE state
 275  * @data: the data to copy
 276  * @length: the length of the data
 277  */
 278 void hfi1_copy_sge(
 279         struct hfi1_sge_state *ss,
 280         void *data, u32 length,
 281         int release)
 282 {
 283         struct hfi1_sge *sge = &ss->sge;
 284
 285         while (length) {
 286                 u32 len = sge->length;
 287
 288                 if (len > length)
 289                         len = length;
 290                 if (len > sge->sge_length)
 291                         len = sge->sge_length;
 292                 WARN_ON_ONCE(len == 0);
 293                 memcpy(sge->vaddr, data, len);
 294                 sge->vaddr += len;
 295                 sge->length -= len;
 296                 sge->sge_length -= len;
 297                 if (sge->sge_length == 0) {
 298                         if (release)
 299                                 hfi1_put_mr(sge->mr);
 300                         if (--ss->num_sge)
 301                                 *sge = *ss->sg_list++;
 302                 } else if (sge->length == 0 && sge->mr->lkey) {
 303                         if (++sge->n >= HFI1_SEGSZ) {
 304                                 if (++sge->m >= sge->mr->mapsz)
 305                                         break;
 306                                 sge->n = 0;
 307                         }
 308                         sge->vaddr =
 309                                 sge->mr->map[sge->m]->segs[sge->n].vaddr;
 310                         sge->length =
 311                                 sge->mr->map[sge->m]->segs[sge->n].length;
 312                 }
 313                 data += len;
 314                 length -= len;
 315         }
 316 }
 317
 318 /**
 319  * hfi1_skip_sge - skip over SGE memory
 320  * @ss: the SGE state
 321  * @length: the number of bytes to skip
 322  */
 323 void hfi1_skip_sge(struct hfi1_sge_state *ss, u32 length, int release)
 324 {
 325         struct hfi1_sge *sge = &ss->sge;
 326
 327         while (length) {
 328                 u32 len = sge->length;
 329
 330                 if (len > length)
 331                         len = length;
 332                 if (len > sge->sge_length)
 333                         len = sge->sge_length;
 334                 WARN_ON_ONCE(len == 0);
 335                 sge->vaddr += len;
 336                 sge->length -= len;
 337                 sge->sge_length -= len;
 338                 if (sge->sge_length == 0) {
 339                         if (release)
 340                                 hfi1_put_mr(sge->mr);
 341                         if (--ss->num_sge)
 342                                 *sge = *ss->sg_list++;
 343                 } else if (sge->length == 0 && sge->mr->lkey) {
 344                         if (++sge->n >= HFI1_SEGSZ) {
 345                                 if (++sge->m >= sge->mr->mapsz)
 346                                         break;
 347                                 sge->n = 0;
 348                         }
 349                         sge->vaddr =
 350                                 sge->mr->map[sge->m]->segs[sge->n].vaddr;
 351                         sge->length =
 352                                 sge->mr->map[sge->m]->segs[sge->n].length;
 353                 }
 354                 length -= len;
 355         }
 356 }
 357
 358 /**
 359  * post_one_send - post one RC, UC, or UD send work request
 360  * @qp: the QP to post on
 361  * @wr: the work request to send
 362  */
 363 static int post_one_send(struct hfi1_qp *qp, struct ib_send_wr *wr)
 364 {
 365         struct hfi1_swqe *wqe;
 366         u32 next;
 367         int i;
 368         int j;
 369         int acc;
 370         struct hfi1_lkey_table *rkt;
 371         struct hfi1_pd *pd;
 372         struct hfi1_devdata *dd = dd_from_ibdev(qp->ibqp.device);
 373         struct hfi1_pportdata *ppd;
 374         struct hfi1_ibport *ibp;
 375
 376         /* IB spec says that num_sge == 0 is OK. */
 377         if (unlikely(wr->num_sge > qp->s_max_sge))
 378                 return -EINVAL;
 379
 380         ppd = &dd->pport[qp->port_num - 1];
 381         ibp = &ppd->ibport_data;
 382
 383         /*
 384          * Don't allow RDMA reads or atomic operations on UC or
 385          * undefined operations.
 386          * Make sure buffer is large enough to hold the result for atomics.
 387          */
 388         if (qp->ibqp.qp_type == IB_QPT_UC) {
 389                 if ((unsigned) wr->opcode >= IB_WR_RDMA_READ)
 390                         return -EINVAL;
 391         } else if (qp->ibqp.qp_type != IB_QPT_RC) {
 392                 /* Check IB_QPT_SMI, IB_QPT_GSI, IB_QPT_UD opcode */
 393                 if (wr->opcode != IB_WR_SEND &&
 394                     wr->opcode != IB_WR_SEND_WITH_IMM)
 395                         return -EINVAL;
 396                 /* Check UD destination address PD */
 397                 if (qp->ibqp.pd != ud_wr(wr)->ah->pd)
 398                         return -EINVAL;
 399         } else if ((unsigned) wr->opcode > IB_WR_ATOMIC_FETCH_AND_ADD)
 400                 return -EINVAL;
 401         else if (wr->opcode >= IB_WR_ATOMIC_CMP_AND_SWP &&
 402                    (wr->num_sge == 0 ||
 403                     wr->sg_list[0].length < sizeof(u64) ||
 404                     wr->sg_list[0].addr & (sizeof(u64) - 1)))
 405                 return -EINVAL;
 406         else if (wr->opcode >= IB_WR_RDMA_READ && !qp->s_max_rd_atomic)
 407                 return -EINVAL;
 408
 409         next = qp->s_head + 1;
 410         if (next >= qp->s_size)
 411                 next = 0;
 412         if (next == qp->s_last)
 413                 return -ENOMEM;
 414
 415         rkt = &to_idev(qp->ibqp.device)->lk_table;
 416         pd = to_ipd(qp->ibqp.pd);
 417         wqe = get_swqe_ptr(qp, qp->s_head);
 418
 419
 420         if (qp->ibqp.qp_type != IB_QPT_UC &&
 421             qp->ibqp.qp_type != IB_QPT_RC)
 422                 memcpy(&wqe->ud_wr, ud_wr(wr), sizeof(wqe->ud_wr));
 423         else if (wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM ||
 424                  wr->opcode == IB_WR_RDMA_WRITE ||
 425                  wr->opcode == IB_WR_RDMA_READ)
 426                 memcpy(&wqe->rdma_wr, rdma_wr(wr), sizeof(wqe->rdma_wr));
 427         else if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP ||
 428                  wr->opcode == IB_WR_ATOMIC_FETCH_AND_ADD)
 429                 memcpy(&wqe->atomic_wr, atomic_wr(wr), sizeof(wqe->atomic_wr));
 430         else
 431                 memcpy(&wqe->wr, wr, sizeof(wqe->wr));
 432
 433         wqe->length = 0;
 434         j = 0;
 435         if (wr->num_sge) {
 436                 acc = wr->opcode >= IB_WR_RDMA_READ ?
 437                         IB_ACCESS_LOCAL_WRITE : 0;
 438                 for (i = 0; i < wr->num_sge; i++) {
 439                         u32 length = wr->sg_list[i].length;
 440                         int ok;
 441
 442                         if (length == 0)
 443                                 continue;
 444                         ok = hfi1_lkey_ok(rkt, pd, &wqe->sg_list[j],
 445                                           &wr->sg_list[i], acc);
 446                         if (!ok)
 447                                 goto bail_inval_free;
 448                         wqe->length += length;
 449                         j++;
 450                 }
 451                 wqe->wr.num_sge = j;
 452         }
 453         if (qp->ibqp.qp_type == IB_QPT_UC ||
 454             qp->ibqp.qp_type == IB_QPT_RC) {
 455                 if (wqe->length > 0x80000000U)
 456                         goto bail_inval_free;
 457         } else {
 458                 struct hfi1_ah *ah = to_iah(ud_wr(wr)->ah);
 459
 460                 atomic_inc(&ah->refcount);
 461         }
 462         wqe->ssn = qp->s_ssn++;
 463         qp->s_head = next;
 464
 465         return 0;
 466
 467 bail_inval_free:
 468         /* release mr holds */
 469         while (j) {
 470                 struct hfi1_sge *sge = &wqe->sg_list[--j];
 471
 472                 hfi1_put_mr(sge->mr);
 473         }
 474         return -EINVAL;
 475 }
 476
 477 /**
 478  * post_send - post a send on a QP
 479  * @ibqp: the QP to post the send on
 480  * @wr: the list of work requests to post
 481  * @bad_wr: the first bad WR is put here
 482  *
 483  * This may be called from interrupt context.
 484  */
 485 static int post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
 486                      struct ib_send_wr **bad_wr)
 487 {
 488         struct hfi1_qp *qp = to_iqp(ibqp);
 489         int err = 0;
 490         int call_send;
 491         unsigned long flags;
 492         unsigned nreq = 0;
 493
 494         spin_lock_irqsave(&qp->s_lock, flags);
 495
 496         /* Check that state is OK to post send. */
 497         if (unlikely(!(ib_hfi1_state_ops[qp->state] & HFI1_POST_SEND_OK))) {
 498                 spin_unlock_irqrestore(&qp->s_lock, flags);
 499                 return -EINVAL;
 500         }
 501
 502         /* sq empty and not list -> call send */
 503         call_send = qp->s_head == qp->s_last && !wr->next;
 504
 505         for (; wr; wr = wr->next) {
 506                 err = post_one_send(qp, wr);
 507                 if (unlikely(err)) {
 508                         *bad_wr = wr;
 509                         goto bail;
 510                 }
 511                 nreq++;
 512         }
 513 bail:
 514         spin_unlock_irqrestore(&qp->s_lock, flags);
 515         if (nreq && !call_send)
 516                 _hfi1_schedule_send(qp);
 517         if (nreq && call_send)
 518                 hfi1_do_send(&qp->s_iowait.iowork);
 519         return err;
 520 }
 521
 522 /**
 523  * post_receive - post a receive on a QP
 524  * @ibqp: the QP to post the receive on
 525  * @wr: the WR to post
 526  * @bad_wr: the first bad WR is put here
 527  *
 528  * This may be called from interrupt context.
 529  */
 530 static int post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
 531                         struct ib_recv_wr **bad_wr)
 532 {
 533         struct hfi1_qp *qp = to_iqp(ibqp);
 534         struct hfi1_rwq *wq = qp->r_rq.wq;
 535         unsigned long flags;
 536         int ret;
 537
 538         /* Check that state is OK to post receive. */
 539         if (!(ib_hfi1_state_ops[qp->state] & HFI1_POST_RECV_OK) || !wq) {
 540                 *bad_wr = wr;
 541                 ret = -EINVAL;
 542                 goto bail;
 543         }
 544
 545         for (; wr; wr = wr->next) {
 546                 struct hfi1_rwqe *wqe;
 547                 u32 next;
 548                 int i;
 549
 550                 if ((unsigned) wr->num_sge > qp->r_rq.max_sge) {
 551                         *bad_wr = wr;
 552                         ret = -EINVAL;
 553                         goto bail;
 554                 }
 555
 556                 spin_lock_irqsave(&qp->r_rq.lock, flags);
 557                 next = wq->head + 1;
 558                 if (next >= qp->r_rq.size)
 559                         next = 0;
 560                 if (next == wq->tail) {
 561                         spin_unlock_irqrestore(&qp->r_rq.lock, flags);
 562                         *bad_wr = wr;
 563                         ret = -ENOMEM;
 564                         goto bail;
 565                 }
 566
 567                 wqe = get_rwqe_ptr(&qp->r_rq, wq->head);
 568                 wqe->wr_id = wr->wr_id;
 569                 wqe->num_sge = wr->num_sge;
 570                 for (i = 0; i < wr->num_sge; i++)
 571                         wqe->sg_list[i] = wr->sg_list[i];
 572                 /* Make sure queue entry is written before the head index. */
 573                 smp_wmb();
 574                 wq->head = next;
 575                 spin_unlock_irqrestore(&qp->r_rq.lock, flags);
 576         }
 577         ret = 0;
 578
 579 bail:
 580         return ret;
 581 }
 582
 583 /*
 584  * Make sure the QP is ready and able to accept the given opcode.
 585  */
 586 static inline int qp_ok(int opcode, struct hfi1_packet *packet)
 587 {
 588         struct hfi1_ibport *ibp;
 589
 590         if (!(ib_hfi1_state_ops[packet->qp->state] & HFI1_PROCESS_RECV_OK))
 591                 goto dropit;
 592         if (((opcode & OPCODE_QP_MASK) == packet->qp->allowed_ops) ||
 593             (opcode == IB_OPCODE_CNP))
 594                 return 1;
 595 dropit:
 596         ibp = &packet->rcd->ppd->ibport_data;
 597         ibp->n_pkt_drops++;
 598         return 0;
 599 }
 600
 601
 602 /**
 603  * hfi1_ib_rcv - process an incoming packet
 604  * @packet: data packet information
 605  *
 606  * This is called to process an incoming packet at interrupt level.
 607  *
 608  * Tlen is the length of the header + data + CRC in bytes.
 609  */
 610 void hfi1_ib_rcv(struct hfi1_packet *packet)
 611 {
 612         struct hfi1_ctxtdata *rcd = packet->rcd;
 613         struct hfi1_ib_header *hdr = packet->hdr;
 614         u32 tlen = packet->tlen;
 615         struct hfi1_pportdata *ppd = rcd->ppd;
 616         struct hfi1_ibport *ibp = &ppd->ibport_data;
 617         unsigned long flags;
 618         u32 qp_num;
 619         int lnh;
 620         u8 opcode;
 621         u16 lid;
 622
 623         /* Check for GRH */
 624         lnh = be16_to_cpu(hdr->lrh[0]) & 3;
 625         if (lnh == HFI1_LRH_BTH)
 626                 packet->ohdr = &hdr->u.oth;
 627         else if (lnh == HFI1_LRH_GRH) {
 628                 u32 vtf;
 629
 630                 packet->ohdr = &hdr->u.l.oth;
 631                 if (hdr->u.l.grh.next_hdr != IB_GRH_NEXT_HDR)
 632                         goto drop;
 633                 vtf = be32_to_cpu(hdr->u.l.grh.version_tclass_flow);
 634                 if ((vtf >> IB_GRH_VERSION_SHIFT) != IB_GRH_VERSION)
 635                         goto drop;
 636                 packet->rcv_flags |= HFI1_HAS_GRH;
 637         } else
 638                 goto drop;
 639
 640         trace_input_ibhdr(rcd->dd, hdr);
 641
 642         opcode = (be32_to_cpu(packet->ohdr->bth[0]) >> 24);
 643         inc_opstats(tlen, &rcd->opstats->stats[opcode]);
 644
 645         /* Get the destination QP number. */
 646         qp_num = be32_to_cpu(packet->ohdr->bth[1]) & HFI1_QPN_MASK;
 647         lid = be16_to_cpu(hdr->lrh[1]);
 648         if (unlikely((lid >= HFI1_MULTICAST_LID_BASE) &&
 649             (lid != HFI1_PERMISSIVE_LID))) {
 650                 struct hfi1_mcast *mcast;
 651                 struct hfi1_mcast_qp *p;
 652
 653                 if (lnh != HFI1_LRH_GRH)
 654                         goto drop;
 655                 mcast = hfi1_mcast_find(ibp, &hdr->u.l.grh.dgid);
 656                 if (mcast == NULL)
 657                         goto drop;
 658                 list_for_each_entry_rcu(p, &mcast->qp_list, list) {
 659                         packet->qp = p->qp;
 660                         spin_lock_irqsave(&packet->qp->r_lock, flags);
 661                         if (likely((qp_ok(opcode, packet))))
 662                                 opcode_handler_tbl[opcode](packet);
 663                         spin_unlock_irqrestore(&packet->qp->r_lock, flags);
 664                 }
 665                 /*
 666                  * Notify hfi1_multicast_detach() if it is waiting for us
 667                  * to finish.
 668                  */
 669                 if (atomic_dec_return(&mcast->refcount) <= 1)
 670                         wake_up(&mcast->wait);
 671         } else {
 672                 rcu_read_lock();
 673                 packet->qp = hfi1_lookup_qpn(ibp, qp_num);
 674                 if (!packet->qp) {
 675                         rcu_read_unlock();
 676                         goto drop;
 677                 }
 678                 spin_lock_irqsave(&packet->qp->r_lock, flags);
 679                 if (likely((qp_ok(opcode, packet))))
 680                         opcode_handler_tbl[opcode](packet);
 681                 spin_unlock_irqrestore(&packet->qp->r_lock, flags);
 682                 rcu_read_unlock();
 683         }
 684         return;
 685
 686 drop:
 687         ibp->n_pkt_drops++;
 688 }
 689
 690 /*
 691  * This is called from a timer to check for QPs
 692  * which need kernel memory in order to send a packet.
 693  */
 694 static void mem_timer(unsigned long data)
 695 {
 696         struct hfi1_ibdev *dev = (struct hfi1_ibdev *)data;
 697         struct list_head *list = &dev->memwait;
 698         struct hfi1_qp *qp = NULL;
 699         struct iowait *wait;
 700         unsigned long flags;
 701
 702         write_seqlock_irqsave(&dev->iowait_lock, flags);
 703         if (!list_empty(list)) {
 704                 wait = list_first_entry(list, struct iowait, list);
 705                 qp = container_of(wait, struct hfi1_qp, s_iowait);
 706                 list_del_init(&qp->s_iowait.list);
 707                 /* refcount held until actual wake up */
 708                 if (!list_empty(list))
 709                         mod_timer(&dev->mem_timer, jiffies + 1);
 710         }
 711         write_sequnlock_irqrestore(&dev->iowait_lock, flags);
 712
 713         if (qp)
 714                 hfi1_qp_wakeup(qp, HFI1_S_WAIT_KMEM);
 715 }
 716
 717 void update_sge(struct hfi1_sge_state *ss, u32 length)
 718 {
 719         struct hfi1_sge *sge = &ss->sge;
 720
 721         sge->vaddr += length;
 722         sge->length -= length;
 723         sge->sge_length -= length;
 724         if (sge->sge_length == 0) {
 725                 if (--ss->num_sge)
 726                         *sge = *ss->sg_list++;
 727         } else if (sge->length == 0 && sge->mr->lkey) {
 728                 if (++sge->n >= HFI1_SEGSZ) {
 729                         if (++sge->m >= sge->mr->mapsz)
 730                                 return;
 731                         sge->n = 0;
 732                 }
 733                 sge->vaddr = sge->mr->map[sge->m]->segs[sge->n].vaddr;
 734                 sge->length = sge->mr->map[sge->m]->segs[sge->n].length;
 735         }
 736 }
 737
 738 static noinline struct verbs_txreq *__get_txreq(struct hfi1_ibdev *dev,
 739                                                 struct hfi1_qp *qp)
 740 {
 741         struct verbs_txreq *tx;
 742         unsigned long flags;
 743
 744         tx = kmem_cache_alloc(dev->verbs_txreq_cache, GFP_ATOMIC);
 745         if (!tx) {
 746                 spin_lock_irqsave(&qp->s_lock, flags);
 747                 write_seqlock(&dev->iowait_lock);
 748                 if (ib_hfi1_state_ops[qp->state] & HFI1_PROCESS_RECV_OK &&
 749                     list_empty(&qp->s_iowait.list)) {
 750                         dev->n_txwait++;
 751                         qp->s_flags |= HFI1_S_WAIT_TX;
 752                         list_add_tail(&qp->s_iowait.list, &dev->txwait);
 753                         trace_hfi1_qpsleep(qp, HFI1_S_WAIT_TX);
 754                         atomic_inc(&qp->refcount);
 755                 }
 756                 qp->s_flags &= ~HFI1_S_BUSY;
 757                 write_sequnlock(&dev->iowait_lock);
 758                 spin_unlock_irqrestore(&qp->s_lock, flags);
 759                 tx = ERR_PTR(-EBUSY);
 760         }
 761         return tx;
 762 }
 763
 764 static inline struct verbs_txreq *get_txreq(struct hfi1_ibdev *dev,
 765                                             struct hfi1_qp *qp)
 766 {
 767         struct verbs_txreq *tx;
 768
 769         tx = kmem_cache_alloc(dev->verbs_txreq_cache, GFP_ATOMIC);
 770         if (!tx) {
 771                 /* call slow path to get the lock */
 772                 tx =  __get_txreq(dev, qp);
 773                 if (IS_ERR(tx))
 774                         return tx;
 775         }
 776         tx->qp = qp;
 777         return tx;
 778 }
 779
 780 void hfi1_put_txreq(struct verbs_txreq *tx)
 781 {
 782         struct hfi1_ibdev *dev;
 783         struct hfi1_qp *qp;
 784         unsigned long flags;
 785         unsigned int seq;
 786
 787         qp = tx->qp;
 788         dev = to_idev(qp->ibqp.device);
 789
 790         if (tx->mr) {
 791                 hfi1_put_mr(tx->mr);
 792                 tx->mr = NULL;
 793         }
 794         sdma_txclean(dd_from_dev(dev), &tx->txreq);
 795
 796         /* Free verbs_txreq and return to slab cache */
 797         kmem_cache_free(dev->verbs_txreq_cache, tx);
 798
 799         do {
 800                 seq = read_seqbegin(&dev->iowait_lock);
 801                 if (!list_empty(&dev->txwait)) {
 802                         struct iowait *wait;
 803
 804                         write_seqlock_irqsave(&dev->iowait_lock, flags);
 805                         /* Wake up first QP wanting a free struct */
 806                         wait = list_first_entry(&dev->txwait, struct iowait,
 807                                                 list);
 808                         qp = container_of(wait, struct hfi1_qp, s_iowait);
 809                         list_del_init(&qp->s_iowait.list);
 810                         /* refcount held until actual wake up */
 811                         write_sequnlock_irqrestore(&dev->iowait_lock, flags);
 812                         hfi1_qp_wakeup(qp, HFI1_S_WAIT_TX);
 813                         break;
 814                 }
 815         } while (read_seqretry(&dev->iowait_lock, seq));
 816 }
 817
 818 /*
 819  * This is called with progress side lock held.
 820  */
 821 /* New API */
 822 static void verbs_sdma_complete(
 823         struct sdma_txreq *cookie,
 824         int status,
 825         int drained)
 826 {
 827         struct verbs_txreq *tx =
 828                 container_of(cookie, struct verbs_txreq, txreq);
 829         struct hfi1_qp *qp = tx->qp;
 830
 831         spin_lock(&qp->s_lock);
 832         if (tx->wqe)
 833                 hfi1_send_complete(qp, tx->wqe, IB_WC_SUCCESS);
 834         else if (qp->ibqp.qp_type == IB_QPT_RC) {
 835                 struct hfi1_ib_header *hdr;
 836
 837                 hdr = &tx->phdr.hdr;
 838                 hfi1_rc_send_complete(qp, hdr);
 839         }
 840         if (drained) {
 841                 /*
 842                  * This happens when the send engine notes
 843                  * a QP in the error state and cannot
 844                  * do the flush work until that QP's
 845                  * sdma work has finished.
 846                  */
 847                 if (qp->s_flags & HFI1_S_WAIT_DMA) {
 848                         qp->s_flags &= ~HFI1_S_WAIT_DMA;
 849                         hfi1_schedule_send(qp);
 850                 }
 851         }
 852         spin_unlock(&qp->s_lock);
 853
 854         hfi1_put_txreq(tx);
 855 }
 856
 857 static int wait_kmem(struct hfi1_ibdev *dev, struct hfi1_qp *qp)
 858 {
 859         unsigned long flags;
 860         int ret = 0;
 861
 862         spin_lock_irqsave(&qp->s_lock, flags);
 863         if (ib_hfi1_state_ops[qp->state] & HFI1_PROCESS_RECV_OK) {
 864                 write_seqlock(&dev->iowait_lock);
 865                 if (list_empty(&qp->s_iowait.list)) {
 866                         if (list_empty(&dev->memwait))
 867                                 mod_timer(&dev->mem_timer, jiffies + 1);
 868                         qp->s_flags |= HFI1_S_WAIT_KMEM;
 869                         list_add_tail(&qp->s_iowait.list, &dev->memwait);
 870                         trace_hfi1_qpsleep(qp, HFI1_S_WAIT_KMEM);
 871                         atomic_inc(&qp->refcount);
 872                 }
 873                 write_sequnlock(&dev->iowait_lock);
 874                 qp->s_flags &= ~HFI1_S_BUSY;
 875                 ret = -EBUSY;
 876         }
 877         spin_unlock_irqrestore(&qp->s_lock, flags);
 878
 879         return ret;
 880 }
 881
 882 /*
 883  * This routine calls txadds for each sg entry.
 884  *
 885  * Add failures will revert the sge cursor
 886  */
 887 static int build_verbs_ulp_payload(
 888         struct sdma_engine *sde,
 889         struct hfi1_sge_state *ss,
 890         u32 length,
 891         struct verbs_txreq *tx)
 892 {
 893         struct hfi1_sge *sg_list = ss->sg_list;
 894         struct hfi1_sge sge = ss->sge;
 895         u8 num_sge = ss->num_sge;
 896         u32 len;
 897         int ret = 0;
 898
 899         while (length) {
 900                 len = ss->sge.length;
 901                 if (len > length)
 902                         len = length;
 903                 if (len > ss->sge.sge_length)
 904                         len = ss->sge.sge_length;
 905                 WARN_ON_ONCE(len == 0);
 906                 ret = sdma_txadd_kvaddr(
 907                         sde->dd,
 908                         &tx->txreq,
 909                         ss->sge.vaddr,
 910                         len);
 911                 if (ret)
 912                         goto bail_txadd;
 913                 update_sge(ss, len);
 914                 length -= len;
 915         }
 916         return ret;
 917 bail_txadd:
 918         /* unwind cursor */
 919         ss->sge = sge;
 920         ss->num_sge = num_sge;
 921         ss->sg_list = sg_list;
 922         return ret;
 923 }
 924
 925 /*
 926  * Build the number of DMA descriptors needed to send length bytes of data.
 927  *
 928  * NOTE: DMA mapping is held in the tx until completed in the ring or
 929  *       the tx desc is freed without having been submitted to the ring
 930  *
 931  * This routine insures the following all the helper routine
 932  * calls succeed.
 933  */
 934 /* New API */
 935 static int build_verbs_tx_desc(
 936         struct sdma_engine *sde,
 937         struct hfi1_sge_state *ss,
 938         u32 length,
 939         struct verbs_txreq *tx,
 940         struct ahg_ib_header *ahdr,
 941         u64 pbc)
 942 {
 943         int ret = 0;
 944         struct hfi1_pio_header *phdr;
 945         u16 hdrbytes = tx->hdr_dwords << 2;
 946
 947         phdr = &tx->phdr;
 948         if (!ahdr->ahgcount) {
 949                 ret = sdma_txinit_ahg(
 950                         &tx->txreq,
 951                         ahdr->tx_flags,
 952                         hdrbytes + length,
 953                         ahdr->ahgidx,
 954                         0,
 955                         NULL,
 956                         0,
 957                         verbs_sdma_complete);
 958                 if (ret)
 959                         goto bail_txadd;
 960                 phdr->pbc = cpu_to_le64(pbc);
 961                 memcpy(&phdr->hdr, &ahdr->ibh, hdrbytes - sizeof(phdr->pbc));
 962                 /* add the header */
 963                 ret = sdma_txadd_kvaddr(
 964                         sde->dd,
 965                         &tx->txreq,
 966                         &tx->phdr,
 967                         tx->hdr_dwords << 2);
 968                 if (ret)
 969                         goto bail_txadd;
 970         } else {
 971                 struct hfi1_other_headers *sohdr = &ahdr->ibh.u.oth;
 972                 struct hfi1_other_headers *dohdr = &phdr->hdr.u.oth;
 973
 974                 /* needed in rc_send_complete() */
 975                 phdr->hdr.lrh[0] = ahdr->ibh.lrh[0];
 976                 if ((be16_to_cpu(phdr->hdr.lrh[0]) & 3) == HFI1_LRH_GRH) {
 977                         sohdr = &ahdr->ibh.u.l.oth;
 978                         dohdr = &phdr->hdr.u.l.oth;
 979                 }
 980                 /* opcode */
 981                 dohdr->bth[0] = sohdr->bth[0];
 982                 /* PSN/ACK  */
 983                 dohdr->bth[2] = sohdr->bth[2];
 984                 ret = sdma_txinit_ahg(
 985                         &tx->txreq,
 986                         ahdr->tx_flags,
 987                         length,
 988                         ahdr->ahgidx,
 989                         ahdr->ahgcount,
 990                         ahdr->ahgdesc,
 991                         hdrbytes,
 992                         verbs_sdma_complete);
 993                 if (ret)
 994                         goto bail_txadd;
 995         }
 996
 997         /* add the ulp payload - if any.  ss can be NULL for acks */
 998         if (ss)
 999                 ret = build_verbs_ulp_payload(sde, ss, length, tx);
1000 bail_txadd:
1001         return ret;
1002 }
1003
1004 int hfi1_verbs_send_dma(struct hfi1_qp *qp, struct hfi1_pkt_state *ps,
1005                         u64 pbc)
1006 {
1007         struct ahg_ib_header *ahdr = qp->s_hdr;
1008         u32 hdrwords = qp->s_hdrwords;
1009         struct hfi1_sge_state *ss = qp->s_cur_sge;
1010         u32 len = qp->s_cur_size;
1011         u32 plen = hdrwords + ((len + 3) >> 2) + 2; /* includes pbc */
1012         struct hfi1_ibdev *dev = ps->dev;
1013         struct hfi1_pportdata *ppd = ps->ppd;
1014         struct verbs_txreq *tx;
1015         struct sdma_txreq *stx;
1016         u64 pbc_flags = 0;
1017         u8 sc5 = qp->s_sc;
1018         int ret;
1019
1020         if (!list_empty(&qp->s_iowait.tx_head)) {
1021                 stx = list_first_entry(
1022                         &qp->s_iowait.tx_head,
1023                         struct sdma_txreq,
1024                         list);
1025                 list_del_init(&stx->list);
1026                 tx = container_of(stx, struct verbs_txreq, txreq);
1027                 ret = sdma_send_txreq(tx->sde, &qp->s_iowait, stx);
1028                 if (unlikely(ret == -ECOMM))
1029                         goto bail_ecomm;
1030                 return ret;
1031         }
1032
1033         tx = get_txreq(dev, qp);
1034         if (IS_ERR(tx))
1035                 goto bail_tx;
1036
1037         tx->sde = qp->s_sde;
1038
1039         if (likely(pbc == 0)) {
1040                 u32 vl = sc_to_vlt(dd_from_ibdev(qp->ibqp.device), sc5);
1041                 /* No vl15 here */
1042                 /* set PBC_DC_INFO bit (aka SC[4]) in pbc_flags */
1043                 pbc_flags |= (!!(sc5 & 0x10)) << PBC_DC_INFO_SHIFT;
1044
1045                 pbc = create_pbc(ppd, pbc_flags, qp->srate_mbps, vl, plen);
1046         }
1047         tx->wqe = qp->s_wqe;
1048         tx->mr = qp->s_rdma_mr;
1049         if (qp->s_rdma_mr)
1050                 qp->s_rdma_mr = NULL;
1051         tx->hdr_dwords = hdrwords + 2;
1052         ret = build_verbs_tx_desc(tx->sde, ss, len, tx, ahdr, pbc);
1053         if (unlikely(ret))
1054                 goto bail_build;
1055         trace_output_ibhdr(dd_from_ibdev(qp->ibqp.device), &ahdr->ibh);
1056         ret =  sdma_send_txreq(tx->sde, &qp->s_iowait, &tx->txreq);
1057         if (unlikely(ret == -ECOMM))
1058                 goto bail_ecomm;
1059         return ret;
1060
1061 bail_ecomm:
1062         /* The current one got "sent" */
1063         return 0;
1064 bail_build:
1065         /* kmalloc or mapping fail */
1066         hfi1_put_txreq(tx);
1067         return wait_kmem(dev, qp);
1068 bail_tx:
1069         return PTR_ERR(tx);
1070 }
1071
1072 /*
1073  * If we are now in the error state, return zero to flush the
1074  * send work request.
1075  */
1076 static int no_bufs_available(struct hfi1_qp *qp, struct send_context *sc)
1077 {
1078         struct hfi1_devdata *dd = sc->dd;
1079         struct hfi1_ibdev *dev = &dd->verbs_dev;
1080         unsigned long flags;
1081         int ret = 0;
1082
1083         /*
1084          * Note that as soon as want_buffer() is called and
1085          * possibly before it returns, sc_piobufavail()
1086          * could be called. Therefore, put QP on the I/O wait list before
1087          * enabling the PIO avail interrupt.
1088          */
1089         spin_lock_irqsave(&qp->s_lock, flags);
1090         if (ib_hfi1_state_ops[qp->state] & HFI1_PROCESS_RECV_OK) {
1091                 write_seqlock(&dev->iowait_lock);
1092                 if (list_empty(&qp->s_iowait.list)) {
1093                         struct hfi1_ibdev *dev = &dd->verbs_dev;
1094                         int was_empty;
1095
1096                         dev->n_piowait++;
1097                         qp->s_flags |= HFI1_S_WAIT_PIO;
1098                         was_empty = list_empty(&sc->piowait);
1099                         list_add_tail(&qp->s_iowait.list, &sc->piowait);
1100                         trace_hfi1_qpsleep(qp, HFI1_S_WAIT_PIO);
1101                         atomic_inc(&qp->refcount);
1102                         /* counting: only call wantpiobuf_intr if first user */
1103                         if (was_empty)
1104                                 hfi1_sc_wantpiobuf_intr(sc, 1);
1105                 }
1106                 write_sequnlock(&dev->iowait_lock);
1107                 qp->s_flags &= ~HFI1_S_BUSY;
1108                 ret = -EBUSY;
1109         }
1110         spin_unlock_irqrestore(&qp->s_lock, flags);
1111         return ret;
1112 }
1113
1114 struct send_context *qp_to_send_context(struct hfi1_qp *qp, u8 sc5)
1115 {
1116         struct hfi1_devdata *dd = dd_from_ibdev(qp->ibqp.device);
1117         struct hfi1_pportdata *ppd = dd->pport + (qp->port_num - 1);
1118         u8 vl;
1119
1120         vl = sc_to_vlt(dd, sc5);
1121         if (vl >= ppd->vls_supported && vl != 15)
1122                 return NULL;
1123         return dd->vld[vl].sc;
1124 }
1125
1126 int hfi1_verbs_send_pio(struct hfi1_qp *qp, struct hfi1_pkt_state *ps,
1127                         u64 pbc)
1128 {
1129         struct ahg_ib_header *ahdr = qp->s_hdr;
1130         u32 hdrwords = qp->s_hdrwords;
1131         struct hfi1_sge_state *ss = qp->s_cur_sge;
1132         u32 len = qp->s_cur_size;
1133         u32 dwords = (len + 3) >> 2;
1134         u32 plen = hdrwords + dwords + 2; /* includes pbc */
1135         struct hfi1_pportdata *ppd = ps->ppd;
1136         u32 *hdr = (u32 *)&ahdr->ibh;
1137         u64 pbc_flags = 0;
1138         u32 sc5;
1139         unsigned long flags = 0;
1140         struct send_context *sc;
1141         struct pio_buf *pbuf;
1142         int wc_status = IB_WC_SUCCESS;
1143
1144         /* vl15 special case taken care of in ud.c */
1145         sc5 = qp->s_sc;
1146         sc = qp_to_send_context(qp, sc5);
1147
1148         if (!sc)
1149                 return -EINVAL;
1150         if (likely(pbc == 0)) {
1151                 u32 vl = sc_to_vlt(dd_from_ibdev(qp->ibqp.device), sc5);
1152                 /* set PBC_DC_INFO bit (aka SC[4]) in pbc_flags */
1153                 pbc_flags |= (!!(sc5 & 0x10)) << PBC_DC_INFO_SHIFT;
1154                 pbc = create_pbc(ppd, pbc_flags, qp->srate_mbps, vl, plen);
1155         }
1156         pbuf = sc_buffer_alloc(sc, plen, NULL, NULL);
1157         if (unlikely(pbuf == NULL)) {
1158                 if (ppd->host_link_state != HLS_UP_ACTIVE) {
1159                         /*
1160                          * If we have filled the PIO buffers to capacity and are
1161                          * not in an active state this request is not going to
1162                          * go out to so just complete it with an error or else a
1163                          * ULP or the core may be stuck waiting.
1164                          */
1165                         hfi1_cdbg(
1166                                 PIO,
1167                                 "alloc failed. state not active, completing");
1168                         wc_status = IB_WC_GENERAL_ERR;
1169                         goto pio_bail;
1170                 } else {
1171                         /*
1172                          * This is a normal occurrence. The PIO buffs are full
1173                          * up but we are still happily sending, well we could be
1174                          * so lets continue to queue the request.
1175                          */
1176                         hfi1_cdbg(PIO, "alloc failed. state active, queuing");
1177                         return no_bufs_available(qp, sc);
1178                 }
1179         }
1180
1181         if (len == 0) {
1182                 pio_copy(ppd->dd, pbuf, pbc, hdr, hdrwords);
1183         } else {
1184                 if (ss) {
1185                         seg_pio_copy_start(pbuf, pbc, hdr, hdrwords*4);
1186                         while (len) {
1187                                 void *addr = ss->sge.vaddr;
1188                                 u32 slen = ss->sge.length;
1189
1190                                 if (slen > len)
1191                                         slen = len;
1192                                 update_sge(ss, slen);
1193                                 seg_pio_copy_mid(pbuf, addr, slen);
1194                                 len -= slen;
1195                         }
1196                         seg_pio_copy_end(pbuf);
1197                 }
1198         }
1199
1200         trace_output_ibhdr(dd_from_ibdev(qp->ibqp.device), &ahdr->ibh);
1201
1202         if (qp->s_rdma_mr) {
1203                 hfi1_put_mr(qp->s_rdma_mr);
1204                 qp->s_rdma_mr = NULL;
1205         }
1206
1207 pio_bail:
1208         if (qp->s_wqe) {
1209                 spin_lock_irqsave(&qp->s_lock, flags);
1210                 hfi1_send_complete(qp, qp->s_wqe, wc_status);
1211                 spin_unlock_irqrestore(&qp->s_lock, flags);
1212         } else if (qp->ibqp.qp_type == IB_QPT_RC) {
1213                 spin_lock_irqsave(&qp->s_lock, flags);
1214                 hfi1_rc_send_complete(qp, &ahdr->ibh);
1215                 spin_unlock_irqrestore(&qp->s_lock, flags);
1216         }
1217         return 0;
1218 }
1219
1220 /*
1221  * egress_pkey_matches_entry - return 1 if the pkey matches ent (ent
1222  * being an entry from the ingress partition key table), return 0
1223  * otherwise. Use the matching criteria for egress partition keys
1224  * specified in the OPAv1 spec., section 9.1l.7.
1225  */
1226 static inline int egress_pkey_matches_entry(u16 pkey, u16 ent)
1227 {
1228         u16 mkey = pkey & PKEY_LOW_15_MASK;
1229         u16 ment = ent & PKEY_LOW_15_MASK;
1230
1231         if (mkey == ment) {
1232                 /*
1233                  * If pkey[15] is set (full partition member),
1234                  * is bit 15 in the corresponding table element
1235                  * clear (limited member)?
1236                  */
1237                 if (pkey & PKEY_MEMBER_MASK)
1238                         return !!(ent & PKEY_MEMBER_MASK);
1239                 return 1;
1240         }
1241         return 0;
1242 }
1243
1244 /*
1245  * egress_pkey_check - return 0 if hdr's pkey matches according to the
1246  * criteria in the OPAv1 spec., section 9.11.7.
1247  */
1248 static inline int egress_pkey_check(struct hfi1_pportdata *ppd,
1249                                     struct hfi1_ib_header *hdr,
1250                                     struct hfi1_qp *qp)
1251 {
1252         struct hfi1_other_headers *ohdr;
1253         struct hfi1_devdata *dd;
1254         int i = 0;
1255         u16 pkey;
1256         u8 lnh, sc5 = qp->s_sc;
1257
1258         if (!(ppd->part_enforce & HFI1_PART_ENFORCE_OUT))
1259                 return 0;
1260
1261         /* locate the pkey within the headers */
1262         lnh = be16_to_cpu(hdr->lrh[0]) & 3;
1263         if (lnh == HFI1_LRH_GRH)
1264                 ohdr = &hdr->u.l.oth;
1265         else
1266                 ohdr = &hdr->u.oth;
1267
1268         pkey = (u16)be32_to_cpu(ohdr->bth[0]);
1269
1270         /* If SC15, pkey[0:14] must be 0x7fff */
1271         if ((sc5 == 0xf) && ((pkey & PKEY_LOW_15_MASK) != PKEY_LOW_15_MASK))
1272                 goto bad;
1273
1274
1275         /* Is the pkey = 0x0, or 0x8000? */
1276         if ((pkey & PKEY_LOW_15_MASK) == 0)
1277                 goto bad;
1278
1279         /* The most likely matching pkey has index qp->s_pkey_index */
1280         if (unlikely(!egress_pkey_matches_entry(pkey,
1281                                         ppd->pkeys[qp->s_pkey_index]))) {
1282                 /* no match - try the entire table */
1283                 for (; i < MAX_PKEY_VALUES; i++) {
1284                         if (egress_pkey_matches_entry(pkey, ppd->pkeys[i]))
1285                                 break;
1286                 }
1287         }
1288
1289         if (i < MAX_PKEY_VALUES)
1290                 return 0;
1291 bad:
1292         incr_cntr64(&ppd->port_xmit_constraint_errors);
1293         dd = ppd->dd;
1294         if (!(dd->err_info_xmit_constraint.status & OPA_EI_STATUS_SMASK)) {
1295                 u16 slid = be16_to_cpu(hdr->lrh[3]);
1296
1297                 dd->err_info_xmit_constraint.status |= OPA_EI_STATUS_SMASK;
1298                 dd->err_info_xmit_constraint.slid = slid;
1299                 dd->err_info_xmit_constraint.pkey = pkey;
1300         }
1301         return 1;
1302 }
1303
1304 /**
1305  * hfi1_verbs_send - send a packet
1306  * @qp: the QP to send on
1307  * @ps: the state of the packet to send
1308  *
1309  * Return zero if packet is sent or queued OK.
1310  * Return non-zero and clear qp->s_flags HFI1_S_BUSY otherwise.
1311  */
1312 int hfi1_verbs_send(struct hfi1_qp *qp, struct hfi1_pkt_state *ps)
1313 {
1314         struct hfi1_devdata *dd = dd_from_ibdev(qp->ibqp.device);
1315         struct ahg_ib_header *ahdr = qp->s_hdr;
1316         int ret;
1317         int pio = 0;
1318         unsigned long flags = 0;
1319
1320         /*
1321          * VL15 packets (IB_QPT_SMI) will always use PIO, so we
1322          * can defer SDMA restart until link goes ACTIVE without
1323          * worrying about just how we got there.
1324          */
1325         if ((qp->ibqp.qp_type == IB_QPT_SMI) ||
1326             !(dd->flags & HFI1_HAS_SEND_DMA))
1327                 pio = 1;
1328
1329         ret = egress_pkey_check(dd->pport, &ahdr->ibh, qp);
1330         if (unlikely(ret)) {
1331                 /*
1332                  * The value we are returning here does not get propagated to
1333                  * the verbs caller. Thus we need to complete the request with
1334                  * error otherwise the caller could be sitting waiting on the
1335                  * completion event. Only do this for PIO. SDMA has its own
1336                  * mechanism for handling the errors. So for SDMA we can just
1337                  * return.
1338                  */
1339                 if (pio) {
1340                         hfi1_cdbg(PIO, "%s() Failed. Completing with err",
1341                                   __func__);
1342                         spin_lock_irqsave(&qp->s_lock, flags);
1343                         hfi1_send_complete(qp, qp->s_wqe, IB_WC_GENERAL_ERR);
1344                         spin_unlock_irqrestore(&qp->s_lock, flags);
1345                 }
1346                 return -EINVAL;
1347         }
1348
1349         if (pio) {
1350                 ret = dd->process_pio_send(qp, ps, 0);
1351         } else {
1352 #ifdef CONFIG_SDMA_VERBOSITY
1353                 dd_dev_err(dd, "CONFIG SDMA %s:%d %s()\n",
1354                            slashstrip(__FILE__), __LINE__, __func__);
1355                 dd_dev_err(dd, "SDMA hdrwords = %u, len = %u\n", qp->s_hdrwords,
1356                            qp->s_cur_size);
1357 #endif
1358                 ret = dd->process_dma_send(qp, ps, 0);
1359         }
1360
1361         return ret;
1362 }
1363
1364 static int query_device(struct ib_device *ibdev,
1365                         struct ib_device_attr *props,
1366                         struct ib_udata *uhw)
1367 {
1368         struct hfi1_devdata *dd = dd_from_ibdev(ibdev);
1369         struct hfi1_ibdev *dev = to_idev(ibdev);
1370
1371         if (uhw->inlen || uhw->outlen)
1372                 return -EINVAL;
1373         memset(props, 0, sizeof(*props));
1374
1375         props->device_cap_flags = IB_DEVICE_BAD_PKEY_CNTR |
1376                 IB_DEVICE_BAD_QKEY_CNTR | IB_DEVICE_SHUTDOWN_PORT |
1377                 IB_DEVICE_SYS_IMAGE_GUID | IB_DEVICE_RC_RNR_NAK_GEN |
1378                 IB_DEVICE_PORT_ACTIVE_EVENT | IB_DEVICE_SRQ_RESIZE;
1379
1380         props->page_size_cap = PAGE_SIZE;
1381         props->vendor_id =
1382                 dd->oui1 << 16 | dd->oui2 << 8 | dd->oui3;
1383         props->vendor_part_id = dd->pcidev->device;
1384         props->hw_ver = dd->minrev;
1385         props->sys_image_guid = ib_hfi1_sys_image_guid;
1386         props->max_mr_size = ~0ULL;
1387         props->max_qp = hfi1_max_qps;
1388         props->max_qp_wr = hfi1_max_qp_wrs;
1389         props->max_sge = hfi1_max_sges;
1390         props->max_sge_rd = hfi1_max_sges;
1391         props->max_cq = hfi1_max_cqs;
1392         props->max_ah = hfi1_max_ahs;
1393         props->max_cqe = hfi1_max_cqes;
1394         props->max_mr = dev->lk_table.max;
1395         props->max_fmr = dev->lk_table.max;
1396         props->max_map_per_fmr = 32767;
1397         props->max_pd = hfi1_max_pds;
1398         props->max_qp_rd_atom = HFI1_MAX_RDMA_ATOMIC;
1399         props->max_qp_init_rd_atom = 255;
1400         /* props->max_res_rd_atom */
1401         props->max_srq = hfi1_max_srqs;
1402         props->max_srq_wr = hfi1_max_srq_wrs;
1403         props->max_srq_sge = hfi1_max_srq_sges;
1404         /* props->local_ca_ack_delay */
1405         props->atomic_cap = IB_ATOMIC_GLOB;
1406         props->max_pkeys = hfi1_get_npkeys(dd);
1407         props->max_mcast_grp = hfi1_max_mcast_grps;
1408         props->max_mcast_qp_attach = hfi1_max_mcast_qp_attached;
1409         props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
1410                 props->max_mcast_grp;
1411
1412         return 0;
1413 }
1414
1415 static inline u16 opa_speed_to_ib(u16 in)
1416 {
1417         u16 out = 0;
1418
1419         if (in & OPA_LINK_SPEED_25G)
1420                 out |= IB_SPEED_EDR;
1421         if (in & OPA_LINK_SPEED_12_5G)
1422                 out |= IB_SPEED_FDR;
1423
1424         return out;
1425 }
1426
1427 /*
1428  * Convert a single OPA link width (no multiple flags) to an IB value.
1429  * A zero OPA link width means link down, which means the IB width value
1430  * is a don't care.
1431  */
1432 static inline u16 opa_width_to_ib(u16 in)
1433 {
1434         switch (in) {
1435         case OPA_LINK_WIDTH_1X:
1436         /* map 2x and 3x to 1x as they don't exist in IB */
1437         case OPA_LINK_WIDTH_2X:
1438         case OPA_LINK_WIDTH_3X:
1439                 return IB_WIDTH_1X;
1440         default: /* link down or unknown, return our largest width */
1441         case OPA_LINK_WIDTH_4X:
1442                 return IB_WIDTH_4X;
1443         }
1444 }
1445
1446 static int query_port(struct ib_device *ibdev, u8 port,
1447                       struct ib_port_attr *props)
1448 {
1449         struct hfi1_devdata *dd = dd_from_ibdev(ibdev);
1450         struct hfi1_ibport *ibp = to_iport(ibdev, port);
1451         struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
1452         u16 lid = ppd->lid;
1453
1454         memset(props, 0, sizeof(*props));
1455         props->lid = lid ? lid : 0;
1456         props->lmc = ppd->lmc;
1457         props->sm_lid = ibp->sm_lid;
1458         props->sm_sl = ibp->sm_sl;
1459         /* OPA logical states match IB logical states */
1460         props->state = driver_lstate(ppd);
1461         props->phys_state = hfi1_ibphys_portstate(ppd);
1462         props->port_cap_flags = ibp->port_cap_flags;
1463         props->gid_tbl_len = HFI1_GUIDS_PER_PORT;
1464         props->max_msg_sz = 0x80000000;
1465         props->pkey_tbl_len = hfi1_get_npkeys(dd);
1466         props->bad_pkey_cntr = ibp->pkey_violations;
1467         props->qkey_viol_cntr = ibp->qkey_violations;
1468         props->active_width = (u8)opa_width_to_ib(ppd->link_width_active);
1469         /* see rate_show() in ib core/sysfs.c */
1470         props->active_speed = (u8)opa_speed_to_ib(ppd->link_speed_active);
1471         props->max_vl_num = ppd->vls_supported;
1472         props->init_type_reply = 0;
1473
1474         /* Once we are a "first class" citizen and have added the OPA MTUs to
1475          * the core we can advertise the larger MTU enum to the ULPs, for now
1476          * advertise only 4K.
1477          *
1478          * Those applications which are either OPA aware or pass the MTU enum
1479          * from the Path Records to us will get the new 8k MTU.  Those that
1480          * attempt to process the MTU enum may fail in various ways.
1481          */
1482         props->max_mtu = mtu_to_enum((!valid_ib_mtu(hfi1_max_mtu) ?
1483                                       4096 : hfi1_max_mtu), IB_MTU_4096);
1484         props->active_mtu = !valid_ib_mtu(ppd->ibmtu) ? props->max_mtu :
1485                 mtu_to_enum(ppd->ibmtu, IB_MTU_2048);
1486         props->subnet_timeout = ibp->subnet_timeout;
1487
1488         return 0;
1489 }
1490
1491 static int port_immutable(struct ib_device *ibdev, u8 port_num,
1492                           struct ib_port_immutable *immutable)
1493 {
1494         struct ib_port_attr attr;
1495         int err;
1496
1497         err = query_port(ibdev, port_num, &attr);
1498         if (err)
1499                 return err;
1500
1501         memset(immutable, 0, sizeof(*immutable));
1502
1503         immutable->pkey_tbl_len = attr.pkey_tbl_len;
1504         immutable->gid_tbl_len = attr.gid_tbl_len;
1505         immutable->core_cap_flags = RDMA_CORE_PORT_INTEL_OPA;
1506         immutable->max_mad_size = OPA_MGMT_MAD_SIZE;
1507
1508         return 0;
1509 }
1510
1511 static int modify_device(struct ib_device *device,
1512                          int device_modify_mask,
1513                          struct ib_device_modify *device_modify)
1514 {
1515         struct hfi1_devdata *dd = dd_from_ibdev(device);
1516         unsigned i;
1517         int ret;
1518
1519         if (device_modify_mask & ~(IB_DEVICE_MODIFY_SYS_IMAGE_GUID |
1520                                    IB_DEVICE_MODIFY_NODE_DESC)) {
1521                 ret = -EOPNOTSUPP;
1522                 goto bail;
1523         }
1524
1525         if (device_modify_mask & IB_DEVICE_MODIFY_NODE_DESC) {
1526                 memcpy(device->node_desc, device_modify->node_desc, 64);
1527                 for (i = 0; i < dd->num_pports; i++) {
1528                         struct hfi1_ibport *ibp = &dd->pport[i].ibport_data;
1529
1530                         hfi1_node_desc_chg(ibp);
1531                 }
1532         }
1533
1534         if (device_modify_mask & IB_DEVICE_MODIFY_SYS_IMAGE_GUID) {
1535                 ib_hfi1_sys_image_guid =
1536                         cpu_to_be64(device_modify->sys_image_guid);
1537                 for (i = 0; i < dd->num_pports; i++) {
1538                         struct hfi1_ibport *ibp = &dd->pport[i].ibport_data;
1539
1540                         hfi1_sys_guid_chg(ibp);
1541                 }
1542         }
1543
1544         ret = 0;
1545
1546 bail:
1547         return ret;
1548 }
1549
1550 static int modify_port(struct ib_device *ibdev, u8 port,
1551                        int port_modify_mask, struct ib_port_modify *props)
1552 {
1553         struct hfi1_ibport *ibp = to_iport(ibdev, port);
1554         struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
1555         int ret = 0;
1556
1557         ibp->port_cap_flags |= props->set_port_cap_mask;
1558         ibp->port_cap_flags &= ~props->clr_port_cap_mask;
1559         if (props->set_port_cap_mask || props->clr_port_cap_mask)
1560                 hfi1_cap_mask_chg(ibp);
1561         if (port_modify_mask & IB_PORT_SHUTDOWN) {
1562                 set_link_down_reason(ppd, OPA_LINKDOWN_REASON_UNKNOWN, 0,
1563                   OPA_LINKDOWN_REASON_UNKNOWN);
1564                 ret = set_link_state(ppd, HLS_DN_DOWNDEF);
1565         }
1566         if (port_modify_mask & IB_PORT_RESET_QKEY_CNTR)
1567                 ibp->qkey_violations = 0;
1568         return ret;
1569 }
1570
1571 static int query_gid(struct ib_device *ibdev, u8 port,
1572                      int index, union ib_gid *gid)
1573 {
1574         struct hfi1_devdata *dd = dd_from_ibdev(ibdev);
1575         int ret = 0;
1576
1577         if (!port || port > dd->num_pports)
1578                 ret = -EINVAL;
1579         else {
1580                 struct hfi1_ibport *ibp = to_iport(ibdev, port);
1581                 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
1582
1583                 gid->global.subnet_prefix = ibp->gid_prefix;
1584                 if (index == 0)
1585                         gid->global.interface_id = cpu_to_be64(ppd->guid);
1586                 else if (index < HFI1_GUIDS_PER_PORT)
1587                         gid->global.interface_id = ibp->guids[index - 1];
1588                 else
1589                         ret = -EINVAL;
1590         }
1591
1592         return ret;
1593 }
1594
1595 static struct ib_pd *alloc_pd(struct ib_device *ibdev,
1596                               struct ib_ucontext *context,
1597                               struct ib_udata *udata)
1598 {
1599         struct hfi1_ibdev *dev = to_idev(ibdev);
1600         struct hfi1_pd *pd;
1601         struct ib_pd *ret;
1602
1603         /*
1604          * This is actually totally arbitrary.  Some correctness tests
1605          * assume there's a maximum number of PDs that can be allocated.
1606          * We don't actually have this limit, but we fail the test if
1607          * we allow allocations of more than we report for this value.
1608          */
1609
1610         pd = kmalloc(sizeof(*pd), GFP_KERNEL);
1611         if (!pd) {
1612                 ret = ERR_PTR(-ENOMEM);
1613                 goto bail;
1614         }
1615
1616         spin_lock(&dev->n_pds_lock);
1617         if (dev->n_pds_allocated == hfi1_max_pds) {
1618                 spin_unlock(&dev->n_pds_lock);
1619                 kfree(pd);
1620                 ret = ERR_PTR(-ENOMEM);
1621                 goto bail;
1622         }
1623
1624         dev->n_pds_allocated++;
1625         spin_unlock(&dev->n_pds_lock);
1626
1627         /* ib_alloc_pd() will initialize pd->ibpd. */
1628         pd->user = udata != NULL;
1629
1630         ret = &pd->ibpd;
1631
1632 bail:
1633         return ret;
1634 }
1635
1636 static int dealloc_pd(struct ib_pd *ibpd)
1637 {
1638         struct hfi1_pd *pd = to_ipd(ibpd);
1639         struct hfi1_ibdev *dev = to_idev(ibpd->device);
1640
1641         spin_lock(&dev->n_pds_lock);
1642         dev->n_pds_allocated--;
1643         spin_unlock(&dev->n_pds_lock);
1644
1645         kfree(pd);
1646
1647         return 0;
1648 }
1649
1650 /*
1651  * convert ah port,sl to sc
1652  */
1653 u8 ah_to_sc(struct ib_device *ibdev, struct ib_ah_attr *ah)
1654 {
1655         struct hfi1_ibport *ibp = to_iport(ibdev, ah->port_num);
1656
1657         return ibp->sl_to_sc[ah->sl];
1658 }
1659
1660 int hfi1_check_ah(struct ib_device *ibdev, struct ib_ah_attr *ah_attr)
1661 {
1662         struct hfi1_ibport *ibp;
1663         struct hfi1_pportdata *ppd;
1664         struct hfi1_devdata *dd;
1665         u8 sc5;
1666
1667         /* A multicast address requires a GRH (see ch. 8.4.1). */
1668         if (ah_attr->dlid >= HFI1_MULTICAST_LID_BASE &&
1669             ah_attr->dlid != HFI1_PERMISSIVE_LID &&
1670             !(ah_attr->ah_flags & IB_AH_GRH))
1671                 goto bail;
1672         if ((ah_attr->ah_flags & IB_AH_GRH) &&
1673             ah_attr->grh.sgid_index >= HFI1_GUIDS_PER_PORT)
1674                 goto bail;
1675         if (ah_attr->dlid == 0)
1676                 goto bail;
1677         if (ah_attr->port_num < 1 ||
1678             ah_attr->port_num > ibdev->phys_port_cnt)
1679                 goto bail;
1680         if (ah_attr->static_rate != IB_RATE_PORT_CURRENT &&
1681             ib_rate_to_mbps(ah_attr->static_rate) < 0)
1682                 goto bail;
1683         if (ah_attr->sl >= OPA_MAX_SLS)
1684                 goto bail;
1685         /* test the mapping for validity */
1686         ibp = to_iport(ibdev, ah_attr->port_num);
1687         ppd = ppd_from_ibp(ibp);
1688         sc5 = ibp->sl_to_sc[ah_attr->sl];
1689         dd = dd_from_ppd(ppd);
1690         if (sc_to_vlt(dd, sc5) > num_vls && sc_to_vlt(dd, sc5) != 0xf)
1691                 goto bail;
1692         return 0;
1693 bail:
1694         return -EINVAL;
1695 }
1696
1697 /**
1698  * create_ah - create an address handle
1699  * @pd: the protection domain
1700  * @ah_attr: the attributes of the AH
1701  *
1702  * This may be called from interrupt context.
1703  */
1704 static struct ib_ah *create_ah(struct ib_pd *pd,
1705                                struct ib_ah_attr *ah_attr)
1706 {
1707         struct hfi1_ah *ah;
1708         struct ib_ah *ret;
1709         struct hfi1_ibdev *dev = to_idev(pd->device);
1710         unsigned long flags;
1711
1712         if (hfi1_check_ah(pd->device, ah_attr)) {
1713                 ret = ERR_PTR(-EINVAL);
1714                 goto bail;
1715         }
1716
1717         ah = kmalloc(sizeof(*ah), GFP_ATOMIC);
1718         if (!ah) {
1719                 ret = ERR_PTR(-ENOMEM);
1720                 goto bail;
1721         }
1722
1723         spin_lock_irqsave(&dev->n_ahs_lock, flags);
1724         if (dev->n_ahs_allocated == hfi1_max_ahs) {
1725                 spin_unlock_irqrestore(&dev->n_ahs_lock, flags);
1726                 kfree(ah);
1727                 ret = ERR_PTR(-ENOMEM);
1728                 goto bail;
1729         }
1730
1731         dev->n_ahs_allocated++;
1732         spin_unlock_irqrestore(&dev->n_ahs_lock, flags);
1733
1734         /* ib_create_ah() will initialize ah->ibah. */
1735         ah->attr = *ah_attr;
1736         atomic_set(&ah->refcount, 0);
1737
1738         ret = &ah->ibah;
1739
1740 bail:
1741         return ret;
1742 }
1743
1744 struct ib_ah *hfi1_create_qp0_ah(struct hfi1_ibport *ibp, u16 dlid)
1745 {
1746         struct ib_ah_attr attr;
1747         struct ib_ah *ah = ERR_PTR(-EINVAL);
1748         struct hfi1_qp *qp0;
1749
1750         memset(&attr, 0, sizeof(attr));
1751         attr.dlid = dlid;
1752         attr.port_num = ppd_from_ibp(ibp)->port;
1753         rcu_read_lock();
1754         qp0 = rcu_dereference(ibp->qp[0]);
1755         if (qp0)
1756                 ah = ib_create_ah(qp0->ibqp.pd, &attr);
1757         rcu_read_unlock();
1758         return ah;
1759 }
1760
1761 /**
1762  * destroy_ah - destroy an address handle
1763  * @ibah: the AH to destroy
1764  *
1765  * This may be called from interrupt context.
1766  */
1767 static int destroy_ah(struct ib_ah *ibah)
1768 {
1769         struct hfi1_ibdev *dev = to_idev(ibah->device);
1770         struct hfi1_ah *ah = to_iah(ibah);
1771         unsigned long flags;
1772
1773         if (atomic_read(&ah->refcount) != 0)
1774                 return -EBUSY;
1775
1776         spin_lock_irqsave(&dev->n_ahs_lock, flags);
1777         dev->n_ahs_allocated--;
1778         spin_unlock_irqrestore(&dev->n_ahs_lock, flags);
1779
1780         kfree(ah);
1781
1782         return 0;
1783 }
1784
1785 static int modify_ah(struct ib_ah *ibah, struct ib_ah_attr *ah_attr)
1786 {
1787         struct hfi1_ah *ah = to_iah(ibah);
1788
1789         if (hfi1_check_ah(ibah->device, ah_attr))
1790                 return -EINVAL;
1791
1792         ah->attr = *ah_attr;
1793
1794         return 0;
1795 }
1796
1797 static int query_ah(struct ib_ah *ibah, struct ib_ah_attr *ah_attr)
1798 {
1799         struct hfi1_ah *ah = to_iah(ibah);
1800
1801         *ah_attr = ah->attr;
1802
1803         return 0;
1804 }
1805
1806 /**
1807  * hfi1_get_npkeys - return the size of the PKEY table for context 0
1808  * @dd: the hfi1_ib device
1809  */
1810 unsigned hfi1_get_npkeys(struct hfi1_devdata *dd)
1811 {
1812         return ARRAY_SIZE(dd->pport[0].pkeys);
1813 }
1814
1815 static int query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1816                       u16 *pkey)
1817 {
1818         struct hfi1_devdata *dd = dd_from_ibdev(ibdev);
1819         int ret;
1820
1821         if (index >= hfi1_get_npkeys(dd)) {
1822                 ret = -EINVAL;
1823                 goto bail;
1824         }
1825
1826         *pkey = hfi1_get_pkey(to_iport(ibdev, port), index);
1827         ret = 0;
1828
1829 bail:
1830         return ret;
1831 }
1832
1833 /**
1834  * alloc_ucontext - allocate a ucontest
1835  * @ibdev: the infiniband device
1836  * @udata: not used by the driver
1837  */
1838
1839 static struct ib_ucontext *alloc_ucontext(struct ib_device *ibdev,
1840                                           struct ib_udata *udata)
1841 {
1842         struct hfi1_ucontext *context;
1843         struct ib_ucontext *ret;
1844
1845         context = kmalloc(sizeof(*context), GFP_KERNEL);
1846         if (!context) {
1847                 ret = ERR_PTR(-ENOMEM);
1848                 goto bail;
1849         }
1850
1851         ret = &context->ibucontext;
1852
1853 bail:
1854         return ret;
1855 }
1856
1857 static int dealloc_ucontext(struct ib_ucontext *context)
1858 {
1859         kfree(to_iucontext(context));
1860         return 0;
1861 }
1862
1863 static void init_ibport(struct hfi1_pportdata *ppd)
1864 {
1865         struct hfi1_ibport *ibp = &ppd->ibport_data;
1866         size_t sz = ARRAY_SIZE(ibp->sl_to_sc);
1867         int i;
1868
1869         for (i = 0; i < sz; i++) {
1870                 ibp->sl_to_sc[i] = i;
1871                 ibp->sc_to_sl[i] = i;
1872         }
1873
1874         spin_lock_init(&ibp->lock);
1875         /* Set the prefix to the default value (see ch. 4.1.1) */
1876         ibp->gid_prefix = IB_DEFAULT_GID_PREFIX;
1877         ibp->sm_lid = 0;
1878         /* Below should only set bits defined in OPA PortInfo.CapabilityMask */
1879         ibp->port_cap_flags = IB_PORT_AUTO_MIGR_SUP |
1880                 IB_PORT_CAP_MASK_NOTICE_SUP;
1881         ibp->pma_counter_select[0] = IB_PMA_PORT_XMIT_DATA;
1882         ibp->pma_counter_select[1] = IB_PMA_PORT_RCV_DATA;
1883         ibp->pma_counter_select[2] = IB_PMA_PORT_XMIT_PKTS;
1884         ibp->pma_counter_select[3] = IB_PMA_PORT_RCV_PKTS;
1885         ibp->pma_counter_select[4] = IB_PMA_PORT_XMIT_WAIT;
1886
1887         RCU_INIT_POINTER(ibp->qp[0], NULL);
1888         RCU_INIT_POINTER(ibp->qp[1], NULL);
1889 }
1890
1891 static void verbs_txreq_kmem_cache_ctor(void *obj)
1892 {
1893         struct verbs_txreq *tx = obj;
1894
1895         memset(tx, 0, sizeof(*tx));
1896 }
1897
1898 /**
1899  * hfi1_register_ib_device - register our device with the infiniband core
1900  * @dd: the device data structure
1901  * Return 0 if successful, errno if unsuccessful.
1902  */
1903 int hfi1_register_ib_device(struct hfi1_devdata *dd)
1904 {
1905         struct hfi1_ibdev *dev = &dd->verbs_dev;
1906         struct ib_device *ibdev = &dev->ibdev;
1907         struct hfi1_pportdata *ppd = dd->pport;
1908         unsigned i, lk_tab_size;
1909         int ret;
1910         size_t lcpysz = IB_DEVICE_NAME_MAX;
1911         u16 descq_cnt;
1912         char buf[TXREQ_NAME_LEN];
1913
1914         ret = hfi1_qp_init(dev);
1915         if (ret)
1916                 goto err_qp_init;
1917
1918
1919         for (i = 0; i < dd->num_pports; i++)
1920                 init_ibport(ppd + i);
1921
1922         /* Only need to initialize non-zero fields. */
1923         spin_lock_init(&dev->n_pds_lock);
1924         spin_lock_init(&dev->n_ahs_lock);
1925         spin_lock_init(&dev->n_cqs_lock);
1926         spin_lock_init(&dev->n_qps_lock);
1927         spin_lock_init(&dev->n_srqs_lock);
1928         spin_lock_init(&dev->n_mcast_grps_lock);
1929         init_timer(&dev->mem_timer);
1930         dev->mem_timer.function = mem_timer;
1931         dev->mem_timer.data = (unsigned long) dev;
1932
1933         /*
1934          * The top hfi1_lkey_table_size bits are used to index the
1935          * table.  The lower 8 bits can be owned by the user (copied from
1936          * the LKEY).  The remaining bits act as a generation number or tag.
1937          */
1938         spin_lock_init(&dev->lk_table.lock);
1939         dev->lk_table.max = 1 << hfi1_lkey_table_size;
1940         /* ensure generation is at least 4 bits (keys.c) */
1941         if (hfi1_lkey_table_size > MAX_LKEY_TABLE_BITS) {
1942                 dd_dev_warn(dd, "lkey bits %u too large, reduced to %u\n",
1943                               hfi1_lkey_table_size, MAX_LKEY_TABLE_BITS);
1944                 hfi1_lkey_table_size = MAX_LKEY_TABLE_BITS;
1945         }
1946         lk_tab_size = dev->lk_table.max * sizeof(*dev->lk_table.table);
1947         dev->lk_table.table = (struct hfi1_mregion __rcu **)
1948                 vmalloc(lk_tab_size);
1949         if (dev->lk_table.table == NULL) {
1950                 ret = -ENOMEM;
1951                 goto err_lk;
1952         }
1953         RCU_INIT_POINTER(dev->dma_mr, NULL);
1954         for (i = 0; i < dev->lk_table.max; i++)
1955                 RCU_INIT_POINTER(dev->lk_table.table[i], NULL);
1956         INIT_LIST_HEAD(&dev->pending_mmaps);
1957         spin_lock_init(&dev->pending_lock);
1958         seqlock_init(&dev->iowait_lock);
1959         dev->mmap_offset = PAGE_SIZE;
1960         spin_lock_init(&dev->mmap_offset_lock);
1961         INIT_LIST_HEAD(&dev->txwait);
1962         INIT_LIST_HEAD(&dev->memwait);
1963
1964         descq_cnt = sdma_get_descq_cnt();
1965
1966         snprintf(buf, sizeof(buf), "hfi1_%u_vtxreq_cache", dd->unit);
1967         /* SLAB_HWCACHE_ALIGN for AHG */
1968         dev->verbs_txreq_cache = kmem_cache_create(buf,
1969                                                    sizeof(struct verbs_txreq),
1970                                                    0, SLAB_HWCACHE_ALIGN,
1971                                                    verbs_txreq_kmem_cache_ctor);
1972         if (!dev->verbs_txreq_cache) {
1973                 ret = -ENOMEM;
1974                 goto err_verbs_txreq;
1975         }
1976
1977         /*
1978          * The system image GUID is supposed to be the same for all
1979          * HFIs in a single system but since there can be other
1980          * device types in the system, we can't be sure this is unique.
1981          */
1982         if (!ib_hfi1_sys_image_guid)
1983                 ib_hfi1_sys_image_guid = cpu_to_be64(ppd->guid);
1984         lcpysz = strlcpy(ibdev->name, class_name(), lcpysz);
1985         strlcpy(ibdev->name + lcpysz, "_%d", IB_DEVICE_NAME_MAX - lcpysz);
1986         ibdev->owner = THIS_MODULE;
1987         ibdev->node_guid = cpu_to_be64(ppd->guid);
1988         ibdev->uverbs_abi_ver = HFI1_UVERBS_ABI_VERSION;
1989         ibdev->uverbs_cmd_mask =
1990                 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT)         |
1991                 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE)        |
1992                 (1ull << IB_USER_VERBS_CMD_QUERY_PORT)          |
1993                 (1ull << IB_USER_VERBS_CMD_ALLOC_PD)            |
1994                 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD)          |
1995                 (1ull << IB_USER_VERBS_CMD_CREATE_AH)           |
1996                 (1ull << IB_USER_VERBS_CMD_MODIFY_AH)           |
1997                 (1ull << IB_USER_VERBS_CMD_QUERY_AH)            |
1998                 (1ull << IB_USER_VERBS_CMD_DESTROY_AH)          |
1999                 (1ull << IB_USER_VERBS_CMD_REG_MR)              |
2000                 (1ull << IB_USER_VERBS_CMD_DEREG_MR)            |
2001                 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
2002                 (1ull << IB_USER_VERBS_CMD_CREATE_CQ)           |
2003                 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ)           |
2004                 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ)          |
2005                 (1ull << IB_USER_VERBS_CMD_POLL_CQ)             |
2006                 (1ull << IB_USER_VERBS_CMD_REQ_NOTIFY_CQ)       |
2007                 (1ull << IB_USER_VERBS_CMD_CREATE_QP)           |
2008                 (1ull << IB_USER_VERBS_CMD_QUERY_QP)            |
2009                 (1ull << IB_USER_VERBS_CMD_MODIFY_QP)           |
2010                 (1ull << IB_USER_VERBS_CMD_DESTROY_QP)          |
2011                 (1ull << IB_USER_VERBS_CMD_POST_SEND)           |
2012                 (1ull << IB_USER_VERBS_CMD_POST_RECV)           |
2013                 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST)        |
2014                 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST)        |
2015                 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ)          |
2016                 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ)          |
2017                 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ)           |
2018                 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ)         |
2019                 (1ull << IB_USER_VERBS_CMD_POST_SRQ_RECV);
2020         ibdev->node_type = RDMA_NODE_IB_CA;
2021         ibdev->phys_port_cnt = dd->num_pports;
2022         ibdev->num_comp_vectors = 1;
2023         ibdev->dma_device = &dd->pcidev->dev;
2024         ibdev->query_device = query_device;
2025         ibdev->modify_device = modify_device;
2026         ibdev->query_port = query_port;
2027         ibdev->modify_port = modify_port;
2028         ibdev->query_pkey = query_pkey;
2029         ibdev->query_gid = query_gid;
2030         ibdev->alloc_ucontext = alloc_ucontext;
2031         ibdev->dealloc_ucontext = dealloc_ucontext;
2032         ibdev->alloc_pd = alloc_pd;
2033         ibdev->dealloc_pd = dealloc_pd;
2034         ibdev->create_ah = create_ah;
2035         ibdev->destroy_ah = destroy_ah;
2036         ibdev->modify_ah = modify_ah;
2037         ibdev->query_ah = query_ah;
2038         ibdev->create_srq = hfi1_create_srq;
2039         ibdev->modify_srq = hfi1_modify_srq;
2040         ibdev->query_srq = hfi1_query_srq;
2041         ibdev->destroy_srq = hfi1_destroy_srq;
2042         ibdev->create_qp = hfi1_create_qp;
2043         ibdev->modify_qp = hfi1_modify_qp;
2044         ibdev->query_qp = hfi1_query_qp;
2045         ibdev->destroy_qp = hfi1_destroy_qp;
2046         ibdev->post_send = post_send;
2047         ibdev->post_recv = post_receive;
2048         ibdev->post_srq_recv = hfi1_post_srq_receive;
2049         ibdev->create_cq = hfi1_create_cq;
2050         ibdev->destroy_cq = hfi1_destroy_cq;
2051         ibdev->resize_cq = hfi1_resize_cq;
2052         ibdev->poll_cq = hfi1_poll_cq;
2053         ibdev->req_notify_cq = hfi1_req_notify_cq;
2054         ibdev->get_dma_mr = hfi1_get_dma_mr;
2055         ibdev->reg_user_mr = hfi1_reg_user_mr;
2056         ibdev->dereg_mr = hfi1_dereg_mr;
2057         ibdev->alloc_mr = hfi1_alloc_mr;
2058         ibdev->alloc_fmr = hfi1_alloc_fmr;
2059         ibdev->map_phys_fmr = hfi1_map_phys_fmr;
2060         ibdev->unmap_fmr = hfi1_unmap_fmr;
2061         ibdev->dealloc_fmr = hfi1_dealloc_fmr;
2062         ibdev->attach_mcast = hfi1_multicast_attach;
2063         ibdev->detach_mcast = hfi1_multicast_detach;
2064         ibdev->process_mad = hfi1_process_mad;
2065         ibdev->mmap = hfi1_mmap;
2066         ibdev->dma_ops = &hfi1_dma_mapping_ops;
2067         ibdev->get_port_immutable = port_immutable;
2068
2069         strncpy(ibdev->node_desc, init_utsname()->nodename,
2070                 sizeof(ibdev->node_desc));
2071
2072         ret = ib_register_device(ibdev, hfi1_create_port_files);
2073         if (ret)
2074                 goto err_reg;
2075
2076         ret = hfi1_create_agents(dev);
2077         if (ret)
2078                 goto err_agents;
2079
2080         ret = hfi1_verbs_register_sysfs(dd);
2081         if (ret)
2082                 goto err_class;
2083
2084         goto bail;
2085
2086 err_class:
2087         hfi1_free_agents(dev);
2088 err_agents:
2089         ib_unregister_device(ibdev);
2090 err_reg:
2091 err_verbs_txreq:
2092         kmem_cache_destroy(dev->verbs_txreq_cache);
2093         vfree(dev->lk_table.table);
2094 err_lk:
2095         hfi1_qp_exit(dev);
2096 err_qp_init:
2097         dd_dev_err(dd, "cannot register verbs: %d!\n", -ret);
2098 bail:
2099         return ret;
2100 }
2101
2102 void hfi1_unregister_ib_device(struct hfi1_devdata *dd)
2103 {
2104         struct hfi1_ibdev *dev = &dd->verbs_dev;
2105         struct ib_device *ibdev = &dev->ibdev;
2106
2107         hfi1_verbs_unregister_sysfs(dd);
2108
2109         hfi1_free_agents(dev);
2110
2111         ib_unregister_device(ibdev);
2112
2113         if (!list_empty(&dev->txwait))
2114                 dd_dev_err(dd, "txwait list not empty!\n");
2115         if (!list_empty(&dev->memwait))
2116                 dd_dev_err(dd, "memwait list not empty!\n");
2117         if (dev->dma_mr)
2118                 dd_dev_err(dd, "DMA MR not NULL!\n");
2119
2120         hfi1_qp_exit(dev);
2121         del_timer_sync(&dev->mem_timer);
2122         kmem_cache_destroy(dev->verbs_txreq_cache);
2123         vfree(dev->lk_table.table);
2124 }
2125
2126 void hfi1_cnp_rcv(struct hfi1_packet *packet)
2127 {
2128         struct hfi1_ibport *ibp = &packet->rcd->ppd->ibport_data;
2129         struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
2130         struct hfi1_ib_header *hdr = packet->hdr;
2131         struct hfi1_qp *qp = packet->qp;
2132         u32 lqpn, rqpn = 0;
2133         u16 rlid = 0;
2134         u8 sl, sc5, sc4_bit, svc_type;
2135         bool sc4_set = has_sc4_bit(packet);
2136
2137         switch (packet->qp->ibqp.qp_type) {
2138         case IB_QPT_UC:
2139                 rlid = qp->remote_ah_attr.dlid;
2140                 rqpn = qp->remote_qpn;
2141                 svc_type = IB_CC_SVCTYPE_UC;
2142                 break;
2143         case IB_QPT_RC:
2144                 rlid = qp->remote_ah_attr.dlid;
2145                 rqpn = qp->remote_qpn;
2146                 svc_type = IB_CC_SVCTYPE_RC;
2147                 break;
2148         case IB_QPT_SMI:
2149         case IB_QPT_GSI:
2150         case IB_QPT_UD:
2151                 svc_type = IB_CC_SVCTYPE_UD;
2152                 break;
2153         default:
2154                 ibp->n_pkt_drops++;
2155                 return;
2156         }
2157
2158         sc4_bit = sc4_set << 4;
2159         sc5 = (be16_to_cpu(hdr->lrh[0]) >> 12) & 0xf;
2160         sc5 |= sc4_bit;
2161         sl = ibp->sc_to_sl[sc5];
2162         lqpn = qp->ibqp.qp_num;
2163
2164         process_becn(ppd, sl, rlid, lqpn, rqpn, svc_type);
2165 }