drivers/staging/rtl8192e/r8192E_phy.c

   1 /******************************************************************************
   2  * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
   3  *
   4  * This program is distributed in the hope that it will be useful, but WITHOUT
   5  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   6  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
   7  * more details.
   8  *
   9  * You should have received a copy of the GNU General Public License along with
  10  * this program; if not, write to the Free Software Foundation, Inc.,
  11  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  12  *
  13  * The full GNU General Public License is included in this distribution in the
  14  * file called LICENSE.
  15  *
  16  * Contact Information:
  17  * wlanfae <wlanfae@realtek.com>
  18 ******************************************************************************/
  19
  20 #include "rtl_core.h"
  21 #include "r8192E_hw.h"
  22 #include "r8192E_phyreg.h"
  23 #include "r8190P_rtl8256.h"
  24 #include "r8192E_phy.h"
  25 #include "rtl_dm.h"
  26 #include "dot11d.h"
  27
  28 #include "r8192E_hwimg.h"
  29
  30 static u32 RF_CHANNEL_TABLE_ZEBRA[] = {
  31         0,
  32         0x085c,
  33         0x08dc,
  34         0x095c,
  35         0x09dc,
  36         0x0a5c,
  37         0x0adc,
  38         0x0b5c,
  39         0x0bdc,
  40         0x0c5c,
  41         0x0cdc,
  42         0x0d5c,
  43         0x0ddc,
  44         0x0e5c,
  45         0x0f72,
  46 };
  47
  48 /*************************Define local function prototype**********************/
  49
  50 static u32 phy_FwRFSerialRead(struct net_device* dev,enum rf90_radio_path eRFPath,u32 Offset);
  51 static void phy_FwRFSerialWrite(struct net_device* dev,enum rf90_radio_path eRFPath,u32 Offset,u32      Data);
  52 u32 rtl8192_CalculateBitShift(u32 dwBitMask)
  53 {
  54         u32 i;
  55         for (i=0; i<=31; i++)
  56         {
  57                 if (((dwBitMask>>i)&0x1) == 1)
  58                         break;
  59         }
  60         return i;
  61 }
  62 u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device* dev, u32 eRFPath)
  63 {
  64         u8 ret = 1;
  65         struct r8192_priv *priv = rtllib_priv(dev);
  66         if (priv->rf_type == RF_2T4R)
  67                 ret = 0;
  68         else if (priv->rf_type == RF_1T2R)
  69         {
  70                 if (eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B)
  71                         ret = 1;
  72                 else if (eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D)
  73                         ret = 0;
  74         }
  75         return ret;
  76 }
  77 void rtl8192_setBBreg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask, u32 dwData)
  78 {
  79
  80         u32 OriginalValue, BitShift, NewValue;
  81
  82         if (dwBitMask!= bMaskDWord)
  83         {
  84                 OriginalValue = read_nic_dword(dev, dwRegAddr);
  85                 BitShift = rtl8192_CalculateBitShift(dwBitMask);
  86                 NewValue = (((OriginalValue) & (~dwBitMask)) | (dwData << BitShift));
  87                 write_nic_dword(dev, dwRegAddr, NewValue);
  88         }else
  89                 write_nic_dword(dev, dwRegAddr, dwData);
  90         return;
  91 }
  92 u32 rtl8192_QueryBBReg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask)
  93 {
  94         u32 Ret = 0, OriginalValue, BitShift;
  95
  96         OriginalValue = read_nic_dword(dev, dwRegAddr);
  97         BitShift = rtl8192_CalculateBitShift(dwBitMask);
  98         Ret = (OriginalValue & dwBitMask) >> BitShift;
  99
 100         return (Ret);
 101 }
 102 u32 rtl8192_phy_RFSerialRead(struct net_device* dev, enum rf90_radio_path eRFPath, u32 Offset)
 103 {
 104         struct r8192_priv *priv = rtllib_priv(dev);
 105         u32 ret = 0;
 106         u32 NewOffset = 0;
 107         struct bb_reg_definition* pPhyReg = &priv->PHYRegDef[eRFPath];
 108         Offset &= 0x3f;
 109
 110         if (priv->rf_chip == RF_8256)
 111         {
 112                 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);
 113                 if (Offset >= 31)
 114                 {
 115                         priv->RfReg0Value[eRFPath] |= 0x140;
 116                         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16) );
 117                         NewOffset = Offset -30;
 118                 }
 119                 else if (Offset >= 16)
 120                 {
 121                         priv->RfReg0Value[eRFPath] |= 0x100;
 122                         priv->RfReg0Value[eRFPath] &= (~0x40);
 123                         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16) );
 124
 125                         NewOffset = Offset - 15;
 126                 }
 127                 else
 128                         NewOffset = Offset;
 129         }
 130         else
 131         {
 132                 RT_TRACE((COMP_PHY|COMP_ERR), "check RF type here, need to be 8256\n");
 133                 NewOffset = Offset;
 134         }
 135         rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress, NewOffset);
 136         rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2,  bLSSIReadEdge, 0x0);
 137         rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2,  bLSSIReadEdge, 0x1);
 138
 139
 140         msleep(1);
 141
 142         ret = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData);
 143
 144
 145         if (priv->rf_chip == RF_8256)
 146         {
 147                 priv->RfReg0Value[eRFPath] &= 0xebf;
 148
 149                 rtl8192_setBBreg(
 150                         dev,
 151                         pPhyReg->rf3wireOffset,
 152                         bMaskDWord,
 153                         (priv->RfReg0Value[eRFPath] << 16));
 154
 155                 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);
 156         }
 157
 158
 159         return ret;
 160
 161 }
 162
 163 void rtl8192_phy_RFSerialWrite(struct net_device* dev, enum rf90_radio_path eRFPath, u32 Offset, u32 Data)
 164 {
 165         struct r8192_priv *priv = rtllib_priv(dev);
 166         u32 DataAndAddr = 0, NewOffset = 0;
 167         struct bb_reg_definition *pPhyReg = &priv->PHYRegDef[eRFPath];
 168
 169         Offset &= 0x3f;
 170         if (priv->rf_chip == RF_8256)
 171         {
 172                 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);
 173
 174                 if (Offset >= 31)
 175                 {
 176                         priv->RfReg0Value[eRFPath] |= 0x140;
 177                         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath] << 16));
 178                         NewOffset = Offset - 30;
 179                 }
 180                 else if (Offset >= 16)
 181                 {
 182                         priv->RfReg0Value[eRFPath] |= 0x100;
 183                         priv->RfReg0Value[eRFPath] &= (~0x40);
 184                         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16));
 185                         NewOffset = Offset - 15;
 186                 }
 187                 else
 188                         NewOffset = Offset;
 189         }
 190         else
 191         {
 192                 RT_TRACE((COMP_PHY|COMP_ERR), "check RF type here, need to be 8256\n");
 193                 NewOffset = Offset;
 194         }
 195
 196         DataAndAddr = (Data<<16) | (NewOffset&0x3f);
 197
 198         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
 199
 200
 201         if (Offset==0x0)
 202                 priv->RfReg0Value[eRFPath] = Data;
 203
 204         if (priv->rf_chip == RF_8256)
 205         {
 206                 if (Offset != 0)
 207                 {
 208                         priv->RfReg0Value[eRFPath] &= 0xebf;
 209                         rtl8192_setBBreg(
 210                                 dev,
 211                                 pPhyReg->rf3wireOffset,
 212                                 bMaskDWord,
 213                                 (priv->RfReg0Value[eRFPath] << 16));
 214                 }
 215                 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);
 216         }
 217
 218         return;
 219 }
 220
 221 void rtl8192_phy_SetRFReg(struct net_device* dev, enum rf90_radio_path eRFPath, u32 RegAddr, u32 BitMask, u32 Data)
 222 {
 223         struct r8192_priv *priv = rtllib_priv(dev);
 224         u32 Original_Value, BitShift, New_Value;
 225
 226         if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
 227                 return;
 228         if (priv->rtllib->eRFPowerState != eRfOn && !priv->being_init_adapter)
 229                 return;
 230
 231         RT_TRACE(COMP_PHY, "FW RF CTRL is not ready now\n");
 232         if (priv->Rf_Mode == RF_OP_By_FW)
 233         {
 234                 if (BitMask != bMask12Bits)
 235                 {
 236                         Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr);
 237                         BitShift =  rtl8192_CalculateBitShift(BitMask);
 238                         New_Value = (((Original_Value) & (~BitMask)) | (Data<< BitShift));
 239
 240                         phy_FwRFSerialWrite(dev, eRFPath, RegAddr, New_Value);
 241                 }else
 242                         phy_FwRFSerialWrite(dev, eRFPath, RegAddr, Data);
 243                 udelay(200);
 244
 245         }
 246         else
 247         {
 248                 if (BitMask != bMask12Bits)
 249                 {
 250                         Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath, RegAddr);
 251                         BitShift =  rtl8192_CalculateBitShift(BitMask);
 252                         New_Value = (((Original_Value) & (~BitMask)) | (Data<< BitShift));
 253
 254                         rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, New_Value);
 255                 }else
 256                         rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, Data);
 257         }
 258         return;
 259 }
 260
 261 u32 rtl8192_phy_QueryRFReg(struct net_device* dev, enum rf90_radio_path eRFPath, u32 RegAddr, u32 BitMask)
 262 {
 263         u32 Original_Value, Readback_Value, BitShift;
 264         struct r8192_priv *priv = rtllib_priv(dev);
 265         if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
 266                 return 0;
 267         if (priv->rtllib->eRFPowerState != eRfOn && !priv->being_init_adapter)
 268                 return  0;
 269         down(&priv->rf_sem);
 270         if (priv->Rf_Mode == RF_OP_By_FW)
 271         {
 272                 Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr);
 273                 udelay(200);
 274         }
 275         else
 276         {
 277                 Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath, RegAddr);
 278
 279         }
 280         BitShift =  rtl8192_CalculateBitShift(BitMask);
 281         Readback_Value = (Original_Value & BitMask) >> BitShift;
 282         up(&priv->rf_sem);
 283         return (Readback_Value);
 284 }
 285
 286 static u32 phy_FwRFSerialRead(
 287         struct net_device* dev,
 288         enum rf90_radio_path eRFPath,
 289         u32                             Offset  )
 290 {
 291         u32             retValue = 0;
 292         u32             Data = 0;
 293         u8              time = 0;
 294         Data |= ((Offset&0xFF)<<12);
 295         Data |= ((eRFPath&0x3)<<20);
 296         Data |= 0x80000000;
 297         while (read_nic_dword(dev, QPNR)&0x80000000)
 298         {
 299                 if (time++ < 100)
 300                 {
 301                         udelay(10);
 302                 }
 303                 else
 304                         break;
 305         }
 306         write_nic_dword(dev, QPNR, Data);
 307         while (read_nic_dword(dev, QPNR)&0x80000000)
 308         {
 309                 if (time++ < 100)
 310                 {
 311                         udelay(10);
 312                 }
 313                 else
 314                         return  (0);
 315         }
 316         retValue = read_nic_dword(dev, RF_DATA);
 317
 318         return  (retValue);
 319
 320 }       /* phy_FwRFSerialRead */
 321
 322 static void
 323 phy_FwRFSerialWrite(
 324                 struct net_device* dev,
 325                 enum rf90_radio_path eRFPath,
 326                 u32                             Offset,
 327                 u32                             Data    )
 328 {
 329         u8      time = 0;
 330
 331
 332         Data |= ((Offset&0xFF)<<12);
 333         Data |= ((eRFPath&0x3)<<20);
 334         Data |= 0x400000;
 335         Data |= 0x80000000;
 336
 337         while (read_nic_dword(dev, QPNR)&0x80000000)
 338         {
 339                 if (time++ < 100)
 340                 {
 341                         udelay(10);
 342                 }
 343                 else
 344                         break;
 345         }
 346         write_nic_dword(dev, QPNR, Data);
 347
 348 }       /* phy_FwRFSerialWrite */
 349
 350
 351 void rtl8192_phy_configmac(struct net_device* dev)
 352 {
 353         u32 dwArrayLen = 0, i = 0;
 354         u32* pdwArray = NULL;
 355         struct r8192_priv *priv = rtllib_priv(dev);
 356          if (priv->bTXPowerDataReadFromEEPORM)
 357         {
 358                 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array_PG\n");
 359                 dwArrayLen = MACPHY_Array_PGLength;
 360                 pdwArray = Rtl819XMACPHY_Array_PG;
 361
 362         }
 363         else
 364         {
 365                 RT_TRACE(COMP_PHY,"Read rtl819XMACPHY_Array\n");
 366                 dwArrayLen = MACPHY_ArrayLength;
 367                 pdwArray = Rtl819XMACPHY_Array;
 368         }
 369         for (i = 0; i<dwArrayLen; i=i+3){
 370                 RT_TRACE(COMP_DBG, "The Rtl8190MACPHY_Array[0] is %x Rtl8190MACPHY_Array[1] is %x Rtl8190MACPHY_Array[2] is %x\n",
 371                                 pdwArray[i], pdwArray[i+1], pdwArray[i+2]);
 372                 if (pdwArray[i] == 0x318)
 373                 {
 374                         pdwArray[i+2] = 0x00000800;
 375                 }
 376                 rtl8192_setBBreg(dev, pdwArray[i], pdwArray[i+1], pdwArray[i+2]);
 377         }
 378         return;
 379
 380 }
 381
 382 void rtl8192_phyConfigBB(struct net_device* dev, u8 ConfigType)
 383 {
 384         int i;
 385         u32*    Rtl819XPHY_REGArray_Table = NULL;
 386         u32*    Rtl819XAGCTAB_Array_Table = NULL;
 387         u16     AGCTAB_ArrayLen, PHY_REGArrayLen = 0;
 388         struct r8192_priv *priv = rtllib_priv(dev);
 389         {
 390                 AGCTAB_ArrayLen = AGCTAB_ArrayLength;
 391                 Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_Array;
 392                 if (priv->rf_type == RF_2T4R)
 393                 {
 394                         PHY_REGArrayLen = PHY_REGArrayLength;
 395                         Rtl819XPHY_REGArray_Table = Rtl819XPHY_REGArray;
 396                 }
 397                 else if (priv->rf_type == RF_1T2R)
 398                 {
 399                         PHY_REGArrayLen = PHY_REG_1T2RArrayLength;
 400                         Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1T2RArray;
 401                 }
 402         }
 403
 404         if (ConfigType == BaseBand_Config_PHY_REG)
 405         {
 406                 for (i=0; i<PHY_REGArrayLen; i+=2)
 407                 {
 408                         rtl8192_setBBreg(dev, Rtl819XPHY_REGArray_Table[i], bMaskDWord, Rtl819XPHY_REGArray_Table[i+1]);
 409                         RT_TRACE(COMP_DBG, "i: %x, The Rtl819xUsbPHY_REGArray[0] is %x Rtl819xUsbPHY_REGArray[1] is %x \n",i, Rtl819XPHY_REGArray_Table[i], Rtl819XPHY_REGArray_Table[i+1]);
 410                 }
 411         }
 412         else if (ConfigType == BaseBand_Config_AGC_TAB)
 413         {
 414                 for (i=0; i<AGCTAB_ArrayLen; i+=2)
 415                 {
 416                         rtl8192_setBBreg(dev, Rtl819XAGCTAB_Array_Table[i], bMaskDWord, Rtl819XAGCTAB_Array_Table[i+1]);
 417                         RT_TRACE(COMP_DBG, "i:%x, The rtl819XAGCTAB_Array[0] is %x rtl819XAGCTAB_Array[1] is %x \n",i, Rtl819XAGCTAB_Array_Table[i], Rtl819XAGCTAB_Array_Table[i+1]);
 418                 }
 419         }
 420         return;
 421
 422
 423 }
 424 void rtl8192_InitBBRFRegDef(struct net_device* dev)
 425 {
 426         struct r8192_priv *priv = rtllib_priv(dev);
 427         priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW;
 428         priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW;
 429         priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;
 430         priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;
 431
 432         priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB;
 433         priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;
 434         priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;
 435         priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;
 436
 437         priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE;
 438         priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE;
 439         priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE;
 440         priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE;
 441
 442         priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE;
 443         priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE;
 444         priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE;
 445         priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE;
 446
 447         priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter;
 448         priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
 449         priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter;
 450         priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter;
 451
 452         priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter;
 453         priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter;
 454         priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter;
 455         priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter;
 456
 457         priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage;
 458         priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage;
 459         priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage;
 460         priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage;
 461
 462         priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1;
 463         priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1;
 464         priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1;
 465         priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1;
 466
 467         priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2;
 468         priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2;
 469         priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2;
 470         priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2;
 471
 472         priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl;
 473         priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl;
 474         priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl;
 475         priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl;
 476
 477         priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1;
 478         priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1;
 479         priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1;
 480         priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1;
 481
 482         priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2;
 483         priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2;
 484         priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2;
 485         priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2;
 486
 487         priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance;
 488         priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance;
 489         priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance;
 490         priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance;
 491
 492         priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE;
 493         priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE;
 494         priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE;
 495         priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE;
 496
 497         priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance;
 498         priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance;
 499         priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance;
 500         priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance;
 501
 502         priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE;
 503         priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE;
 504         priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE;
 505         priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE;
 506
 507         priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
 508         priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
 509         priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack;
 510         priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack;
 511
 512 }
 513 bool rtl8192_phy_checkBBAndRF(struct net_device* dev, enum hw90_block CheckBlock, enum rf90_radio_path eRFPath)
 514 {
 515         bool ret = true;
 516         u32 i, CheckTimes = 4, dwRegRead = 0;
 517         u32 WriteAddr[4];
 518         u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f};
 519         WriteAddr[HW90_BLOCK_MAC] = 0x100;
 520         WriteAddr[HW90_BLOCK_PHY0] = 0x900;
 521         WriteAddr[HW90_BLOCK_PHY1] = 0x800;
 522         WriteAddr[HW90_BLOCK_RF] = 0x3;
 523         RT_TRACE(COMP_PHY, "=======>%s(), CheckBlock:%d\n", __func__, CheckBlock);
 524         for (i=0 ; i < CheckTimes ; i++)
 525         {
 526
 527                 switch (CheckBlock)
 528                 {
 529                 case HW90_BLOCK_MAC:
 530                         RT_TRACE(COMP_ERR, "PHY_CheckBBRFOK(): Never Write 0x100 here!");
 531                         break;
 532
 533                 case HW90_BLOCK_PHY0:
 534                 case HW90_BLOCK_PHY1:
 535                         write_nic_dword(dev, WriteAddr[CheckBlock], WriteData[i]);
 536                         dwRegRead = read_nic_dword(dev, WriteAddr[CheckBlock]);
 537                         break;
 538
 539                 case HW90_BLOCK_RF:
 540                         WriteData[i] &= 0xfff;
 541                         rtl8192_phy_SetRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bMask12Bits, WriteData[i]);
 542                         mdelay(10);
 543                         dwRegRead = rtl8192_phy_QueryRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bMaskDWord);
 544                         mdelay(10);
 545                         break;
 546
 547                 default:
 548                         ret = false;
 549                         break;
 550                 }
 551
 552
 553                 if (dwRegRead != WriteData[i])
 554                 {
 555                         RT_TRACE(COMP_ERR, "====>error=====dwRegRead: %x, WriteData: %x \n", dwRegRead, WriteData[i]);
 556                         ret = false;
 557                         break;
 558                 }
 559         }
 560
 561         return ret;
 562 }
 563
 564 bool rtl8192_BB_Config_ParaFile(struct net_device* dev)
 565 {
 566         struct r8192_priv *priv = rtllib_priv(dev);
 567         bool rtStatus = true;
 568         u8 bRegValue = 0, eCheckItem = 0;
 569         u32 dwRegValue = 0;
 570         /**************************************
 571         **************************************/
 572
 573         bRegValue = read_nic_byte(dev, BB_GLOBAL_RESET);
 574         write_nic_byte(dev, BB_GLOBAL_RESET,(bRegValue|BB_GLOBAL_RESET_BIT));
 575
 576         dwRegValue = read_nic_dword(dev, CPU_GEN);
 577         write_nic_dword(dev, CPU_GEN, (dwRegValue&(~CPU_GEN_BB_RST)));
 578
 579         for (eCheckItem=(enum hw90_block)HW90_BLOCK_PHY0; eCheckItem<=HW90_BLOCK_PHY1; eCheckItem++)
 580         {
 581                 rtStatus  = rtl8192_phy_checkBBAndRF(dev, (enum hw90_block)eCheckItem, (enum rf90_radio_path)0);
 582                 if (rtStatus != true)
 583                 {
 584                         RT_TRACE((COMP_ERR | COMP_PHY), "PHY_RF8256_Config():Check PHY%d Fail!!\n", eCheckItem-1);
 585                         return rtStatus;
 586                 }
 587         }
 588         rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0);
 589         rtl8192_phyConfigBB(dev, BaseBand_Config_PHY_REG);
 590
 591         dwRegValue = read_nic_dword(dev, CPU_GEN);
 592         write_nic_dword(dev, CPU_GEN, (dwRegValue|CPU_GEN_BB_RST));
 593
 594         rtl8192_phyConfigBB(dev, BaseBand_Config_AGC_TAB);
 595
 596         if (priv->IC_Cut  > VERSION_8190_BD)
 597         {
 598                 if (priv->rf_type == RF_2T4R)
 599                 {
 600                 dwRegValue = (  priv->AntennaTxPwDiff[2]<<8 |
 601                                                 priv->AntennaTxPwDiff[1]<<4 |
 602                                                 priv->AntennaTxPwDiff[0]);
 603                 }
 604                 else
 605                         dwRegValue = 0x0;
 606                 rtl8192_setBBreg(dev, rFPGA0_TxGainStage,
 607                         (bXBTxAGC|bXCTxAGC|bXDTxAGC), dwRegValue);
 608
 609
 610                 dwRegValue = priv->CrystalCap;
 611                 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap92x, dwRegValue);
 612         }
 613
 614         return rtStatus;
 615 }
 616 bool rtl8192_BBConfig(struct net_device* dev)
 617 {
 618         bool rtStatus = true;
 619         rtl8192_InitBBRFRegDef(dev);
 620         rtStatus = rtl8192_BB_Config_ParaFile(dev);
 621         return rtStatus;
 622 }
 623
 624 void rtl8192_phy_getTxPower(struct net_device* dev)
 625 {
 626         struct r8192_priv *priv = rtllib_priv(dev);
 627         priv->MCSTxPowerLevelOriginalOffset[0] =
 628                 read_nic_dword(dev, rTxAGC_Rate18_06);
 629         priv->MCSTxPowerLevelOriginalOffset[1] =
 630                 read_nic_dword(dev, rTxAGC_Rate54_24);
 631         priv->MCSTxPowerLevelOriginalOffset[2] =
 632                 read_nic_dword(dev, rTxAGC_Mcs03_Mcs00);
 633         priv->MCSTxPowerLevelOriginalOffset[3] =
 634                 read_nic_dword(dev, rTxAGC_Mcs07_Mcs04);
 635         priv->MCSTxPowerLevelOriginalOffset[4] =
 636                 read_nic_dword(dev, rTxAGC_Mcs11_Mcs08);
 637         priv->MCSTxPowerLevelOriginalOffset[5] =
 638                 read_nic_dword(dev, rTxAGC_Mcs15_Mcs12);
 639
 640         priv->DefaultInitialGain[0] = read_nic_byte(dev, rOFDM0_XAAGCCore1);
 641         priv->DefaultInitialGain[1] = read_nic_byte(dev, rOFDM0_XBAGCCore1);
 642         priv->DefaultInitialGain[2] = read_nic_byte(dev, rOFDM0_XCAGCCore1);
 643         priv->DefaultInitialGain[3] = read_nic_byte(dev, rOFDM0_XDAGCCore1);
 644         RT_TRACE(COMP_INIT, "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x) \n",
 645                 priv->DefaultInitialGain[0], priv->DefaultInitialGain[1],
 646                 priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]);
 647
 648         priv->framesync = read_nic_byte(dev, rOFDM0_RxDetector3);
 649         priv->framesyncC34 = read_nic_dword(dev, rOFDM0_RxDetector2);
 650         RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x \n",
 651                 rOFDM0_RxDetector3, priv->framesync);
 652         priv->SifsTime = read_nic_word(dev, SIFS);
 653         return;
 654 }
 655
 656 void rtl8192_phy_setTxPower(struct net_device* dev, u8 channel)
 657 {
 658         struct r8192_priv *priv = rtllib_priv(dev);
 659         u8      powerlevel = 0,powerlevelOFDM24G = 0;
 660         char ant_pwr_diff;
 661         u32     u4RegValue;
 662
 663         if (priv->epromtype == EEPROM_93C46)
 664         {
 665                 powerlevel = priv->TxPowerLevelCCK[channel-1];
 666                 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
 667         }
 668         else if (priv->epromtype == EEPROM_93C56)
 669         {
 670                 if (priv->rf_type == RF_1T2R)
 671                 {
 672                         powerlevel = priv->TxPowerLevelCCK_C[channel-1];
 673                         powerlevelOFDM24G = priv->TxPowerLevelOFDM24G_C[channel-1];
 674                 }
 675                 else if (priv->rf_type == RF_2T4R)
 676                 {
 677                         powerlevel = priv->TxPowerLevelCCK_A[channel-1];
 678                         powerlevelOFDM24G = priv->TxPowerLevelOFDM24G_A[channel-1];
 679
 680                         ant_pwr_diff = priv->TxPowerLevelOFDM24G_C[channel-1]
 681                                                 -priv->TxPowerLevelOFDM24G_A[channel-1];
 682
 683                         priv->RF_C_TxPwDiff = ant_pwr_diff;
 684
 685                         ant_pwr_diff &= 0xf;
 686
 687                         priv->AntennaTxPwDiff[2] = 0;
 688                         priv->AntennaTxPwDiff[1] = (u8)(ant_pwr_diff);
 689                         priv->AntennaTxPwDiff[0] = 0;
 690
 691                         u4RegValue = (  priv->AntennaTxPwDiff[2]<<8 |
 692                                                 priv->AntennaTxPwDiff[1]<<4 |
 693                                                 priv->AntennaTxPwDiff[0]);
 694
 695                         rtl8192_setBBreg(dev, rFPGA0_TxGainStage,
 696                         (bXBTxAGC|bXCTxAGC|bXDTxAGC), u4RegValue);
 697                 }
 698         }
 699         switch (priv->rf_chip) {
 700         case RF_8225:
 701                 break;
 702         case RF_8256:
 703                 PHY_SetRF8256CCKTxPower(dev, powerlevel);
 704                 PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G);
 705                 break;
 706         case RF_8258:
 707                 break;
 708         default:
 709                 RT_TRACE(COMP_ERR, "unknown rf chip in funtion %s()\n", __func__);
 710                 break;
 711         }
 712         return;
 713 }
 714
 715 bool rtl8192_phy_RFConfig(struct net_device* dev)
 716 {
 717         struct r8192_priv *priv = rtllib_priv(dev);
 718         bool rtStatus = true;
 719         switch (priv->rf_chip)
 720         {
 721                 case RF_8225:
 722                         break;
 723                 case RF_8256:
 724                         rtStatus = PHY_RF8256_Config(dev);
 725                         break;
 726
 727                 case RF_8258:
 728                         break;
 729                 case RF_PSEUDO_11N:
 730                 break;
 731
 732                 default:
 733                         RT_TRACE(COMP_ERR, "error chip id\n");
 734                         break;
 735         }
 736         return rtStatus;
 737 }
 738
 739 void rtl8192_phy_updateInitGain(struct net_device* dev)
 740 {
 741         return;
 742 }
 743
 744 u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device* dev, enum rf90_radio_path eRFPath)
 745 {
 746
 747         int i;
 748         u8 ret = 0;
 749
 750         switch (eRFPath){
 751                 case RF90_PATH_A:
 752                         for (i = 0;i<RadioA_ArrayLength; i=i+2){
 753
 754                                 if (Rtl819XRadioA_Array[i] == 0xfe){
 755                                                 msleep(100);
 756                                                 continue;
 757                                 }
 758                                 rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioA_Array[i], bMask12Bits, Rtl819XRadioA_Array[i+1]);
 759
 760                         }
 761                         break;
 762                 case RF90_PATH_B:
 763                         for (i = 0;i<RadioB_ArrayLength; i=i+2){
 764
 765                                 if (Rtl819XRadioB_Array[i] == 0xfe){
 766                                                 msleep(100);
 767                                                 continue;
 768                                 }
 769                                 rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioB_Array[i], bMask12Bits, Rtl819XRadioB_Array[i+1]);
 770
 771                         }
 772                         break;
 773                 case RF90_PATH_C:
 774                         for (i = 0;i<RadioC_ArrayLength; i=i+2){
 775
 776                                 if (Rtl819XRadioC_Array[i] == 0xfe){
 777                                                 msleep(100);
 778                                                 continue;
 779                                 }
 780                                 rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioC_Array[i], bMask12Bits, Rtl819XRadioC_Array[i+1]);
 781
 782                         }
 783                         break;
 784                 case RF90_PATH_D:
 785                         for (i = 0;i<RadioD_ArrayLength; i=i+2){
 786
 787                                 if (Rtl819XRadioD_Array[i] == 0xfe){
 788                                                 msleep(100);
 789                                                 continue;
 790                                 }
 791                                 rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioD_Array[i], bMask12Bits, Rtl819XRadioD_Array[i+1]);
 792
 793                         }
 794                         break;
 795                 default:
 796                         break;
 797         }
 798
 799         return ret;;
 800
 801 }
 802 void rtl8192_SetTxPowerLevel(struct net_device *dev, u8 channel)
 803 {
 804         struct r8192_priv *priv = rtllib_priv(dev);
 805         u8      powerlevel = priv->TxPowerLevelCCK[channel-1];
 806         u8      powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
 807
 808         switch (priv->rf_chip)
 809         {
 810         case RF_8225:
 811                 break;
 812
 813         case RF_8256:
 814                 PHY_SetRF8256CCKTxPower(dev, powerlevel);
 815                 PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G);
 816                 break;
 817
 818         case RF_8258:
 819                 break;
 820         default:
 821                 RT_TRACE(COMP_ERR, "unknown rf chip ID in rtl8192_SetTxPowerLevel()\n");
 822                 break;
 823         }
 824         return;
 825 }
 826 u8 rtl8192_phy_SetSwChnlCmdArray(
 827         struct sw_chnl_cmd*             CmdTable,
 828         u32                     CmdTableIdx,
 829         u32                     CmdTableSz,
 830         enum sw_chnl_cmd_id CmdID,
 831         u32                     Para1,
 832         u32                     Para2,
 833         u32                     msDelay
 834         )
 835 {
 836         struct sw_chnl_cmd* pCmd;
 837
 838         if (CmdTable == NULL)
 839         {
 840                 RT_TRACE(COMP_ERR, "phy_SetSwChnlCmdArray(): CmdTable cannot be NULL.\n");
 841                 return false;
 842         }
 843         if (CmdTableIdx >= CmdTableSz)
 844         {
 845                 RT_TRACE(COMP_ERR, "phy_SetSwChnlCmdArray(): Access invalid index, please check size of the table, CmdTableIdx:%d, CmdTableSz:%d\n",
 846                                 CmdTableIdx, CmdTableSz);
 847                 return false;
 848         }
 849
 850         pCmd = CmdTable + CmdTableIdx;
 851         pCmd->CmdID = CmdID;
 852         pCmd->Para1 = Para1;
 853         pCmd->Para2 = Para2;
 854         pCmd->msDelay = msDelay;
 855
 856         return true;
 857 }
 858 u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, u8* stage, u8* step, u32* delay)
 859 {
 860         struct r8192_priv *priv = rtllib_priv(dev);
 861         struct sw_chnl_cmd PreCommonCmd[MAX_PRECMD_CNT];
 862         u32                                     PreCommonCmdCnt;
 863         struct sw_chnl_cmd PostCommonCmd[MAX_POSTCMD_CNT];
 864         u32                                     PostCommonCmdCnt;
 865         struct sw_chnl_cmd RfDependCmd[MAX_RFDEPENDCMD_CNT];
 866         u32                                     RfDependCmdCnt;
 867         struct sw_chnl_cmd *CurrentCmd = NULL;
 868         u8              eRFPath;
 869
 870         RT_TRACE(COMP_TRACE, "====>%s()====stage:%d, step:%d, channel:%d\n", __func__, *stage, *step, channel);
 871
 872         if (!IsLegalChannel(priv->rtllib, channel))
 873         {
 874                 RT_TRACE(COMP_ERR, "=============>set to illegal channel:%d\n", channel);
 875                 return true;
 876         }
 877
 878         {
 879                 PreCommonCmdCnt = 0;
 880                 rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
 881                                         CmdID_SetTxPowerLevel, 0, 0, 0);
 882                 rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
 883                                         CmdID_End, 0, 0, 0);
 884
 885                 PostCommonCmdCnt = 0;
 886
 887                 rtl8192_phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++, MAX_POSTCMD_CNT,
 888                                         CmdID_End, 0, 0, 0);
 889
 890                 RfDependCmdCnt = 0;
 891                 switch ( priv->rf_chip )
 892                 {
 893                 case RF_8225:
 894                         if (!(channel >= 1 && channel <= 14))
 895                         {
 896                                 RT_TRACE(COMP_ERR, "illegal channel for Zebra 8225: %d\n", channel);
 897                                 return false;
 898                         }
 899                         rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
 900                                 CmdID_RF_WriteReg, rZebra1_Channel, RF_CHANNEL_TABLE_ZEBRA[channel], 10);
 901                         rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
 902                                 CmdID_End, 0, 0, 0);
 903                         break;
 904
 905                 case RF_8256:
 906                         if (!(channel >= 1 && channel <= 14))
 907                         {
 908                                 RT_TRACE(COMP_ERR, "illegal channel for Zebra 8256: %d\n", channel);
 909                                 return false;
 910                         }
 911                         rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
 912                                 CmdID_RF_WriteReg, rZebra1_Channel, channel, 10);
 913                         rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
 914                         CmdID_End, 0, 0, 0);
 915                         break;
 916
 917                 case RF_8258:
 918                         break;
 919
 920                 default:
 921                         RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip);
 922                         return false;
 923                         break;
 924                 }
 925
 926
 927                 do{
 928                         switch (*stage)
 929                         {
 930                         case 0:
 931                                 CurrentCmd=&PreCommonCmd[*step];
 932                                 break;
 933                         case 1:
 934                                 CurrentCmd=&RfDependCmd[*step];
 935                                 break;
 936                         case 2:
 937                                 CurrentCmd=&PostCommonCmd[*step];
 938                                 break;
 939                         }
 940
 941                         if (CurrentCmd->CmdID==CmdID_End)
 942                         {
 943                                 if ((*stage)==2)
 944                                 {
 945                                         return true;
 946                                 }
 947                                 else
 948                                 {
 949                                         (*stage)++;
 950                                         (*step)=0;
 951                                         continue;
 952                                 }
 953                         }
 954
 955                         switch (CurrentCmd->CmdID)
 956                         {
 957                         case CmdID_SetTxPowerLevel:
 958                                 if (priv->IC_Cut > (u8)VERSION_8190_BD)
 959                                         rtl8192_SetTxPowerLevel(dev,channel);
 960                                 break;
 961                         case CmdID_WritePortUlong:
 962                                 write_nic_dword(dev, CurrentCmd->Para1, CurrentCmd->Para2);
 963                                 break;
 964                         case CmdID_WritePortUshort:
 965                                 write_nic_word(dev, CurrentCmd->Para1, (u16)CurrentCmd->Para2);
 966                                 break;
 967                         case CmdID_WritePortUchar:
 968                                 write_nic_byte(dev, CurrentCmd->Para1, (u8)CurrentCmd->Para2);
 969                                 break;
 970                         case CmdID_RF_WriteReg:
 971                                 for (eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++)
 972                                         rtl8192_phy_SetRFReg(dev, (enum rf90_radio_path)eRFPath, CurrentCmd->Para1, bMask12Bits, CurrentCmd->Para2<<7);
 973                                 break;
 974                         default:
 975                                 break;
 976                         }
 977
 978                         break;
 979                 }while(true);
 980         }/*for (Number of RF paths)*/
 981
 982         (*delay)=CurrentCmd->msDelay;
 983         (*step)++;
 984         return false;
 985 }
 986
 987 void rtl8192_phy_FinishSwChnlNow(struct net_device *dev, u8 channel)
 988 {
 989         struct r8192_priv *priv = rtllib_priv(dev);
 990         u32     delay = 0;
 991
 992         while(!rtl8192_phy_SwChnlStepByStep(dev,channel,&priv->SwChnlStage,&priv->SwChnlStep,&delay))
 993         {
 994                 if (delay>0)
 995                         msleep(delay);
 996                 if (IS_NIC_DOWN(priv))
 997                         break;
 998         }
 999 }
1000 void rtl8192_SwChnl_WorkItem(struct net_device *dev)
1001 {
1002
1003         struct r8192_priv *priv = rtllib_priv(dev);
1004
1005         RT_TRACE(COMP_TRACE, "==> SwChnlCallback819xUsbWorkItem()\n");
1006
1007         RT_TRACE(COMP_TRACE, "=====>--%s(), set chan:%d, priv:%p\n", __func__, priv->chan, priv);
1008
1009         rtl8192_phy_FinishSwChnlNow(dev , priv->chan);
1010
1011         RT_TRACE(COMP_TRACE, "<== SwChnlCallback819xUsbWorkItem()\n");
1012 }
1013
1014 u8 rtl8192_phy_SwChnl(struct net_device* dev, u8 channel)
1015 {
1016         struct r8192_priv *priv = rtllib_priv(dev);
1017         RT_TRACE(COMP_PHY, "=====>%s()\n", __func__);
1018         if (IS_NIC_DOWN(priv))
1019         {
1020                 RT_TRACE(COMP_ERR, "%s(): ERR !! driver is not up\n",__func__);
1021                 return false;
1022         }
1023         if (priv->SwChnlInProgress)
1024                 return false;
1025
1026
1027         switch (priv->rtllib->mode)
1028         {
1029         case WIRELESS_MODE_A:
1030         case WIRELESS_MODE_N_5G:
1031                 if (channel<=14){
1032                         RT_TRACE(COMP_ERR, "WIRELESS_MODE_A but channel<=14");
1033                         return false;
1034                 }
1035                 break;
1036         case WIRELESS_MODE_B:
1037                 if (channel>14){
1038                         RT_TRACE(COMP_ERR, "WIRELESS_MODE_B but channel>14");
1039                         return false;
1040                 }
1041                 break;
1042         case WIRELESS_MODE_G:
1043         case WIRELESS_MODE_N_24G:
1044                 if (channel>14){
1045                         RT_TRACE(COMP_ERR, "WIRELESS_MODE_G but channel>14");
1046                         return false;
1047                 }
1048                 break;
1049         }
1050
1051         priv->SwChnlInProgress = true;
1052         if (channel == 0)
1053                 channel = 1;
1054
1055         priv->chan=channel;
1056
1057         priv->SwChnlStage=0;
1058         priv->SwChnlStep=0;
1059
1060         if (!IS_NIC_DOWN(priv)){
1061                 rtl8192_SwChnl_WorkItem(dev);
1062         }
1063         priv->SwChnlInProgress = false;
1064         return true;
1065 }
1066
1067 static void CCK_Tx_Power_Track_BW_Switch_TSSI(struct net_device *dev    )
1068 {
1069         struct r8192_priv *priv = rtllib_priv(dev);
1070
1071         switch (priv->CurrentChannelBW)
1072         {
1073                 case HT_CHANNEL_WIDTH_20:
1074                         priv->CCKPresentAttentuation =
1075                                 priv->CCKPresentAttentuation_20Mdefault + priv->CCKPresentAttentuation_difference;
1076
1077                         if (priv->CCKPresentAttentuation > (CCKTxBBGainTableLength-1))
1078                                 priv->CCKPresentAttentuation = CCKTxBBGainTableLength-1;
1079                         if (priv->CCKPresentAttentuation < 0)
1080                                 priv->CCKPresentAttentuation = 0;
1081
1082                         RT_TRACE(COMP_POWER_TRACKING, "20M, priv->CCKPresentAttentuation = %d\n", priv->CCKPresentAttentuation);
1083
1084                         if (priv->rtllib->current_network.channel== 14 && !priv->bcck_in_ch14)
1085                         {
1086                                 priv->bcck_in_ch14 = true;
1087                                 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
1088                         }
1089                         else if (priv->rtllib->current_network.channel != 14 && priv->bcck_in_ch14)
1090                         {
1091                                 priv->bcck_in_ch14 = false;
1092                                 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
1093                         }
1094                         else
1095                                 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
1096                 break;
1097
1098                 case HT_CHANNEL_WIDTH_20_40:
1099                         priv->CCKPresentAttentuation =
1100                                 priv->CCKPresentAttentuation_40Mdefault + priv->CCKPresentAttentuation_difference;
1101
1102                         RT_TRACE(COMP_POWER_TRACKING, "40M, priv->CCKPresentAttentuation = %d\n", priv->CCKPresentAttentuation);
1103                         if (priv->CCKPresentAttentuation > (CCKTxBBGainTableLength-1))
1104                                 priv->CCKPresentAttentuation = CCKTxBBGainTableLength-1;
1105                         if (priv->CCKPresentAttentuation < 0)
1106                                 priv->CCKPresentAttentuation = 0;
1107
1108                         if (priv->rtllib->current_network.channel == 14 && !priv->bcck_in_ch14)
1109                         {
1110                                 priv->bcck_in_ch14 = true;
1111                                 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
1112                         }
1113                         else if (priv->rtllib->current_network.channel != 14 && priv->bcck_in_ch14)
1114                         {
1115                                 priv->bcck_in_ch14 = false;
1116                                 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
1117                         }
1118                         else
1119                                 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
1120                 break;
1121         }
1122 }
1123
1124 static void CCK_Tx_Power_Track_BW_Switch_ThermalMeter(struct net_device *dev)
1125 {
1126         struct r8192_priv *priv = rtllib_priv(dev);
1127
1128         if (priv->rtllib->current_network.channel == 14 && !priv->bcck_in_ch14)
1129                 priv->bcck_in_ch14 = true;
1130         else if (priv->rtllib->current_network.channel != 14 && priv->bcck_in_ch14)
1131                 priv->bcck_in_ch14 = false;
1132
1133         switch (priv->CurrentChannelBW)
1134         {
1135                 case HT_CHANNEL_WIDTH_20:
1136                         if (priv->Record_CCK_20Mindex == 0)
1137                                 priv->Record_CCK_20Mindex = 6;
1138                         priv->CCK_index = priv->Record_CCK_20Mindex;
1139                         RT_TRACE(COMP_POWER_TRACKING, "20MHz, CCK_Tx_Power_Track_BW_Switch_ThermalMeter(),CCK_index = %d\n", priv->CCK_index);
1140                 break;
1141
1142                 case HT_CHANNEL_WIDTH_20_40:
1143                         priv->CCK_index = priv->Record_CCK_40Mindex;
1144                         RT_TRACE(COMP_POWER_TRACKING, "40MHz, CCK_Tx_Power_Track_BW_Switch_ThermalMeter(), CCK_index = %d\n", priv->CCK_index);
1145                 break;
1146         }
1147         dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1148 }
1149
1150 static void CCK_Tx_Power_Track_BW_Switch(struct net_device *dev)
1151 {
1152         struct r8192_priv *priv = rtllib_priv(dev);
1153
1154         if (priv->IC_Cut >= IC_VersionCut_D)
1155                 CCK_Tx_Power_Track_BW_Switch_TSSI(dev);
1156         else
1157                 CCK_Tx_Power_Track_BW_Switch_ThermalMeter(dev);
1158 }
1159
1160 void rtl8192_SetBWModeWorkItem(struct net_device *dev)
1161 {
1162
1163         struct r8192_priv *priv = rtllib_priv(dev);
1164         u8 regBwOpMode;
1165
1166         RT_TRACE(COMP_SWBW, "==>rtl8192_SetBWModeWorkItem()  Switch to %s bandwidth\n", \
1167                                         priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz")
1168
1169
1170         if (priv->rf_chip== RF_PSEUDO_11N)
1171         {
1172                 priv->SetBWModeInProgress= false;
1173                 return;
1174         }
1175         if (IS_NIC_DOWN(priv)){
1176                 RT_TRACE(COMP_ERR,"%s(): ERR!! driver is not up\n",__func__);
1177                 return;
1178         }
1179         regBwOpMode = read_nic_byte(dev, BW_OPMODE);
1180
1181         switch (priv->CurrentChannelBW)
1182         {
1183                 case HT_CHANNEL_WIDTH_20:
1184                         regBwOpMode |= BW_OPMODE_20MHZ;
1185                         write_nic_byte(dev, BW_OPMODE, regBwOpMode);
1186                         break;
1187
1188                 case HT_CHANNEL_WIDTH_20_40:
1189                         regBwOpMode &= ~BW_OPMODE_20MHZ;
1190                         write_nic_byte(dev, BW_OPMODE, regBwOpMode);
1191                         break;
1192
1193                 default:
1194                         RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n",priv->CurrentChannelBW);
1195                         break;
1196         }
1197
1198         switch (priv->CurrentChannelBW)
1199         {
1200                 case HT_CHANNEL_WIDTH_20:
1201                         rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
1202                         rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
1203
1204                         if (!priv->btxpower_tracking)
1205                         {
1206                                 write_nic_dword(dev, rCCK0_TxFilter1, 0x1a1b0000);
1207                                 write_nic_dword(dev, rCCK0_TxFilter2, 0x090e1317);
1208                                 write_nic_dword(dev, rCCK0_DebugPort, 0x00000204);
1209                         }
1210                         else
1211                                 CCK_Tx_Power_Track_BW_Switch(dev);
1212
1213                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1);
1214
1215                         break;
1216                 case HT_CHANNEL_WIDTH_20_40:
1217                         rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
1218                         rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
1219
1220                         if (!priv->btxpower_tracking)
1221                         {
1222                                 write_nic_dword(dev, rCCK0_TxFilter1, 0x35360000);
1223                                 write_nic_dword(dev, rCCK0_TxFilter2, 0x121c252e);
1224                                 write_nic_dword(dev, rCCK0_DebugPort, 0x00000409);
1225                         }
1226                         else
1227                                 CCK_Tx_Power_Track_BW_Switch(dev);
1228
1229                         rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
1230                         rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC);
1231
1232
1233                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0);
1234                         break;
1235                 default:
1236                         RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n" ,priv->CurrentChannelBW);
1237                         break;
1238
1239         }
1240
1241         switch ( priv->rf_chip )
1242         {
1243                 case RF_8225:
1244                         break;
1245
1246                 case RF_8256:
1247                         PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW);
1248                         break;
1249
1250                 case RF_8258:
1251                         break;
1252
1253                 case RF_PSEUDO_11N:
1254                         break;
1255
1256                 default:
1257                         RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip);
1258                         break;
1259         }
1260
1261         atomic_dec(&(priv->rtllib->atm_swbw));
1262         priv->SetBWModeInProgress= false;
1263
1264         RT_TRACE(COMP_SWBW, "<==SetBWMode819xUsb()");
1265 }
1266
1267 void rtl8192_SetBWMode(struct net_device *dev, enum ht_channel_width Bandwidth, enum ht_extchnl_offset Offset)
1268 {
1269         struct r8192_priv *priv = rtllib_priv(dev);
1270
1271
1272         if (priv->SetBWModeInProgress)
1273                 return;
1274
1275          atomic_inc(&(priv->rtllib->atm_swbw));
1276         priv->SetBWModeInProgress= true;
1277
1278         priv->CurrentChannelBW = Bandwidth;
1279
1280         if (Offset==HT_EXTCHNL_OFFSET_LOWER)
1281                 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
1282         else if (Offset==HT_EXTCHNL_OFFSET_UPPER)
1283                 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
1284         else
1285                 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
1286
1287         rtl8192_SetBWModeWorkItem(dev);
1288
1289 }
1290
1291
1292 void InitialGain819xPci(struct net_device *dev, u8 Operation)
1293 {
1294 #define SCAN_RX_INITIAL_GAIN    0x17
1295 #define POWER_DETECTION_TH      0x08
1296         struct r8192_priv *priv = rtllib_priv(dev);
1297         u32                                     BitMask;
1298         u8                                      initial_gain;
1299
1300         if (!IS_NIC_DOWN(priv)){
1301                 switch (Operation)
1302                 {
1303                         case IG_Backup:
1304                         RT_TRACE(COMP_SCAN, "IG_Backup, backup the initial gain.\n");
1305                                 initial_gain = SCAN_RX_INITIAL_GAIN;
1306                                 BitMask = bMaskByte0;
1307                                 if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
1308                                         rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);
1309                                 priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, BitMask);
1310                                 priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, BitMask);
1311                                 priv->initgain_backup.xcagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, BitMask);
1312                                 priv->initgain_backup.xdagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, BitMask);
1313                                 BitMask  = bMaskByte2;
1314                                 priv->initgain_backup.cca               = (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, BitMask);
1315
1316                         RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc50 is %x\n",priv->initgain_backup.xaagccore1);
1317                         RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc58 is %x\n",priv->initgain_backup.xbagccore1);
1318                         RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc60 is %x\n",priv->initgain_backup.xcagccore1);
1319                         RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc68 is %x\n",priv->initgain_backup.xdagccore1);
1320                         RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xa0a is %x\n",priv->initgain_backup.cca);
1321
1322                         RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x \n", initial_gain);
1323                                 write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain);
1324                                 write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
1325                                 write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain);
1326                                 write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain);
1327                                 RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x \n", POWER_DETECTION_TH);
1328                                 write_nic_byte(dev, 0xa0a, POWER_DETECTION_TH);
1329                                 break;
1330                         case IG_Restore:
1331                         RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial gain.\n");
1332                                 BitMask = 0x7f;
1333                                 if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
1334                                         rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);
1335
1336                                 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, BitMask, (u32)priv->initgain_backup.xaagccore1);
1337                                 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, BitMask, (u32)priv->initgain_backup.xbagccore1);
1338                                 rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, BitMask, (u32)priv->initgain_backup.xcagccore1);
1339                                 rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, BitMask, (u32)priv->initgain_backup.xdagccore1);
1340                                 BitMask  = bMaskByte2;
1341                                 rtl8192_setBBreg(dev, rCCK0_CCA, BitMask, (u32)priv->initgain_backup.cca);
1342
1343                         RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc50 is %x\n",priv->initgain_backup.xaagccore1);
1344                         RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc58 is %x\n",priv->initgain_backup.xbagccore1);
1345                         RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc60 is %x\n",priv->initgain_backup.xcagccore1);
1346                         RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc68 is %x\n",priv->initgain_backup.xdagccore1);
1347                         RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xa0a is %x\n",priv->initgain_backup.cca);
1348
1349                                 rtl8192_phy_setTxPower(dev,priv->rtllib->current_network.channel);
1350
1351
1352                                 if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
1353                                         rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1);
1354                                 break;
1355                         default:
1356                         RT_TRACE(COMP_SCAN, "Unknown IG Operation. \n");
1357                                 break;
1358                 }
1359         }
1360 }
1361
1362 extern  void
1363 PHY_SetRtl8192eRfOff(struct net_device* dev     )
1364 {
1365
1366         rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x0);
1367         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x0);
1368         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, 0x0);
1369         rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0x0);
1370         rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0);
1371         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x0);
1372         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x4, 0x0);
1373         write_nic_byte(dev, ANAPAR_FOR_8192PciE, 0x07);
1374
1375 }
1376
1377 bool
1378 SetRFPowerState8190(
1379         struct net_device* dev,
1380         RT_RF_POWER_STATE       eRFPowerState
1381         )
1382 {
1383         struct r8192_priv *priv = rtllib_priv(dev);
1384         struct rt_pwr_save_ctrl *pPSC = (struct rt_pwr_save_ctrl *)(&(priv->rtllib->PowerSaveControl));
1385         bool bResult = true;
1386         u8      i = 0, QueueID = 0;
1387         struct rtl8192_tx_ring  *ring = NULL;
1388
1389         if (priv->SetRFPowerStateInProgress == true)
1390                 return false;
1391         RT_TRACE(COMP_PS, "===========> SetRFPowerState8190()!\n");
1392         priv->SetRFPowerStateInProgress = true;
1393
1394         switch (priv->rf_chip)
1395         {
1396                 case RF_8256:
1397                 switch ( eRFPowerState )
1398                 {
1399                         case eRfOn:
1400                                 RT_TRACE(COMP_PS, "SetRFPowerState8190() eRfOn !\n");
1401                                 if ((priv->rtllib->eRFPowerState == eRfOff) && RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC))
1402                                 {
1403                                         bool rtstatus = true;
1404                                         u32 InitilizeCount = 3;
1405                                         do
1406                                         {
1407                                                 InitilizeCount--;
1408                                                 priv->RegRfOff = false;
1409                                                 rtstatus = NicIFEnableNIC(dev);
1410                                         }while( (rtstatus != true) &&(InitilizeCount >0) );
1411
1412                                         if (rtstatus != true)
1413                                         {
1414                                                 RT_TRACE(COMP_ERR,"%s():Initialize Adapter fail,return\n",__func__);
1415                                                 priv->SetRFPowerStateInProgress = false;
1416                                                 return false;
1417                                         }
1418
1419                                         RT_CLEAR_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC);
1420                                 } else {
1421                                 write_nic_byte(dev, ANAPAR, 0x37);
1422                                 mdelay(1);
1423                                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x4, 0x1);
1424                                 priv->bHwRfOffAction = 0;
1425
1426                                         rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x1);
1427                                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);
1428                                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, 0x3);
1429                                         rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x3, 0x3);
1430                                         rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x3, 0x3);
1431                                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x3);
1432
1433                                 }
1434
1435                                                 break;
1436
1437                         case eRfSleep:
1438                         {
1439                                 if (priv->rtllib->eRFPowerState == eRfOff)
1440                                         break;
1441
1442
1443                                 {
1444                                         for (QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; )
1445                                         {
1446                                                         ring = &priv->tx_ring[QueueID];
1447
1448                                                         if (skb_queue_len(&ring->queue) == 0) {
1449                                                                 QueueID++;
1450                                                                 continue;
1451                                                         }
1452                                                         else
1453                                                         {
1454                                                                 RT_TRACE((COMP_POWER|COMP_RF), "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 before doze!\n", (i+1), QueueID);
1455                                                                 udelay(10);
1456                                                                 i++;
1457                                                         }
1458
1459                                                         if (i >= MAX_DOZE_WAITING_TIMES_9x)
1460                                                         {
1461                                                                 RT_TRACE(COMP_POWER, "\n\n\n TimeOut!! SetRFPowerState8190(): eRfOff: %d times TcbBusyQueue[%d] != 0 !!!\n\n\n", MAX_DOZE_WAITING_TIMES_9x, QueueID);
1462                                                                 break;
1463                                                         }
1464                                                 }
1465                                 }
1466
1467                                 {
1468                                         PHY_SetRtl8192eRfOff(dev);
1469                                 }
1470                         }
1471                                                                 break;
1472
1473                         case eRfOff:
1474                                 RT_TRACE(COMP_PS, "SetRFPowerState8190() eRfOff/Sleep !\n");
1475
1476
1477                                 for (QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; ) {
1478                                         ring = &priv->tx_ring[QueueID];
1479
1480                                         if (skb_queue_len(&ring->queue) == 0) {
1481                                                         QueueID++;
1482                                                         continue;
1483                                         }
1484                                                 else
1485                                                 {
1486                                                 RT_TRACE(COMP_POWER,
1487                                                 "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 before doze!\n", (i+1), QueueID);
1488                                                         udelay(10);
1489                                                         i++;
1490                                                 }
1491
1492                                                 if (i >= MAX_DOZE_WAITING_TIMES_9x)
1493                                                 {
1494                                                 RT_TRACE(COMP_POWER, "\n\n\n SetZebraRFPowerState8185B(): eRfOff: %d times TcbBusyQueue[%d] != 0 !!!\n\n\n", MAX_DOZE_WAITING_TIMES_9x, QueueID);
1495                                                         break;
1496                                                 }
1497                                         }
1498
1499                                 {
1500                                         if (pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_HALT_NIC && !RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC))
1501                                         {
1502
1503                                                 NicIFDisableNIC(dev);
1504                                                 RT_SET_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC);
1505                                         }
1506                                         else if (!(pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_HALT_NIC))
1507                                         {
1508                                                 PHY_SetRtl8192eRfOff(dev);
1509                                         }
1510                                 }
1511
1512                                         break;
1513
1514                         default:
1515                                         bResult = false;
1516                                         RT_TRACE(COMP_ERR, "SetRFPowerState8190(): unknow state to set: 0x%X!!!\n", eRFPowerState);
1517                                         break;
1518                 }
1519
1520                 break;
1521
1522                 default:
1523                         RT_TRACE(COMP_ERR, "SetRFPowerState8190(): Unknown RF type\n");
1524                         break;
1525         }
1526
1527         if (bResult) {
1528                 priv->rtllib->eRFPowerState = eRFPowerState;
1529
1530                 switch (priv->rf_chip) {
1531                 case RF_8256:
1532                         break;
1533
1534                 default:
1535                         RT_TRACE(COMP_ERR, "SetRFPowerState8190(): Unknown RF type\n");
1536                         break;
1537                 }
1538         }
1539
1540         priv->SetRFPowerStateInProgress = false;
1541         RT_TRACE(COMP_PS, "<=========== SetRFPowerState8190() bResult = %d!\n", bResult);
1542         return bResult;
1543 }
1544
1545
1546
1547 bool
1548 SetRFPowerState(
1549         struct net_device* dev,
1550         RT_RF_POWER_STATE       eRFPowerState
1551         )
1552 {
1553         struct r8192_priv *priv = rtllib_priv(dev);
1554
1555         bool bResult = false;
1556
1557         RT_TRACE(COMP_PS,"---------> SetRFPowerState(): eRFPowerState(%d)\n", eRFPowerState);
1558         if (eRFPowerState == priv->rtllib->eRFPowerState && priv->bHwRfOffAction == 0) {
1559                 RT_TRACE(COMP_PS, "<--------- SetRFPowerState(): discard the request for eRFPowerState(%d) is the same.\n", eRFPowerState);
1560                 return bResult;
1561         }
1562
1563         bResult = SetRFPowerState8190(dev, eRFPowerState);
1564
1565         RT_TRACE(COMP_PS, "<--------- SetRFPowerState(): bResult(%d)\n", bResult);
1566
1567         return bResult;
1568 }
1569
1570 extern void
1571 PHY_ScanOperationBackup8192(
1572         struct net_device* dev,
1573         u8 Operation
1574         )
1575 {
1576         struct r8192_priv *priv = rtllib_priv(dev);
1577
1578         if (priv->up) {
1579                 switch (Operation) {
1580                         case SCAN_OPT_BACKUP:
1581                                 priv->rtllib->InitialGainHandler(dev,IG_Backup);
1582                                 break;
1583
1584                         case SCAN_OPT_RESTORE:
1585                                 priv->rtllib->InitialGainHandler(dev,IG_Restore);
1586                                 break;
1587
1588                         default:
1589                                 RT_TRACE(COMP_SCAN, "Unknown Scan Backup Operation. \n");
1590                                 break;
1591                 }
1592         }
1593
1594 }