1 /******************************************************************************
2 * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
4 * This program is distributed in the hope that it will be useful, but WITHOUT
5 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
6 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
9 * You should have received a copy of the GNU General Public License along with
10 * this program; if not, write to the Free Software Foundation, Inc.,
11 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
13 * The full GNU General Public License is included in this distribution in the
14 * file called LICENSE.
16 * Contact Information:
17 * wlanfae <wlanfae@realtek.com>
18 ******************************************************************************/
19 #ifndef _RTL819XU_HTTYPE_H_
20 #define _RTL819XU_HTTYPE_H_
23 #define HT_OPMODE_NO_PROTECT 0
24 #define HT_OPMODE_OPTIONAL 1
25 #define HT_OPMODE_40MHZ_PROTECT 2
26 #define HT_OPMODE_MIXED 3
28 #define MIMO_PS_STATIC 0
29 #define MIMO_PS_DYNAMIC 1
30 #define MIMO_PS_NOLIMIT 3
37 #define HT_SUPPORTED_MCS_1SS_BITMAP 0x000000ff
38 #define HT_SUPPORTED_MCS_2SS_BITMAP 0x0000ff00
39 #define HT_SUPPORTED_MCS_1SS_2SS_BITMAP HT_MCS_1SS_BITMAP|HT_MCS_1SS_2SS_BITMAP
53 HT_MCS10 = 0x00000400,
54 HT_MCS11 = 0x00000800,
55 HT_MCS12 = 0x00001000,
56 HT_MCS13 = 0x00002000,
57 HT_MCS14 = 0x00004000,
58 HT_MCS15 = 0x00008000,
61 enum ht_channel_width {
62 HT_CHANNEL_WIDTH_20 = 0,
63 HT_CHANNEL_WIDTH_20_40 = 1,
66 enum ht_extchnl_offset {
67 HT_EXTCHNL_OFFSET_NO_EXT = 0,
68 HT_EXTCHNL_OFFSET_UPPER = 1,
69 HT_EXTCHNL_OFFSET_NO_DEF = 2,
70 HT_EXTCHNL_OFFSET_LOWER = 3,
80 #define CHHLOP_IN_PROGRESS(_pHTInfo) \
81 ((_pHTInfo)->ChnlOp > CHNLOP_NONE) ? true : false
105 union ht_capability_macpara {
117 typedef enum _HT_ACTION{
118 ACT_RECOMMAND_WIDTH = 0,
119 ACT_MIMO_PWR_SAVE = 1,
121 ACT_SET_PCO_PHASE = 3,
122 ACT_MIMO_CHL_MEASURE = 4,
123 ACT_RECIPROCITY_CORRECT = 5,
124 ACT_MIMO_CSI_MATRICS = 6,
125 ACT_MIMO_NOCOMPR_STEER = 7,
126 ACT_MIMO_COMPR_STEER = 8,
127 ACT_ANTENNA_SELECT = 9,
128 } HT_ACTION, *PHT_ACTION;
131 typedef enum _HT_Bandwidth_40MHZ_Sub_Carrier{
132 SC_MODE_DUPLICATE = 0,
135 SC_MODE_FULL40MHZ = 3,
138 struct ht_capab_ele {
153 u8 LSigTxopProtect:1;
155 u8 MaxRxAMPDUFactor:2;
175 u8 RecommemdedTxWidth:1;
178 u8 SrvIntGranularity:3;
181 u8 NonGFDevPresent:1;
189 u8 SecondaryBeacon:1;
190 u8 LSigTxopProtectFull:1;
204 typedef enum _HT_SPEC_VER{
205 HT_SPEC_VER_IEEE = 0,
207 } HT_SPEC_VER, *PHT_SPEC_VER;
209 typedef enum _HT_AGGRE_MODE_E{
211 HT_AGG_FORCE_ENABLE = 1,
212 HT_AGG_FORCE_DISABLE = 2,
213 } HT_AGGRE_MODE_E, *PHT_AGGRE_MODE_E;
216 struct rt_hi_throughput {
218 u8 bCurrentHTSupport;
232 HT_SPEC_VER ePeerHTSpecVer;
235 struct ht_capab_ele SelfHTCap;
236 struct ht_info_ele SelfHTInfo;
239 u8 PeerHTInfoBuf[32];
244 u8 bCurrent_AMSDU_Support;
245 u16 nCurrent_AMSDU_MaxSize;
248 u8 bCurrentAMPDUEnable;
250 u8 CurrentAMPDUFactor;
252 u8 CurrentMPDUDensity;
254 HT_AGGRE_MODE_E ForcedAMPDUMode;
255 u8 ForcedAMPDUFactor;
256 u8 ForcedMPDUDensity;
258 HT_AGGRE_MODE_E ForcedAMSDUMode;
259 u16 ForcedAMSDUMaxSize;
268 enum ht_extchnl_offset CurSTAExtChnlOffset;
276 u8 bRegRT2RTAggregation;
278 u8 bCurrentRT2RTAggregation;
279 u8 bCurrentRT2RTLongSlotTime;
280 u8 szRT2RTAggBuffer[10];
282 u8 bRegRxReorderEnable;
283 u8 bCurRxReorderEnable;
285 u8 RxReorderPendingTime;
286 u16 RxReorderDropCounter;
302 struct rt_htinfo_sta_entry {
312 u8 HTHighestOperaRate;
326 u8 bCurRxReorderEnable;
346 HT_SPEC_VER bdHTSpecVer;
347 enum ht_channel_width bdBandWidth;
349 u8 bdRT2RTAggregation;
350 u8 bdRT2RTLongSlotTime;
369 struct false_alarm_stats {
371 u32 Cnt_Rate_Illegal;
380 extern u8 MCS_FILTER_ALL[16];
381 extern u8 MCS_FILTER_1SS[16];
383 #define PICK_RATE(_nLegacyRate, _nMcsRate) \
384 (_nMcsRate==0)?(_nLegacyRate&0x7f):(_nMcsRate)
385 #define LEGACY_WIRELESS_MODE IEEE_MODE_MASK
387 #define CURRENT_RATE(WirelessMode, LegacyRate, HTRate) \
388 ((WirelessMode & (LEGACY_WIRELESS_MODE))!=0)?\
390 (PICK_RATE(LegacyRate, HTRate))
394 #define RATE_ADPT_1SS_MASK 0xFF
395 #define RATE_ADPT_2SS_MASK 0xF0
396 #define RATE_ADPT_MCS32_MASK 0x01
398 #define IS_11N_MCS_RATE(rate) (rate&0x80)
400 typedef enum _HT_AGGRE_SIZE_E{
405 } HT_AGGRE_SIZE_E, *PHT_AGGRE_SIZE_E;
407 typedef enum _HT_IOT_PEER_E
409 HT_IOT_PEER_UNKNOWN = 0,
410 HT_IOT_PEER_REALTEK = 1,
411 HT_IOT_PEER_REALTEK_92SE = 2,
412 HT_IOT_PEER_BROADCOM = 3,
413 HT_IOT_PEER_RALINK = 4,
414 HT_IOT_PEER_ATHEROS = 5,
415 HT_IOT_PEER_CISCO= 6,
416 HT_IOT_PEER_MARVELL=7,
417 HT_IOT_PEER_92U_SOFTAP = 8,
418 HT_IOT_PEER_SELF_SOFTAP = 9,
419 HT_IOT_PEER_AIRGO = 10,
420 HT_IOT_PEER_MAX = 11,
421 } HT_IOT_PEER_E, *PHTIOT_PEER_E;
423 typedef enum _HT_IOT_PEER_SUBTYPE_E
425 HT_IOT_PEER_ATHEROS_DIR635 = 0,
426 } HT_IOT_PEER_SUBTYPE_E, *PHTIOT_PEER_SUBTYPE_E;
428 typedef enum _HT_IOT_ACTION_E{
429 HT_IOT_ACT_TX_USE_AMSDU_4K = 0x00000001,
430 HT_IOT_ACT_TX_USE_AMSDU_8K = 0x00000002,
431 HT_IOT_ACT_DISABLE_MCS14 = 0x00000004,
432 HT_IOT_ACT_DISABLE_MCS15 = 0x00000008,
433 HT_IOT_ACT_DISABLE_ALL_2SS = 0x00000010,
434 HT_IOT_ACT_DISABLE_EDCA_TURBO = 0x00000020,
435 HT_IOT_ACT_MGNT_USE_CCK_6M = 0x00000040,
436 HT_IOT_ACT_CDD_FSYNC = 0x00000080,
437 HT_IOT_ACT_PURE_N_MODE = 0x00000100,
438 HT_IOT_ACT_FORCED_CTS2SELF = 0x00000200,
439 HT_IOT_ACT_FORCED_RTS = 0x00000400,
440 HT_IOT_ACT_AMSDU_ENABLE = 0x00000800,
441 HT_IOT_ACT_REJECT_ADDBA_REQ = 0x00001000,
442 HT_IOT_ACT_ALLOW_PEER_AGG_ONE_PKT = 0x00002000,
443 HT_IOT_ACT_EDCA_BIAS_ON_RX = 0x00004000,
445 HT_IOT_ACT_HYBRID_AGGREGATION = 0x00010000,
446 HT_IOT_ACT_DISABLE_SHORT_GI = 0x00020000,
447 HT_IOT_ACT_DISABLE_HIGH_POWER = 0x00040000,
448 HT_IOT_ACT_DISABLE_TX_40_MHZ = 0x00080000,
449 HT_IOT_ACT_TX_NO_AGGREGATION = 0x00100000,
450 HT_IOT_ACT_DISABLE_TX_2SS = 0x00200000,
452 HT_IOT_ACT_MID_HIGHPOWER = 0x00400000,
453 HT_IOT_ACT_NULL_DATA_POWER_SAVING = 0x00800000,
455 HT_IOT_ACT_DISABLE_CCK_RATE = 0x01000000,
456 HT_IOT_ACT_FORCED_ENABLE_BE_TXOP = 0x02000000,
457 HT_IOT_ACT_WA_IOT_Broadcom = 0x04000000,
459 HT_IOT_ACT_DISABLE_RX_40MHZ_SHORT_GI = 0x08000000,
461 } HT_IOT_ACTION_E, *PHT_IOT_ACTION_E;
463 typedef enum _HT_IOT_RAFUNC{
464 HT_IOT_RAFUNC_DISABLE_ALL = 0x00,
465 HT_IOT_RAFUNC_PEER_1R = 0x01,
466 HT_IOT_RAFUNC_TX_AMSDU = 0x02,
467 } HT_IOT_RAFUNC, *PHT_IOT_RAFUNC;
469 typedef enum _RT_HT_CAPBILITY{
470 RT_HT_CAP_USE_TURBO_AGGR = 0x01,
471 RT_HT_CAP_USE_LONG_PREAMBLE = 0x02,
472 RT_HT_CAP_USE_AMPDU = 0x04,
473 RT_HT_CAP_USE_WOW = 0x8,
474 RT_HT_CAP_USE_SOFTAP = 0x10,
475 RT_HT_CAP_USE_92SE = 0x20,
476 } RT_HT_CAPBILITY, *PRT_HT_CAPBILITY;