drivers/staging/rtl8192e/rtl_core.h

   1 /******************************************************************************
   2  * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
   3  *
   4  * Based on the r8180 driver, which is:
   5  * Copyright 2004-2005 Andrea Merello <andreamrl@tiscali.it>, et al.
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of version 2 of the GNU General Public License as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program; if not, write to the Free Software Foundation, Inc.,
  17  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  18  *
  19  * The full GNU General Public License is included in this distribution in the
  20  * file called LICENSE.
  21  *
  22  * Contact Information:
  23  * wlanfae <wlanfae@realtek.com>
  24 ******************************************************************************/
  25
  26 #ifndef _RTL_CORE_H
  27 #define _RTL_CORE_H
  28
  29 #include <linux/module.h>
  30 #include <linux/kernel.h>
  31 #include <linux/init.h>
  32 #include <linux/ioport.h>
  33 #include <linux/sched.h>
  34 #include <linux/types.h>
  35 #include <linux/interrupt.h>
  36 #include <linux/slab.h>
  37 #include <linux/netdevice.h>
  38 #include <linux/pci.h>
  39 #include <linux/etherdevice.h>
  40 #include <linux/delay.h>
  41 #include <linux/rtnetlink.h>
  42 #include <linux/wireless.h>
  43 #include <linux/timer.h>
  44 #include <linux/proc_fs.h>
  45 #include <linux/if_arp.h>
  46 #include <linux/random.h>
  47 #include <linux/version.h>
  48 #include <asm/io.h>
  49 #include "rtllib.h"
  50
  51 #include "dot11d.h"
  52
  53 #include "r8192E_firmware.h"
  54 #include "r8192E_hw.h"
  55
  56 #include "r8190P_def.h"
  57 #include "r8192E_dev.h"
  58
  59 #include "rtl_debug.h"
  60 #include "rtl_eeprom.h"
  61 #include "rtl_ps.h"
  62 #include "rtl_pci.h"
  63 #include "rtl_cam.h"
  64
  65 #define DRV_COPYRIGHT  "Copyright(c) 2008 - 2010 Realsil Semiconductor Corporation"
  66 #define DRV_AUTHOR  "<wlanfae@realtek.com>"
  67 #define DRV_VERSION  "0014.0401.2010"
  68
  69 #define DRV_NAME "rtl819xE"
  70
  71 #define IS_HARDWARE_TYPE_819xP(_priv) ((((struct r8192_priv *)rtllib_priv(dev))->card_8192==NIC_8190P)||\
  72                                         (((struct r8192_priv *)rtllib_priv(dev))->card_8192==NIC_8192E))
  73 #define IS_HARDWARE_TYPE_8192SE(_priv)  (((struct r8192_priv *)rtllib_priv(dev))->card_8192==NIC_8192SE)
  74 #define IS_HARDWARE_TYPE_8192CE(_priv)  (((struct r8192_priv *)rtllib_priv(dev))->card_8192==NIC_8192CE)
  75 #define IS_HARDWARE_TYPE_8192CU(_priv)  (((struct r8192_priv *)rtllib_priv(dev))->card_8192==NIC_8192CU)
  76 #define IS_HARDWARE_TYPE_8192DE(_priv)  (((struct r8192_priv *)rtllib_priv(dev))->card_8192==NIC_8192DE)
  77 #define IS_HARDWARE_TYPE_8192DU(_priv)  (((struct r8192_priv *)rtllib_priv(dev))->card_8192==NIC_8192DU)
  78
  79 #define RTL_PCI_DEVICE(vend, dev, cfg) \
  80         .vendor = (vend), .device = (dev), \
  81         .subvendor = PCI_ANY_ID, .subdevice =PCI_ANY_ID , \
  82         .driver_data = (kernel_ulong_t)&(cfg)
  83         typedef irqreturn_t irqreturn_type;
  84
  85
  86 #define rtl8192_interrupt(x,y,z) rtl8192_interrupt_rsl(x,y)
  87
  88 #define RTL_MAX_SCAN_SIZE 128
  89
  90 #define RTL_RATE_MAX            30
  91
  92 #define TOTAL_CAM_ENTRY         32
  93 #define CAM_CONTENT_COUNT       8
  94
  95 #ifndef BIT
  96 #define BIT(_i)                         (1<<(_i))
  97 #endif
  98
  99 #define IS_NIC_DOWN(priv)       (!(priv)->up)
 100
 101 #define IS_ADAPTER_SENDS_BEACON(dev) 0
 102
 103 #define IS_UNDER_11N_AES_MODE(_rtllib)  ((_rtllib->pHTInfo->bCurrentHTSupport == true) &&\
 104                                         (_rtllib->pairwise_key_type == KEY_TYPE_CCMP))
 105
 106 #define HAL_MEMORY_MAPPED_IO_RANGE_8190PCI      0x1000
 107 #define HAL_HW_PCI_REVISION_ID_8190PCI                  0x00
 108 #define HAL_MEMORY_MAPPED_IO_RANGE_8192PCIE     0x4000
 109 #define HAL_HW_PCI_REVISION_ID_8192PCIE         0x01
 110 #define HAL_MEMORY_MAPPED_IO_RANGE_8192SE       0x4000
 111 #define HAL_HW_PCI_REVISION_ID_8192SE   0x10
 112 #define HAL_HW_PCI_REVISION_ID_8192CE                   0x1
 113 #define HAL_MEMORY_MAPPED_IO_RANGE_8192CE       0x4000
 114 #define HAL_HW_PCI_REVISION_ID_8192DE                   0x0
 115 #define HAL_MEMORY_MAPPED_IO_RANGE_8192DE       0x4000
 116
 117 #define HAL_HW_PCI_8180_DEVICE_ID                       0x8180
 118 #define HAL_HW_PCI_8185_DEVICE_ID                       0x8185
 119 #define HAL_HW_PCI_8188_DEVICE_ID                       0x8188
 120 #define HAL_HW_PCI_8198_DEVICE_ID                       0x8198
 121 #define HAL_HW_PCI_8190_DEVICE_ID                       0x8190
 122 #define HAL_HW_PCI_8192_DEVICE_ID                       0x8192
 123 #define HAL_HW_PCI_8192SE_DEVICE_ID                             0x8192
 124 #define HAL_HW_PCI_8174_DEVICE_ID                       0x8174
 125 #define HAL_HW_PCI_8173_DEVICE_ID                       0x8173
 126 #define HAL_HW_PCI_8172_DEVICE_ID                       0x8172
 127 #define HAL_HW_PCI_8171_DEVICE_ID                       0x8171
 128 #define HAL_HW_PCI_0045_DEVICE_ID                               0x0045
 129 #define HAL_HW_PCI_0046_DEVICE_ID                               0x0046
 130 #define HAL_HW_PCI_0044_DEVICE_ID                               0x0044
 131 #define HAL_HW_PCI_0047_DEVICE_ID                               0x0047
 132 #define HAL_HW_PCI_700F_DEVICE_ID                               0x700F
 133 #define HAL_HW_PCI_701F_DEVICE_ID                               0x701F
 134 #define HAL_HW_PCI_DLINK_DEVICE_ID                              0x3304
 135 #define HAL_HW_PCI_8192CET_DEVICE_ID                    0x8191
 136 #define HAL_HW_PCI_8192CE_DEVICE_ID                             0x8178
 137 #define HAL_HW_PCI_8191CE_DEVICE_ID                             0x8177
 138 #define HAL_HW_PCI_8188CE_DEVICE_ID                             0x8176
 139 #define HAL_HW_PCI_8192CU_DEVICE_ID                             0x8191
 140 #define HAL_HW_PCI_8192DE_DEVICE_ID                             0x092D
 141 #define HAL_HW_PCI_8192DU_DEVICE_ID                             0x092D
 142
 143 #define RTL819X_DEFAULT_RF_TYPE         RF_1T2R
 144
 145 #define RTLLIB_WATCH_DOG_TIME           2000
 146
 147 #define MAX_DEV_ADDR_SIZE               8  /* support till 64 bit bus width OS */
 148 #define MAX_FIRMWARE_INFORMATION_SIZE   32
 149 #define MAX_802_11_HEADER_LENGTH        (40 + MAX_FIRMWARE_INFORMATION_SIZE)
 150 #define ENCRYPTION_MAX_OVERHEAD         128
 151 #define MAX_FRAGMENT_COUNT              8
 152 #define MAX_TRANSMIT_BUFFER_SIZE        (1600+(MAX_802_11_HEADER_LENGTH+ENCRYPTION_MAX_OVERHEAD)*MAX_FRAGMENT_COUNT)
 153
 154 #define scrclng                         4
 155
 156 #define DEFAULT_FRAG_THRESHOLD  2342U
 157 #define MIN_FRAG_THRESHOLD      256U
 158 #define DEFAULT_BEACONINTERVAL  0x64U
 159
 160 #define DEFAULT_SSID            ""
 161 #define DEFAULT_RETRY_RTS       7
 162 #define DEFAULT_RETRY_DATA      7
 163 #define PRISM_HDR_SIZE          64
 164
 165 #define PHY_RSSI_SLID_WIN_MAX                   100
 166
 167 #define RTL_IOCTL_WPA_SUPPLICANT                SIOCIWFIRSTPRIV+30
 168
 169 #define TxBBGainTableLength                     37
 170 #define CCKTxBBGainTableLength                  23
 171
 172 #define CHANNEL_PLAN_LEN                        10
 173 #define sCrcLng                                 4
 174
 175 #define NIC_SEND_HANG_THRESHOLD_NORMAL          4
 176 #define NIC_SEND_HANG_THRESHOLD_POWERSAVE       8
 177
 178 #define MAX_TX_QUEUE                            9
 179
 180 #define MAX_RX_QUEUE                            1
 181
 182 #define MAX_RX_COUNT                            64
 183 #define MAX_TX_QUEUE_COUNT                      9
 184
 185 enum RTL819x_PHY_PARAM {
 186         RTL819X_PHY_MACPHY_REG          = 0,
 187         RTL819X_PHY_MACPHY_REG_PG       = 1,
 188         RTL8188C_PHY_MACREG                     =2,
 189         RTL8192C_PHY_MACREG                     =3,
 190         RTL819X_PHY_REG                         = 4,
 191         RTL819X_PHY_REG_1T2R                    = 5,
 192         RTL819X_PHY_REG_to1T1R          = 6,
 193         RTL819X_PHY_REG_to1T2R          = 7,
 194         RTL819X_PHY_REG_to2T2R          = 8,
 195         RTL819X_PHY_REG_PG                      = 9,
 196         RTL819X_AGC_TAB                         = 10,
 197         RTL819X_PHY_RADIO_A                     =11,
 198         RTL819X_PHY_RADIO_A_1T          =12,
 199         RTL819X_PHY_RADIO_A_2T          =13,
 200         RTL819X_PHY_RADIO_B                     =14,
 201         RTL819X_PHY_RADIO_B_GM          =15,
 202         RTL819X_PHY_RADIO_C                     =16,
 203         RTL819X_PHY_RADIO_D                     =17,
 204         RTL819X_EEPROM_MAP                      =18,
 205         RTL819X_EFUSE_MAP                               =19,
 206 };
 207
 208 enum RTL_DEBUG {
 209         COMP_TRACE              = BIT0,
 210         COMP_DBG                = BIT1,
 211         COMP_INIT               = BIT2,
 212         COMP_RECV               = BIT3,
 213         COMP_SEND               = BIT4,
 214         COMP_CMD                = BIT5,
 215         COMP_POWER              = BIT6,
 216         COMP_EPROM              = BIT7,
 217         COMP_SWBW               = BIT8,
 218         COMP_SEC                = BIT9,
 219         COMP_LPS                = BIT10,
 220         COMP_QOS                = BIT11,
 221         COMP_RATE               = BIT12,
 222         COMP_RXDESC             = BIT13,
 223         COMP_PHY                = BIT14,
 224         COMP_DIG                = BIT15,
 225         COMP_TXAGC              = BIT16,
 226         COMP_HALDM              = BIT17,
 227         COMP_POWER_TRACKING     = BIT18,
 228         COMP_CH                 = BIT19,
 229         COMP_RF                 = BIT20,
 230         COMP_FIRMWARE           = BIT21,
 231         COMP_HT                 = BIT22,
 232         COMP_RESET              = BIT23,
 233         COMP_CMDPKT             = BIT24,
 234         COMP_SCAN               = BIT25,
 235         COMP_PS                 = BIT26,
 236         COMP_DOWN               = BIT27,
 237         COMP_INTR               = BIT28,
 238         COMP_LED                = BIT29,
 239         COMP_MLME               = BIT30,
 240         COMP_ERR                = BIT31
 241 };
 242
 243 enum nic_t {
 244         NIC_UNKNOWN     = 0,
 245         NIC_8192E       = 1,
 246         NIC_8190P       = 2,
 247         NIC_8192SE      = 4,
 248         NIC_8192CE              = 5,
 249         NIC_8192CU              = 6,
 250         NIC_8192DE              = 7,
 251         NIC_8192DU              = 8,
 252         };
 253
 254 enum rt_eeprom_type {
 255         EEPROM_93C46,
 256         EEPROM_93C56,
 257         EEPROM_BOOT_EFUSE,
 258 };
 259
 260 enum dcmg_txcmd_op {
 261         TXCMD_TXRA_HISTORY_CTRL         = 0xFF900000,
 262         TXCMD_RESET_TX_PKT_BUFF         = 0xFF900001,
 263         TXCMD_RESET_RX_PKT_BUFF         = 0xFF900002,
 264         TXCMD_SET_TX_DURATION           = 0xFF900003,
 265         TXCMD_SET_RX_RSSI               = 0xFF900004,
 266         TXCMD_SET_TX_PWR_TRACKING       = 0xFF900005,
 267         TXCMD_XXXX_CTRL,
 268 };
 269
 270 enum rt_rf_type_819xu {
 271         RF_TYPE_MIN = 0,
 272         RF_8225,
 273         RF_8256,
 274         RF_8258,
 275         RF_6052=4,
 276         RF_PSEUDO_11N = 5,
 277 };
 278
 279 enum rf_step {
 280     RF_STEP_INIT = 0,
 281     RF_STEP_NORMAL,
 282     RF_STEP_MAX
 283 };
 284
 285 enum rt_status {
 286         RT_STATUS_SUCCESS,
 287         RT_STATUS_FAILURE,
 288         RT_STATUS_PENDING,
 289         RT_STATUS_RESOURCE
 290 };
 291
 292 enum rt_customer_id {
 293         RT_CID_DEFAULT          = 0,
 294         RT_CID_8187_ALPHA0      = 1,
 295         RT_CID_8187_SERCOMM_PS  = 2,
 296         RT_CID_8187_HW_LED      = 3,
 297         RT_CID_8187_NETGEAR     = 4,
 298         RT_CID_WHQL             = 5,
 299         RT_CID_819x_CAMEO       = 6,
 300         RT_CID_819x_RUNTOP      = 7,
 301         RT_CID_819x_Senao       = 8,
 302         RT_CID_TOSHIBA          = 9,
 303         RT_CID_819x_Netcore     = 10,
 304         RT_CID_Nettronix        = 11,
 305         RT_CID_DLINK            = 12,
 306         RT_CID_PRONET           = 13,
 307         RT_CID_COREGA           = 14,
 308         RT_CID_819x_ALPHA       = 15,
 309         RT_CID_819x_Sitecom     = 16,
 310         RT_CID_CCX              = 17,
 311         RT_CID_819x_Lenovo      = 18,
 312         RT_CID_819x_QMI         = 19,
 313         RT_CID_819x_Edimax_Belkin = 20,
 314         RT_CID_819x_Sercomm_Belkin = 21,
 315         RT_CID_819x_CAMEO1 = 22,
 316         RT_CID_819x_MSI = 23,
 317         RT_CID_819x_Acer = 24,
 318         RT_CID_819x_HP  =27,
 319         RT_CID_819x_CLEVO = 28,
 320         RT_CID_819x_Arcadyan_Belkin = 29,
 321         RT_CID_819x_SAMSUNG = 30,
 322         RT_CID_819x_WNC_COREGA = 31,
 323 };
 324
 325 enum reset_type {
 326         RESET_TYPE_NORESET = 0x00,
 327         RESET_TYPE_NORMAL = 0x01,
 328         RESET_TYPE_SILENT = 0x02
 329 };
 330
 331 typedef enum _IC_INFERIORITY_8192S{
 332         IC_INFERIORITY_A            = 0,
 333         IC_INFERIORITY_B            = 1,
 334 } IC_INFERIORITY_8192S, *PIC_INFERIORITY_8192S;
 335
 336 typedef enum _PCI_BRIDGE_VENDOR {
 337         PCI_BRIDGE_VENDOR_INTEL = 0x0,
 338         PCI_BRIDGE_VENDOR_ATI,
 339         PCI_BRIDGE_VENDOR_AMD,
 340         PCI_BRIDGE_VENDOR_SIS ,
 341         PCI_BRIDGE_VENDOR_UNKNOWN,
 342         PCI_BRIDGE_VENDOR_MAX ,
 343 } PCI_BRIDGE_VENDOR;
 344
 345 struct buffer {
 346         struct buffer *next;
 347         u32 *buf;
 348         dma_addr_t dma;
 349
 350 };
 351
 352 struct rtl_reg_debug {
 353         unsigned int  cmd;
 354         struct {
 355                 unsigned char type;
 356                 unsigned char addr;
 357                 unsigned char page;
 358                 unsigned char length;
 359         } head;
 360         unsigned char buf[0xff];
 361 };
 362
 363 struct rt_tx_rahis {
 364         u32             cck[4];
 365         u32             ofdm[8];
 366         u32             ht_mcs[4][16];
 367 };
 368
 369 struct rt_smooth_data_4rf {
 370         char    elements[4][100];
 371         u32     index;
 372         u32     TotalNum;
 373         u32     TotalVal[4];
 374 };
 375
 376 struct rt_stats {
 377         unsigned long txrdu;
 378         unsigned long rxrdu;
 379         unsigned long rxok;
 380         unsigned long rxframgment;
 381         unsigned long rxcmdpkt[4];
 382         unsigned long rxurberr;
 383         unsigned long rxstaterr;
 384         unsigned long rxdatacrcerr;
 385         unsigned long rxmgmtcrcerr;
 386         unsigned long rxcrcerrmin;
 387         unsigned long rxcrcerrmid;
 388         unsigned long rxcrcerrmax;
 389         unsigned long received_rate_histogram[4][32];
 390         unsigned long received_preamble_GI[2][32];
 391         unsigned long   rx_AMPDUsize_histogram[5];
 392         unsigned long rx_AMPDUnum_histogram[5];
 393         unsigned long numpacket_matchbssid;
 394         unsigned long numpacket_toself;
 395         unsigned long num_process_phyinfo;
 396         unsigned long numqry_phystatus;
 397         unsigned long numqry_phystatusCCK;
 398         unsigned long numqry_phystatusHT;
 399         unsigned long received_bwtype[5];
 400         unsigned long txnperr;
 401         unsigned long txnpdrop;
 402         unsigned long txresumed;
 403         unsigned long rxoverflow;
 404         unsigned long rxint;
 405         unsigned long txnpokint;
 406         unsigned long ints;
 407         unsigned long shints;
 408         unsigned long txoverflow;
 409         unsigned long txlpokint;
 410         unsigned long txlpdrop;
 411         unsigned long txlperr;
 412         unsigned long txbeokint;
 413         unsigned long txbedrop;
 414         unsigned long txbeerr;
 415         unsigned long txbkokint;
 416         unsigned long txbkdrop;
 417         unsigned long txbkerr;
 418         unsigned long txviokint;
 419         unsigned long txvidrop;
 420         unsigned long txvierr;
 421         unsigned long txvookint;
 422         unsigned long txvodrop;
 423         unsigned long txvoerr;
 424         unsigned long txbeaconokint;
 425         unsigned long txbeacondrop;
 426         unsigned long txbeaconerr;
 427         unsigned long txmanageokint;
 428         unsigned long txmanagedrop;
 429         unsigned long txmanageerr;
 430         unsigned long txcmdpktokint;
 431         unsigned long txdatapkt;
 432         unsigned long txfeedback;
 433         unsigned long txfeedbackok;
 434         unsigned long txoktotal;
 435         unsigned long txokbytestotal;
 436         unsigned long txokinperiod;
 437         unsigned long txmulticast;
 438         unsigned long txbytesmulticast;
 439         unsigned long txbroadcast;
 440         unsigned long txbytesbroadcast;
 441         unsigned long txunicast;
 442         unsigned long txbytesunicast;
 443         unsigned long rxbytesunicast;
 444         unsigned long txfeedbackfail;
 445         unsigned long txerrtotal;
 446         unsigned long txerrbytestotal;
 447         unsigned long txerrmulticast;
 448         unsigned long txerrbroadcast;
 449         unsigned long txerrunicast;
 450         unsigned long txretrycount;
 451         unsigned long txfeedbackretry;
 452         u8                      last_packet_rate;
 453         unsigned long slide_signal_strength[100];
 454         unsigned long slide_evm[100];
 455         unsigned long   slide_rssi_total;
 456         unsigned long slide_evm_total;
 457         long signal_strength;
 458         long signal_quality;
 459         long last_signal_strength_inpercent;
 460         long    recv_signal_power;
 461         u8 rx_rssi_percentage[4];
 462         u8 rx_evm_percentage[2];
 463         long rxSNRdB[4];
 464         struct rt_tx_rahis txrate;
 465         u32 Slide_Beacon_pwdb[100];
 466         u32 Slide_Beacon_Total;
 467         struct rt_smooth_data_4rf cck_adc_pwdb;
 468         u32     CurrentShowTxate;
 469 };
 470
 471 struct channel_access_setting {
 472         u16 SIFS_Timer;
 473         u16 DIFS_Timer;
 474         u16 SlotTimeTimer;
 475         u16 EIFS_Timer;
 476         u16 CWminIndex;
 477         u16 CWmaxIndex;
 478 };
 479
 480 typedef enum _TWO_PORT_STATUS
 481 {
 482         TWO_PORT_STATUS__DEFAULT_ONLY,
 483         TWO_PORT_STATUS__EXTENSION_ONLY,
 484         TWO_PORT_STATUS__EXTENSION_FOLLOW_DEFAULT,
 485         TWO_PORT_STATUS__DEFAULT_G_EXTENSION_N20,
 486         TWO_PORT_STATUS__ADHOC,
 487         TWO_PORT_STATUS__WITHOUT_ANY_ASSOCIATE
 488 } TWO_PORT_STATUS;
 489
 490 struct txbbgain_struct {
 491         long    txbb_iq_amplifygain;
 492         u32     txbbgain_value;
 493 };
 494
 495 struct ccktxbbgain {
 496         u8      ccktxbb_valuearray[8];
 497 };
 498
 499 struct init_gain {
 500         u8                              xaagccore1;
 501         u8                              xbagccore1;
 502         u8                              xcagccore1;
 503         u8                              xdagccore1;
 504         u8                              cca;
 505
 506 };
 507
 508 struct tx_ring {
 509         u32 * desc;
 510         u8 nStuckCount;
 511         struct tx_ring * next;
 512 } __packed;
 513
 514 struct rtl8192_tx_ring {
 515     struct tx_desc *desc;
 516     dma_addr_t dma;
 517     unsigned int idx;
 518     unsigned int entries;
 519     struct sk_buff_head queue;
 520 };
 521
 522
 523
 524 struct rtl819x_ops{
 525         enum nic_t nic_type;
 526         void (* get_eeprom_size)(struct net_device* dev);
 527         void (* init_adapter_variable)(struct net_device* dev);
 528         void (* init_before_adapter_start)(struct net_device* dev);
 529         bool (* initialize_adapter)(struct net_device* dev);
 530         void (*link_change)(struct net_device* dev);
 531         void (* tx_fill_descriptor)(struct net_device* dev, struct tx_desc *tx_desc, struct cb_desc *cb_desc, struct sk_buff *skb);
 532         void (* tx_fill_cmd_descriptor)(struct net_device* dev, struct tx_desc_cmd * entry, struct cb_desc *cb_desc, struct sk_buff *skb);
 533         bool (* rx_query_status_descriptor)(struct net_device* dev, struct rtllib_rx_stats*  stats, struct rx_desc *pdesc, struct sk_buff* skb);
 534         bool (* rx_command_packet_handler)(struct net_device *dev, struct sk_buff* skb, struct rx_desc *pdesc);
 535         void (* stop_adapter)(struct net_device *dev, bool reset);
 536         void (* update_ratr_table)(struct net_device* dev);
 537         void (* irq_enable)(struct net_device* dev);
 538         void (* irq_disable)(struct net_device* dev);
 539         void (* irq_clear)(struct net_device* dev);
 540         void (* rx_enable)(struct net_device* dev);
 541         void (* tx_enable)(struct net_device* dev);
 542         void (* interrupt_recognized)(struct net_device *dev, u32 *p_inta, u32 *p_intb);
 543         bool (* TxCheckStuckHandler)(struct net_device* dev);
 544         bool (* RxCheckStuckHandler)(struct net_device* dev);
 545 };
 546
 547 struct r8192_priv {
 548         struct pci_dev *pdev;
 549         struct pci_dev *bridge_pdev;
 550
 551         bool            bfirst_init;
 552         bool            bfirst_after_down;
 553         bool            initialized_at_probe;
 554         bool            being_init_adapter;
 555         bool            bDriverIsGoingToUnload;
 556
 557         int             irq;
 558         short   irq_enabled;
 559
 560         short   up;
 561         short   up_first_time;
 562         struct delayed_work             update_beacon_wq;
 563         struct delayed_work             watch_dog_wq;
 564         struct delayed_work             txpower_tracking_wq;
 565         struct delayed_work             rfpath_check_wq;
 566         struct delayed_work             gpio_change_rf_wq;
 567         struct delayed_work             initialgain_operate_wq;
 568         struct delayed_work             check_hw_scan_wq;
 569         struct delayed_work             hw_scan_simu_wq;
 570         struct delayed_work             start_hw_scan_wq;
 571
 572         struct workqueue_struct         *priv_wq;
 573
 574         struct channel_access_setting ChannelAccessSetting;
 575
 576         struct mp_adapter NdisAdapter;
 577
 578         struct rtl819x_ops                      *ops;
 579         struct rtllib_device                    *rtllib;
 580
 581         struct work_struct                              reset_wq;
 582
 583         struct log_int_8190 InterruptLog;
 584
 585         enum rt_customer_id CustomerID;
 586
 587
 588         enum rt_rf_type_819xu rf_chip;
 589         IC_INFERIORITY_8192S            IC_Class;
 590         enum ht_channel_width CurrentChannelBW;
 591         struct bb_reg_definition PHYRegDef[4];
 592         struct rate_adaptive rate_adaptive;
 593
 594         struct ccktxbbgain cck_txbbgain_table[CCKTxBBGainTableLength];
 595         struct ccktxbbgain cck_txbbgain_ch14_table[CCKTxBBGainTableLength];
 596
 597         struct txbbgain_struct txbbgain_table[TxBBGainTableLength];
 598
 599         enum acm_method AcmMethod;
 600
 601         struct rt_firmware                      *pFirmware;
 602         enum rtl819x_loopback LoopbackMode;
 603         enum firmware_source firmware_source;
 604
 605         struct timer_list                       watch_dog_timer;
 606         struct timer_list                       fsync_timer;
 607         struct timer_list                       gpio_polling_timer;
 608
 609         spinlock_t                              fw_scan_lock;
 610         spinlock_t                              irq_lock;
 611         spinlock_t                              irq_th_lock;
 612         spinlock_t                              tx_lock;
 613         spinlock_t                              rf_ps_lock;
 614         spinlock_t                              rw_lock;
 615         spinlock_t                              rt_h2c_lock;
 616         spinlock_t                              rf_lock;
 617         spinlock_t                              ps_lock;
 618
 619         struct sk_buff_head             rx_queue;
 620         struct sk_buff_head             skb_queue;
 621
 622         struct tasklet_struct           irq_rx_tasklet;
 623         struct tasklet_struct           irq_tx_tasklet;
 624         struct tasklet_struct           irq_prepare_beacon_tasklet;
 625
 626         struct semaphore                        wx_sem;
 627         struct semaphore                        rf_sem;
 628         struct mutex                            mutex;
 629
 630         struct rt_stats stats;
 631         struct iw_statistics                    wstats;
 632         struct proc_dir_entry           *dir_dev;
 633
 634         short (*rf_set_sens)(struct net_device *dev,short sens);
 635         u8 (*rf_set_chan)(struct net_device *dev,u8 ch);
 636         void (*rf_close)(struct net_device *dev);
 637         void (*rf_init)(struct net_device *dev);
 638
 639         struct rx_desc *rx_ring[MAX_RX_QUEUE];
 640         struct sk_buff  *rx_buf[MAX_RX_QUEUE][MAX_RX_COUNT];
 641         dma_addr_t      rx_ring_dma[MAX_RX_QUEUE];
 642         unsigned int    rx_idx[MAX_RX_QUEUE];
 643         int             rxringcount;
 644         u16             rxbuffersize;
 645
 646         u32             LastRxDescTSFHigh;
 647         u32             LastRxDescTSFLow;
 648
 649         u16             EarlyRxThreshold;
 650         u32             ReceiveConfig;
 651         u8              AcmControl;
 652         u8              RFProgType;
 653         u8              retry_data;
 654         u8              retry_rts;
 655         u16             rts;
 656
 657         struct rtl8192_tx_ring tx_ring[MAX_TX_QUEUE_COUNT];
 658         int              txringcount;
 659         int             txbuffsize;
 660         int             txfwbuffersize;
 661         atomic_t        tx_pending[0x10];
 662
 663         u16             ShortRetryLimit;
 664         u16             LongRetryLimit;
 665         u32             TransmitConfig;
 666         u8              RegCWinMin;
 667         u8              keepAliveLevel;
 668
 669         bool            sw_radio_on;
 670         bool            bHwRadioOff;
 671         bool            pwrdown;
 672         bool            blinked_ingpio;
 673         u8              polling_timer_on;
 674
 675         /**********************************************************/
 676
 677         enum card_type {PCI,MINIPCI,CARDBUS,USB}card_type;
 678
 679         struct work_struct qos_activate;
 680
 681         u8              bIbssCoordinator;
 682
 683         short   promisc;
 684         short   crcmon;
 685
 686         int             txbeaconcount;
 687
 688         short   chan;
 689         short   sens;
 690         short   max_sens;
 691         u32             rx_prevlen;
 692
 693         u8              ScanDelay;
 694         bool            ps_force;
 695
 696         u32             irq_mask[2];
 697
 698         u8              Rf_Mode;
 699         enum nic_t card_8192;
 700         u8              card_8192_version;
 701
 702         short   enable_gpio0;
 703
 704         u8              rf_type;
 705         u8              IC_Cut;
 706         char            nick[IW_ESSID_MAX_SIZE + 1];
 707
 708         u8              RegBcnCtrlVal;
 709         bool            bHwAntDiv;
 710
 711         bool            bTKIPinNmodeFromReg;
 712         bool            bWEPinNmodeFromReg;
 713
 714         bool            bLedOpenDrain;
 715
 716         u8              check_roaming_cnt;
 717
 718         bool            bIgnoreSilentReset;
 719         u32             SilentResetRxSoltNum;
 720         u32             SilentResetRxSlotIndex;
 721         u32             SilentResetRxStuckEvent[MAX_SILENT_RESET_RX_SLOT_NUM];
 722
 723         void            *scan_cmd;
 724         u8      hwscan_bw_40;
 725
 726         u16             nrxAMPDU_size;
 727         u8              nrxAMPDU_aggr_num;
 728
 729         u32             last_rxdesc_tsf_high;
 730         u32             last_rxdesc_tsf_low;
 731
 732
 733         u16             basic_rate;
 734         u8              short_preamble;
 735         u8              dot11CurrentPreambleMode;
 736         u8              slot_time;
 737         u16             SifsTime;
 738
 739         u8              RegWirelessMode;
 740
 741         u8              firmware_version;
 742         u16             FirmwareSubVersion;
 743         u16             rf_pathmap;
 744         bool            AutoloadFailFlag;
 745
 746         u8              RegPciASPM;
 747         u8              RegAMDPciASPM;
 748         u8              RegHwSwRfOffD3;
 749         u8              RegSupportPciASPM;
 750         bool            bSupportASPM;
 751
 752         u32             RfRegChnlVal[2];
 753
 754         u8              ShowRateMode;
 755         u8              RATRTableBitmap;
 756
 757         u8              EfuseMap[2][HWSET_MAX_SIZE_92S];
 758         u16             EfuseUsedBytes;
 759         u8              EfuseUsedPercentage;
 760
 761         short   epromtype;
 762         u16             eeprom_vid;
 763         u16             eeprom_did;
 764         u16             eeprom_svid;
 765         u16             eeprom_smid;
 766         u8              eeprom_CustomerID;
 767         u16     eeprom_ChannelPlan;
 768         u8              eeprom_version;
 769
 770         u8              EEPROMRegulatory;
 771         u8              EEPROMPwrGroup[2][3];
 772         u8              EEPROMOptional;
 773
 774         u8              EEPROMTxPowerLevelCCK[14];
 775         u8              EEPROMTxPowerLevelOFDM24G[14];
 776         u8              EEPROMTxPowerLevelOFDM5G[24];
 777         u8              EEPROMRfACCKChnl1TxPwLevel[3];
 778         u8              EEPROMRfAOfdmChnlTxPwLevel[3];
 779         u8              EEPROMRfCCCKChnl1TxPwLevel[3];
 780         u8              EEPROMRfCOfdmChnlTxPwLevel[3];
 781         u16             EEPROMTxPowerDiff;
 782         u16             EEPROMAntPwDiff;
 783         u8              EEPROMThermalMeter;
 784         u8              EEPROMPwDiff;
 785         u8              EEPROMCrystalCap;
 786
 787         u8              EEPROMBluetoothCoexist;
 788         u8              EEPROMBluetoothType;
 789         u8              EEPROMBluetoothAntNum;
 790         u8              EEPROMBluetoothAntIsolation;
 791         u8              EEPROMBluetoothRadioShared;
 792
 793
 794         u8              EEPROMSupportWoWLAN;
 795         u8              EEPROMBoardType;
 796         u8              EEPROM_Def_Ver;
 797         u8              EEPROMHT2T_TxPwr[6];
 798         u8              EEPROMTSSI_A;
 799         u8              EEPROMTSSI_B;
 800         u8              EEPROMTxPowerLevelCCK_V1[3];
 801         u8              EEPROMLegacyHTTxPowerDiff;
 802
 803         u8              BluetoothCoexist;
 804
 805         u8              CrystalCap;
 806         u8              ThermalMeter[2];
 807
 808         u16             FwCmdIOMap;
 809         u32             FwCmdIOParam;
 810
 811         u8              SwChnlInProgress;
 812         u8              SwChnlStage;
 813         u8              SwChnlStep;
 814         u8              SetBWModeInProgress;
 815
 816         u8              nCur40MhzPrimeSC;
 817
 818         u32             RfReg0Value[4];
 819         u8              NumTotalRFPath;
 820         bool            brfpath_rxenable[4];
 821
 822         bool            bTXPowerDataReadFromEEPORM;
 823
 824         u16             RegChannelPlan;
 825         u16             ChannelPlan;
 826         bool            bChnlPlanFromHW;
 827
 828         bool            RegRfOff;
 829         bool            isRFOff;
 830         bool            bInPowerSaveMode;
 831         u8              bHwRfOffAction;
 832
 833         bool            aspm_clkreq_enable;
 834         u32             pci_bridge_vendor;
 835         u8              RegHostPciASPMSetting;
 836         u8              RegDevicePciASPMSetting;
 837
 838         bool            RFChangeInProgress;
 839         bool            SetRFPowerStateInProgress;
 840         bool            bdisable_nic;
 841
 842         u8              pwrGroupCnt;
 843
 844         u8              ThermalValue_LCK;
 845         u8              ThermalValue_IQK;
 846         bool            bRfPiEnable;
 847
 848         u32             APKoutput[2][2];
 849         bool            bAPKdone;
 850
 851         long            RegE94;
 852         long            RegE9C;
 853         long            RegEB4;
 854         long            RegEBC;
 855
 856         u32             RegC04;
 857         u32             Reg874;
 858         u32             RegC08;
 859         u32             ADDA_backup[16];
 860         u32             IQK_MAC_backup[3];
 861
 862         bool            SetFwCmdInProgress;
 863         u8              CurrentFwCmdIO;
 864
 865         u8              rssi_level;
 866
 867         bool            bInformFWDriverControlDM;
 868         u8              PwrGroupHT20[2][14];
 869         u8              PwrGroupHT40[2][14];
 870
 871         u8              ThermalValue;
 872         long            EntryMinUndecoratedSmoothedPWDB;
 873         long            EntryMaxUndecoratedSmoothedPWDB;
 874         u8              DynamicTxHighPowerLvl;
 875         u8              LastDTPLvl;
 876         u32             CurrentRATR0;
 877         struct false_alarm_stats FalseAlmCnt;
 878
 879         u8              DMFlag;
 880         u8              DM_Type;
 881
 882         u8              CckPwEnl;
 883         u16             TSSI_13dBm;
 884         u32             Pwr_Track;
 885         u8              CCKPresentAttentuation_20Mdefault;
 886         u8              CCKPresentAttentuation_40Mdefault;
 887         char            CCKPresentAttentuation_difference;
 888         char            CCKPresentAttentuation;
 889         u8              bCckHighPower;
 890         long            undecorated_smoothed_pwdb;
 891         long            undecorated_smoothed_cck_adc_pwdb[4];
 892
 893         u32             MCSTxPowerLevelOriginalOffset[6];
 894         u32             CCKTxPowerLevelOriginalOffset;
 895         u8              TxPowerLevelCCK[14];
 896         u8              TxPowerLevelCCK_A[14];
 897         u8              TxPowerLevelCCK_C[14];
 898         u8              TxPowerLevelOFDM24G[14];
 899         u8              TxPowerLevelOFDM5G[14];
 900         u8              TxPowerLevelOFDM24G_A[14];
 901         u8              TxPowerLevelOFDM24G_C[14];
 902         u8              LegacyHTTxPowerDiff;
 903         u8              TxPowerDiff;
 904         s8              RF_C_TxPwDiff;
 905         s8              RF_B_TxPwDiff;
 906         u8              RfTxPwrLevelCck[2][14];
 907         u8              RfTxPwrLevelOfdm1T[2][14];
 908         u8              RfTxPwrLevelOfdm2T[2][14];
 909         u8              AntennaTxPwDiff[3];
 910         u8              TxPwrHt20Diff[2][14];
 911         u8              TxPwrLegacyHtDiff[2][14];
 912         u8              TxPwrSafetyFlag;
 913         u8              HT2T_TxPwr_A[14];
 914         u8              HT2T_TxPwr_B[14];
 915         u8              CurrentCckTxPwrIdx;
 916         u8              CurrentOfdm24GTxPwrIdx;
 917
 918         bool            bdynamic_txpower;
 919         bool            bDynamicTxHighPower;
 920         bool            bDynamicTxLowPower;
 921         bool            bLastDTPFlag_High;
 922         bool            bLastDTPFlag_Low;
 923
 924         bool            bstore_last_dtpflag;
 925         bool            bstart_txctrl_bydtp;
 926
 927         u8              rfa_txpowertrackingindex;
 928         u8              rfa_txpowertrackingindex_real;
 929         u8              rfa_txpowertracking_default;
 930         u8              rfc_txpowertrackingindex;
 931         u8              rfc_txpowertrackingindex_real;
 932         u8              rfc_txpowertracking_default;
 933         bool            btxpower_tracking;
 934         bool            bcck_in_ch14;
 935
 936         u8              TxPowerTrackControl;
 937         u8              txpower_count;
 938         bool            btxpower_trackingInit;
 939
 940         u8              OFDM_index[2];
 941         u8              CCK_index;
 942
 943         u8              Record_CCK_20Mindex;
 944         u8              Record_CCK_40Mindex;
 945
 946         struct init_gain initgain_backup;
 947         u8              DefaultInitialGain[4];
 948         bool            bis_any_nonbepkts;
 949         bool            bcurrent_turbo_EDCA;
 950         bool            bis_cur_rdlstate;
 951
 952         bool            bCCKinCH14;
 953
 954         u8              MidHighPwrTHR_L1;
 955         u8              MidHighPwrTHR_L2;
 956
 957         bool            bfsync_processing;
 958         u32             rate_record;
 959         u32             rateCountDiffRecord;
 960         u32             ContiuneDiffCount;
 961         bool            bswitch_fsync;
 962         u8              framesync;
 963         u32             framesyncC34;
 964         u8              framesyncMonitor;
 965
 966         bool            bDMInitialGainEnable;
 967         bool            MutualAuthenticationFail;
 968
 969         bool            bDisableFrameBursting;
 970
 971         u32             reset_count;
 972         bool            bpbc_pressed;
 973
 974         u32             txpower_checkcnt;
 975         u32             txpower_tracking_callback_cnt;
 976         u8              thermal_read_val[40];
 977         u8              thermal_readback_index;
 978         u32             ccktxpower_adjustcnt_not_ch14;
 979         u32             ccktxpower_adjustcnt_ch14;
 980
 981         enum reset_type ResetProgress;
 982         bool            bForcedSilentReset;
 983         bool            bDisableNormalResetCheck;
 984         u16             TxCounter;
 985         u16             RxCounter;
 986         int             IrpPendingCount;
 987         bool            bResetInProgress;
 988         bool            force_reset;
 989         bool            force_lps;
 990         u8              InitialGainOperateType;
 991
 992         bool            chan_forced;
 993         bool            bSingleCarrier;
 994         bool            RegBoard;
 995         bool            bCckContTx;
 996         bool            bOfdmContTx;
 997         bool            bStartContTx;
 998         u8              RegPaModel;
 999         u8              btMpCckTxPower;
1000         u8              btMpOfdmTxPower;
1001
1002         u32             MptActType;
1003         u32             MptIoOffset;
1004         u32             MptIoValue;
1005         u32             MptRfPath;
1006
1007         u32             MptBandWidth;
1008         u32             MptRateIndex;
1009         u8              MptChannelToSw;
1010         u32     MptRCR;
1011
1012         u8              PwrDomainProtect;
1013         u8              H2CTxCmdSeq;
1014
1015
1016 };
1017
1018 extern const struct ethtool_ops rtl819x_ethtool_ops;
1019
1020 void rtl8192_tx_cmd(struct net_device *dev, struct sk_buff *skb);
1021 short rtl8192_tx(struct net_device *dev, struct sk_buff* skb);
1022
1023 u8 read_nic_io_byte(struct net_device *dev, int x);
1024 u32 read_nic_io_dword(struct net_device *dev, int x);
1025 u16 read_nic_io_word(struct net_device *dev, int x) ;
1026 void write_nic_io_byte(struct net_device *dev, int x,u8 y);
1027 void write_nic_io_word(struct net_device *dev, int x,u16 y);
1028 void write_nic_io_dword(struct net_device *dev, int x,u32 y);
1029
1030 u8 read_nic_byte(struct net_device *dev, int x);
1031 u32 read_nic_dword(struct net_device *dev, int x);
1032 u16 read_nic_word(struct net_device *dev, int x) ;
1033 void write_nic_byte(struct net_device *dev, int x,u8 y);
1034 void write_nic_word(struct net_device *dev, int x,u16 y);
1035 void write_nic_dword(struct net_device *dev, int x,u32 y);
1036
1037 void force_pci_posting(struct net_device *dev);
1038
1039 void rtl8192_rx_enable(struct net_device *);
1040 void rtl8192_tx_enable(struct net_device *);
1041
1042 int rtl8192_hard_start_xmit(struct sk_buff *skb,struct net_device *dev);
1043 void rtl8192_hard_data_xmit(struct sk_buff *skb, struct net_device *dev, int rate);
1044 void rtl8192_data_hard_stop(struct net_device *dev);
1045 void rtl8192_data_hard_resume(struct net_device *dev);
1046 void rtl8192_restart(void *data);
1047 void rtl819x_watchdog_wqcallback(void *data);
1048 void rtl8192_hw_sleep_wq (void *data);
1049 void watch_dog_timer_callback(unsigned long data);
1050 void rtl8192_irq_rx_tasklet(struct r8192_priv *priv);
1051 void rtl8192_irq_tx_tasklet(struct r8192_priv *priv);
1052 int rtl8192_down(struct net_device *dev,bool shutdownrf);
1053 int rtl8192_up(struct net_device *dev);
1054 void rtl8192_commit(struct net_device *dev);
1055 void rtl8192_set_chan(struct net_device *dev,short ch);
1056
1057 void check_rfctrl_gpio_timer(unsigned long data);
1058
1059 void rtl8192_hw_wakeup_wq(void *data);
1060 irqreturn_type rtl8192_interrupt(int irq, void *netdev, struct pt_regs *regs);
1061
1062 short rtl8192_pci_initdescring(struct net_device *dev);
1063
1064 void rtl8192_cancel_deferred_work(struct r8192_priv * priv);
1065
1066 int _rtl8192_up(struct net_device *dev,bool is_silent_reset);
1067
1068 short rtl8192_is_tx_queue_empty(struct net_device *dev);
1069 void rtl8192_irq_disable(struct net_device *dev);
1070
1071 void rtl8192_tx_timeout(struct net_device *dev);
1072 void rtl8192_pci_resetdescring(struct net_device *dev);
1073 void rtl8192_SetWirelessMode(struct net_device* dev, u8 wireless_mode);
1074 void rtl8192_irq_enable(struct net_device *dev);
1075 void rtl8192_config_rate(struct net_device* dev, u16* rate_config);
1076 void rtl8192_update_cap(struct net_device* dev, u16 cap);
1077 void rtl8192_irq_disable(struct net_device *dev);
1078
1079 void rtl819x_UpdateRxPktTimeStamp (struct net_device *dev, struct rtllib_rx_stats *stats);
1080 long rtl819x_translate_todbm(struct r8192_priv * priv, u8 signal_strength_index );
1081 void rtl819x_update_rxsignalstatistics8190pci(struct r8192_priv * priv,struct rtllib_rx_stats * pprevious_stats);
1082 u8 rtl819x_evm_dbtopercentage(char value);
1083 void rtl819x_process_cck_rxpathsel(struct r8192_priv * priv,struct rtllib_rx_stats * pprevious_stats);
1084 u8 rtl819x_query_rxpwrpercentage(       char            antpower        );
1085 void rtl8192_record_rxdesc_forlateruse(struct rtllib_rx_stats * psrc_stats,struct rtllib_rx_stats * ptarget_stats);
1086
1087 bool NicIFEnableNIC(struct net_device* dev);
1088 bool NicIFDisableNIC(struct net_device* dev);
1089
1090 bool
1091 MgntActSet_RF_State(
1092         struct net_device* dev,
1093         RT_RF_POWER_STATE       StateToSet,
1094         RT_RF_CHANGE_SOURCE ChangeSource,
1095         bool    ProtectOrNot
1096         );
1097 void
1098 ActUpdateChannelAccessSetting(
1099         struct net_device*                      dev,
1100         WIRELESS_MODE                   WirelessMode,
1101         struct channel_access_setting *ChnlAccessSetting
1102         );
1103
1104 #endif