drivers/staging/tidspbridge/core/tiomap3430.c

   1 /*
   2  * tiomap.c
   3  *
   4  * DSP-BIOS Bridge driver support functions for TI OMAP processors.
   5  *
   6  * Processor Manager Driver for TI OMAP3430 EVM.
   7  *
   8  * Copyright (C) 2005-2006 Texas Instruments, Inc.
   9  *
  10  * This package is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  *
  14  * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
  15  * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
  16  * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
  17  */
  18
  19 #include <linux/platform_data/dsp-omap.h>
  20
  21 #include <linux/types.h>
  22 /*  ----------------------------------- Host OS */
  23 #include <dspbridge/host_os.h>
  24 #include <linux/mm.h>
  25 #include <linux/mmzone.h>
  26
  27 /*  ----------------------------------- DSP/BIOS Bridge */
  28 #include <dspbridge/dbdefs.h>
  29
  30 /*  ----------------------------------- OS Adaptation Layer */
  31 #include <dspbridge/drv.h>
  32 #include <dspbridge/sync.h>
  33
  34 /* ------------------------------------ Hardware Abstraction Layer */
  35 #include <hw_defs.h>
  36 #include <hw_mmu.h>
  37
  38 /*  ----------------------------------- Link Driver */
  39 #include <dspbridge/dspdefs.h>
  40 #include <dspbridge/dspchnl.h>
  41 #include <dspbridge/dspdeh.h>
  42 #include <dspbridge/dspio.h>
  43 #include <dspbridge/dspmsg.h>
  44 #include <dspbridge/pwr.h>
  45 #include <dspbridge/io_sm.h>
  46
  47 /*  ----------------------------------- Platform Manager */
  48 #include <dspbridge/dev.h>
  49 #include <dspbridge/dspapi.h>
  50 #include <dspbridge/dmm.h>
  51 #include <dspbridge/wdt.h>
  52
  53 /*  ----------------------------------- Local */
  54 #include "_tiomap.h"
  55 #include "_tiomap_pwr.h"
  56 #include "tiomap_io.h"
  57
  58 /* Offset in shared mem to write to in order to synchronize start with DSP */
  59 #define SHMSYNCOFFSET 4         /* GPP byte offset */
  60
  61 #define BUFFERSIZE 1024
  62
  63 #define TIHELEN_ACKTIMEOUT  10000
  64
  65 #define MMU_SECTION_ADDR_MASK    0xFFF00000
  66 #define MMU_SSECTION_ADDR_MASK   0xFF000000
  67 #define MMU_LARGE_PAGE_MASK      0xFFFF0000
  68 #define MMU_SMALL_PAGE_MASK      0xFFFFF000
  69 #define OMAP3_IVA2_BOOTADDR_MASK 0xFFFFFC00
  70 #define PAGES_II_LVL_TABLE   512
  71 #define PHYS_TO_PAGE(phys)      pfn_to_page((phys) >> PAGE_SHIFT)
  72
  73 /* IVA Boot modes */
  74 #define DIRECT          0
  75 #define IDLE            1
  76
  77 /* Forward Declarations: */
  78 static int bridge_brd_monitor(struct bridge_dev_context *dev_ctxt);
  79 static int bridge_brd_read(struct bridge_dev_context *dev_ctxt,
  80                                   u8 *host_buff,
  81                                   u32 dsp_addr, u32 ul_num_bytes,
  82                                   u32 mem_type);
  83 static int bridge_brd_start(struct bridge_dev_context *dev_ctxt,
  84                                    u32 dsp_addr);
  85 static int bridge_brd_status(struct bridge_dev_context *dev_ctxt,
  86                                     int *board_state);
  87 static int bridge_brd_stop(struct bridge_dev_context *dev_ctxt);
  88 static int bridge_brd_write(struct bridge_dev_context *dev_ctxt,
  89                                    u8 *host_buff,
  90                                    u32 dsp_addr, u32 ul_num_bytes,
  91                                    u32 mem_type);
  92 static int bridge_brd_set_state(struct bridge_dev_context *dev_ctxt,
  93                                     u32 brd_state);
  94 static int bridge_brd_mem_copy(struct bridge_dev_context *dev_ctxt,
  95                                    u32 dsp_dest_addr, u32 dsp_src_addr,
  96                                    u32 ul_num_bytes, u32 mem_type);
  97 static int bridge_brd_mem_write(struct bridge_dev_context *dev_ctxt,
  98                                     u8 *host_buff, u32 dsp_addr,
  99                                     u32 ul_num_bytes, u32 mem_type);
 100 static int bridge_brd_mem_map(struct bridge_dev_context *dev_ctxt,
 101                                   u32 ul_mpu_addr, u32 virt_addr,
 102                                   u32 ul_num_bytes, u32 ul_map_attr,
 103                                   struct page **mapped_pages);
 104 static int bridge_brd_mem_un_map(struct bridge_dev_context *dev_ctxt,
 105                                      u32 virt_addr, u32 ul_num_bytes);
 106 static int bridge_dev_create(struct bridge_dev_context
 107                                         **dev_cntxt,
 108                                         struct dev_object *hdev_obj,
 109                                         struct cfg_hostres *config_param);
 110 static int bridge_dev_ctrl(struct bridge_dev_context *dev_context,
 111                                   u32 dw_cmd, void *pargs);
 112 static int bridge_dev_destroy(struct bridge_dev_context *dev_ctxt);
 113 static u32 user_va2_pa(struct mm_struct *mm, u32 address);
 114 static int pte_update(struct bridge_dev_context *dev_ctxt, u32 pa,
 115                              u32 va, u32 size,
 116                              struct hw_mmu_map_attrs_t *map_attrs);
 117 static int pte_set(struct pg_table_attrs *pt, u32 pa, u32 va,
 118                           u32 size, struct hw_mmu_map_attrs_t *attrs);
 119 static int mem_map_vmalloc(struct bridge_dev_context *dev_context,
 120                                   u32 ul_mpu_addr, u32 virt_addr,
 121                                   u32 ul_num_bytes,
 122                                   struct hw_mmu_map_attrs_t *hw_attrs);
 123
 124 bool wait_for_start(struct bridge_dev_context *dev_context,
 125                         void __iomem *sync_addr);
 126
 127 /*  ----------------------------------- Globals */
 128
 129 /* Attributes of L2 page tables for DSP MMU */
 130 struct page_info {
 131         u32 num_entries;        /* Number of valid PTEs in the L2 PT */
 132 };
 133
 134 /* Attributes used to manage the DSP MMU page tables */
 135 struct pg_table_attrs {
 136         spinlock_t pg_lock;     /* Critical section object handle */
 137
 138         u32 l1_base_pa;         /* Physical address of the L1 PT */
 139         u32 l1_base_va;         /* Virtual  address of the L1 PT */
 140         u32 l1_size;            /* Size of the L1 PT */
 141         u32 l1_tbl_alloc_pa;
 142         /* Physical address of Allocated mem for L1 table. May not be aligned */
 143         u32 l1_tbl_alloc_va;
 144         /* Virtual address of Allocated mem for L1 table. May not be aligned */
 145         u32 l1_tbl_alloc_sz;
 146         /* Size of consistent memory allocated for L1 table.
 147          * May not be aligned */
 148
 149         u32 l2_base_pa;         /* Physical address of the L2 PT */
 150         u32 l2_base_va;         /* Virtual  address of the L2 PT */
 151         u32 l2_size;            /* Size of the L2 PT */
 152         u32 l2_tbl_alloc_pa;
 153         /* Physical address of Allocated mem for L2 table. May not be aligned */
 154         u32 l2_tbl_alloc_va;
 155         /* Virtual address of Allocated mem for L2 table. May not be aligned */
 156         u32 l2_tbl_alloc_sz;
 157         /* Size of consistent memory allocated for L2 table.
 158          * May not be aligned */
 159
 160         u32 l2_num_pages;       /* Number of allocated L2 PT */
 161         /* Array [l2_num_pages] of L2 PT info structs */
 162         struct page_info *pg_info;
 163 };
 164
 165 /*
 166  *  This Bridge driver's function interface table.
 167  */
 168 static struct bridge_drv_interface drv_interface_fxns = {
 169         /* Bridge API ver. for which this bridge driver is built. */
 170         BRD_API_MAJOR_VERSION,
 171         BRD_API_MINOR_VERSION,
 172         bridge_dev_create,
 173         bridge_dev_destroy,
 174         bridge_dev_ctrl,
 175         bridge_brd_monitor,
 176         bridge_brd_start,
 177         bridge_brd_stop,
 178         bridge_brd_status,
 179         bridge_brd_read,
 180         bridge_brd_write,
 181         bridge_brd_set_state,
 182         bridge_brd_mem_copy,
 183         bridge_brd_mem_write,
 184         bridge_brd_mem_map,
 185         bridge_brd_mem_un_map,
 186         /* The following CHNL functions are provided by chnl_io.lib: */
 187         bridge_chnl_create,
 188         bridge_chnl_destroy,
 189         bridge_chnl_open,
 190         bridge_chnl_close,
 191         bridge_chnl_add_io_req,
 192         bridge_chnl_get_ioc,
 193         bridge_chnl_cancel_io,
 194         bridge_chnl_flush_io,
 195         bridge_chnl_get_info,
 196         bridge_chnl_get_mgr_info,
 197         bridge_chnl_idle,
 198         bridge_chnl_register_notify,
 199         /* The following IO functions are provided by chnl_io.lib: */
 200         bridge_io_create,
 201         bridge_io_destroy,
 202         bridge_io_on_loaded,
 203         bridge_io_get_proc_load,
 204         /* The following msg_ctrl functions are provided by chnl_io.lib: */
 205         bridge_msg_create,
 206         bridge_msg_create_queue,
 207         bridge_msg_delete,
 208         bridge_msg_delete_queue,
 209         bridge_msg_get,
 210         bridge_msg_put,
 211         bridge_msg_register_notify,
 212         bridge_msg_set_queue_id,
 213 };
 214
 215 static struct notifier_block dsp_mbox_notifier = {
 216         .notifier_call = io_mbox_msg,
 217 };
 218
 219 static inline void flush_all(struct bridge_dev_context *dev_context)
 220 {
 221         if (dev_context->brd_state == BRD_DSP_HIBERNATION ||
 222             dev_context->brd_state == BRD_HIBERNATION)
 223                 wake_dsp(dev_context, NULL);
 224
 225         hw_mmu_tlb_flush_all(dev_context->dsp_mmu_base);
 226 }
 227
 228 static void bad_page_dump(u32 pa, struct page *pg)
 229 {
 230         pr_emerg("DSPBRIDGE: MAP function: COUNT 0 FOR PA 0x%x\n", pa);
 231         pr_emerg("Bad page state in process '%s'\n"
 232                  "page:%p flags:0x%0*lx mapping:%p mapcount:%d count:%d\n"
 233                  "Backtrace:\n",
 234                  current->comm, pg, (int)(2 * sizeof(unsigned long)),
 235                  (unsigned long)pg->flags, pg->mapping,
 236                  page_mapcount(pg), page_count(pg));
 237         dump_stack();
 238 }
 239
 240 /*
 241  *  ======== bridge_drv_entry ========
 242  *  purpose:
 243  *      Bridge Driver entry point.
 244  */
 245 void bridge_drv_entry(struct bridge_drv_interface **drv_intf,
 246                    const char *driver_file_name)
 247 {
 248         if (strcmp(driver_file_name, "UMA") == 0)
 249                 *drv_intf = &drv_interface_fxns;
 250         else
 251                 dev_dbg(bridge, "%s Unknown Bridge file name", __func__);
 252
 253 }
 254
 255 /*
 256  *  ======== bridge_brd_monitor ========
 257  *  purpose:
 258  *      This bridge_brd_monitor puts DSP into a Loadable state.
 259  *      i.e Application can load and start the device.
 260  *
 261  *  Preconditions:
 262  *      Device in 'OFF' state.
 263  */
 264 static int bridge_brd_monitor(struct bridge_dev_context *dev_ctxt)
 265 {
 266         struct bridge_dev_context *dev_context = dev_ctxt;
 267         u32 temp;
 268         struct omap_dsp_platform_data *pdata =
 269                 omap_dspbridge_dev->dev.platform_data;
 270
 271         temp = (*pdata->dsp_prm_read)(OMAP3430_IVA2_MOD, OMAP2_PM_PWSTST) &
 272                                         OMAP_POWERSTATEST_MASK;
 273         if (!(temp & 0x02)) {
 274                 /* IVA2 is not in ON state */
 275                 /* Read and set PM_PWSTCTRL_IVA2  to ON */
 276                 (*pdata->dsp_prm_rmw_bits)(OMAP_POWERSTATEST_MASK,
 277                         PWRDM_POWER_ON, OMAP3430_IVA2_MOD, OMAP2_PM_PWSTCTRL);
 278                 /* Set the SW supervised state transition */
 279                 (*pdata->dsp_cm_write)(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP,
 280                                         OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
 281
 282                 /* Wait until the state has moved to ON */
 283                 while (*pdata->dsp_prm_read(OMAP3430_IVA2_MOD, OMAP2_PM_PWSTST)&
 284                                         OMAP_INTRANSITION_MASK);
 285                 /* Disable Automatic transition */
 286                 (*pdata->dsp_cm_write)(OMAP34XX_CLKSTCTRL_DISABLE_AUTO,
 287                                         OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
 288         }
 289         (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST2_IVA2_MASK, 0,
 290                                         OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 291         dsp_clk_enable(DSP_CLK_IVA2);
 292
 293         /* set the device state to IDLE */
 294         dev_context->brd_state = BRD_IDLE;
 295
 296         return 0;
 297 }
 298
 299 /*
 300  *  ======== bridge_brd_read ========
 301  *  purpose:
 302  *      Reads buffers for DSP memory.
 303  */
 304 static int bridge_brd_read(struct bridge_dev_context *dev_ctxt,
 305                                   u8 *host_buff, u32 dsp_addr,
 306                                   u32 ul_num_bytes, u32 mem_type)
 307 {
 308         int status = 0;
 309         struct bridge_dev_context *dev_context = dev_ctxt;
 310         u32 offset;
 311         u32 dsp_base_addr = dev_ctxt->dsp_base_addr;
 312
 313         if (dsp_addr < dev_context->dsp_start_add) {
 314                 status = -EPERM;
 315                 return status;
 316         }
 317         /* change here to account for the 3 bands of the DSP internal memory */
 318         if ((dsp_addr - dev_context->dsp_start_add) <
 319             dev_context->internal_size) {
 320                 offset = dsp_addr - dev_context->dsp_start_add;
 321         } else {
 322                 status = read_ext_dsp_data(dev_context, host_buff, dsp_addr,
 323                                            ul_num_bytes, mem_type);
 324                 return status;
 325         }
 326         /* copy the data from DSP memory */
 327         memcpy(host_buff, (void *)(dsp_base_addr + offset), ul_num_bytes);
 328         return status;
 329 }
 330
 331 /*
 332  *  ======== bridge_brd_set_state ========
 333  *  purpose:
 334  *      This routine updates the Board status.
 335  */
 336 static int bridge_brd_set_state(struct bridge_dev_context *dev_ctxt,
 337                                     u32 brd_state)
 338 {
 339         int status = 0;
 340         struct bridge_dev_context *dev_context = dev_ctxt;
 341
 342         dev_context->brd_state = brd_state;
 343         return status;
 344 }
 345
 346 /*
 347  *  ======== bridge_brd_start ========
 348  *  purpose:
 349  *      Initializes DSP MMU and Starts DSP.
 350  *
 351  *  Preconditions:
 352  *  a) DSP domain is 'ACTIVE'.
 353  *  b) DSP_RST1 is asserted.
 354  *  b) DSP_RST2 is released.
 355  */
 356 static int bridge_brd_start(struct bridge_dev_context *dev_ctxt,
 357                                    u32 dsp_addr)
 358 {
 359         int status = 0;
 360         struct bridge_dev_context *dev_context = dev_ctxt;
 361         void __iomem *sync_addr;
 362         u32 ul_shm_base;        /* Gpp Phys SM base addr(byte) */
 363         u32 ul_shm_base_virt;   /* Dsp Virt SM base addr */
 364         u32 ul_tlb_base_virt;   /* Base of MMU TLB entry */
 365         u32 shm_sync_pa;
 366         /* Offset of shm_base_virt from tlb_base_virt */
 367         u32 ul_shm_offset_virt;
 368         s32 entry_ndx;
 369         s32 itmp_entry_ndx = 0; /* DSP-MMU TLB entry base address */
 370         struct cfg_hostres *resources = NULL;
 371         u32 temp;
 372         u32 ul_dsp_clk_rate;
 373         u32 ul_dsp_clk_addr;
 374         u32 ul_bios_gp_timer;
 375         u32 clk_cmd;
 376         struct io_mgr *hio_mgr;
 377         u32 ul_load_monitor_timer;
 378         u32 wdt_en = 0;
 379         struct omap_dsp_platform_data *pdata =
 380                 omap_dspbridge_dev->dev.platform_data;
 381
 382         /* The device context contains all the mmu setup info from when the
 383          * last dsp base image was loaded. The first entry is always
 384          * SHMMEM base. */
 385         /* Get SHM_BEG - convert to byte address */
 386         (void)dev_get_symbol(dev_context->dev_obj, SHMBASENAME,
 387                              &ul_shm_base_virt);
 388         ul_shm_base_virt *= DSPWORDSIZE;
 389         /* DSP Virtual address */
 390         ul_tlb_base_virt = dev_context->atlb_entry[0].dsp_va;
 391         ul_shm_offset_virt =
 392             ul_shm_base_virt - (ul_tlb_base_virt * DSPWORDSIZE);
 393         /* Kernel logical address */
 394         ul_shm_base = dev_context->atlb_entry[0].gpp_va + ul_shm_offset_virt;
 395
 396         /* SHM physical sync address */
 397         shm_sync_pa = dev_context->atlb_entry[0].gpp_pa + ul_shm_offset_virt +
 398                         SHMSYNCOFFSET;
 399
 400         /* 2nd wd is used as sync field */
 401         sync_addr = ioremap(shm_sync_pa, SZ_32);
 402         if (!sync_addr)
 403                 return -ENOMEM;
 404
 405         /* Write a signature into the shm base + offset; this will
 406          * get cleared when the DSP program starts. */
 407         if ((ul_shm_base_virt == 0) || (ul_shm_base == 0)) {
 408                 pr_err("%s: Illegal SM base\n", __func__);
 409                 status = -EPERM;
 410         } else
 411                 __raw_writel(0xffffffff, sync_addr);
 412
 413         if (!status) {
 414                 resources = dev_context->resources;
 415                 if (!resources)
 416                         status = -EPERM;
 417
 418                 /* Assert RST1 i.e only the RST only for DSP megacell */
 419                 if (!status) {
 420                         (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST1_IVA2_MASK,
 421                                         OMAP3430_RST1_IVA2_MASK,
 422                                         OMAP3430_IVA2_MOD,
 423                                         OMAP2_RM_RSTCTRL);
 424
 425                         /* Mask address with 1K for compatibility */
 426                         pdata->set_bootaddr(dsp_addr &
 427                                                 OMAP3_IVA2_BOOTADDR_MASK);
 428                         pdata->set_bootmode(dsp_debug ? IDLE : DIRECT);
 429                 }
 430         }
 431         if (!status) {
 432                 /* Reset and Unreset the RST2, so that BOOTADDR is copied to
 433                  * IVA2 SYSC register */
 434                 (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST2_IVA2_MASK,
 435                         OMAP3430_RST2_IVA2_MASK, OMAP3430_IVA2_MOD,
 436                         OMAP2_RM_RSTCTRL);
 437                 udelay(100);
 438                 (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST2_IVA2_MASK, 0,
 439                                         OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 440                 udelay(100);
 441
 442                 /* Disbale the DSP MMU */
 443                 hw_mmu_disable(resources->dmmu_base);
 444                 /* Disable TWL */
 445                 hw_mmu_twl_disable(resources->dmmu_base);
 446
 447                 /* Only make TLB entry if both addresses are non-zero */
 448                 for (entry_ndx = 0; entry_ndx < BRDIOCTL_NUMOFMMUTLB;
 449                      entry_ndx++) {
 450                         struct bridge_ioctl_extproc *e =
 451                                 &dev_context->atlb_entry[entry_ndx];
 452                         struct hw_mmu_map_attrs_t map_attrs = {
 453                                 .endianism = e->endianism,
 454                                 .element_size = e->elem_size,
 455                                 .mixed_size = e->mixed_mode,
 456                         };
 457
 458                         if (!e->gpp_pa || !e->dsp_va)
 459                                 continue;
 460
 461                         dev_dbg(bridge,
 462                                         "MMU %d, pa: 0x%x, va: 0x%x, size: 0x%x",
 463                                         itmp_entry_ndx,
 464                                         e->gpp_pa,
 465                                         e->dsp_va,
 466                                         e->size);
 467
 468                         hw_mmu_tlb_add(dev_context->dsp_mmu_base,
 469                                         e->gpp_pa,
 470                                         e->dsp_va,
 471                                         e->size,
 472                                         itmp_entry_ndx,
 473                                         &map_attrs, 1, 1);
 474
 475                         itmp_entry_ndx++;
 476                 }
 477         }
 478
 479         /* Lock the above TLB entries and get the BIOS and load monitor timer
 480          * information */
 481         if (!status) {
 482                 hw_mmu_num_locked_set(resources->dmmu_base, itmp_entry_ndx);
 483                 hw_mmu_victim_num_set(resources->dmmu_base, itmp_entry_ndx);
 484                 hw_mmu_ttb_set(resources->dmmu_base,
 485                                dev_context->pt_attrs->l1_base_pa);
 486                 hw_mmu_twl_enable(resources->dmmu_base);
 487                 /* Enable the SmartIdle and AutoIdle bit for MMU_SYSCONFIG */
 488
 489                 temp = __raw_readl((resources->dmmu_base) + 0x10);
 490                 temp = (temp & 0xFFFFFFEF) | 0x11;
 491                 __raw_writel(temp, (resources->dmmu_base) + 0x10);
 492
 493                 /* Let the DSP MMU run */
 494                 hw_mmu_enable(resources->dmmu_base);
 495
 496                 /* Enable the BIOS clock */
 497                 (void)dev_get_symbol(dev_context->dev_obj,
 498                                      BRIDGEINIT_BIOSGPTIMER, &ul_bios_gp_timer);
 499                 (void)dev_get_symbol(dev_context->dev_obj,
 500                                      BRIDGEINIT_LOADMON_GPTIMER,
 501                                      &ul_load_monitor_timer);
 502         }
 503
 504         if (!status) {
 505                 if (ul_load_monitor_timer != 0xFFFF) {
 506                         clk_cmd = (BPWR_ENABLE_CLOCK << MBX_PM_CLK_CMDSHIFT) |
 507                             ul_load_monitor_timer;
 508                         dsp_peripheral_clk_ctrl(dev_context, &clk_cmd);
 509                 } else {
 510                         dev_dbg(bridge, "Not able to get the symbol for Load "
 511                                 "Monitor Timer\n");
 512                 }
 513         }
 514
 515         if (!status) {
 516                 if (ul_bios_gp_timer != 0xFFFF) {
 517                         clk_cmd = (BPWR_ENABLE_CLOCK << MBX_PM_CLK_CMDSHIFT) |
 518                             ul_bios_gp_timer;
 519                         dsp_peripheral_clk_ctrl(dev_context, &clk_cmd);
 520                 } else {
 521                         dev_dbg(bridge,
 522                                 "Not able to get the symbol for BIOS Timer\n");
 523                 }
 524         }
 525
 526         if (!status) {
 527                 /* Set the DSP clock rate */
 528                 (void)dev_get_symbol(dev_context->dev_obj,
 529                                      "_BRIDGEINIT_DSP_FREQ", &ul_dsp_clk_addr);
 530                 /*Set Autoidle Mode for IVA2 PLL */
 531                 (*pdata->dsp_cm_write)(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT,
 532                                 OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL);
 533
 534                 if ((unsigned int *)ul_dsp_clk_addr != NULL) {
 535                         /* Get the clock rate */
 536                         ul_dsp_clk_rate = dsp_clk_get_iva2_rate();
 537                         dev_dbg(bridge, "%s: DSP clock rate (KHZ): 0x%x \n",
 538                                 __func__, ul_dsp_clk_rate);
 539                         (void)bridge_brd_write(dev_context,
 540                                                (u8 *) &ul_dsp_clk_rate,
 541                                                ul_dsp_clk_addr, sizeof(u32), 0);
 542                 }
 543                 /*
 544                  * Enable Mailbox events and also drain any pending
 545                  * stale messages.
 546                  */
 547                 dev_context->mbox = omap_mbox_get("dsp", &dsp_mbox_notifier);
 548                 if (IS_ERR(dev_context->mbox)) {
 549                         dev_context->mbox = NULL;
 550                         pr_err("%s: Failed to get dsp mailbox handle\n",
 551                                                                 __func__);
 552                         status = -EPERM;
 553                 }
 554
 555         }
 556         if (!status) {
 557 /*PM_IVA2GRPSEL_PER = 0xC0;*/
 558                 temp = readl(resources->per_pm_base + 0xA8);
 559                 temp = (temp & 0xFFFFFF30) | 0xC0;
 560                 writel(temp, resources->per_pm_base + 0xA8);
 561
 562 /*PM_MPUGRPSEL_PER &= 0xFFFFFF3F; */
 563                 temp = readl(resources->per_pm_base + 0xA4);
 564                 temp = (temp & 0xFFFFFF3F);
 565                 writel(temp, resources->per_pm_base + 0xA4);
 566 /*CM_SLEEPDEP_PER |= 0x04; */
 567                 temp = readl(resources->per_base + 0x44);
 568                 temp = (temp & 0xFFFFFFFB) | 0x04;
 569                 writel(temp, resources->per_base + 0x44);
 570
 571 /*CM_CLKSTCTRL_IVA2 = 0x00000003 -To Allow automatic transitions */
 572                 (*pdata->dsp_cm_write)(OMAP34XX_CLKSTCTRL_ENABLE_AUTO,
 573                                         OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
 574
 575                 /* Let DSP go */
 576                 dev_dbg(bridge, "%s Unreset\n", __func__);
 577                 /* Enable DSP MMU Interrupts */
 578                 hw_mmu_event_enable(resources->dmmu_base,
 579                                     HW_MMU_ALL_INTERRUPTS);
 580                 /* release the RST1, DSP starts executing now .. */
 581                 (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST1_IVA2_MASK, 0,
 582                                         OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 583
 584                 dev_dbg(bridge, "Waiting for Sync @ 0x%x\n", *(u32 *)sync_addr);
 585                 dev_dbg(bridge, "DSP c_int00 Address =  0x%x\n", dsp_addr);
 586                 if (dsp_debug)
 587                         while (__raw_readw(sync_addr))
 588                                 ;
 589
 590                 /* Wait for DSP to clear word in shared memory */
 591                 /* Read the Location */
 592                 if (!wait_for_start(dev_context, sync_addr))
 593                         status = -ETIMEDOUT;
 594
 595                 dev_get_symbol(dev_context->dev_obj, "_WDT_enable", &wdt_en);
 596                 if (wdt_en) {
 597                         /* Start wdt */
 598                         dsp_wdt_sm_set((void *)ul_shm_base);
 599                         dsp_wdt_enable(true);
 600                 }
 601
 602                 status = dev_get_io_mgr(dev_context->dev_obj, &hio_mgr);
 603                 if (hio_mgr) {
 604                         io_sh_msetting(hio_mgr, SHM_OPPINFO, NULL);
 605                         /* Write the synchronization bit to indicate the
 606                          * completion of OPP table update to DSP
 607                          */
 608                         __raw_writel(0XCAFECAFE, sync_addr);
 609
 610                         /* update board state */
 611                         dev_context->brd_state = BRD_RUNNING;
 612                         /* (void)chnlsm_enable_interrupt(dev_context); */
 613                 } else {
 614                         dev_context->brd_state = BRD_UNKNOWN;
 615                 }
 616         }
 617
 618         iounmap(sync_addr);
 619
 620         return status;
 621 }
 622
 623 /*
 624  *  ======== bridge_brd_stop ========
 625  *  purpose:
 626  *      Puts DSP in self loop.
 627  *
 628  *  Preconditions :
 629  *  a) None
 630  */
 631 static int bridge_brd_stop(struct bridge_dev_context *dev_ctxt)
 632 {
 633         int status = 0;
 634         struct bridge_dev_context *dev_context = dev_ctxt;
 635         struct pg_table_attrs *pt_attrs;
 636         u32 dsp_pwr_state;
 637         struct omap_dsp_platform_data *pdata =
 638                 omap_dspbridge_dev->dev.platform_data;
 639
 640         if (dev_context->brd_state == BRD_STOPPED)
 641                 return status;
 642
 643         /* as per TRM, it is advised to first drive the IVA2 to 'Standby' mode,
 644          * before turning off the clocks.. This is to ensure that there are no
 645          * pending L3 or other transactons from IVA2 */
 646         dsp_pwr_state = (*pdata->dsp_prm_read)
 647                 (OMAP3430_IVA2_MOD, OMAP2_PM_PWSTST) & OMAP_POWERSTATEST_MASK;
 648         if (dsp_pwr_state != PWRDM_POWER_OFF) {
 649                 (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST2_IVA2_MASK, 0,
 650                                         OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 651                 sm_interrupt_dsp(dev_context, MBX_PM_DSPIDLE);
 652                 mdelay(10);
 653
 654                 /* IVA2 is not in OFF state */
 655                 /* Set PM_PWSTCTRL_IVA2  to OFF */
 656                 (*pdata->dsp_prm_rmw_bits)(OMAP_POWERSTATEST_MASK,
 657                         PWRDM_POWER_OFF, OMAP3430_IVA2_MOD, OMAP2_PM_PWSTCTRL);
 658                 /* Set the SW supervised state transition for Sleep */
 659                 (*pdata->dsp_cm_write)(OMAP34XX_CLKSTCTRL_FORCE_SLEEP,
 660                                         OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
 661         }
 662         udelay(10);
 663         /* Release the Ext Base virtual Address as the next DSP Program
 664          * may have a different load address */
 665         if (dev_context->dsp_ext_base_addr)
 666                 dev_context->dsp_ext_base_addr = 0;
 667
 668         dev_context->brd_state = BRD_STOPPED;   /* update board state */
 669
 670         dsp_wdt_enable(false);
 671
 672         /* This is a good place to clear the MMU page tables as well */
 673         if (dev_context->pt_attrs) {
 674                 pt_attrs = dev_context->pt_attrs;
 675                 memset((u8 *) pt_attrs->l1_base_va, 0x00, pt_attrs->l1_size);
 676                 memset((u8 *) pt_attrs->l2_base_va, 0x00, pt_attrs->l2_size);
 677                 memset((u8 *) pt_attrs->pg_info, 0x00,
 678                        (pt_attrs->l2_num_pages * sizeof(struct page_info)));
 679         }
 680         /* Disable the mailbox interrupts */
 681         if (dev_context->mbox) {
 682                 omap_mbox_disable_irq(dev_context->mbox, IRQ_RX);
 683                 omap_mbox_put(dev_context->mbox, &dsp_mbox_notifier);
 684                 dev_context->mbox = NULL;
 685         }
 686         /* Reset IVA2 clocks*/
 687         (*pdata->dsp_prm_write)(OMAP3430_RST1_IVA2_MASK |
 688                         OMAP3430_RST2_IVA2_MASK | OMAP3430_RST3_IVA2_MASK,
 689                         OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 690
 691         dsp_clock_disable_all(dev_context->dsp_per_clks);
 692         dsp_clk_disable(DSP_CLK_IVA2);
 693
 694         return status;
 695 }
 696
 697 /*
 698  *  ======== bridge_brd_status ========
 699  *      Returns the board status.
 700  */
 701 static int bridge_brd_status(struct bridge_dev_context *dev_ctxt,
 702                                     int *board_state)
 703 {
 704         struct bridge_dev_context *dev_context = dev_ctxt;
 705         *board_state = dev_context->brd_state;
 706         return 0;
 707 }
 708
 709 /*
 710  *  ======== bridge_brd_write ========
 711  *      Copies the buffers to DSP internal or external memory.
 712  */
 713 static int bridge_brd_write(struct bridge_dev_context *dev_ctxt,
 714                                    u8 *host_buff, u32 dsp_addr,
 715                                    u32 ul_num_bytes, u32 mem_type)
 716 {
 717         int status = 0;
 718         struct bridge_dev_context *dev_context = dev_ctxt;
 719
 720         if (dsp_addr < dev_context->dsp_start_add) {
 721                 status = -EPERM;
 722                 return status;
 723         }
 724         if ((dsp_addr - dev_context->dsp_start_add) <
 725             dev_context->internal_size) {
 726                 status = write_dsp_data(dev_ctxt, host_buff, dsp_addr,
 727                                         ul_num_bytes, mem_type);
 728         } else {
 729                 status = write_ext_dsp_data(dev_context, host_buff, dsp_addr,
 730                                             ul_num_bytes, mem_type, false);
 731         }
 732
 733         return status;
 734 }
 735
 736 /*
 737  *  ======== bridge_dev_create ========
 738  *      Creates a driver object. Puts DSP in self loop.
 739  */
 740 static int bridge_dev_create(struct bridge_dev_context
 741                                         **dev_cntxt,
 742                                         struct dev_object *hdev_obj,
 743                                         struct cfg_hostres *config_param)
 744 {
 745         int status = 0;
 746         struct bridge_dev_context *dev_context = NULL;
 747         s32 entry_ndx;
 748         struct cfg_hostres *resources = config_param;
 749         struct pg_table_attrs *pt_attrs;
 750         u32 pg_tbl_pa;
 751         u32 pg_tbl_va;
 752         u32 align_size;
 753         struct drv_data *drv_datap = dev_get_drvdata(bridge);
 754
 755         /* Allocate and initialize a data structure to contain the bridge driver
 756          *  state, which becomes the context for later calls into this driver */
 757         dev_context = kzalloc(sizeof(struct bridge_dev_context), GFP_KERNEL);
 758         if (!dev_context) {
 759                 status = -ENOMEM;
 760                 goto func_end;
 761         }
 762
 763         dev_context->dsp_start_add = (u32) OMAP_GEM_BASE;
 764         dev_context->self_loop = (u32) NULL;
 765         dev_context->dsp_per_clks = 0;
 766         dev_context->internal_size = OMAP_DSP_SIZE;
 767         /*  Clear dev context MMU table entries.
 768          *  These get set on bridge_io_on_loaded() call after program loaded. */
 769         for (entry_ndx = 0; entry_ndx < BRDIOCTL_NUMOFMMUTLB; entry_ndx++) {
 770                 dev_context->atlb_entry[entry_ndx].gpp_pa =
 771                     dev_context->atlb_entry[entry_ndx].dsp_va = 0;
 772         }
 773         dev_context->dsp_base_addr = (u32) MEM_LINEAR_ADDRESS((void *)
 774                                                                  (config_param->
 775                                                                   mem_base
 776                                                                   [3]),
 777                                                                  config_param->
 778                                                                  mem_length
 779                                                                  [3]);
 780         if (!dev_context->dsp_base_addr)
 781                 status = -EPERM;
 782
 783         pt_attrs = kzalloc(sizeof(struct pg_table_attrs), GFP_KERNEL);
 784         if (pt_attrs != NULL) {
 785                 pt_attrs->l1_size = SZ_16K; /* 4096 entries of 32 bits */
 786                 align_size = pt_attrs->l1_size;
 787                 /* Align sizes are expected to be power of 2 */
 788                 /* we like to get aligned on L1 table size */
 789                 pg_tbl_va = (u32) mem_alloc_phys_mem(pt_attrs->l1_size,
 790                                                      align_size, &pg_tbl_pa);
 791
 792                 /* Check if the PA is aligned for us */
 793                 if ((pg_tbl_pa) & (align_size - 1)) {
 794                         /* PA not aligned to page table size ,
 795                          * try with more allocation and align */
 796                         mem_free_phys_mem((void *)pg_tbl_va, pg_tbl_pa,
 797                                           pt_attrs->l1_size);
 798                         /* we like to get aligned on L1 table size */
 799                         pg_tbl_va =
 800                             (u32) mem_alloc_phys_mem((pt_attrs->l1_size) * 2,
 801                                                      align_size, &pg_tbl_pa);
 802                         /* We should be able to get aligned table now */
 803                         pt_attrs->l1_tbl_alloc_pa = pg_tbl_pa;
 804                         pt_attrs->l1_tbl_alloc_va = pg_tbl_va;
 805                         pt_attrs->l1_tbl_alloc_sz = pt_attrs->l1_size * 2;
 806                         /* Align the PA to the next 'align'  boundary */
 807                         pt_attrs->l1_base_pa =
 808                             ((pg_tbl_pa) +
 809                              (align_size - 1)) & (~(align_size - 1));
 810                         pt_attrs->l1_base_va =
 811                             pg_tbl_va + (pt_attrs->l1_base_pa - pg_tbl_pa);
 812                 } else {
 813                         /* We got aligned PA, cool */
 814                         pt_attrs->l1_tbl_alloc_pa = pg_tbl_pa;
 815                         pt_attrs->l1_tbl_alloc_va = pg_tbl_va;
 816                         pt_attrs->l1_tbl_alloc_sz = pt_attrs->l1_size;
 817                         pt_attrs->l1_base_pa = pg_tbl_pa;
 818                         pt_attrs->l1_base_va = pg_tbl_va;
 819                 }
 820                 if (pt_attrs->l1_base_va)
 821                         memset((u8 *) pt_attrs->l1_base_va, 0x00,
 822                                pt_attrs->l1_size);
 823
 824                 /* number of L2 page tables = DMM pool used + SHMMEM +EXTMEM +
 825                  * L4 pages */
 826                 pt_attrs->l2_num_pages = ((DMMPOOLSIZE >> 20) + 6);
 827                 pt_attrs->l2_size = HW_MMU_COARSE_PAGE_SIZE *
 828                     pt_attrs->l2_num_pages;
 829                 align_size = 4; /* Make it u32 aligned */
 830                 /* we like to get aligned on L1 table size */
 831                 pg_tbl_va = (u32) mem_alloc_phys_mem(pt_attrs->l2_size,
 832                                                      align_size, &pg_tbl_pa);
 833                 pt_attrs->l2_tbl_alloc_pa = pg_tbl_pa;
 834                 pt_attrs->l2_tbl_alloc_va = pg_tbl_va;
 835                 pt_attrs->l2_tbl_alloc_sz = pt_attrs->l2_size;
 836                 pt_attrs->l2_base_pa = pg_tbl_pa;
 837                 pt_attrs->l2_base_va = pg_tbl_va;
 838
 839                 if (pt_attrs->l2_base_va)
 840                         memset((u8 *) pt_attrs->l2_base_va, 0x00,
 841                                pt_attrs->l2_size);
 842
 843                 pt_attrs->pg_info = kzalloc(pt_attrs->l2_num_pages *
 844                                         sizeof(struct page_info), GFP_KERNEL);
 845                 dev_dbg(bridge,
 846                         "L1 pa %x, va %x, size %x\n L2 pa %x, va "
 847                         "%x, size %x\n", pt_attrs->l1_base_pa,
 848                         pt_attrs->l1_base_va, pt_attrs->l1_size,
 849                         pt_attrs->l2_base_pa, pt_attrs->l2_base_va,
 850                         pt_attrs->l2_size);
 851                 dev_dbg(bridge, "pt_attrs %p L2 NumPages %x pg_info %p\n",
 852                         pt_attrs, pt_attrs->l2_num_pages, pt_attrs->pg_info);
 853         }
 854         if ((pt_attrs != NULL) && (pt_attrs->l1_base_va != 0) &&
 855             (pt_attrs->l2_base_va != 0) && (pt_attrs->pg_info != NULL))
 856                 dev_context->pt_attrs = pt_attrs;
 857         else
 858                 status = -ENOMEM;
 859
 860         if (!status) {
 861                 spin_lock_init(&pt_attrs->pg_lock);
 862                 dev_context->tc_word_swap_on = drv_datap->tc_wordswapon;
 863
 864                 /* Set the Clock Divisor for the DSP module */
 865                 udelay(5);
 866                 /* MMU address is obtained from the host
 867                  * resources struct */
 868                 dev_context->dsp_mmu_base = resources->dmmu_base;
 869         }
 870         if (!status) {
 871                 dev_context->dev_obj = hdev_obj;
 872                 /* Store current board state. */
 873                 dev_context->brd_state = BRD_UNKNOWN;
 874                 dev_context->resources = resources;
 875                 dsp_clk_enable(DSP_CLK_IVA2);
 876                 bridge_brd_stop(dev_context);
 877                 /* Return ptr to our device state to the DSP API for storage */
 878                 *dev_cntxt = dev_context;
 879         } else {
 880                 if (pt_attrs != NULL) {
 881                         kfree(pt_attrs->pg_info);
 882
 883                         if (pt_attrs->l2_tbl_alloc_va) {
 884                                 mem_free_phys_mem((void *)
 885                                                   pt_attrs->l2_tbl_alloc_va,
 886                                                   pt_attrs->l2_tbl_alloc_pa,
 887                                                   pt_attrs->l2_tbl_alloc_sz);
 888                         }
 889                         if (pt_attrs->l1_tbl_alloc_va) {
 890                                 mem_free_phys_mem((void *)
 891                                                   pt_attrs->l1_tbl_alloc_va,
 892                                                   pt_attrs->l1_tbl_alloc_pa,
 893                                                   pt_attrs->l1_tbl_alloc_sz);
 894                         }
 895                 }
 896                 kfree(pt_attrs);
 897                 kfree(dev_context);
 898         }
 899 func_end:
 900         return status;
 901 }
 902
 903 /*
 904  *  ======== bridge_dev_ctrl ========
 905  *      Receives device specific commands.
 906  */
 907 static int bridge_dev_ctrl(struct bridge_dev_context *dev_context,
 908                                   u32 dw_cmd, void *pargs)
 909 {
 910         int status = 0;
 911         struct bridge_ioctl_extproc *pa_ext_proc =
 912                                         (struct bridge_ioctl_extproc *)pargs;
 913         s32 ndx;
 914
 915         switch (dw_cmd) {
 916         case BRDIOCTL_CHNLREAD:
 917                 break;
 918         case BRDIOCTL_CHNLWRITE:
 919                 break;
 920         case BRDIOCTL_SETMMUCONFIG:
 921                 /* store away dsp-mmu setup values for later use */
 922                 for (ndx = 0; ndx < BRDIOCTL_NUMOFMMUTLB; ndx++, pa_ext_proc++)
 923                         dev_context->atlb_entry[ndx] = *pa_ext_proc;
 924                 break;
 925         case BRDIOCTL_DEEPSLEEP:
 926         case BRDIOCTL_EMERGENCYSLEEP:
 927                 /* Currently only DSP Idle is supported Need to update for
 928                  * later releases */
 929                 status = sleep_dsp(dev_context, PWR_DEEPSLEEP, pargs);
 930                 break;
 931         case BRDIOCTL_WAKEUP:
 932                 status = wake_dsp(dev_context, pargs);
 933                 break;
 934         case BRDIOCTL_CLK_CTRL:
 935                 status = 0;
 936                 /* Looking For Baseport Fix for Clocks */
 937                 status = dsp_peripheral_clk_ctrl(dev_context, pargs);
 938                 break;
 939         case BRDIOCTL_PWR_HIBERNATE:
 940                 status = handle_hibernation_from_dsp(dev_context);
 941                 break;
 942         case BRDIOCTL_PRESCALE_NOTIFY:
 943                 status = pre_scale_dsp(dev_context, pargs);
 944                 break;
 945         case BRDIOCTL_POSTSCALE_NOTIFY:
 946                 status = post_scale_dsp(dev_context, pargs);
 947                 break;
 948         case BRDIOCTL_CONSTRAINT_REQUEST:
 949                 status = handle_constraints_set(dev_context, pargs);
 950                 break;
 951         default:
 952                 status = -EPERM;
 953                 break;
 954         }
 955         return status;
 956 }
 957
 958 /*
 959  *  ======== bridge_dev_destroy ========
 960  *      Destroys the driver object.
 961  */
 962 static int bridge_dev_destroy(struct bridge_dev_context *dev_ctxt)
 963 {
 964         struct pg_table_attrs *pt_attrs;
 965         int status = 0;
 966         struct bridge_dev_context *dev_context = (struct bridge_dev_context *)
 967             dev_ctxt;
 968         struct cfg_hostres *host_res;
 969         u32 shm_size;
 970         struct drv_data *drv_datap = dev_get_drvdata(bridge);
 971
 972         /* It should never happen */
 973         if (!dev_ctxt)
 974                 return -EFAULT;
 975
 976         /* first put the device to stop state */
 977         bridge_brd_stop(dev_context);
 978         if (dev_context->pt_attrs) {
 979                 pt_attrs = dev_context->pt_attrs;
 980                 kfree(pt_attrs->pg_info);
 981
 982                 if (pt_attrs->l2_tbl_alloc_va) {
 983                         mem_free_phys_mem((void *)pt_attrs->l2_tbl_alloc_va,
 984                                           pt_attrs->l2_tbl_alloc_pa,
 985                                           pt_attrs->l2_tbl_alloc_sz);
 986                 }
 987                 if (pt_attrs->l1_tbl_alloc_va) {
 988                         mem_free_phys_mem((void *)pt_attrs->l1_tbl_alloc_va,
 989                                           pt_attrs->l1_tbl_alloc_pa,
 990                                           pt_attrs->l1_tbl_alloc_sz);
 991                 }
 992                 kfree(pt_attrs);
 993
 994         }
 995
 996         if (dev_context->resources) {
 997                 host_res = dev_context->resources;
 998                 shm_size = drv_datap->shm_size;
 999                 if (shm_size >= 0x10000) {
1000                         if ((host_res->mem_base[1]) &&
1001                             (host_res->mem_phys[1])) {
1002                                 mem_free_phys_mem((void *)
1003                                                   host_res->mem_base
1004                                                   [1],
1005                                                   host_res->mem_phys
1006                                                   [1], shm_size);
1007                         }
1008                 } else {
1009                         dev_dbg(bridge, "%s: Error getting shm size "
1010                                 "from registry: %x. Not calling "
1011                                 "mem_free_phys_mem\n", __func__,
1012                                 status);
1013                 }
1014                 host_res->mem_base[1] = 0;
1015                 host_res->mem_phys[1] = 0;
1016
1017                 if (host_res->mem_base[0])
1018                         iounmap((void *)host_res->mem_base[0]);
1019                 if (host_res->mem_base[2])
1020                         iounmap((void *)host_res->mem_base[2]);
1021                 if (host_res->mem_base[3])
1022                         iounmap((void *)host_res->mem_base[3]);
1023                 if (host_res->mem_base[4])
1024                         iounmap((void *)host_res->mem_base[4]);
1025                 if (host_res->dmmu_base)
1026                         iounmap(host_res->dmmu_base);
1027                 if (host_res->per_base)
1028                         iounmap(host_res->per_base);
1029                 if (host_res->per_pm_base)
1030                         iounmap((void *)host_res->per_pm_base);
1031                 if (host_res->core_pm_base)
1032                         iounmap((void *)host_res->core_pm_base);
1033
1034                 host_res->mem_base[0] = (u32) NULL;
1035                 host_res->mem_base[2] = (u32) NULL;
1036                 host_res->mem_base[3] = (u32) NULL;
1037                 host_res->mem_base[4] = (u32) NULL;
1038                 host_res->dmmu_base = NULL;
1039
1040                 kfree(host_res);
1041         }
1042
1043         /* Free the driver's device context: */
1044         kfree(drv_datap->base_img);
1045         kfree((void *)dev_ctxt);
1046         return status;
1047 }
1048
1049 static int bridge_brd_mem_copy(struct bridge_dev_context *dev_ctxt,
1050                                    u32 dsp_dest_addr, u32 dsp_src_addr,
1051                                    u32 ul_num_bytes, u32 mem_type)
1052 {
1053         int status = 0;
1054         u32 src_addr = dsp_src_addr;
1055         u32 dest_addr = dsp_dest_addr;
1056         u32 copy_bytes = 0;
1057         u32 total_bytes = ul_num_bytes;
1058         u8 host_buf[BUFFERSIZE];
1059         struct bridge_dev_context *dev_context = dev_ctxt;
1060         while (total_bytes > 0 && !status) {
1061                 copy_bytes =
1062                     total_bytes > BUFFERSIZE ? BUFFERSIZE : total_bytes;
1063                 /* Read from External memory */
1064                 status = read_ext_dsp_data(dev_ctxt, host_buf, src_addr,
1065                                            copy_bytes, mem_type);
1066                 if (!status) {
1067                         if (dest_addr < (dev_context->dsp_start_add +
1068                                          dev_context->internal_size)) {
1069                                 /* Write to Internal memory */
1070                                 status = write_dsp_data(dev_ctxt, host_buf,
1071                                                         dest_addr, copy_bytes,
1072                                                         mem_type);
1073                         } else {
1074                                 /* Write to External memory */
1075                                 status =
1076                                     write_ext_dsp_data(dev_ctxt, host_buf,
1077                                                        dest_addr, copy_bytes,
1078                                                        mem_type, false);
1079                         }
1080                 }
1081                 total_bytes -= copy_bytes;
1082                 src_addr += copy_bytes;
1083                 dest_addr += copy_bytes;
1084         }
1085         return status;
1086 }
1087
1088 /* Mem Write does not halt the DSP to write unlike bridge_brd_write */
1089 static int bridge_brd_mem_write(struct bridge_dev_context *dev_ctxt,
1090                                     u8 *host_buff, u32 dsp_addr,
1091                                     u32 ul_num_bytes, u32 mem_type)
1092 {
1093         int status = 0;
1094         struct bridge_dev_context *dev_context = dev_ctxt;
1095         u32 ul_remain_bytes = 0;
1096         u32 ul_bytes = 0;
1097         ul_remain_bytes = ul_num_bytes;
1098         while (ul_remain_bytes > 0 && !status) {
1099                 ul_bytes =
1100                     ul_remain_bytes > BUFFERSIZE ? BUFFERSIZE : ul_remain_bytes;
1101                 if (dsp_addr < (dev_context->dsp_start_add +
1102                                  dev_context->internal_size)) {
1103                         status =
1104                             write_dsp_data(dev_ctxt, host_buff, dsp_addr,
1105                                            ul_bytes, mem_type);
1106                 } else {
1107                         status = write_ext_dsp_data(dev_ctxt, host_buff,
1108                                                     dsp_addr, ul_bytes,
1109                                                     mem_type, true);
1110                 }
1111                 ul_remain_bytes -= ul_bytes;
1112                 dsp_addr += ul_bytes;
1113                 host_buff = host_buff + ul_bytes;
1114         }
1115         return status;
1116 }
1117
1118 /*
1119  *  ======== bridge_brd_mem_map ========
1120  *      This function maps MPU buffer to the DSP address space. It performs
1121  *  linear to physical address translation if required. It translates each
1122  *  page since linear addresses can be physically non-contiguous
1123  *  All address & size arguments are assumed to be page aligned (in proc.c)
1124  *
1125  *  TODO: Disable MMU while updating the page tables (but that'll stall DSP)
1126  */
1127 static int bridge_brd_mem_map(struct bridge_dev_context *dev_ctxt,
1128                                   u32 ul_mpu_addr, u32 virt_addr,
1129                                   u32 ul_num_bytes, u32 ul_map_attr,
1130                                   struct page **mapped_pages)
1131 {
1132         u32 attrs;
1133         int status = 0;
1134         struct bridge_dev_context *dev_context = dev_ctxt;
1135         struct hw_mmu_map_attrs_t hw_attrs;
1136         struct vm_area_struct *vma;
1137         struct mm_struct *mm = current->mm;
1138         u32 write = 0;
1139         u32 num_usr_pgs = 0;
1140         struct page *mapped_page, *pg;
1141         s32 pg_num;
1142         u32 va = virt_addr;
1143         struct task_struct *curr_task = current;
1144         u32 pg_i = 0;
1145         u32 mpu_addr, pa;
1146
1147         dev_dbg(bridge,
1148                 "%s hDevCtxt %p, pa %x, va %x, size %x, ul_map_attr %x\n",
1149                 __func__, dev_ctxt, ul_mpu_addr, virt_addr, ul_num_bytes,
1150                 ul_map_attr);
1151         if (ul_num_bytes == 0)
1152                 return -EINVAL;
1153
1154         if (ul_map_attr & DSP_MAP_DIR_MASK) {
1155                 attrs = ul_map_attr;
1156         } else {
1157                 /* Assign default attributes */
1158                 attrs = ul_map_attr | (DSP_MAPVIRTUALADDR | DSP_MAPELEMSIZE16);
1159         }
1160         /* Take mapping properties */
1161         if (attrs & DSP_MAPBIGENDIAN)
1162                 hw_attrs.endianism = HW_BIG_ENDIAN;
1163         else
1164                 hw_attrs.endianism = HW_LITTLE_ENDIAN;
1165
1166         hw_attrs.mixed_size = (enum hw_mmu_mixed_size_t)
1167             ((attrs & DSP_MAPMIXEDELEMSIZE) >> 2);
1168         /* Ignore element_size if mixed_size is enabled */
1169         if (hw_attrs.mixed_size == 0) {
1170                 if (attrs & DSP_MAPELEMSIZE8) {
1171                         /* Size is 8 bit */
1172                         hw_attrs.element_size = HW_ELEM_SIZE8BIT;
1173                 } else if (attrs & DSP_MAPELEMSIZE16) {
1174                         /* Size is 16 bit */
1175                         hw_attrs.element_size = HW_ELEM_SIZE16BIT;
1176                 } else if (attrs & DSP_MAPELEMSIZE32) {
1177                         /* Size is 32 bit */
1178                         hw_attrs.element_size = HW_ELEM_SIZE32BIT;
1179                 } else if (attrs & DSP_MAPELEMSIZE64) {
1180                         /* Size is 64 bit */
1181                         hw_attrs.element_size = HW_ELEM_SIZE64BIT;
1182                 } else {
1183                         /*
1184                          * Mixedsize isn't enabled, so size can't be
1185                          * zero here
1186                          */
1187                         return -EINVAL;
1188                 }
1189         }
1190         if (attrs & DSP_MAPDONOTLOCK)
1191                 hw_attrs.donotlockmpupage = 1;
1192         else
1193                 hw_attrs.donotlockmpupage = 0;
1194
1195         if (attrs & DSP_MAPVMALLOCADDR) {
1196                 return mem_map_vmalloc(dev_ctxt, ul_mpu_addr, virt_addr,
1197                                        ul_num_bytes, &hw_attrs);
1198         }
1199         /*
1200          * Do OS-specific user-va to pa translation.
1201          * Combine physically contiguous regions to reduce TLBs.
1202          * Pass the translated pa to pte_update.
1203          */
1204         if ((attrs & DSP_MAPPHYSICALADDR)) {
1205                 status = pte_update(dev_context, ul_mpu_addr, virt_addr,
1206                                     ul_num_bytes, &hw_attrs);
1207                 goto func_cont;
1208         }
1209
1210         /*
1211          * Important Note: ul_mpu_addr is mapped from user application process
1212          * to current process - it must lie completely within the current
1213          * virtual memory address space in order to be of use to us here!
1214          */
1215         down_read(&mm->mmap_sem);
1216         vma = find_vma(mm, ul_mpu_addr);
1217         if (vma)
1218                 dev_dbg(bridge,
1219                         "VMAfor UserBuf: ul_mpu_addr=%x, ul_num_bytes=%x, "
1220                         "vm_start=%lx, vm_end=%lx, vm_flags=%lx\n", ul_mpu_addr,
1221                         ul_num_bytes, vma->vm_start, vma->vm_end,
1222                         vma->vm_flags);
1223
1224         /*
1225          * It is observed that under some circumstances, the user buffer is
1226          * spread across several VMAs. So loop through and check if the entire
1227          * user buffer is covered
1228          */
1229         while ((vma) && (ul_mpu_addr + ul_num_bytes > vma->vm_end)) {
1230                 /* jump to the next VMA region */
1231                 vma = find_vma(mm, vma->vm_end + 1);
1232                 dev_dbg(bridge,
1233                         "VMA for UserBuf ul_mpu_addr=%x ul_num_bytes=%x, "
1234                         "vm_start=%lx, vm_end=%lx, vm_flags=%lx\n", ul_mpu_addr,
1235                         ul_num_bytes, vma->vm_start, vma->vm_end,
1236                         vma->vm_flags);
1237         }
1238         if (!vma) {
1239                 pr_err("%s: Failed to get VMA region for 0x%x (%d)\n",
1240                        __func__, ul_mpu_addr, ul_num_bytes);
1241                 status = -EINVAL;
1242                 up_read(&mm->mmap_sem);
1243                 goto func_cont;
1244         }
1245
1246         if (vma->vm_flags & VM_IO) {
1247                 num_usr_pgs = ul_num_bytes / PG_SIZE4K;
1248                 mpu_addr = ul_mpu_addr;
1249
1250                 /* Get the physical addresses for user buffer */
1251                 for (pg_i = 0; pg_i < num_usr_pgs; pg_i++) {
1252                         pa = user_va2_pa(mm, mpu_addr);
1253                         if (!pa) {
1254                                 status = -EPERM;
1255                                 pr_err("DSPBRIDGE: VM_IO mapping physical"
1256                                        "address is invalid\n");
1257                                 break;
1258                         }
1259                         if (pfn_valid(__phys_to_pfn(pa))) {
1260                                 pg = PHYS_TO_PAGE(pa);
1261                                 get_page(pg);
1262                                 if (page_count(pg) < 1) {
1263                                         pr_err("Bad page in VM_IO buffer\n");
1264                                         bad_page_dump(pa, pg);
1265                                 }
1266                         }
1267                         status = pte_set(dev_context->pt_attrs, pa,
1268                                          va, HW_PAGE_SIZE4KB, &hw_attrs);
1269                         if (status)
1270                                 break;
1271
1272                         va += HW_PAGE_SIZE4KB;
1273                         mpu_addr += HW_PAGE_SIZE4KB;
1274                         pa += HW_PAGE_SIZE4KB;
1275                 }
1276         } else {
1277                 num_usr_pgs = ul_num_bytes / PG_SIZE4K;
1278                 if (vma->vm_flags & (VM_WRITE | VM_MAYWRITE))
1279                         write = 1;
1280
1281                 for (pg_i = 0; pg_i < num_usr_pgs; pg_i++) {
1282                         pg_num = get_user_pages(curr_task, mm, ul_mpu_addr, 1,
1283                                                 write, 1, &mapped_page, NULL);
1284                         if (pg_num > 0) {
1285                                 if (page_count(mapped_page) < 1) {
1286                                         pr_err("Bad page count after doing"
1287                                                "get_user_pages on"
1288                                                "user buffer\n");
1289                                         bad_page_dump(page_to_phys(mapped_page),
1290                                                       mapped_page);
1291                                 }
1292                                 status = pte_set(dev_context->pt_attrs,
1293                                                  page_to_phys(mapped_page), va,
1294                                                  HW_PAGE_SIZE4KB, &hw_attrs);
1295                                 if (status)
1296                                         break;
1297
1298                                 if (mapped_pages)
1299                                         mapped_pages[pg_i] = mapped_page;
1300
1301                                 va += HW_PAGE_SIZE4KB;
1302                                 ul_mpu_addr += HW_PAGE_SIZE4KB;
1303                         } else {
1304                                 pr_err("DSPBRIDGE: get_user_pages FAILED,"
1305                                        "MPU addr = 0x%x,"
1306                                        "vma->vm_flags = 0x%lx,"
1307                                        "get_user_pages Err"
1308                                        "Value = %d, Buffer"
1309                                        "size=0x%x\n", ul_mpu_addr,
1310                                        vma->vm_flags, pg_num, ul_num_bytes);
1311                                 status = -EPERM;
1312                                 break;
1313                         }
1314                 }
1315         }
1316         up_read(&mm->mmap_sem);
1317 func_cont:
1318         if (status) {
1319                 /*
1320                  * Roll out the mapped pages incase it failed in middle of
1321                  * mapping
1322                  */
1323                 if (pg_i) {
1324                         bridge_brd_mem_un_map(dev_context, virt_addr,
1325                                            (pg_i * PG_SIZE4K));
1326                 }
1327                 status = -EPERM;
1328         }
1329         /*
1330          * In any case, flush the TLB
1331          * This is called from here instead from pte_update to avoid unnecessary
1332          * repetition while mapping non-contiguous physical regions of a virtual
1333          * region
1334          */
1335         flush_all(dev_context);
1336         dev_dbg(bridge, "%s status %x\n", __func__, status);
1337         return status;
1338 }
1339
1340 /*
1341  *  ======== bridge_brd_mem_un_map ========
1342  *      Invalidate the PTEs for the DSP VA block to be unmapped.
1343  *
1344  *      PTEs of a mapped memory block are contiguous in any page table
1345  *      So, instead of looking up the PTE address for every 4K block,
1346  *      we clear consecutive PTEs until we unmap all the bytes
1347  */
1348 static int bridge_brd_mem_un_map(struct bridge_dev_context *dev_ctxt,
1349                                      u32 virt_addr, u32 ul_num_bytes)
1350 {
1351         u32 l1_base_va;
1352         u32 l2_base_va;
1353         u32 l2_base_pa;
1354         u32 l2_page_num;
1355         u32 pte_val;
1356         u32 pte_size;
1357         u32 pte_count;
1358         u32 pte_addr_l1;
1359         u32 pte_addr_l2 = 0;
1360         u32 rem_bytes;
1361         u32 rem_bytes_l2;
1362         u32 va_curr;
1363         struct page *pg = NULL;
1364         int status = 0;
1365         struct bridge_dev_context *dev_context = dev_ctxt;
1366         struct pg_table_attrs *pt = dev_context->pt_attrs;
1367         u32 temp;
1368         u32 paddr;
1369         u32 numof4k_pages = 0;
1370
1371         va_curr = virt_addr;
1372         rem_bytes = ul_num_bytes;
1373         rem_bytes_l2 = 0;
1374         l1_base_va = pt->l1_base_va;
1375         pte_addr_l1 = hw_mmu_pte_addr_l1(l1_base_va, va_curr);
1376         dev_dbg(bridge, "%s dev_ctxt %p, va %x, NumBytes %x l1_base_va %x, "
1377                 "pte_addr_l1 %x\n", __func__, dev_ctxt, virt_addr,
1378                 ul_num_bytes, l1_base_va, pte_addr_l1);
1379
1380         while (rem_bytes && !status) {
1381                 u32 va_curr_orig = va_curr;
1382                 /* Find whether the L1 PTE points to a valid L2 PT */
1383                 pte_addr_l1 = hw_mmu_pte_addr_l1(l1_base_va, va_curr);
1384                 pte_val = *(u32 *) pte_addr_l1;
1385                 pte_size = hw_mmu_pte_size_l1(pte_val);
1386
1387                 if (pte_size != HW_MMU_COARSE_PAGE_SIZE)
1388                         goto skip_coarse_page;
1389
1390                 /*
1391                  * Get the L2 PA from the L1 PTE, and find
1392                  * corresponding L2 VA
1393                  */
1394                 l2_base_pa = hw_mmu_pte_coarse_l1(pte_val);
1395                 l2_base_va = l2_base_pa - pt->l2_base_pa + pt->l2_base_va;
1396                 l2_page_num =
1397                     (l2_base_pa - pt->l2_base_pa) / HW_MMU_COARSE_PAGE_SIZE;
1398                 /*
1399                  * Find the L2 PTE address from which we will start
1400                  * clearing, the number of PTEs to be cleared on this
1401                  * page, and the size of VA space that needs to be
1402                  * cleared on this L2 page
1403                  */
1404                 pte_addr_l2 = hw_mmu_pte_addr_l2(l2_base_va, va_curr);
1405                 pte_count = pte_addr_l2 & (HW_MMU_COARSE_PAGE_SIZE - 1);
1406                 pte_count = (HW_MMU_COARSE_PAGE_SIZE - pte_count) / sizeof(u32);
1407                 if (rem_bytes < (pte_count * PG_SIZE4K))
1408                         pte_count = rem_bytes / PG_SIZE4K;
1409                 rem_bytes_l2 = pte_count * PG_SIZE4K;
1410
1411                 /*
1412                  * Unmap the VA space on this L2 PT. A quicker way
1413                  * would be to clear pte_count entries starting from
1414                  * pte_addr_l2. However, below code checks that we don't
1415                  * clear invalid entries or less than 64KB for a 64KB
1416                  * entry. Similar checking is done for L1 PTEs too
1417                  * below
1418                  */
1419                 while (rem_bytes_l2 && !status) {
1420                         pte_val = *(u32 *) pte_addr_l2;
1421                         pte_size = hw_mmu_pte_size_l2(pte_val);
1422                         /* va_curr aligned to pte_size? */
1423                         if (pte_size == 0 || rem_bytes_l2 < pte_size ||
1424                             va_curr & (pte_size - 1)) {
1425                                 status = -EPERM;
1426                                 break;
1427                         }
1428
1429                         /* Collect Physical addresses from VA */
1430                         paddr = (pte_val & ~(pte_size - 1));
1431                         if (pte_size == HW_PAGE_SIZE64KB)
1432                                 numof4k_pages = 16;
1433                         else
1434                                 numof4k_pages = 1;
1435                         temp = 0;
1436                         while (temp++ < numof4k_pages) {
1437                                 if (!pfn_valid(__phys_to_pfn(paddr))) {
1438                                         paddr += HW_PAGE_SIZE4KB;
1439                                         continue;
1440                                 }
1441                                 pg = PHYS_TO_PAGE(paddr);
1442                                 if (page_count(pg) < 1) {
1443                                         pr_info("DSPBRIDGE: UNMAP function: "
1444                                                 "COUNT 0 FOR PA 0x%x, size = "
1445                                                 "0x%x\n", paddr, ul_num_bytes);
1446                                         bad_page_dump(paddr, pg);
1447                                 } else {
1448                                         set_page_dirty(pg);
1449                                         page_cache_release(pg);
1450                                 }
1451                                 paddr += HW_PAGE_SIZE4KB;
1452                         }
1453                         if (hw_mmu_pte_clear(pte_addr_l2, va_curr, pte_size)) {
1454                                 status = -EPERM;
1455                                 goto EXIT_LOOP;
1456                         }
1457
1458                         status = 0;
1459                         rem_bytes_l2 -= pte_size;
1460                         va_curr += pte_size;
1461                         pte_addr_l2 += (pte_size >> 12) * sizeof(u32);
1462                 }
1463                 spin_lock(&pt->pg_lock);
1464                 if (rem_bytes_l2 == 0) {
1465                         pt->pg_info[l2_page_num].num_entries -= pte_count;
1466                         if (pt->pg_info[l2_page_num].num_entries == 0) {
1467                                 /*
1468                                  * Clear the L1 PTE pointing to the L2 PT
1469                                  */
1470                                 if (!hw_mmu_pte_clear(l1_base_va, va_curr_orig,
1471                                                      HW_MMU_COARSE_PAGE_SIZE))
1472                                         status = 0;
1473                                 else {
1474                                         status = -EPERM;
1475                                         spin_unlock(&pt->pg_lock);
1476                                         goto EXIT_LOOP;
1477                                 }
1478                         }
1479                         rem_bytes -= pte_count * PG_SIZE4K;
1480                 } else
1481                         status = -EPERM;
1482
1483                 spin_unlock(&pt->pg_lock);
1484                 continue;
1485 skip_coarse_page:
1486                 /* va_curr aligned to pte_size? */
1487                 /* pte_size = 1 MB or 16 MB */
1488                 if (pte_size == 0 || rem_bytes < pte_size ||
1489                     va_curr & (pte_size - 1)) {
1490                         status = -EPERM;
1491                         break;
1492                 }
1493
1494                 if (pte_size == HW_PAGE_SIZE1MB)
1495                         numof4k_pages = 256;
1496                 else
1497                         numof4k_pages = 4096;
1498                 temp = 0;
1499                 /* Collect Physical addresses from VA */
1500                 paddr = (pte_val & ~(pte_size - 1));
1501                 while (temp++ < numof4k_pages) {
1502                         if (pfn_valid(__phys_to_pfn(paddr))) {
1503                                 pg = PHYS_TO_PAGE(paddr);
1504                                 if (page_count(pg) < 1) {
1505                                         pr_info("DSPBRIDGE: UNMAP function: "
1506                                                 "COUNT 0 FOR PA 0x%x, size = "
1507                                                 "0x%x\n", paddr, ul_num_bytes);
1508                                         bad_page_dump(paddr, pg);
1509                                 } else {
1510                                         set_page_dirty(pg);
1511                                         page_cache_release(pg);
1512                                 }
1513                         }
1514                         paddr += HW_PAGE_SIZE4KB;
1515                 }
1516                 if (!hw_mmu_pte_clear(l1_base_va, va_curr, pte_size)) {
1517                         status = 0;
1518                         rem_bytes -= pte_size;
1519                         va_curr += pte_size;
1520                 } else {
1521                         status = -EPERM;
1522                         goto EXIT_LOOP;
1523                 }
1524         }
1525         /*
1526          * It is better to flush the TLB here, so that any stale old entries
1527          * get flushed
1528          */
1529 EXIT_LOOP:
1530         flush_all(dev_context);
1531         dev_dbg(bridge,
1532                 "%s: va_curr %x, pte_addr_l1 %x pte_addr_l2 %x rem_bytes %x,"
1533                 " rem_bytes_l2 %x status %x\n", __func__, va_curr, pte_addr_l1,
1534                 pte_addr_l2, rem_bytes, rem_bytes_l2, status);
1535         return status;
1536 }
1537
1538 /*
1539  *  ======== user_va2_pa ========
1540  *  Purpose:
1541  *      This function walks through the page tables to convert a userland
1542  *      virtual address to physical address
1543  */
1544 static u32 user_va2_pa(struct mm_struct *mm, u32 address)
1545 {
1546         pgd_t *pgd;
1547         pud_t *pud;
1548         pmd_t *pmd;
1549         pte_t *ptep, pte;
1550
1551         pgd = pgd_offset(mm, address);
1552         if (pgd_none(*pgd) || pgd_bad(*pgd))
1553                 return 0;
1554
1555         pud = pud_offset(pgd, address);
1556         if (pud_none(*pud) || pud_bad(*pud))
1557                 return 0;
1558
1559         pmd = pmd_offset(pud, address);
1560         if (pmd_none(*pmd) || pmd_bad(*pmd))
1561                 return 0;
1562
1563         ptep = pte_offset_map(pmd, address);
1564         if (ptep) {
1565                 pte = *ptep;
1566                 if (pte_present(pte))
1567                         return pte & PAGE_MASK;
1568         }
1569
1570         return 0;
1571 }
1572
1573 /*
1574  *  ======== pte_update ========
1575  *      This function calculates the optimum page-aligned addresses and sizes
1576  *      Caller must pass page-aligned values
1577  */
1578 static int pte_update(struct bridge_dev_context *dev_ctxt, u32 pa,
1579                              u32 va, u32 size,
1580                              struct hw_mmu_map_attrs_t *map_attrs)
1581 {
1582         u32 i;
1583         u32 all_bits;
1584         u32 pa_curr = pa;
1585         u32 va_curr = va;
1586         u32 num_bytes = size;
1587         struct bridge_dev_context *dev_context = dev_ctxt;
1588         int status = 0;
1589         u32 page_size[] = { HW_PAGE_SIZE16MB, HW_PAGE_SIZE1MB,
1590                 HW_PAGE_SIZE64KB, HW_PAGE_SIZE4KB
1591         };
1592
1593         while (num_bytes && !status) {
1594                 /* To find the max. page size with which both PA & VA are
1595                  * aligned */
1596                 all_bits = pa_curr | va_curr;
1597
1598                 for (i = 0; i < 4; i++) {
1599                         if ((num_bytes >= page_size[i]) && ((all_bits &
1600                                                              (page_size[i] -
1601                                                               1)) == 0)) {
1602                                 status =
1603                                     pte_set(dev_context->pt_attrs, pa_curr,
1604                                             va_curr, page_size[i], map_attrs);
1605                                 pa_curr += page_size[i];
1606                                 va_curr += page_size[i];
1607                                 num_bytes -= page_size[i];
1608                                 /* Don't try smaller sizes. Hopefully we have
1609                                  * reached an address aligned to a bigger page
1610                                  * size */
1611                                 break;
1612                         }
1613                 }
1614         }
1615
1616         return status;
1617 }
1618
1619 /*
1620  *  ======== pte_set ========
1621  *      This function calculates PTE address (MPU virtual) to be updated
1622  *      It also manages the L2 page tables
1623  */
1624 static int pte_set(struct pg_table_attrs *pt, u32 pa, u32 va,
1625                           u32 size, struct hw_mmu_map_attrs_t *attrs)
1626 {
1627         u32 i;
1628         u32 pte_val;
1629         u32 pte_addr_l1;
1630         u32 pte_size;
1631         /* Base address of the PT that will be updated */
1632         u32 pg_tbl_va;
1633         u32 l1_base_va;
1634         /* Compiler warns that the next three variables might be used
1635          * uninitialized in this function. Doesn't seem so. Working around,
1636          * anyways. */
1637         u32 l2_base_va = 0;
1638         u32 l2_base_pa = 0;
1639         u32 l2_page_num = 0;
1640         int status = 0;
1641
1642         l1_base_va = pt->l1_base_va;
1643         pg_tbl_va = l1_base_va;
1644         if ((size == HW_PAGE_SIZE64KB) || (size == HW_PAGE_SIZE4KB)) {
1645                 /* Find whether the L1 PTE points to a valid L2 PT */
1646                 pte_addr_l1 = hw_mmu_pte_addr_l1(l1_base_va, va);
1647                 if (pte_addr_l1 <= (pt->l1_base_va + pt->l1_size)) {
1648                         pte_val = *(u32 *) pte_addr_l1;
1649                         pte_size = hw_mmu_pte_size_l1(pte_val);
1650                 } else {
1651                         return -EPERM;
1652                 }
1653                 spin_lock(&pt->pg_lock);
1654                 if (pte_size == HW_MMU_COARSE_PAGE_SIZE) {
1655                         /* Get the L2 PA from the L1 PTE, and find
1656                          * corresponding L2 VA */
1657                         l2_base_pa = hw_mmu_pte_coarse_l1(pte_val);
1658                         l2_base_va =
1659                             l2_base_pa - pt->l2_base_pa + pt->l2_base_va;
1660                         l2_page_num =
1661                             (l2_base_pa -
1662                              pt->l2_base_pa) / HW_MMU_COARSE_PAGE_SIZE;
1663                 } else if (pte_size == 0) {
1664                         /* L1 PTE is invalid. Allocate a L2 PT and
1665                          * point the L1 PTE to it */
1666                         /* Find a free L2 PT. */
1667                         for (i = 0; (i < pt->l2_num_pages) &&
1668                              (pt->pg_info[i].num_entries != 0); i++)
1669                                 ;
1670                         if (i < pt->l2_num_pages) {
1671                                 l2_page_num = i;
1672                                 l2_base_pa = pt->l2_base_pa + (l2_page_num *
1673                                                 HW_MMU_COARSE_PAGE_SIZE);
1674                                 l2_base_va = pt->l2_base_va + (l2_page_num *
1675                                                 HW_MMU_COARSE_PAGE_SIZE);
1676                                 /* Endianness attributes are ignored for
1677                                  * HW_MMU_COARSE_PAGE_SIZE */
1678                                 status =
1679                                     hw_mmu_pte_set(l1_base_va, l2_base_pa, va,
1680                                                    HW_MMU_COARSE_PAGE_SIZE,
1681                                                    attrs);
1682                         } else {
1683                                 status = -ENOMEM;
1684                         }
1685                 } else {
1686                         /* Found valid L1 PTE of another size.
1687                          * Should not overwrite it. */
1688                         status = -EPERM;
1689                 }
1690                 if (!status) {
1691                         pg_tbl_va = l2_base_va;
1692                         if (size == HW_PAGE_SIZE64KB)
1693                                 pt->pg_info[l2_page_num].num_entries += 16;
1694                         else
1695                                 pt->pg_info[l2_page_num].num_entries++;
1696                         dev_dbg(bridge, "PTE: L2 BaseVa %x, BasePa %x, PageNum "
1697                                 "%x, num_entries %x\n", l2_base_va,
1698                                 l2_base_pa, l2_page_num,
1699                                 pt->pg_info[l2_page_num].num_entries);
1700                 }
1701                 spin_unlock(&pt->pg_lock);
1702         }
1703         if (!status) {
1704                 dev_dbg(bridge, "PTE: pg_tbl_va %x, pa %x, va %x, size %x\n",
1705                         pg_tbl_va, pa, va, size);
1706                 dev_dbg(bridge, "PTE: endianism %x, element_size %x, "
1707                         "mixed_size %x\n", attrs->endianism,
1708                         attrs->element_size, attrs->mixed_size);
1709                 status = hw_mmu_pte_set(pg_tbl_va, pa, va, size, attrs);
1710         }
1711
1712         return status;
1713 }
1714
1715 /* Memory map kernel VA -- memory allocated with vmalloc */
1716 static int mem_map_vmalloc(struct bridge_dev_context *dev_context,
1717                                   u32 ul_mpu_addr, u32 virt_addr,
1718                                   u32 ul_num_bytes,
1719                                   struct hw_mmu_map_attrs_t *hw_attrs)
1720 {
1721         int status = 0;
1722         struct page *page[1];
1723         u32 i;
1724         u32 pa_curr;
1725         u32 pa_next;
1726         u32 va_curr;
1727         u32 size_curr;
1728         u32 num_pages;
1729         u32 pa;
1730         u32 num_of4k_pages;
1731         u32 temp = 0;
1732
1733         /*
1734          * Do Kernel va to pa translation.
1735          * Combine physically contiguous regions to reduce TLBs.
1736          * Pass the translated pa to pte_update.
1737          */
1738         num_pages = ul_num_bytes / PAGE_SIZE;   /* PAGE_SIZE = OS page size */
1739         i = 0;
1740         va_curr = ul_mpu_addr;
1741         page[0] = vmalloc_to_page((void *)va_curr);
1742         pa_next = page_to_phys(page[0]);
1743         while (!status && (i < num_pages)) {
1744                 /*
1745                  * Reuse pa_next from the previous iteration to avoid
1746                  * an extra va2pa call
1747                  */
1748                 pa_curr = pa_next;
1749                 size_curr = PAGE_SIZE;
1750                 /*
1751                  * If the next page is physically contiguous,
1752                  * map it with the current one by increasing
1753                  * the size of the region to be mapped
1754                  */
1755                 while (++i < num_pages) {
1756                         page[0] =
1757                             vmalloc_to_page((void *)(va_curr + size_curr));
1758                         pa_next = page_to_phys(page[0]);
1759
1760                         if (pa_next == (pa_curr + size_curr))
1761                                 size_curr += PAGE_SIZE;
1762                         else
1763                                 break;
1764
1765                 }
1766                 if (pa_next == 0) {
1767                         status = -ENOMEM;
1768                         break;
1769                 }
1770                 pa = pa_curr;
1771                 num_of4k_pages = size_curr / HW_PAGE_SIZE4KB;
1772                 while (temp++ < num_of4k_pages) {
1773                         get_page(PHYS_TO_PAGE(pa));
1774                         pa += HW_PAGE_SIZE4KB;
1775                 }
1776                 status = pte_update(dev_context, pa_curr, virt_addr +
1777                                     (va_curr - ul_mpu_addr), size_curr,
1778                                     hw_attrs);
1779                 va_curr += size_curr;
1780         }
1781         /*
1782          * In any case, flush the TLB
1783          * This is called from here instead from pte_update to avoid unnecessary
1784          * repetition while mapping non-contiguous physical regions of a virtual
1785          * region
1786          */
1787         flush_all(dev_context);
1788         dev_dbg(bridge, "%s status %x\n", __func__, status);
1789         return status;
1790 }
1791
1792 /*
1793  *  ======== wait_for_start ========
1794  *      Wait for the singal from DSP that it has started, or time out.
1795  */
1796 bool wait_for_start(struct bridge_dev_context *dev_context,
1797                         void __iomem *sync_addr)
1798 {
1799         u16 timeout = TIHELEN_ACKTIMEOUT;
1800
1801         /*  Wait for response from board */
1802         while (__raw_readw(sync_addr) && --timeout)
1803                 udelay(10);
1804
1805         /*  If timed out: return false */
1806         if (!timeout) {
1807                 pr_err("%s: Timed out waiting DSP to Start\n", __func__);
1808                 return false;
1809         }
1810         return true;
1811 }