2 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
22 * Purpose: Implement functions to access baseband
29 * BBuGetFrameTime - Calculate data frame transmitting time
30 * BBvCaculateParameter - Caculate PhyLength, PhyService and Phy Signal parameter for baseband Tx
31 * BBbReadEmbeded - Embeded read baseband register via MAC
32 * BBbWriteEmbeded - Embeded write baseband register via MAC
33 * BBbIsRegBitsOn - Test if baseband register bits on
34 * BBbIsRegBitsOff - Test if baseband register bits off
35 * BBbVT3253Init - VIA VT3253 baseband chip init code
36 * BBvReadAllRegs - Read All Baseband Registers
37 * BBvLoopbackOn - Turn on BaseBand Loopback mode
38 * BBvLoopbackOff - Turn off BaseBand Loopback mode
41 * 06-10-2003 Bryan YC Fan: Re-write codes to support VT3253 spec.
42 * 08-07-2003 Bryan YC Fan: Add MAXIM2827/2825 and RFMD2959 support.
43 * 08-26-2003 Kyle Hsu : Modify BBuGetFrameTime() and BBvCaculateParameter().
44 * cancel the setting of MAC_REG_SOFTPWRCTL on BBbVT3253Init().
46 * 09-01-2003 Bryan YC Fan: RF & BB tables updated.
47 * Modified BBvLoopbackOn & BBvLoopbackOff().
59 /*--------------------- Static Definitions -------------------------*/
60 //static int msglevel =MSG_LEVEL_DEBUG;
61 static int msglevel =MSG_LEVEL_INFO;
65 /*--------------------- Static Classes ----------------------------*/
67 /*--------------------- Static Variables --------------------------*/
69 /*--------------------- Static Functions --------------------------*/
71 /*--------------------- Export Variables --------------------------*/
73 /*--------------------- Static Definitions -------------------------*/
75 /*--------------------- Static Classes ----------------------------*/
77 /*--------------------- Static Variables --------------------------*/
81 #define CB_VT3253_INIT_FOR_RFMD 446
82 unsigned char byVT3253InitTab_RFMD[CB_VT3253_INIT_FOR_RFMD][2] = {
531 #define CB_VT3253B0_INIT_FOR_RFMD 256
532 unsigned char byVT3253B0_RFMD[CB_VT3253B0_INIT_FOR_RFMD][2] = {
791 #define CB_VT3253B0_AGC_FOR_RFMD2959 195
793 unsigned char byVT3253B0_AGC4_RFMD2959[CB_VT3253B0_AGC_FOR_RFMD2959][2] = {
991 #define CB_VT3253B0_INIT_FOR_AIROHA2230 256
993 unsigned char byVT3253B0_AIROHA2230[CB_VT3253B0_INIT_FOR_AIROHA2230][2] = {
1103 {0x6c, 0x00}, //RobertYu:20050125, request by JJSue
1255 #define CB_VT3253B0_INIT_FOR_UW2451 256
1257 unsigned char byVT3253B0_UW2451[CB_VT3253B0_INIT_FOR_UW2451][2] = {
1367 {0x6c, 0x00}, //RobertYu:20050125, request by JJSue
1517 #define CB_VT3253B0_AGC 193
1519 unsigned char byVT3253B0_AGC[CB_VT3253B0_AGC][2] = {
1715 const unsigned short awcFrameTime[MAX_RATE] =
1716 {10, 20, 55, 110, 24, 36, 48, 72, 96, 144, 192, 216};
1719 /*--------------------- Static Functions --------------------------*/
1723 s_ulGetRatio(PSDevice pDevice);
1739 //printk("Enter s_vChangeAntenna:original RxMode is %d,TxMode is %d\n",pDevice->byRxAntennaMode,pDevice->byTxAntennaMode);
1741 if ( pDevice->dwRxAntennaSel == 0) {
1742 pDevice->dwRxAntennaSel=1;
1743 if (pDevice->bTxRxAntInv == true)
1744 BBvSetRxAntennaMode(pDevice->PortOffset, ANT_A);
1746 BBvSetRxAntennaMode(pDevice->PortOffset, ANT_B);
1748 pDevice->dwRxAntennaSel=0;
1749 if (pDevice->bTxRxAntInv == true)
1750 BBvSetRxAntennaMode(pDevice->PortOffset, ANT_B);
1752 BBvSetRxAntennaMode(pDevice->PortOffset, ANT_A);
1754 if ( pDevice->dwTxAntennaSel == 0) {
1755 pDevice->dwTxAntennaSel=1;
1756 BBvSetTxAntennaMode(pDevice->PortOffset, ANT_B);
1758 pDevice->dwTxAntennaSel=0;
1759 BBvSetTxAntennaMode(pDevice->PortOffset, ANT_A);
1764 /*--------------------- Export Variables --------------------------*/
1766 * Description: Calculate data frame transmitting time
1770 * byPreambleType - Preamble Type
1771 * byPktType - PK_TYPE_11A, PK_TYPE_11B, PK_TYPE_11GB, PK_TYPE_11GA
1772 * cbFrameLength - Baseband Type
1776 * Return Value: FrameTime
1781 unsigned char byPreambleType,
1782 unsigned char byPktType,
1783 unsigned int cbFrameLength,
1784 unsigned short wRate
1787 unsigned int uFrameTime;
1788 unsigned int uPreamble;
1790 unsigned int uRateIdx = (unsigned int) wRate;
1791 unsigned int uRate = 0;
1794 if (uRateIdx > RATE_54M) {
1799 uRate = (unsigned int) awcFrameTime[uRateIdx];
1801 if (uRateIdx <= 3) { //CCK mode
1803 if (byPreambleType == 1) {//Short
1808 uFrameTime = (cbFrameLength * 80) / uRate; //?????
1809 uTmp = (uFrameTime * uRate) / 80;
1810 if (cbFrameLength != uTmp) {
1814 return (uPreamble + uFrameTime);
1817 uFrameTime = (cbFrameLength * 8 + 22) / uRate; //????????
1818 uTmp = ((uFrameTime * uRate) - 22) / 8;
1819 if(cbFrameLength != uTmp) {
1822 uFrameTime = uFrameTime * 4; //???????
1823 if(byPktType != PK_TYPE_11A) {
1824 uFrameTime += 6; //??????
1826 return (20 + uFrameTime); //??????
1831 * Description: Caculate Length, Service, and Signal fields of Phy for Tx
1835 * pDevice - Device Structure
1836 * cbFrameLength - Tx Frame Length
1839 * pwPhyLen - pointer to Phy Length field
1840 * pbyPhySrv - pointer to Phy Service field
1841 * pbyPhySgn - pointer to Phy Signal field
1843 * Return Value: none
1847 BBvCaculateParameter (
1849 unsigned int cbFrameLength,
1850 unsigned short wRate,
1851 unsigned char byPacketType,
1852 unsigned short *pwPhyLen,
1853 unsigned char *pbyPhySrv,
1854 unsigned char *pbyPhySgn
1857 unsigned int cbBitCount;
1858 unsigned int cbUsCount = 0;
1861 unsigned char byPreambleType = pDevice->byPreambleType;
1862 bool bCCK = pDevice->bCCK;
1864 cbBitCount = cbFrameLength * 8;
1869 cbUsCount = cbBitCount;
1874 cbUsCount = cbBitCount / 2;
1875 if (byPreambleType == 1)
1877 else // long preamble
1884 cbUsCount = (cbBitCount * 10) / 55;
1885 cbTmp = (cbUsCount * 55) / 10;
1886 if (cbTmp != cbBitCount)
1888 if (byPreambleType == 1)
1890 else // long preamble
1898 cbUsCount = cbBitCount / 11;
1899 cbTmp = cbUsCount * 11;
1900 if (cbTmp != cbBitCount) {
1902 if ((cbBitCount - cbTmp) <= 3)
1905 if (byPreambleType == 1)
1907 else // long preamble
1912 if(byPacketType == PK_TYPE_11A) {//11a, 5GHZ
1913 *pbyPhySgn = 0x9B; //1001 1011
1916 *pbyPhySgn = 0x8B; //1000 1011
1921 if(byPacketType == PK_TYPE_11A) {//11a, 5GHZ
1922 *pbyPhySgn = 0x9F; //1001 1111
1925 *pbyPhySgn = 0x8F; //1000 1111
1930 if(byPacketType == PK_TYPE_11A) {//11a, 5GHZ
1931 *pbyPhySgn = 0x9A; //1001 1010
1934 *pbyPhySgn = 0x8A; //1000 1010
1939 if(byPacketType == PK_TYPE_11A) {//11a, 5GHZ
1940 *pbyPhySgn = 0x9E; //1001 1110
1943 *pbyPhySgn = 0x8E; //1000 1110
1948 if(byPacketType == PK_TYPE_11A) {//11a, 5GHZ
1949 *pbyPhySgn = 0x99; //1001 1001
1952 *pbyPhySgn = 0x89; //1000 1001
1957 if(byPacketType == PK_TYPE_11A) {//11a, 5GHZ
1958 *pbyPhySgn = 0x9D; //1001 1101
1961 *pbyPhySgn = 0x8D; //1000 1101
1966 if(byPacketType == PK_TYPE_11A) {//11a, 5GHZ
1967 *pbyPhySgn = 0x98; //1001 1000
1970 *pbyPhySgn = 0x88; //1000 1000
1975 if (byPacketType == PK_TYPE_11A) {//11a, 5GHZ
1976 *pbyPhySgn = 0x9C; //1001 1100
1979 *pbyPhySgn = 0x8C; //1000 1100
1984 if (byPacketType == PK_TYPE_11A) {//11a, 5GHZ
1985 *pbyPhySgn = 0x9C; //1001 1100
1988 *pbyPhySgn = 0x8C; //1000 1100
1993 if (byPacketType == PK_TYPE_11B) {
1996 *pbyPhySrv = *pbyPhySrv | 0x80;
1997 *pwPhyLen = (unsigned short)cbUsCount;
2001 *pwPhyLen = (unsigned short)cbFrameLength;
2006 * Description: Read a byte from BASEBAND, by embeded programming
2010 * dwIoBase - I/O base address
2011 * byBBAddr - address of register in Baseband
2013 * pbyData - data read
2015 * Return Value: true if succeeded; false if failed.
2018 bool BBbReadEmbeded (unsigned long dwIoBase, unsigned char byBBAddr, unsigned char *pbyData)
2021 unsigned char byValue;
2024 VNSvOutPortB(dwIoBase + MAC_REG_BBREGADR, byBBAddr);
2027 MACvRegBitsOn(dwIoBase, MAC_REG_BBREGCTL, BBREGCTL_REGR);
2028 // W_MAX_TIMEOUT is the timeout period
2029 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
2030 VNSvInPortB(dwIoBase + MAC_REG_BBREGCTL, &byValue);
2031 if (byValue & BBREGCTL_DONE)
2036 VNSvInPortB(dwIoBase + MAC_REG_BBREGDATA, pbyData);
2038 if (ww == W_MAX_TIMEOUT) {
2040 DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO" DBG_PORT80(0x30)\n");
2048 * Description: Write a Byte to BASEBAND, by embeded programming
2052 * dwIoBase - I/O base address
2053 * byBBAddr - address of register in Baseband
2054 * byData - data to write
2058 * Return Value: true if succeeded; false if failed.
2061 bool BBbWriteEmbeded (unsigned long dwIoBase, unsigned char byBBAddr, unsigned char byData)
2064 unsigned char byValue;
2067 VNSvOutPortB(dwIoBase + MAC_REG_BBREGADR, byBBAddr);
2069 VNSvOutPortB(dwIoBase + MAC_REG_BBREGDATA, byData);
2071 // turn on BBREGCTL_REGW
2072 MACvRegBitsOn(dwIoBase, MAC_REG_BBREGCTL, BBREGCTL_REGW);
2073 // W_MAX_TIMEOUT is the timeout period
2074 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
2075 VNSvInPortB(dwIoBase + MAC_REG_BBREGCTL, &byValue);
2076 if (byValue & BBREGCTL_DONE)
2080 if (ww == W_MAX_TIMEOUT) {
2082 DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO" DBG_PORT80(0x31)\n");
2090 * Description: Test if all bits are set for the Baseband register
2094 * dwIoBase - I/O base address
2095 * byBBAddr - address of register in Baseband
2096 * byTestBits - TestBits
2100 * Return Value: true if all TestBits are set; false otherwise.
2103 bool BBbIsRegBitsOn (unsigned long dwIoBase, unsigned char byBBAddr, unsigned char byTestBits)
2105 unsigned char byOrgData;
2107 BBbReadEmbeded(dwIoBase, byBBAddr, &byOrgData);
2108 return (byOrgData & byTestBits) == byTestBits;
2113 * Description: Test if all bits are clear for the Baseband register
2117 * dwIoBase - I/O base address
2118 * byBBAddr - address of register in Baseband
2119 * byTestBits - TestBits
2123 * Return Value: true if all TestBits are clear; false otherwise.
2126 bool BBbIsRegBitsOff (unsigned long dwIoBase, unsigned char byBBAddr, unsigned char byTestBits)
2128 unsigned char byOrgData;
2130 BBbReadEmbeded(dwIoBase, byBBAddr, &byOrgData);
2131 return (byOrgData & byTestBits) == 0;
2135 * Description: VIA VT3253 Baseband chip init function
2139 * dwIoBase - I/O base address
2140 * byRevId - Revision ID
2141 * byRFType - RF type
2145 * Return Value: true if succeeded; false if failed.
2149 bool BBbVT3253Init (PSDevice pDevice)
2151 bool bResult = true;
2153 unsigned long dwIoBase = pDevice->PortOffset;
2154 unsigned char byRFType = pDevice->byRFType;
2155 unsigned char byLocalID = pDevice->byLocalID;
2157 if (byRFType == RF_RFMD2959) {
2158 if (byLocalID <= REV_ID_VT3253_A1) {
2159 for (ii = 0; ii < CB_VT3253_INIT_FOR_RFMD; ii++) {
2160 bResult &= BBbWriteEmbeded(dwIoBase,byVT3253InitTab_RFMD[ii][0],byVT3253InitTab_RFMD[ii][1]);
2163 for (ii = 0; ii < CB_VT3253B0_INIT_FOR_RFMD; ii++) {
2164 bResult &= BBbWriteEmbeded(dwIoBase,byVT3253B0_RFMD[ii][0],byVT3253B0_RFMD[ii][1]);
2166 for (ii = 0; ii < CB_VT3253B0_AGC_FOR_RFMD2959; ii++) {
2167 bResult &= BBbWriteEmbeded(dwIoBase,byVT3253B0_AGC4_RFMD2959[ii][0],byVT3253B0_AGC4_RFMD2959[ii][1]);
2169 VNSvOutPortD(dwIoBase + MAC_REG_ITRTMSET, 0x23);
2170 MACvRegBitsOn(dwIoBase, MAC_REG_PAPEDELAY, BIT0);
2172 pDevice->abyBBVGA[0] = 0x18;
2173 pDevice->abyBBVGA[1] = 0x0A;
2174 pDevice->abyBBVGA[2] = 0x0;
2175 pDevice->abyBBVGA[3] = 0x0;
2176 pDevice->ldBmThreshold[0] = -70;
2177 pDevice->ldBmThreshold[1] = -50;
2178 pDevice->ldBmThreshold[2] = 0;
2179 pDevice->ldBmThreshold[3] = 0;
2180 } else if ((byRFType == RF_AIROHA) || (byRFType == RF_AL2230S) ) {
2181 for (ii = 0; ii < CB_VT3253B0_INIT_FOR_AIROHA2230; ii++) {
2182 bResult &= BBbWriteEmbeded(dwIoBase,byVT3253B0_AIROHA2230[ii][0],byVT3253B0_AIROHA2230[ii][1]);
2184 for (ii = 0; ii < CB_VT3253B0_AGC; ii++) {
2185 bResult &= BBbWriteEmbeded(dwIoBase,byVT3253B0_AGC[ii][0],byVT3253B0_AGC[ii][1]);
2187 pDevice->abyBBVGA[0] = 0x1C;
2188 pDevice->abyBBVGA[1] = 0x10;
2189 pDevice->abyBBVGA[2] = 0x0;
2190 pDevice->abyBBVGA[3] = 0x0;
2191 pDevice->ldBmThreshold[0] = -70;
2192 pDevice->ldBmThreshold[1] = -48;
2193 pDevice->ldBmThreshold[2] = 0;
2194 pDevice->ldBmThreshold[3] = 0;
2195 } else if (byRFType == RF_UW2451) {
2196 for (ii = 0; ii < CB_VT3253B0_INIT_FOR_UW2451; ii++) {
2197 bResult &= BBbWriteEmbeded(dwIoBase,byVT3253B0_UW2451[ii][0],byVT3253B0_UW2451[ii][1]);
2199 for (ii = 0; ii < CB_VT3253B0_AGC; ii++) {
2200 bResult &= BBbWriteEmbeded(dwIoBase,byVT3253B0_AGC[ii][0],byVT3253B0_AGC[ii][1]);
2202 VNSvOutPortB(dwIoBase + MAC_REG_ITRTMSET, 0x23);
2203 MACvRegBitsOn(dwIoBase, MAC_REG_PAPEDELAY, BIT0);
2205 pDevice->abyBBVGA[0] = 0x14;
2206 pDevice->abyBBVGA[1] = 0x0A;
2207 pDevice->abyBBVGA[2] = 0x0;
2208 pDevice->abyBBVGA[3] = 0x0;
2209 pDevice->ldBmThreshold[0] = -60;
2210 pDevice->ldBmThreshold[1] = -50;
2211 pDevice->ldBmThreshold[2] = 0;
2212 pDevice->ldBmThreshold[3] = 0;
2213 } else if (byRFType == RF_UW2452) {
2214 for (ii = 0; ii < CB_VT3253B0_INIT_FOR_UW2451; ii++) {
2215 bResult &= BBbWriteEmbeded(dwIoBase,byVT3253B0_UW2451[ii][0],byVT3253B0_UW2451[ii][1]);
2217 // Init ANT B select,TX Config CR09 = 0x61->0x45, 0x45->0x41(VC1/VC2 define, make the ANT_A, ANT_B inverted)
2218 //bResult &= BBbWriteEmbeded(dwIoBase,0x09,0x41);
2219 // Init ANT B select,RX Config CR10 = 0x28->0x2A, 0x2A->0x28(VC1/VC2 define, make the ANT_A, ANT_B inverted)
2220 //bResult &= BBbWriteEmbeded(dwIoBase,0x0a,0x28);
2221 // Select VC1/VC2, CR215 = 0x02->0x06
2222 bResult &= BBbWriteEmbeded(dwIoBase,0xd7,0x06);
2224 //{{RobertYu:20050125, request by Jack
2225 bResult &= BBbWriteEmbeded(dwIoBase,0x90,0x20);
2226 bResult &= BBbWriteEmbeded(dwIoBase,0x97,0xeb);
2229 //{{RobertYu:20050221, request by Jack
2230 bResult &= BBbWriteEmbeded(dwIoBase,0xa6,0x00);
2231 bResult &= BBbWriteEmbeded(dwIoBase,0xa8,0x30);
2233 bResult &= BBbWriteEmbeded(dwIoBase,0xb0,0x58);
2235 for (ii = 0; ii < CB_VT3253B0_AGC; ii++) {
2236 bResult &= BBbWriteEmbeded(dwIoBase,byVT3253B0_AGC[ii][0],byVT3253B0_AGC[ii][1]);
2238 //VNSvOutPortB(dwIoBase + MAC_REG_ITRTMSET, 0x23); // RobertYu: 20050104, 20050131 disable PA_Delay
2239 //MACvRegBitsOn(dwIoBase, MAC_REG_PAPEDELAY, BIT0); // RobertYu: 20050104, 20050131 disable PA_Delay
2241 pDevice->abyBBVGA[0] = 0x14;
2242 pDevice->abyBBVGA[1] = 0x0A;
2243 pDevice->abyBBVGA[2] = 0x0;
2244 pDevice->abyBBVGA[3] = 0x0;
2245 pDevice->ldBmThreshold[0] = -60;
2246 pDevice->ldBmThreshold[1] = -50;
2247 pDevice->ldBmThreshold[2] = 0;
2248 pDevice->ldBmThreshold[3] = 0;
2251 } else if (byRFType == RF_VT3226) {
2252 for (ii = 0; ii < CB_VT3253B0_INIT_FOR_AIROHA2230; ii++) {
2253 bResult &= BBbWriteEmbeded(dwIoBase,byVT3253B0_AIROHA2230[ii][0],byVT3253B0_AIROHA2230[ii][1]);
2255 for (ii = 0; ii < CB_VT3253B0_AGC; ii++) {
2256 bResult &= BBbWriteEmbeded(dwIoBase,byVT3253B0_AGC[ii][0],byVT3253B0_AGC[ii][1]);
2258 pDevice->abyBBVGA[0] = 0x1C;
2259 pDevice->abyBBVGA[1] = 0x10;
2260 pDevice->abyBBVGA[2] = 0x0;
2261 pDevice->abyBBVGA[3] = 0x0;
2262 pDevice->ldBmThreshold[0] = -70;
2263 pDevice->ldBmThreshold[1] = -48;
2264 pDevice->ldBmThreshold[2] = 0;
2265 pDevice->ldBmThreshold[3] = 0;
2266 // Fix VT3226 DFC system timing issue
2267 MACvSetRFLE_LatchBase(dwIoBase);
2268 //{{ RobertYu: 20050104
2269 } else if (byRFType == RF_AIROHA7230) {
2270 for (ii = 0; ii < CB_VT3253B0_INIT_FOR_AIROHA2230; ii++) {
2271 bResult &= BBbWriteEmbeded(dwIoBase,byVT3253B0_AIROHA2230[ii][0],byVT3253B0_AIROHA2230[ii][1]);
2274 //{{ RobertYu:20050223, request by JerryChung
2275 // Init ANT B select,TX Config CR09 = 0x61->0x45, 0x45->0x41(VC1/VC2 define, make the ANT_A, ANT_B inverted)
2276 //bResult &= BBbWriteEmbeded(dwIoBase,0x09,0x41);
2277 // Init ANT B select,RX Config CR10 = 0x28->0x2A, 0x2A->0x28(VC1/VC2 define, make the ANT_A, ANT_B inverted)
2278 //bResult &= BBbWriteEmbeded(dwIoBase,0x0a,0x28);
2279 // Select VC1/VC2, CR215 = 0x02->0x06
2280 bResult &= BBbWriteEmbeded(dwIoBase,0xd7,0x06);
2283 for (ii = 0; ii < CB_VT3253B0_AGC; ii++) {
2284 bResult &= BBbWriteEmbeded(dwIoBase,byVT3253B0_AGC[ii][0],byVT3253B0_AGC[ii][1]);
2286 pDevice->abyBBVGA[0] = 0x1C;
2287 pDevice->abyBBVGA[1] = 0x10;
2288 pDevice->abyBBVGA[2] = 0x0;
2289 pDevice->abyBBVGA[3] = 0x0;
2290 pDevice->ldBmThreshold[0] = -70;
2291 pDevice->ldBmThreshold[1] = -48;
2292 pDevice->ldBmThreshold[2] = 0;
2293 pDevice->ldBmThreshold[3] = 0;
2297 pDevice->bUpdateBBVGA = false;
2298 pDevice->abyBBVGA[0] = 0x1C;
2301 if (byLocalID > REV_ID_VT3253_A1) {
2302 BBbWriteEmbeded(dwIoBase, 0x04, 0x7F);
2303 BBbWriteEmbeded(dwIoBase, 0x0D, 0x01);
2312 * Description: Read All Baseband Registers
2316 * dwIoBase - I/O base address
2317 * pbyBBRegs - Point to struct that stores Baseband Registers
2321 * Return Value: none
2324 void BBvReadAllRegs (unsigned long dwIoBase, unsigned char *pbyBBRegs)
2327 unsigned char byBase = 1;
2328 for (ii = 0; ii < BB_MAX_CONTEXT_SIZE; ii++) {
2329 BBbReadEmbeded(dwIoBase, (unsigned char)(ii*byBase), pbyBBRegs);
2330 pbyBBRegs += byBase;
2335 * Description: Turn on BaseBand Loopback mode
2339 * dwIoBase - I/O base address
2340 * bCCK - If CCK is set
2344 * Return Value: none
2349 void BBvLoopbackOn (PSDevice pDevice)
2351 unsigned char byData;
2352 unsigned long dwIoBase = pDevice->PortOffset;
2355 BBbReadEmbeded(dwIoBase, 0xC9, &pDevice->byBBCRc9);//CR201
2356 BBbWriteEmbeded(dwIoBase, 0xC9, 0);
2357 BBbReadEmbeded(dwIoBase, 0x4D, &pDevice->byBBCR4d);//CR77
2358 BBbWriteEmbeded(dwIoBase, 0x4D, 0x90);
2360 //CR 88 = 0x02(CCK), 0x03(OFDM)
2361 BBbReadEmbeded(dwIoBase, 0x88, &pDevice->byBBCR88);//CR136
2363 if (pDevice->uConnectionRate <= RATE_11M) { //CCK
2364 // Enable internal digital loopback: CR33 |= 0000 0001
2365 BBbReadEmbeded(dwIoBase, 0x21, &byData);//CR33
2366 BBbWriteEmbeded(dwIoBase, 0x21, (unsigned char)(byData | 0x01));//CR33
2368 BBbWriteEmbeded(dwIoBase, 0x9A, 0); //CR154
2370 BBbWriteEmbeded(dwIoBase, 0x88, 0x02);//CR239
2373 // Enable internal digital loopback:CR154 |= 0000 0001
2374 BBbReadEmbeded(dwIoBase, 0x9A, &byData);//CR154
2375 BBbWriteEmbeded(dwIoBase, 0x9A, (unsigned char)(byData | 0x01));//CR154
2377 BBbWriteEmbeded(dwIoBase, 0x21, 0); //CR33
2379 BBbWriteEmbeded(dwIoBase, 0x88, 0x03);//CR239
2383 BBbWriteEmbeded(dwIoBase, 0x0E, 0);//CR14
2386 BBbReadEmbeded(pDevice->PortOffset, 0x09, &pDevice->byBBCR09);
2387 BBbWriteEmbeded(pDevice->PortOffset, 0x09, (unsigned char)(pDevice->byBBCR09 & 0xDE));
2391 * Description: Turn off BaseBand Loopback mode
2395 * pDevice - Device Structure
2400 * Return Value: none
2403 void BBvLoopbackOff (PSDevice pDevice)
2405 unsigned char byData;
2406 unsigned long dwIoBase = pDevice->PortOffset;
2408 BBbWriteEmbeded(dwIoBase, 0xC9, pDevice->byBBCRc9);//CR201
2409 BBbWriteEmbeded(dwIoBase, 0x88, pDevice->byBBCR88);//CR136
2410 BBbWriteEmbeded(dwIoBase, 0x09, pDevice->byBBCR09);//CR136
2411 BBbWriteEmbeded(dwIoBase, 0x4D, pDevice->byBBCR4d);//CR77
2413 if (pDevice->uConnectionRate <= RATE_11M) { // CCK
2414 // Set the CR33 Bit2 to disable internal Loopback.
2415 BBbReadEmbeded(dwIoBase, 0x21, &byData);//CR33
2416 BBbWriteEmbeded(dwIoBase, 0x21, (unsigned char)(byData & 0xFE));//CR33
2419 BBbReadEmbeded(dwIoBase, 0x9A, &byData);//CR154
2420 BBbWriteEmbeded(dwIoBase, 0x9A, (unsigned char)(byData & 0xFE));//CR154
2422 BBbReadEmbeded(dwIoBase, 0x0E, &byData);//CR14
2423 BBbWriteEmbeded(dwIoBase, 0x0E, (unsigned char)(byData | 0x80));//CR14
2430 * Description: Set ShortSlotTime mode
2434 * pDevice - Device Structure
2438 * Return Value: none
2442 BBvSetShortSlotTime (PSDevice pDevice)
2444 unsigned char byBBRxConf=0;
2445 unsigned char byBBVGA=0;
2447 BBbReadEmbeded(pDevice->PortOffset, 0x0A, &byBBRxConf);//CR10
2449 if (pDevice->bShortSlotTime) {
2450 byBBRxConf &= 0xDF;//1101 1111
2452 byBBRxConf |= 0x20;//0010 0000
2455 // patch for 3253B0 Baseband with Cardbus module
2456 BBbReadEmbeded(pDevice->PortOffset, 0xE7, &byBBVGA);
2457 if (byBBVGA == pDevice->abyBBVGA[0]) {
2458 byBBRxConf |= 0x20;//0010 0000
2461 BBbWriteEmbeded(pDevice->PortOffset, 0x0A, byBBRxConf);//CR10
2465 void BBvSetVGAGainOffset(PSDevice pDevice, unsigned char byData)
2467 unsigned char byBBRxConf=0;
2469 BBbWriteEmbeded(pDevice->PortOffset, 0xE7, byData);
2471 BBbReadEmbeded(pDevice->PortOffset, 0x0A, &byBBRxConf);//CR10
2472 // patch for 3253B0 Baseband with Cardbus module
2473 if (byData == pDevice->abyBBVGA[0]) {
2474 byBBRxConf |= 0x20;//0010 0000
2475 } else if (pDevice->bShortSlotTime) {
2476 byBBRxConf &= 0xDF;//1101 1111
2478 byBBRxConf |= 0x20;//0010 0000
2480 pDevice->byBBVGACurrent = byData;
2481 BBbWriteEmbeded(pDevice->PortOffset, 0x0A, byBBRxConf);//CR10
2486 * Description: Baseband SoftwareReset
2490 * dwIoBase - I/O base address
2494 * Return Value: none
2498 BBvSoftwareReset (unsigned long dwIoBase)
2500 BBbWriteEmbeded(dwIoBase, 0x50, 0x40);
2501 BBbWriteEmbeded(dwIoBase, 0x50, 0);
2502 BBbWriteEmbeded(dwIoBase, 0x9C, 0x01);
2503 BBbWriteEmbeded(dwIoBase, 0x9C, 0);
2507 * Description: Baseband Power Save Mode ON
2511 * dwIoBase - I/O base address
2515 * Return Value: none
2519 BBvPowerSaveModeON (unsigned long dwIoBase)
2521 unsigned char byOrgData;
2523 BBbReadEmbeded(dwIoBase, 0x0D, &byOrgData);
2525 BBbWriteEmbeded(dwIoBase, 0x0D, byOrgData);
2529 * Description: Baseband Power Save Mode OFF
2533 * dwIoBase - I/O base address
2537 * Return Value: none
2541 BBvPowerSaveModeOFF (unsigned long dwIoBase)
2543 unsigned char byOrgData;
2545 BBbReadEmbeded(dwIoBase, 0x0D, &byOrgData);
2546 byOrgData &= ~(BIT0);
2547 BBbWriteEmbeded(dwIoBase, 0x0D, byOrgData);
2551 * Description: Set Tx Antenna mode
2555 * pDevice - Device Structure
2556 * byAntennaMode - Antenna Mode
2560 * Return Value: none
2565 BBvSetTxAntennaMode (unsigned long dwIoBase, unsigned char byAntennaMode)
2567 unsigned char byBBTxConf;
2570 //printk("Enter BBvSetTxAntennaMode\n");
2572 BBbReadEmbeded(dwIoBase, 0x09, &byBBTxConf);//CR09
2573 if (byAntennaMode == ANT_DIVERSITY) {
2574 // bit 1 is diversity
2576 } else if (byAntennaMode == ANT_A) {
2578 byBBTxConf &= 0xF9; // 1111 1001
2579 } else if (byAntennaMode == ANT_B) {
2581 //printk("BBvSetTxAntennaMode:ANT_B\n");
2583 byBBTxConf &= 0xFD; // 1111 1101
2586 BBbWriteEmbeded(dwIoBase, 0x09, byBBTxConf);//CR09
2593 * Description: Set Rx Antenna mode
2597 * pDevice - Device Structure
2598 * byAntennaMode - Antenna Mode
2602 * Return Value: none
2607 BBvSetRxAntennaMode (unsigned long dwIoBase, unsigned char byAntennaMode)
2609 unsigned char byBBRxConf;
2611 BBbReadEmbeded(dwIoBase, 0x0A, &byBBRxConf);//CR10
2612 if (byAntennaMode == ANT_DIVERSITY) {
2615 } else if (byAntennaMode == ANT_A) {
2616 byBBRxConf &= 0xFC; // 1111 1100
2617 } else if (byAntennaMode == ANT_B) {
2618 byBBRxConf &= 0xFE; // 1111 1110
2621 BBbWriteEmbeded(dwIoBase, 0x0A, byBBRxConf);//CR10
2626 * Description: BBvSetDeepSleep
2630 * pDevice - Device Structure
2634 * Return Value: none
2638 BBvSetDeepSleep (unsigned long dwIoBase, unsigned char byLocalID)
2640 BBbWriteEmbeded(dwIoBase, 0x0C, 0x17);//CR12
2641 BBbWriteEmbeded(dwIoBase, 0x0D, 0xB9);//CR13
2645 BBvExitDeepSleep (unsigned long dwIoBase, unsigned char byLocalID)
2647 BBbWriteEmbeded(dwIoBase, 0x0C, 0x00);//CR12
2648 BBbWriteEmbeded(dwIoBase, 0x0D, 0x01);//CR13
2655 s_ulGetRatio (PSDevice pDevice)
2657 unsigned long ulRatio = 0;
2658 unsigned long ulMaxPacket;
2659 unsigned long ulPacketNum;
2661 //This is a thousand-ratio
2662 ulMaxPacket = pDevice->uNumSQ3[RATE_54M];
2663 if ( pDevice->uNumSQ3[RATE_54M] != 0 ) {
2664 ulPacketNum = pDevice->uNumSQ3[RATE_54M];
2665 ulRatio = (ulPacketNum * 1000 / pDevice->uDiversityCnt);
2666 //ulRatio = (pDevice->uNumSQ3[RATE_54M] * 1000 / pDevice->uDiversityCnt);
2667 ulRatio += TOP_RATE_54M;
2669 if ( pDevice->uNumSQ3[RATE_48M] > ulMaxPacket ) {
2670 ulPacketNum = pDevice->uNumSQ3[RATE_54M] + pDevice->uNumSQ3[RATE_48M];
2671 ulRatio = (ulPacketNum * 1000 / pDevice->uDiversityCnt);
2672 //ulRatio = (pDevice->uNumSQ3[RATE_48M] * 1000 / pDevice->uDiversityCnt);
2673 ulRatio += TOP_RATE_48M;
2674 ulMaxPacket = pDevice->uNumSQ3[RATE_48M];
2676 if ( pDevice->uNumSQ3[RATE_36M] > ulMaxPacket ) {
2677 ulPacketNum = pDevice->uNumSQ3[RATE_54M] + pDevice->uNumSQ3[RATE_48M] +
2678 pDevice->uNumSQ3[RATE_36M];
2679 ulRatio = (ulPacketNum * 1000 / pDevice->uDiversityCnt);
2680 //ulRatio = (pDevice->uNumSQ3[RATE_36M] * 1000 / pDevice->uDiversityCnt);
2681 ulRatio += TOP_RATE_36M;
2682 ulMaxPacket = pDevice->uNumSQ3[RATE_36M];
2684 if ( pDevice->uNumSQ3[RATE_24M] > ulMaxPacket ) {
2685 ulPacketNum = pDevice->uNumSQ3[RATE_54M] + pDevice->uNumSQ3[RATE_48M] +
2686 pDevice->uNumSQ3[RATE_36M] + pDevice->uNumSQ3[RATE_24M];
2687 ulRatio = (ulPacketNum * 1000 / pDevice->uDiversityCnt);
2688 //ulRatio = (pDevice->uNumSQ3[RATE_24M] * 1000 / pDevice->uDiversityCnt);
2689 ulRatio += TOP_RATE_24M;
2690 ulMaxPacket = pDevice->uNumSQ3[RATE_24M];
2692 if ( pDevice->uNumSQ3[RATE_18M] > ulMaxPacket ) {
2693 ulPacketNum = pDevice->uNumSQ3[RATE_54M] + pDevice->uNumSQ3[RATE_48M] +
2694 pDevice->uNumSQ3[RATE_36M] + pDevice->uNumSQ3[RATE_24M] +
2695 pDevice->uNumSQ3[RATE_18M];
2696 ulRatio = (ulPacketNum * 1000 / pDevice->uDiversityCnt);
2697 //ulRatio = (pDevice->uNumSQ3[RATE_18M] * 1000 / pDevice->uDiversityCnt);
2698 ulRatio += TOP_RATE_18M;
2699 ulMaxPacket = pDevice->uNumSQ3[RATE_18M];
2701 if ( pDevice->uNumSQ3[RATE_12M] > ulMaxPacket ) {
2702 ulPacketNum = pDevice->uNumSQ3[RATE_54M] + pDevice->uNumSQ3[RATE_48M] +
2703 pDevice->uNumSQ3[RATE_36M] + pDevice->uNumSQ3[RATE_24M] +
2704 pDevice->uNumSQ3[RATE_18M] + pDevice->uNumSQ3[RATE_12M];
2705 ulRatio = (ulPacketNum * 1000 / pDevice->uDiversityCnt);
2706 //ulRatio = (pDevice->uNumSQ3[RATE_12M] * 1000 / pDevice->uDiversityCnt);
2707 ulRatio += TOP_RATE_12M;
2708 ulMaxPacket = pDevice->uNumSQ3[RATE_12M];
2710 if ( pDevice->uNumSQ3[RATE_11M] > ulMaxPacket ) {
2711 ulPacketNum = pDevice->uDiversityCnt - pDevice->uNumSQ3[RATE_1M] -
2712 pDevice->uNumSQ3[RATE_2M] - pDevice->uNumSQ3[RATE_5M] -
2713 pDevice->uNumSQ3[RATE_6M] - pDevice->uNumSQ3[RATE_9M];
2714 ulRatio = (ulPacketNum * 1000 / pDevice->uDiversityCnt);
2715 //ulRatio = (pDevice->uNumSQ3[RATE_11M] * 1000 / pDevice->uDiversityCnt);
2716 ulRatio += TOP_RATE_11M;
2717 ulMaxPacket = pDevice->uNumSQ3[RATE_11M];
2719 if ( pDevice->uNumSQ3[RATE_9M] > ulMaxPacket ) {
2720 ulPacketNum = pDevice->uDiversityCnt - pDevice->uNumSQ3[RATE_1M] -
2721 pDevice->uNumSQ3[RATE_2M] - pDevice->uNumSQ3[RATE_5M] -
2722 pDevice->uNumSQ3[RATE_6M];
2723 ulRatio = (ulPacketNum * 1000 / pDevice->uDiversityCnt);
2724 //ulRatio = (pDevice->uNumSQ3[RATE_9M] * 1000 / pDevice->uDiversityCnt);
2725 ulRatio += TOP_RATE_9M;
2726 ulMaxPacket = pDevice->uNumSQ3[RATE_9M];
2728 if ( pDevice->uNumSQ3[RATE_6M] > ulMaxPacket ) {
2729 ulPacketNum = pDevice->uDiversityCnt - pDevice->uNumSQ3[RATE_1M] -
2730 pDevice->uNumSQ3[RATE_2M] - pDevice->uNumSQ3[RATE_5M];
2731 ulRatio = (ulPacketNum * 1000 / pDevice->uDiversityCnt);
2732 //ulRatio = (pDevice->uNumSQ3[RATE_6M] * 1000 / pDevice->uDiversityCnt);
2733 ulRatio += TOP_RATE_6M;
2734 ulMaxPacket = pDevice->uNumSQ3[RATE_6M];
2736 if ( pDevice->uNumSQ3[RATE_5M] > ulMaxPacket ) {
2737 ulPacketNum = pDevice->uDiversityCnt - pDevice->uNumSQ3[RATE_1M] -
2738 pDevice->uNumSQ3[RATE_2M];
2739 ulRatio = (ulPacketNum * 1000 / pDevice->uDiversityCnt);
2740 //ulRatio = (pDevice->uNumSQ3[RATE_5M] * 1000 / pDevice->uDiversityCnt);
2741 ulRatio += TOP_RATE_55M;
2742 ulMaxPacket = pDevice->uNumSQ3[RATE_5M];
2744 if ( pDevice->uNumSQ3[RATE_2M] > ulMaxPacket ) {
2745 ulPacketNum = pDevice->uDiversityCnt - pDevice->uNumSQ3[RATE_1M];
2746 ulRatio = (ulPacketNum * 1000 / pDevice->uDiversityCnt);
2747 //ulRatio = (pDevice->uNumSQ3[RATE_2M] * 1000 / pDevice->uDiversityCnt);
2748 ulRatio += TOP_RATE_2M;
2749 ulMaxPacket = pDevice->uNumSQ3[RATE_2M];
2751 if ( pDevice->uNumSQ3[RATE_1M] > ulMaxPacket ) {
2752 ulPacketNum = pDevice->uDiversityCnt;
2753 ulRatio = (ulPacketNum * 1000 / pDevice->uDiversityCnt);
2754 //ulRatio = (pDevice->uNumSQ3[RATE_1M] * 1000 / pDevice->uDiversityCnt);
2755 ulRatio += TOP_RATE_1M;
2763 BBvClearAntDivSQ3Value (PSDevice pDevice)
2767 pDevice->uDiversityCnt = 0;
2768 for (ii = 0; ii < MAX_RATE; ii++) {
2769 pDevice->uNumSQ3[ii] = 0;
2775 * Description: Antenna Diversity
2779 * pDevice - Device Structure
2780 * byRSR - RSR from received packet
2781 * bySQ3 - SQ3 value from received packet
2785 * Return Value: none
2790 BBvAntennaDiversity (PSDevice pDevice, unsigned char byRxRate, unsigned char bySQ3)
2793 if ((byRxRate >= MAX_RATE) || (pDevice->wAntDiversityMaxRate >= MAX_RATE)) {
2796 pDevice->uDiversityCnt++;
2797 // DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO "pDevice->uDiversityCnt = %d\n", (int)pDevice->uDiversityCnt);
2799 pDevice->uNumSQ3[byRxRate]++;
2801 if (pDevice->byAntennaState == 0) {
2803 if (pDevice->uDiversityCnt > pDevice->ulDiversityNValue) {
2804 DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO"ulDiversityNValue=[%d],54M-[%d]\n",
2805 (int)pDevice->ulDiversityNValue, (int)pDevice->uNumSQ3[(int)pDevice->wAntDiversityMaxRate]);
2807 if (pDevice->uNumSQ3[pDevice->wAntDiversityMaxRate] < pDevice->uDiversityCnt/2) {
2809 pDevice->ulRatio_State0 = s_ulGetRatio(pDevice);
2810 DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO"SQ3_State0, rate = [%08x]\n", (int)pDevice->ulRatio_State0);
2812 if ( pDevice->byTMax == 0 )
2814 DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO"1.[%08x], uNumSQ3[%d]=%d, %d\n",
2815 (int)pDevice->ulRatio_State0, (int)pDevice->wAntDiversityMaxRate,
2816 (int)pDevice->uNumSQ3[(int)pDevice->wAntDiversityMaxRate], (int)pDevice->uDiversityCnt);
2818 //printk("BBvAntennaDiversity1:call s_vChangeAntenna\n");
2820 s_vChangeAntenna(pDevice);
2821 pDevice->byAntennaState = 1;
2822 del_timer(&pDevice->TimerSQ3Tmax3);
2823 del_timer(&pDevice->TimerSQ3Tmax2);
2824 pDevice->TimerSQ3Tmax1.expires = RUN_AT(pDevice->byTMax * HZ);
2825 add_timer(&pDevice->TimerSQ3Tmax1);
2829 pDevice->TimerSQ3Tmax3.expires = RUN_AT(pDevice->byTMax3 * HZ);
2830 add_timer(&pDevice->TimerSQ3Tmax3);
2832 BBvClearAntDivSQ3Value(pDevice);
2835 } else { //byAntennaState == 1
2837 if (pDevice->uDiversityCnt > pDevice->ulDiversityMValue) {
2839 del_timer(&pDevice->TimerSQ3Tmax1);
2841 pDevice->ulRatio_State1 = s_ulGetRatio(pDevice);
2842 DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO"RX:SQ3_State1, rate0 = %08x,rate1 = %08x\n",
2843 (int)pDevice->ulRatio_State0,(int)pDevice->ulRatio_State1);
2845 if (pDevice->ulRatio_State1 < pDevice->ulRatio_State0) {
2846 DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO"2.[%08x][%08x], uNumSQ3[%d]=%d, %d\n",
2847 (int)pDevice->ulRatio_State0, (int)pDevice->ulRatio_State1,
2848 (int)pDevice->wAntDiversityMaxRate,
2849 (int)pDevice->uNumSQ3[(int)pDevice->wAntDiversityMaxRate], (int)pDevice->uDiversityCnt);
2851 //printk("BBvAntennaDiversity2:call s_vChangeAntenna\n");
2853 s_vChangeAntenna(pDevice);
2854 pDevice->TimerSQ3Tmax3.expires = RUN_AT(pDevice->byTMax3 * HZ);
2855 pDevice->TimerSQ3Tmax2.expires = RUN_AT(pDevice->byTMax2 * HZ);
2856 add_timer(&pDevice->TimerSQ3Tmax3);
2857 add_timer(&pDevice->TimerSQ3Tmax2);
2859 pDevice->byAntennaState = 0;
2860 BBvClearAntDivSQ3Value(pDevice);
2868 * Timer for SQ3 antenna diversity
2875 * Return Value: none
2881 void *hDeviceContext
2884 PSDevice pDevice = (PSDevice)hDeviceContext;
2886 DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO"TimerSQ3CallBack...");
2887 spin_lock_irq(&pDevice->lock);
2889 DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO"3.[%08x][%08x], %d\n",(int)pDevice->ulRatio_State0, (int)pDevice->ulRatio_State1, (int)pDevice->uDiversityCnt);
2891 //printk("TimerSQ3CallBack1:call s_vChangeAntenna\n");
2894 s_vChangeAntenna(pDevice);
2895 pDevice->byAntennaState = 0;
2896 BBvClearAntDivSQ3Value(pDevice);
2898 pDevice->TimerSQ3Tmax3.expires = RUN_AT(pDevice->byTMax3 * HZ);
2899 pDevice->TimerSQ3Tmax2.expires = RUN_AT(pDevice->byTMax2 * HZ);
2900 add_timer(&pDevice->TimerSQ3Tmax3);
2901 add_timer(&pDevice->TimerSQ3Tmax2);
2904 spin_unlock_irq(&pDevice->lock);
2912 * Timer for SQ3 antenna diversity
2917 * hDeviceContext - Pointer to the adapter
2923 * Return Value: none
2928 TimerState1CallBack (
2929 void *hDeviceContext
2932 PSDevice pDevice = (PSDevice)hDeviceContext;
2934 DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO"TimerState1CallBack...");
2936 spin_lock_irq(&pDevice->lock);
2937 if (pDevice->uDiversityCnt < pDevice->ulDiversityMValue/100) {
2939 //printk("TimerSQ3CallBack2:call s_vChangeAntenna\n");
2942 s_vChangeAntenna(pDevice);
2943 pDevice->TimerSQ3Tmax3.expires = RUN_AT(pDevice->byTMax3 * HZ);
2944 pDevice->TimerSQ3Tmax2.expires = RUN_AT(pDevice->byTMax2 * HZ);
2945 add_timer(&pDevice->TimerSQ3Tmax3);
2946 add_timer(&pDevice->TimerSQ3Tmax2);
2948 pDevice->ulRatio_State1 = s_ulGetRatio(pDevice);
2949 DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO"SQ3_State1, rate0 = %08x,rate1 = %08x\n",
2950 (int)pDevice->ulRatio_State0,(int)pDevice->ulRatio_State1);
2952 if ( pDevice->ulRatio_State1 < pDevice->ulRatio_State0 ) {
2953 DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO"2.[%08x][%08x], uNumSQ3[%d]=%d, %d\n",
2954 (int)pDevice->ulRatio_State0, (int)pDevice->ulRatio_State1,
2955 (int)pDevice->wAntDiversityMaxRate,
2956 (int)pDevice->uNumSQ3[(int)pDevice->wAntDiversityMaxRate], (int)pDevice->uDiversityCnt);
2958 //printk("TimerSQ3CallBack3:call s_vChangeAntenna\n");
2961 s_vChangeAntenna(pDevice);
2963 pDevice->TimerSQ3Tmax3.expires = RUN_AT(pDevice->byTMax3 * HZ);
2964 pDevice->TimerSQ3Tmax2.expires = RUN_AT(pDevice->byTMax2 * HZ);
2965 add_timer(&pDevice->TimerSQ3Tmax3);
2966 add_timer(&pDevice->TimerSQ3Tmax2);
2969 pDevice->byAntennaState = 0;
2970 BBvClearAntDivSQ3Value(pDevice);
2971 spin_unlock_irq(&pDevice->lock);