2 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
22 * Purpose: Implement functions to access baseband
29 * BBuGetFrameTime - Calculate data frame transmitting time
30 * BBvCaculateParameter - Caculate PhyLength, PhyService and Phy Signal parameter for baseband Tx
31 * BBbReadEmbedded - Embedded read baseband register via MAC
32 * BBbWriteEmbedded - Embedded write baseband register via MAC
33 * BBbIsRegBitsOn - Test if baseband register bits on
34 * BBbIsRegBitsOff - Test if baseband register bits off
35 * BBbVT3253Init - VIA VT3253 baseband chip init code
36 * BBvReadAllRegs - Read All Baseband Registers
37 * BBvLoopbackOn - Turn on BaseBand Loopback mode
38 * BBvLoopbackOff - Turn off BaseBand Loopback mode
41 * 06-10-2003 Bryan YC Fan: Re-write codes to support VT3253 spec.
42 * 08-07-2003 Bryan YC Fan: Add MAXIM2827/2825 and RFMD2959 support.
43 * 08-26-2003 Kyle Hsu : Modify BBuGetFrameTime() and BBvCalculateParameter().
44 * cancel the setting of MAC_REG_SOFTPWRCTL on BBbVT3253Init().
46 * 09-01-2003 Bryan YC Fan: RF & BB tables updated.
47 * Modified BBvLoopbackOn & BBvLoopbackOff().
59 /*--------------------- Static Classes ----------------------------*/
61 /*--------------------- Static Variables --------------------------*/
63 /*--------------------- Static Functions --------------------------*/
65 /*--------------------- Export Variables --------------------------*/
67 /*--------------------- Static Definitions -------------------------*/
69 /*--------------------- Static Classes ----------------------------*/
71 /*--------------------- Static Variables --------------------------*/
73 #define CB_VT3253_INIT_FOR_RFMD 446
74 static unsigned char byVT3253InitTab_RFMD[CB_VT3253_INIT_FOR_RFMD][2] = {
523 #define CB_VT3253B0_INIT_FOR_RFMD 256
524 static unsigned char byVT3253B0_RFMD[CB_VT3253B0_INIT_FOR_RFMD][2] = {
783 #define CB_VT3253B0_AGC_FOR_RFMD2959 195
785 static unsigned char byVT3253B0_AGC4_RFMD2959[CB_VT3253B0_AGC_FOR_RFMD2959][2] = {
983 #define CB_VT3253B0_INIT_FOR_AIROHA2230 256
985 static unsigned char byVT3253B0_AIROHA2230[CB_VT3253B0_INIT_FOR_AIROHA2230][2] = {
1094 {0x6c, 0x00}, /* RobertYu:20050125, request by JJSue */
1244 #define CB_VT3253B0_INIT_FOR_UW2451 256
1246 static unsigned char byVT3253B0_UW2451[CB_VT3253B0_INIT_FOR_UW2451][2] = {
1355 {0x6c, 0x00}, /* RobertYu:20050125, request by JJSue */
1505 #define CB_VT3253B0_AGC 193
1507 static unsigned char byVT3253B0_AGC[CB_VT3253B0_AGC][2] = {
1703 static const unsigned short awcFrameTime[MAX_RATE] =
1704 {10, 20, 55, 110, 24, 36, 48, 72, 96, 144, 192, 216};
1706 /*--------------------- Static Functions --------------------------*/
1710 s_ulGetRatio(struct vnt_private *pDevice);
1715 struct vnt_private *pDevice
1721 struct vnt_private *pDevice
1724 if (pDevice->dwRxAntennaSel == 0) {
1725 pDevice->dwRxAntennaSel = 1;
1726 if (pDevice->bTxRxAntInv == true)
1727 BBvSetRxAntennaMode(pDevice->PortOffset, ANT_A);
1729 BBvSetRxAntennaMode(pDevice->PortOffset, ANT_B);
1731 pDevice->dwRxAntennaSel = 0;
1732 if (pDevice->bTxRxAntInv == true)
1733 BBvSetRxAntennaMode(pDevice->PortOffset, ANT_B);
1735 BBvSetRxAntennaMode(pDevice->PortOffset, ANT_A);
1737 if (pDevice->dwTxAntennaSel == 0) {
1738 pDevice->dwTxAntennaSel = 1;
1739 BBvSetTxAntennaMode(pDevice->PortOffset, ANT_B);
1741 pDevice->dwTxAntennaSel = 0;
1742 BBvSetTxAntennaMode(pDevice->PortOffset, ANT_A);
1746 /*--------------------- Export Variables --------------------------*/
1748 * Description: Calculate data frame transmitting time
1752 * byPreambleType - Preamble Type
1753 * byPktType - PK_TYPE_11A, PK_TYPE_11B, PK_TYPE_11GB, PK_TYPE_11GA
1754 * cbFrameLength - Baseband Type
1758 * Return Value: FrameTime
1763 unsigned char byPreambleType,
1764 unsigned char byPktType,
1765 unsigned int cbFrameLength,
1766 unsigned short wRate
1769 unsigned int uFrameTime;
1770 unsigned int uPreamble;
1772 unsigned int uRateIdx = (unsigned int) wRate;
1773 unsigned int uRate = 0;
1775 if (uRateIdx > RATE_54M) {
1780 uRate = (unsigned int)awcFrameTime[uRateIdx];
1782 if (uRateIdx <= 3) { /* CCK mode */
1783 if (byPreambleType == 1) /* Short */
1788 uFrameTime = (cbFrameLength * 80) / uRate; /* ????? */
1789 uTmp = (uFrameTime * uRate) / 80;
1790 if (cbFrameLength != uTmp)
1793 return uPreamble + uFrameTime;
1795 uFrameTime = (cbFrameLength * 8 + 22) / uRate; /* ???????? */
1796 uTmp = ((uFrameTime * uRate) - 22) / 8;
1797 if (cbFrameLength != uTmp)
1800 uFrameTime = uFrameTime * 4; /* ??????? */
1801 if (byPktType != PK_TYPE_11A)
1802 uFrameTime += 6; /* ?????? */
1804 return 20 + uFrameTime; /* ?????? */
1809 * Description: Calculate Length, Service, and Signal fields of Phy for Tx
1813 * pDevice - Device Structure
1814 * cbFrameLength - Tx Frame Length
1817 * pwPhyLen - pointer to Phy Length field
1818 * pbyPhySrv - pointer to Phy Service field
1819 * pbyPhySgn - pointer to Phy Signal field
1821 * Return Value: none
1825 BBvCalculateParameter(
1826 struct vnt_private *pDevice,
1827 unsigned int cbFrameLength,
1828 unsigned short wRate,
1829 unsigned char byPacketType,
1830 unsigned short *pwPhyLen,
1831 unsigned char *pbyPhySrv,
1832 unsigned char *pbyPhySgn
1835 unsigned int cbBitCount;
1836 unsigned int cbUsCount = 0;
1839 unsigned char byPreambleType = pDevice->byPreambleType;
1840 bool bCCK = pDevice->bCCK;
1842 cbBitCount = cbFrameLength * 8;
1847 cbUsCount = cbBitCount;
1852 cbUsCount = cbBitCount / 2;
1853 if (byPreambleType == 1)
1855 else /* long preamble */
1862 cbUsCount = (cbBitCount * 10) / 55;
1863 cbTmp = (cbUsCount * 55) / 10;
1864 if (cbTmp != cbBitCount)
1866 if (byPreambleType == 1)
1868 else /* long preamble */
1876 cbUsCount = cbBitCount / 11;
1877 cbTmp = cbUsCount * 11;
1878 if (cbTmp != cbBitCount) {
1880 if ((cbBitCount - cbTmp) <= 3)
1883 if (byPreambleType == 1)
1885 else /* long preamble */
1890 if (byPacketType == PK_TYPE_11A) { /*11a, 5GHZ */
1891 *pbyPhySgn = 0x9B; /* 1001 1011 */
1892 } else {/* 11g, 2.4GHZ */
1893 *pbyPhySgn = 0x8B; /* 1000 1011 */
1898 if (byPacketType == PK_TYPE_11A) {/* 11a, 5GHZ */
1899 *pbyPhySgn = 0x9F; /* 1001 1111 */
1900 } else {/* 11g, 2.4GHZ */
1901 *pbyPhySgn = 0x8F; /* 1000 1111 */
1906 if (byPacketType == PK_TYPE_11A) {/* 11a, 5GHZ */
1907 *pbyPhySgn = 0x9A; /* 1001 1010 */
1908 } else {/* 11g, 2.4GHZ */
1909 *pbyPhySgn = 0x8A; /* 1000 1010 */
1914 if (byPacketType == PK_TYPE_11A) {/* 11a, 5GHZ */
1915 *pbyPhySgn = 0x9E; /* 1001 1110 */
1916 } else {/* 11g, 2.4GHZ */
1917 *pbyPhySgn = 0x8E; /* 1000 1110 */
1922 if (byPacketType == PK_TYPE_11A) {/* 11a, 5GHZ */
1923 *pbyPhySgn = 0x99; /* 1001 1001 */
1924 } else {/* 11g, 2.4GHZ */
1925 *pbyPhySgn = 0x89; /* 1000 1001 */
1930 if (byPacketType == PK_TYPE_11A) {/* 11a, 5GHZ */
1931 *pbyPhySgn = 0x9D; /* 1001 1101 */
1932 } else {/* 11g, 2.4GHZ */
1933 *pbyPhySgn = 0x8D; /* 1000 1101 */
1938 if (byPacketType == PK_TYPE_11A) {/* 11a, 5GHZ */
1939 *pbyPhySgn = 0x98; /* 1001 1000 */
1940 } else {/* 11g, 2.4GHZ */
1941 *pbyPhySgn = 0x88; /* 1000 1000 */
1946 if (byPacketType == PK_TYPE_11A) {/* 11a, 5GHZ */
1947 *pbyPhySgn = 0x9C; /* 1001 1100 */
1948 } else {/* 11g, 2.4GHZ */
1949 *pbyPhySgn = 0x8C; /* 1000 1100 */
1954 if (byPacketType == PK_TYPE_11A) {/* 11a, 5GHZ */
1955 *pbyPhySgn = 0x9C; /* 1001 1100 */
1956 } else {/* 11g, 2.4GHZ */
1957 *pbyPhySgn = 0x8C; /* 1000 1100 */
1962 if (byPacketType == PK_TYPE_11B) {
1965 *pbyPhySrv = *pbyPhySrv | 0x80;
1966 *pwPhyLen = (unsigned short)cbUsCount;
1969 *pwPhyLen = (unsigned short)cbFrameLength;
1974 * Description: Read a byte from BASEBAND, by embedded programming
1978 * dwIoBase - I/O base address
1979 * byBBAddr - address of register in Baseband
1981 * pbyData - data read
1983 * Return Value: true if succeeded; false if failed.
1986 bool BBbReadEmbedded(void __iomem *dwIoBase, unsigned char byBBAddr, unsigned char *pbyData)
1989 unsigned char byValue;
1992 VNSvOutPortB(dwIoBase + MAC_REG_BBREGADR, byBBAddr);
1995 MACvRegBitsOn(dwIoBase, MAC_REG_BBREGCTL, BBREGCTL_REGR);
1996 /* W_MAX_TIMEOUT is the timeout period */
1997 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
1998 VNSvInPortB(dwIoBase + MAC_REG_BBREGCTL, &byValue);
1999 if (byValue & BBREGCTL_DONE)
2004 VNSvInPortB(dwIoBase + MAC_REG_BBREGDATA, pbyData);
2006 if (ww == W_MAX_TIMEOUT) {
2008 pr_debug(" DBG_PORT80(0x30)\n");
2015 * Description: Write a Byte to BASEBAND, by embedded programming
2019 * dwIoBase - I/O base address
2020 * byBBAddr - address of register in Baseband
2021 * byData - data to write
2025 * Return Value: true if succeeded; false if failed.
2028 bool BBbWriteEmbedded(void __iomem *dwIoBase, unsigned char byBBAddr, unsigned char byData)
2031 unsigned char byValue;
2034 VNSvOutPortB(dwIoBase + MAC_REG_BBREGADR, byBBAddr);
2036 VNSvOutPortB(dwIoBase + MAC_REG_BBREGDATA, byData);
2038 /* turn on BBREGCTL_REGW */
2039 MACvRegBitsOn(dwIoBase, MAC_REG_BBREGCTL, BBREGCTL_REGW);
2040 /* W_MAX_TIMEOUT is the timeout period */
2041 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
2042 VNSvInPortB(dwIoBase + MAC_REG_BBREGCTL, &byValue);
2043 if (byValue & BBREGCTL_DONE)
2047 if (ww == W_MAX_TIMEOUT) {
2049 pr_debug(" DBG_PORT80(0x31)\n");
2056 * Description: Test if all bits are set for the Baseband register
2060 * dwIoBase - I/O base address
2061 * byBBAddr - address of register in Baseband
2062 * byTestBits - TestBits
2066 * Return Value: true if all TestBits are set; false otherwise.
2069 bool BBbIsRegBitsOn(void __iomem *dwIoBase, unsigned char byBBAddr, unsigned char byTestBits)
2071 unsigned char byOrgData;
2073 BBbReadEmbedded(dwIoBase, byBBAddr, &byOrgData);
2074 return (byOrgData & byTestBits) == byTestBits;
2078 * Description: Test if all bits are clear for the Baseband register
2082 * dwIoBase - I/O base address
2083 * byBBAddr - address of register in Baseband
2084 * byTestBits - TestBits
2088 * Return Value: true if all TestBits are clear; false otherwise.
2091 bool BBbIsRegBitsOff(void __iomem *dwIoBase, unsigned char byBBAddr, unsigned char byTestBits)
2093 unsigned char byOrgData;
2095 BBbReadEmbedded(dwIoBase, byBBAddr, &byOrgData);
2096 return (byOrgData & byTestBits) == 0;
2100 * Description: VIA VT3253 Baseband chip init function
2104 * dwIoBase - I/O base address
2105 * byRevId - Revision ID
2106 * byRFType - RF type
2110 * Return Value: true if succeeded; false if failed.
2114 bool BBbVT3253Init(struct vnt_private *pDevice)
2116 bool bResult = true;
2118 void __iomem *dwIoBase = pDevice->PortOffset;
2119 unsigned char byRFType = pDevice->byRFType;
2120 unsigned char byLocalID = pDevice->byLocalID;
2122 if (byRFType == RF_RFMD2959) {
2123 if (byLocalID <= REV_ID_VT3253_A1) {
2124 for (ii = 0; ii < CB_VT3253_INIT_FOR_RFMD; ii++)
2125 bResult &= BBbWriteEmbedded(dwIoBase, byVT3253InitTab_RFMD[ii][0], byVT3253InitTab_RFMD[ii][1]);
2128 for (ii = 0; ii < CB_VT3253B0_INIT_FOR_RFMD; ii++)
2129 bResult &= BBbWriteEmbedded(dwIoBase, byVT3253B0_RFMD[ii][0], byVT3253B0_RFMD[ii][1]);
2131 for (ii = 0; ii < CB_VT3253B0_AGC_FOR_RFMD2959; ii++)
2132 bResult &= BBbWriteEmbedded(dwIoBase, byVT3253B0_AGC4_RFMD2959[ii][0], byVT3253B0_AGC4_RFMD2959[ii][1]);
2134 VNSvOutPortD(dwIoBase + MAC_REG_ITRTMSET, 0x23);
2135 MACvRegBitsOn(dwIoBase, MAC_REG_PAPEDELAY, BIT0);
2137 pDevice->abyBBVGA[0] = 0x18;
2138 pDevice->abyBBVGA[1] = 0x0A;
2139 pDevice->abyBBVGA[2] = 0x0;
2140 pDevice->abyBBVGA[3] = 0x0;
2141 pDevice->ldBmThreshold[0] = -70;
2142 pDevice->ldBmThreshold[1] = -50;
2143 pDevice->ldBmThreshold[2] = 0;
2144 pDevice->ldBmThreshold[3] = 0;
2145 } else if ((byRFType == RF_AIROHA) || (byRFType == RF_AL2230S)) {
2146 for (ii = 0; ii < CB_VT3253B0_INIT_FOR_AIROHA2230; ii++)
2147 bResult &= BBbWriteEmbedded(dwIoBase, byVT3253B0_AIROHA2230[ii][0], byVT3253B0_AIROHA2230[ii][1]);
2149 for (ii = 0; ii < CB_VT3253B0_AGC; ii++)
2150 bResult &= BBbWriteEmbedded(dwIoBase, byVT3253B0_AGC[ii][0], byVT3253B0_AGC[ii][1]);
2152 pDevice->abyBBVGA[0] = 0x1C;
2153 pDevice->abyBBVGA[1] = 0x10;
2154 pDevice->abyBBVGA[2] = 0x0;
2155 pDevice->abyBBVGA[3] = 0x0;
2156 pDevice->ldBmThreshold[0] = -70;
2157 pDevice->ldBmThreshold[1] = -48;
2158 pDevice->ldBmThreshold[2] = 0;
2159 pDevice->ldBmThreshold[3] = 0;
2160 } else if (byRFType == RF_UW2451) {
2161 for (ii = 0; ii < CB_VT3253B0_INIT_FOR_UW2451; ii++)
2162 bResult &= BBbWriteEmbedded(dwIoBase, byVT3253B0_UW2451[ii][0], byVT3253B0_UW2451[ii][1]);
2164 for (ii = 0; ii < CB_VT3253B0_AGC; ii++)
2165 bResult &= BBbWriteEmbedded(dwIoBase, byVT3253B0_AGC[ii][0], byVT3253B0_AGC[ii][1]);
2167 VNSvOutPortB(dwIoBase + MAC_REG_ITRTMSET, 0x23);
2168 MACvRegBitsOn(dwIoBase, MAC_REG_PAPEDELAY, BIT0);
2170 pDevice->abyBBVGA[0] = 0x14;
2171 pDevice->abyBBVGA[1] = 0x0A;
2172 pDevice->abyBBVGA[2] = 0x0;
2173 pDevice->abyBBVGA[3] = 0x0;
2174 pDevice->ldBmThreshold[0] = -60;
2175 pDevice->ldBmThreshold[1] = -50;
2176 pDevice->ldBmThreshold[2] = 0;
2177 pDevice->ldBmThreshold[3] = 0;
2178 } else if (byRFType == RF_UW2452) {
2179 for (ii = 0; ii < CB_VT3253B0_INIT_FOR_UW2451; ii++)
2180 bResult &= BBbWriteEmbedded(dwIoBase, byVT3253B0_UW2451[ii][0], byVT3253B0_UW2451[ii][1]);
2182 /* Init ANT B select,TX Config CR09 = 0x61->0x45, 0x45->0x41(VC1/VC2 define, make the ANT_A, ANT_B inverted) */
2183 /*bResult &= BBbWriteEmbedded(dwIoBase,0x09,0x41);*/
2184 /* Init ANT B select,RX Config CR10 = 0x28->0x2A, 0x2A->0x28(VC1/VC2 define, make the ANT_A, ANT_B inverted) */
2185 /*bResult &= BBbWriteEmbedded(dwIoBase,0x0a,0x28);*/
2186 /* Select VC1/VC2, CR215 = 0x02->0x06 */
2187 bResult &= BBbWriteEmbedded(dwIoBase, 0xd7, 0x06);
2189 /* {{RobertYu:20050125, request by Jack */
2190 bResult &= BBbWriteEmbedded(dwIoBase, 0x90, 0x20);
2191 bResult &= BBbWriteEmbedded(dwIoBase, 0x97, 0xeb);
2194 /* {{RobertYu:20050221, request by Jack */
2195 bResult &= BBbWriteEmbedded(dwIoBase, 0xa6, 0x00);
2196 bResult &= BBbWriteEmbedded(dwIoBase, 0xa8, 0x30);
2198 bResult &= BBbWriteEmbedded(dwIoBase, 0xb0, 0x58);
2200 for (ii = 0; ii < CB_VT3253B0_AGC; ii++)
2201 bResult &= BBbWriteEmbedded(dwIoBase, byVT3253B0_AGC[ii][0], byVT3253B0_AGC[ii][1]);
2203 pDevice->abyBBVGA[0] = 0x14;
2204 pDevice->abyBBVGA[1] = 0x0A;
2205 pDevice->abyBBVGA[2] = 0x0;
2206 pDevice->abyBBVGA[3] = 0x0;
2207 pDevice->ldBmThreshold[0] = -60;
2208 pDevice->ldBmThreshold[1] = -50;
2209 pDevice->ldBmThreshold[2] = 0;
2210 pDevice->ldBmThreshold[3] = 0;
2213 } else if (byRFType == RF_VT3226) {
2214 for (ii = 0; ii < CB_VT3253B0_INIT_FOR_AIROHA2230; ii++)
2215 bResult &= BBbWriteEmbedded(dwIoBase, byVT3253B0_AIROHA2230[ii][0], byVT3253B0_AIROHA2230[ii][1]);
2217 for (ii = 0; ii < CB_VT3253B0_AGC; ii++)
2218 bResult &= BBbWriteEmbedded(dwIoBase, byVT3253B0_AGC[ii][0], byVT3253B0_AGC[ii][1]);
2220 pDevice->abyBBVGA[0] = 0x1C;
2221 pDevice->abyBBVGA[1] = 0x10;
2222 pDevice->abyBBVGA[2] = 0x0;
2223 pDevice->abyBBVGA[3] = 0x0;
2224 pDevice->ldBmThreshold[0] = -70;
2225 pDevice->ldBmThreshold[1] = -48;
2226 pDevice->ldBmThreshold[2] = 0;
2227 pDevice->ldBmThreshold[3] = 0;
2228 /* Fix VT3226 DFC system timing issue */
2229 MACvSetRFLE_LatchBase(dwIoBase);
2230 /* {{ RobertYu: 20050104 */
2231 } else if (byRFType == RF_AIROHA7230) {
2232 for (ii = 0; ii < CB_VT3253B0_INIT_FOR_AIROHA2230; ii++)
2233 bResult &= BBbWriteEmbedded(dwIoBase, byVT3253B0_AIROHA2230[ii][0], byVT3253B0_AIROHA2230[ii][1]);
2236 /* {{ RobertYu:20050223, request by JerryChung */
2237 /* Init ANT B select,TX Config CR09 = 0x61->0x45, 0x45->0x41(VC1/VC2 define, make the ANT_A, ANT_B inverted) */
2238 /*bResult &= BBbWriteEmbedded(dwIoBase,0x09,0x41);*/
2239 /* Init ANT B select,RX Config CR10 = 0x28->0x2A, 0x2A->0x28(VC1/VC2 define, make the ANT_A, ANT_B inverted) */
2240 /*bResult &= BBbWriteEmbedded(dwIoBase,0x0a,0x28);*/
2241 /* Select VC1/VC2, CR215 = 0x02->0x06 */
2242 bResult &= BBbWriteEmbedded(dwIoBase, 0xd7, 0x06);
2245 for (ii = 0; ii < CB_VT3253B0_AGC; ii++)
2246 bResult &= BBbWriteEmbedded(dwIoBase, byVT3253B0_AGC[ii][0], byVT3253B0_AGC[ii][1]);
2248 pDevice->abyBBVGA[0] = 0x1C;
2249 pDevice->abyBBVGA[1] = 0x10;
2250 pDevice->abyBBVGA[2] = 0x0;
2251 pDevice->abyBBVGA[3] = 0x0;
2252 pDevice->ldBmThreshold[0] = -70;
2253 pDevice->ldBmThreshold[1] = -48;
2254 pDevice->ldBmThreshold[2] = 0;
2255 pDevice->ldBmThreshold[3] = 0;
2258 /* No VGA Table now */
2259 pDevice->bUpdateBBVGA = false;
2260 pDevice->abyBBVGA[0] = 0x1C;
2263 if (byLocalID > REV_ID_VT3253_A1) {
2264 BBbWriteEmbedded(dwIoBase, 0x04, 0x7F);
2265 BBbWriteEmbedded(dwIoBase, 0x0D, 0x01);
2272 * Description: Read All Baseband Registers
2276 * dwIoBase - I/O base address
2277 * pbyBBRegs - Point to struct that stores Baseband Registers
2281 * Return Value: none
2284 void BBvReadAllRegs(void __iomem *dwIoBase, unsigned char *pbyBBRegs)
2287 unsigned char byBase = 1;
2289 for (ii = 0; ii < BB_MAX_CONTEXT_SIZE; ii++) {
2290 BBbReadEmbedded(dwIoBase, (unsigned char)(ii*byBase), pbyBBRegs);
2291 pbyBBRegs += byBase;
2296 * Description: Turn on BaseBand Loopback mode
2300 * dwIoBase - I/O base address
2301 * bCCK - If CCK is set
2305 * Return Value: none
2309 void BBvLoopbackOn(struct vnt_private *pDevice)
2311 unsigned char byData;
2312 void __iomem *dwIoBase = pDevice->PortOffset;
2315 BBbReadEmbedded(dwIoBase, 0xC9, &pDevice->byBBCRc9); /* CR201 */
2316 BBbWriteEmbedded(dwIoBase, 0xC9, 0);
2317 BBbReadEmbedded(dwIoBase, 0x4D, &pDevice->byBBCR4d); /* CR77 */
2318 BBbWriteEmbedded(dwIoBase, 0x4D, 0x90);
2320 /* CR 88 = 0x02(CCK), 0x03(OFDM) */
2321 BBbReadEmbedded(dwIoBase, 0x88, &pDevice->byBBCR88); /* CR136 */
2323 if (pDevice->uConnectionRate <= RATE_11M) { /* CCK */
2324 /* Enable internal digital loopback: CR33 |= 0000 0001 */
2325 BBbReadEmbedded(dwIoBase, 0x21, &byData); /* CR33 */
2326 BBbWriteEmbedded(dwIoBase, 0x21, (unsigned char)(byData | 0x01)); /* CR33 */
2328 BBbWriteEmbedded(dwIoBase, 0x9A, 0); /* CR154 */
2330 BBbWriteEmbedded(dwIoBase, 0x88, 0x02); /* CR239 */
2332 /* Enable internal digital loopback:CR154 |= 0000 0001 */
2333 BBbReadEmbedded(dwIoBase, 0x9A, &byData); /* CR154 */
2334 BBbWriteEmbedded(dwIoBase, 0x9A, (unsigned char)(byData | 0x01)); /* CR154 */
2336 BBbWriteEmbedded(dwIoBase, 0x21, 0); /* CR33 */
2338 BBbWriteEmbedded(dwIoBase, 0x88, 0x03); /* CR239 */
2342 BBbWriteEmbedded(dwIoBase, 0x0E, 0); /* CR14 */
2344 /* Disable TX_IQUN */
2345 BBbReadEmbedded(pDevice->PortOffset, 0x09, &pDevice->byBBCR09);
2346 BBbWriteEmbedded(pDevice->PortOffset, 0x09, (unsigned char)(pDevice->byBBCR09 & 0xDE));
2350 * Description: Turn off BaseBand Loopback mode
2354 * pDevice - Device Structure
2359 * Return Value: none
2362 void BBvLoopbackOff(struct vnt_private *pDevice)
2364 unsigned char byData;
2365 void __iomem *dwIoBase = pDevice->PortOffset;
2367 BBbWriteEmbedded(dwIoBase, 0xC9, pDevice->byBBCRc9); /* CR201 */
2368 BBbWriteEmbedded(dwIoBase, 0x88, pDevice->byBBCR88); /* CR136 */
2369 BBbWriteEmbedded(dwIoBase, 0x09, pDevice->byBBCR09); /* CR136 */
2370 BBbWriteEmbedded(dwIoBase, 0x4D, pDevice->byBBCR4d); /* CR77 */
2372 if (pDevice->uConnectionRate <= RATE_11M) { /* CCK */
2373 /* Set the CR33 Bit2 to disable internal Loopback. */
2374 BBbReadEmbedded(dwIoBase, 0x21, &byData);/* CR33 */
2375 BBbWriteEmbedded(dwIoBase, 0x21, (unsigned char)(byData & 0xFE)); /* CR33 */
2377 BBbReadEmbedded(dwIoBase, 0x9A, &byData); /* CR154 */
2378 BBbWriteEmbedded(dwIoBase, 0x9A, (unsigned char)(byData & 0xFE)); /* CR154 */
2380 BBbReadEmbedded(dwIoBase, 0x0E, &byData); /* CR14 */
2381 BBbWriteEmbedded(dwIoBase, 0x0E, (unsigned char)(byData | 0x80)); /* CR14 */
2385 * Description: Set ShortSlotTime mode
2389 * pDevice - Device Structure
2393 * Return Value: none
2397 BBvSetShortSlotTime(struct vnt_private *pDevice)
2399 unsigned char byBBRxConf = 0;
2400 unsigned char byBBVGA = 0;
2402 BBbReadEmbedded(pDevice->PortOffset, 0x0A, &byBBRxConf); /* CR10 */
2404 if (pDevice->bShortSlotTime)
2405 byBBRxConf &= 0xDF; /* 1101 1111 */
2407 byBBRxConf |= 0x20; /* 0010 0000 */
2409 /* patch for 3253B0 Baseband with Cardbus module */
2410 BBbReadEmbedded(pDevice->PortOffset, 0xE7, &byBBVGA);
2411 if (byBBVGA == pDevice->abyBBVGA[0])
2412 byBBRxConf |= 0x20; /* 0010 0000 */
2414 BBbWriteEmbedded(pDevice->PortOffset, 0x0A, byBBRxConf); /* CR10 */
2417 void BBvSetVGAGainOffset(struct vnt_private *pDevice, unsigned char byData)
2419 unsigned char byBBRxConf = 0;
2421 BBbWriteEmbedded(pDevice->PortOffset, 0xE7, byData);
2423 BBbReadEmbedded(pDevice->PortOffset, 0x0A, &byBBRxConf); /* CR10 */
2424 /* patch for 3253B0 Baseband with Cardbus module */
2425 if (byData == pDevice->abyBBVGA[0])
2426 byBBRxConf |= 0x20; /* 0010 0000 */
2427 else if (pDevice->bShortSlotTime)
2428 byBBRxConf &= 0xDF; /* 1101 1111 */
2430 byBBRxConf |= 0x20; /* 0010 0000 */
2431 pDevice->byBBVGACurrent = byData;
2432 BBbWriteEmbedded(pDevice->PortOffset, 0x0A, byBBRxConf); /* CR10 */
2436 * Description: Baseband SoftwareReset
2440 * dwIoBase - I/O base address
2444 * Return Value: none
2448 BBvSoftwareReset(void __iomem *dwIoBase)
2450 BBbWriteEmbedded(dwIoBase, 0x50, 0x40);
2451 BBbWriteEmbedded(dwIoBase, 0x50, 0);
2452 BBbWriteEmbedded(dwIoBase, 0x9C, 0x01);
2453 BBbWriteEmbedded(dwIoBase, 0x9C, 0);
2457 * Description: Baseband Power Save Mode ON
2461 * dwIoBase - I/O base address
2465 * Return Value: none
2469 BBvPowerSaveModeON(void __iomem *dwIoBase)
2471 unsigned char byOrgData;
2473 BBbReadEmbedded(dwIoBase, 0x0D, &byOrgData);
2475 BBbWriteEmbedded(dwIoBase, 0x0D, byOrgData);
2479 * Description: Baseband Power Save Mode OFF
2483 * dwIoBase - I/O base address
2487 * Return Value: none
2491 BBvPowerSaveModeOFF(void __iomem *dwIoBase)
2493 unsigned char byOrgData;
2495 BBbReadEmbedded(dwIoBase, 0x0D, &byOrgData);
2496 byOrgData &= ~(BIT0);
2497 BBbWriteEmbedded(dwIoBase, 0x0D, byOrgData);
2501 * Description: Set Tx Antenna mode
2505 * pDevice - Device Structure
2506 * byAntennaMode - Antenna Mode
2510 * Return Value: none
2515 BBvSetTxAntennaMode(void __iomem *dwIoBase, unsigned char byAntennaMode)
2517 unsigned char byBBTxConf;
2519 BBbReadEmbedded(dwIoBase, 0x09, &byBBTxConf); /* CR09 */
2520 if (byAntennaMode == ANT_DIVERSITY) {
2521 /* bit 1 is diversity */
2523 } else if (byAntennaMode == ANT_A) {
2524 /* bit 2 is ANTSEL */
2525 byBBTxConf &= 0xF9; /* 1111 1001 */
2526 } else if (byAntennaMode == ANT_B) {
2527 byBBTxConf &= 0xFD; /* 1111 1101 */
2530 BBbWriteEmbedded(dwIoBase, 0x09, byBBTxConf); /* CR09 */
2534 * Description: Set Rx Antenna mode
2538 * pDevice - Device Structure
2539 * byAntennaMode - Antenna Mode
2543 * Return Value: none
2548 BBvSetRxAntennaMode(void __iomem *dwIoBase, unsigned char byAntennaMode)
2550 unsigned char byBBRxConf;
2552 BBbReadEmbedded(dwIoBase, 0x0A, &byBBRxConf); /* CR10 */
2553 if (byAntennaMode == ANT_DIVERSITY) {
2556 } else if (byAntennaMode == ANT_A) {
2557 byBBRxConf &= 0xFC; /* 1111 1100 */
2558 } else if (byAntennaMode == ANT_B) {
2559 byBBRxConf &= 0xFE; /* 1111 1110 */
2562 BBbWriteEmbedded(dwIoBase, 0x0A, byBBRxConf); /* CR10 */
2566 * Description: BBvSetDeepSleep
2570 * pDevice - Device Structure
2574 * Return Value: none
2578 BBvSetDeepSleep(void __iomem *dwIoBase, unsigned char byLocalID)
2580 BBbWriteEmbedded(dwIoBase, 0x0C, 0x17); /* CR12 */
2581 BBbWriteEmbedded(dwIoBase, 0x0D, 0xB9); /* CR13 */
2585 BBvExitDeepSleep(void __iomem *dwIoBase, unsigned char byLocalID)
2587 BBbWriteEmbedded(dwIoBase, 0x0C, 0x00); /* CR12 */
2588 BBbWriteEmbedded(dwIoBase, 0x0D, 0x01); /* CR13 */
2593 s_ulGetRatio(struct vnt_private *pDevice)
2595 unsigned long ulRatio = 0;
2596 unsigned long ulMaxPacket;
2597 unsigned long ulPacketNum;
2599 /* This is a thousand-ratio */
2600 ulMaxPacket = pDevice->uNumSQ3[RATE_54M];
2601 if (pDevice->uNumSQ3[RATE_54M] != 0) {
2602 ulPacketNum = pDevice->uNumSQ3[RATE_54M];
2603 ulRatio = (ulPacketNum * 1000 / pDevice->uDiversityCnt);
2604 ulRatio += TOP_RATE_54M;
2606 if (pDevice->uNumSQ3[RATE_48M] > ulMaxPacket) {
2607 ulPacketNum = pDevice->uNumSQ3[RATE_54M] + pDevice->uNumSQ3[RATE_48M];
2608 ulRatio = (ulPacketNum * 1000 / pDevice->uDiversityCnt);
2609 ulRatio += TOP_RATE_48M;
2610 ulMaxPacket = pDevice->uNumSQ3[RATE_48M];
2612 if (pDevice->uNumSQ3[RATE_36M] > ulMaxPacket) {
2613 ulPacketNum = pDevice->uNumSQ3[RATE_54M] + pDevice->uNumSQ3[RATE_48M] +
2614 pDevice->uNumSQ3[RATE_36M];
2615 ulRatio = (ulPacketNum * 1000 / pDevice->uDiversityCnt);
2616 ulRatio += TOP_RATE_36M;
2617 ulMaxPacket = pDevice->uNumSQ3[RATE_36M];
2619 if (pDevice->uNumSQ3[RATE_24M] > ulMaxPacket) {
2620 ulPacketNum = pDevice->uNumSQ3[RATE_54M] + pDevice->uNumSQ3[RATE_48M] +
2621 pDevice->uNumSQ3[RATE_36M] + pDevice->uNumSQ3[RATE_24M];
2622 ulRatio = (ulPacketNum * 1000 / pDevice->uDiversityCnt);
2623 ulRatio += TOP_RATE_24M;
2624 ulMaxPacket = pDevice->uNumSQ3[RATE_24M];
2626 if (pDevice->uNumSQ3[RATE_18M] > ulMaxPacket) {
2627 ulPacketNum = pDevice->uNumSQ3[RATE_54M] + pDevice->uNumSQ3[RATE_48M] +
2628 pDevice->uNumSQ3[RATE_36M] + pDevice->uNumSQ3[RATE_24M] +
2629 pDevice->uNumSQ3[RATE_18M];
2630 ulRatio = (ulPacketNum * 1000 / pDevice->uDiversityCnt);
2631 ulRatio += TOP_RATE_18M;
2632 ulMaxPacket = pDevice->uNumSQ3[RATE_18M];
2634 if (pDevice->uNumSQ3[RATE_12M] > ulMaxPacket) {
2635 ulPacketNum = pDevice->uNumSQ3[RATE_54M] + pDevice->uNumSQ3[RATE_48M] +
2636 pDevice->uNumSQ3[RATE_36M] + pDevice->uNumSQ3[RATE_24M] +
2637 pDevice->uNumSQ3[RATE_18M] + pDevice->uNumSQ3[RATE_12M];
2638 ulRatio = (ulPacketNum * 1000 / pDevice->uDiversityCnt);
2639 ulRatio += TOP_RATE_12M;
2640 ulMaxPacket = pDevice->uNumSQ3[RATE_12M];
2642 if (pDevice->uNumSQ3[RATE_11M] > ulMaxPacket) {
2643 ulPacketNum = pDevice->uDiversityCnt - pDevice->uNumSQ3[RATE_1M] -
2644 pDevice->uNumSQ3[RATE_2M] - pDevice->uNumSQ3[RATE_5M] -
2645 pDevice->uNumSQ3[RATE_6M] - pDevice->uNumSQ3[RATE_9M];
2646 ulRatio = (ulPacketNum * 1000 / pDevice->uDiversityCnt);
2647 ulRatio += TOP_RATE_11M;
2648 ulMaxPacket = pDevice->uNumSQ3[RATE_11M];
2650 if (pDevice->uNumSQ3[RATE_9M] > ulMaxPacket) {
2651 ulPacketNum = pDevice->uDiversityCnt - pDevice->uNumSQ3[RATE_1M] -
2652 pDevice->uNumSQ3[RATE_2M] - pDevice->uNumSQ3[RATE_5M] -
2653 pDevice->uNumSQ3[RATE_6M];
2654 ulRatio = (ulPacketNum * 1000 / pDevice->uDiversityCnt);
2655 ulRatio += TOP_RATE_9M;
2656 ulMaxPacket = pDevice->uNumSQ3[RATE_9M];
2658 if (pDevice->uNumSQ3[RATE_6M] > ulMaxPacket) {
2659 ulPacketNum = pDevice->uDiversityCnt - pDevice->uNumSQ3[RATE_1M] -
2660 pDevice->uNumSQ3[RATE_2M] - pDevice->uNumSQ3[RATE_5M];
2661 ulRatio = (ulPacketNum * 1000 / pDevice->uDiversityCnt);
2662 ulRatio += TOP_RATE_6M;
2663 ulMaxPacket = pDevice->uNumSQ3[RATE_6M];
2665 if (pDevice->uNumSQ3[RATE_5M] > ulMaxPacket) {
2666 ulPacketNum = pDevice->uDiversityCnt - pDevice->uNumSQ3[RATE_1M] -
2667 pDevice->uNumSQ3[RATE_2M];
2668 ulRatio = (ulPacketNum * 1000 / pDevice->uDiversityCnt);
2669 ulRatio += TOP_RATE_55M;
2670 ulMaxPacket = pDevice->uNumSQ3[RATE_5M];
2672 if (pDevice->uNumSQ3[RATE_2M] > ulMaxPacket) {
2673 ulPacketNum = pDevice->uDiversityCnt - pDevice->uNumSQ3[RATE_1M];
2674 ulRatio = (ulPacketNum * 1000 / pDevice->uDiversityCnt);
2675 ulRatio += TOP_RATE_2M;
2676 ulMaxPacket = pDevice->uNumSQ3[RATE_2M];
2678 if (pDevice->uNumSQ3[RATE_1M] > ulMaxPacket) {
2679 ulPacketNum = pDevice->uDiversityCnt;
2680 ulRatio = (ulPacketNum * 1000 / pDevice->uDiversityCnt);
2681 ulRatio += TOP_RATE_1M;
2688 BBvClearAntDivSQ3Value(struct vnt_private *pDevice)
2692 pDevice->uDiversityCnt = 0;
2693 for (ii = 0; ii < MAX_RATE; ii++)
2694 pDevice->uNumSQ3[ii] = 0;
2698 * Description: Antenna Diversity
2702 * pDevice - Device Structure
2703 * byRSR - RSR from received packet
2704 * bySQ3 - SQ3 value from received packet
2708 * Return Value: none
2712 void BBvAntennaDiversity(struct vnt_private *pDevice,
2713 unsigned char byRxRate, unsigned char bySQ3)
2715 if ((byRxRate >= MAX_RATE) || (pDevice->wAntDiversityMaxRate >= MAX_RATE))
2718 pDevice->uDiversityCnt++;
2720 pDevice->uNumSQ3[byRxRate]++;
2722 if (pDevice->byAntennaState == 0) {
2723 if (pDevice->uDiversityCnt > pDevice->ulDiversityNValue) {
2724 pr_debug("ulDiversityNValue=[%d],54M-[%d]\n",
2725 (int)pDevice->ulDiversityNValue,
2726 (int)pDevice->uNumSQ3[(int)pDevice->wAntDiversityMaxRate]);
2728 if (pDevice->uNumSQ3[pDevice->wAntDiversityMaxRate] < pDevice->uDiversityCnt/2) {
2729 pDevice->ulRatio_State0 = s_ulGetRatio(pDevice);
2730 pr_debug("SQ3_State0, rate = [%08x]\n",
2731 (int)pDevice->ulRatio_State0);
2733 if (pDevice->byTMax == 0)
2735 pr_debug("1.[%08x], uNumSQ3[%d]=%d, %d\n",
2736 (int)pDevice->ulRatio_State0,
2737 (int)pDevice->wAntDiversityMaxRate,
2738 (int)pDevice->uNumSQ3[(int)pDevice->wAntDiversityMaxRate],
2739 (int)pDevice->uDiversityCnt);
2741 s_vChangeAntenna(pDevice);
2742 pDevice->byAntennaState = 1;
2743 del_timer(&pDevice->TimerSQ3Tmax3);
2744 del_timer(&pDevice->TimerSQ3Tmax2);
2745 pDevice->TimerSQ3Tmax1.expires = RUN_AT(pDevice->byTMax * HZ);
2746 add_timer(&pDevice->TimerSQ3Tmax1);
2749 pDevice->TimerSQ3Tmax3.expires = RUN_AT(pDevice->byTMax3 * HZ);
2750 add_timer(&pDevice->TimerSQ3Tmax3);
2752 BBvClearAntDivSQ3Value(pDevice);
2755 } else { /* byAntennaState == 1 */
2757 if (pDevice->uDiversityCnt > pDevice->ulDiversityMValue) {
2758 del_timer(&pDevice->TimerSQ3Tmax1);
2760 pDevice->ulRatio_State1 = s_ulGetRatio(pDevice);
2761 pr_debug("RX:SQ3_State1, rate0 = %08x,rate1 = %08x\n",
2762 (int)pDevice->ulRatio_State0,
2763 (int)pDevice->ulRatio_State1);
2765 if (pDevice->ulRatio_State1 < pDevice->ulRatio_State0) {
2766 pr_debug("2.[%08x][%08x], uNumSQ3[%d]=%d, %d\n",
2767 (int)pDevice->ulRatio_State0,
2768 (int)pDevice->ulRatio_State1,
2769 (int)pDevice->wAntDiversityMaxRate,
2770 (int)pDevice->uNumSQ3[(int)pDevice->wAntDiversityMaxRate],
2771 (int)pDevice->uDiversityCnt);
2773 s_vChangeAntenna(pDevice);
2774 pDevice->TimerSQ3Tmax3.expires = RUN_AT(pDevice->byTMax3 * HZ);
2775 pDevice->TimerSQ3Tmax2.expires = RUN_AT(pDevice->byTMax2 * HZ);
2776 add_timer(&pDevice->TimerSQ3Tmax3);
2777 add_timer(&pDevice->TimerSQ3Tmax2);
2779 pDevice->byAntennaState = 0;
2780 BBvClearAntDivSQ3Value(pDevice);
2782 } /* byAntennaState */
2788 * Timer for SQ3 antenna diversity
2795 * Return Value: none
2801 void *hDeviceContext
2804 struct vnt_private *pDevice = hDeviceContext;
2806 pr_debug("TimerSQ3CallBack...\n");
2807 spin_lock_irq(&pDevice->lock);
2809 pr_debug("3.[%08x][%08x], %d\n",
2810 (int)pDevice->ulRatio_State0, (int)pDevice->ulRatio_State1,
2811 (int)pDevice->uDiversityCnt);
2813 s_vChangeAntenna(pDevice);
2814 pDevice->byAntennaState = 0;
2815 BBvClearAntDivSQ3Value(pDevice);
2817 pDevice->TimerSQ3Tmax3.expires = RUN_AT(pDevice->byTMax3 * HZ);
2818 pDevice->TimerSQ3Tmax2.expires = RUN_AT(pDevice->byTMax2 * HZ);
2819 add_timer(&pDevice->TimerSQ3Tmax3);
2820 add_timer(&pDevice->TimerSQ3Tmax2);
2822 spin_unlock_irq(&pDevice->lock);
2828 * Timer for SQ3 antenna diversity
2833 * hDeviceContext - Pointer to the adapter
2839 * Return Value: none
2844 TimerState1CallBack(
2845 void *hDeviceContext
2848 struct vnt_private *pDevice = hDeviceContext;
2850 pr_debug("TimerState1CallBack...\n");
2852 spin_lock_irq(&pDevice->lock);
2853 if (pDevice->uDiversityCnt < pDevice->ulDiversityMValue/100) {
2854 s_vChangeAntenna(pDevice);
2855 pDevice->TimerSQ3Tmax3.expires = RUN_AT(pDevice->byTMax3 * HZ);
2856 pDevice->TimerSQ3Tmax2.expires = RUN_AT(pDevice->byTMax2 * HZ);
2857 add_timer(&pDevice->TimerSQ3Tmax3);
2858 add_timer(&pDevice->TimerSQ3Tmax2);
2860 pDevice->ulRatio_State1 = s_ulGetRatio(pDevice);
2861 pr_debug("SQ3_State1, rate0 = %08x,rate1 = %08x\n",
2862 (int)pDevice->ulRatio_State0,
2863 (int)pDevice->ulRatio_State1);
2865 if (pDevice->ulRatio_State1 < pDevice->ulRatio_State0) {
2866 pr_debug("2.[%08x][%08x], uNumSQ3[%d]=%d, %d\n",
2867 (int)pDevice->ulRatio_State0,
2868 (int)pDevice->ulRatio_State1,
2869 (int)pDevice->wAntDiversityMaxRate,
2870 (int)pDevice->uNumSQ3[(int)pDevice->wAntDiversityMaxRate],
2871 (int)pDevice->uDiversityCnt);
2873 s_vChangeAntenna(pDevice);
2875 pDevice->TimerSQ3Tmax3.expires = RUN_AT(pDevice->byTMax3 * HZ);
2876 pDevice->TimerSQ3Tmax2.expires = RUN_AT(pDevice->byTMax2 * HZ);
2877 add_timer(&pDevice->TimerSQ3Tmax3);
2878 add_timer(&pDevice->TimerSQ3Tmax2);
2881 pDevice->byAntennaState = 0;
2882 BBvClearAntDivSQ3Value(pDevice);
2883 spin_unlock_irq(&pDevice->lock);