drivers/thermal/samsung/exynos_tmu_data.c

   1 /*
   2  * exynos_tmu_data.c - Samsung EXYNOS tmu data file
   3  *
   4  *  Copyright (C) 2013 Samsung Electronics
   5  *  Amit Daniel Kachhap <amit.daniel@samsung.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  *
  21  */
  22
  23 #include "exynos_thermal_common.h"
  24 #include "exynos_tmu.h"
  25 #include "exynos_tmu_data.h"
  26
  27 #if defined(CONFIG_CPU_EXYNOS4210)
  28 static const struct exynos_tmu_registers exynos4210_tmu_registers = {
  29         .triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
  30         .tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
  31         .tmu_status = EXYNOS_TMU_REG_STATUS,
  32         .tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
  33         .threshold_temp = EXYNOS4210_TMU_REG_THRESHOLD_TEMP,
  34         .threshold_th0 = EXYNOS4210_TMU_REG_TRIG_LEVEL0,
  35         .tmu_inten = EXYNOS_TMU_REG_INTEN,
  36         .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
  37         .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
  38         .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
  39         .inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
  40         .tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
  41         .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
  42 };
  43
  44 struct exynos_tmu_init_data const exynos4210_default_tmu_data = {
  45         .tmu_data = {
  46                 {
  47                 .threshold = 80,
  48                 .trigger_levels[0] = 5,
  49                 .trigger_levels[1] = 20,
  50                 .trigger_levels[2] = 30,
  51                 .trigger_enable[0] = true,
  52                 .trigger_enable[1] = true,
  53                 .trigger_enable[2] = true,
  54                 .trigger_enable[3] = false,
  55                 .trigger_type[0] = THROTTLE_ACTIVE,
  56                 .trigger_type[1] = THROTTLE_ACTIVE,
  57                 .trigger_type[2] = SW_TRIP,
  58                 .max_trigger_level = 4,
  59                 .non_hw_trigger_levels = 3,
  60                 .gain = 15,
  61                 .reference_voltage = 7,
  62                 .cal_type = TYPE_ONE_POINT_TRIMMING,
  63                 .min_efuse_value = 40,
  64                 .max_efuse_value = 100,
  65                 .first_point_trim = 25,
  66                 .second_point_trim = 85,
  67                 .default_temp_offset = 50,
  68                 .freq_tab[0] = {
  69                         .freq_clip_max = 800 * 1000,
  70                         .temp_level = 85,
  71                         },
  72                 .freq_tab[1] = {
  73                         .freq_clip_max = 200 * 1000,
  74                         .temp_level = 100,
  75                 },
  76                 .freq_tab_count = 2,
  77                 .type = SOC_ARCH_EXYNOS4210,
  78                 .registers = &exynos4210_tmu_registers,
  79                 .features = TMU_SUPPORT_READY_STATUS,
  80                 },
  81         },
  82         .tmu_count = 1,
  83 };
  84 #endif
  85
  86 #if defined(CONFIG_SOC_EXYNOS3250)
  87 static const struct exynos_tmu_registers exynos3250_tmu_registers = {
  88         .triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
  89         .triminfo_ctrl[0] = EXYNOS_TMU_TRIMINFO_CON1,
  90         .triminfo_ctrl[1] = EXYNOS_TMU_TRIMINFO_CON2,
  91         .triminfo_ctrl_count = 2,
  92         .tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
  93         .test_mux_addr_shift = EXYNOS4412_MUX_ADDR_SHIFT,
  94         .therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
  95         .therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
  96         .therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
  97         .tmu_status = EXYNOS_TMU_REG_STATUS,
  98         .tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
  99         .threshold_th0 = EXYNOS_THD_TEMP_RISE,
 100         .threshold_th1 = EXYNOS_THD_TEMP_FALL,
 101         .tmu_inten = EXYNOS_TMU_REG_INTEN,
 102         .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
 103         .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
 104         .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
 105         .inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
 106         .tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
 107         .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
 108         .emul_con = EXYNOS_EMUL_CON,
 109         .emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
 110         .emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
 111 };
 112
 113 #define EXYNOS3250_TMU_DATA \
 114         .threshold_falling = 10, \
 115         .trigger_levels[0] = 70, \
 116         .trigger_levels[1] = 95, \
 117         .trigger_levels[2] = 110, \
 118         .trigger_levels[3] = 120, \
 119         .trigger_enable[0] = true, \
 120         .trigger_enable[1] = true, \
 121         .trigger_enable[2] = true, \
 122         .trigger_enable[3] = false, \
 123         .trigger_type[0] = THROTTLE_ACTIVE, \
 124         .trigger_type[1] = THROTTLE_ACTIVE, \
 125         .trigger_type[2] = SW_TRIP, \
 126         .trigger_type[3] = HW_TRIP, \
 127         .max_trigger_level = 4, \
 128         .non_hw_trigger_levels = 3, \
 129         .gain = 8, \
 130         .reference_voltage = 16, \
 131         .noise_cancel_mode = 4, \
 132         .cal_type = TYPE_TWO_POINT_TRIMMING, \
 133         .efuse_value = 55, \
 134         .min_efuse_value = 40, \
 135         .max_efuse_value = 100, \
 136         .first_point_trim = 25, \
 137         .second_point_trim = 85, \
 138         .default_temp_offset = 50, \
 139         .freq_tab[0] = { \
 140                 .freq_clip_max = 800 * 1000, \
 141                 .temp_level = 70, \
 142         }, \
 143         .freq_tab[1] = { \
 144                 .freq_clip_max = 400 * 1000, \
 145                 .temp_level = 95, \
 146         }, \
 147         .freq_tab_count = 2, \
 148         .triminfo_reload[0] = EXYNOS_TRIMINFO_RELOAD_ENABLE, \
 149         .triminfo_reload[1] = EXYNOS_TRIMINFO_RELOAD_ENABLE, \
 150         .registers = &exynos3250_tmu_registers, \
 151         .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
 152                         TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
 153                         TMU_SUPPORT_EMUL_TIME)
 154 #endif
 155
 156 #if defined(CONFIG_SOC_EXYNOS3250)
 157 struct exynos_tmu_init_data const exynos3250_default_tmu_data = {
 158         .tmu_data = {
 159                 {
 160                         EXYNOS3250_TMU_DATA,
 161                         .type = SOC_ARCH_EXYNOS3250,
 162                         .test_mux = EXYNOS4412_MUX_ADDR_VALUE,
 163                 },
 164         },
 165         .tmu_count = 1,
 166 };
 167 #endif
 168
 169 #if defined(CONFIG_SOC_EXYNOS4412) || defined(CONFIG_SOC_EXYNOS5250)
 170 static const struct exynos_tmu_registers exynos4412_tmu_registers = {
 171         .triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
 172         .triminfo_ctrl[0] = EXYNOS_TMU_TRIMINFO_CON2,
 173         .triminfo_ctrl_count = 1,
 174         .tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
 175         .test_mux_addr_shift = EXYNOS4412_MUX_ADDR_SHIFT,
 176         .therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
 177         .therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
 178         .therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
 179         .tmu_status = EXYNOS_TMU_REG_STATUS,
 180         .tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
 181         .threshold_th0 = EXYNOS_THD_TEMP_RISE,
 182         .threshold_th1 = EXYNOS_THD_TEMP_FALL,
 183         .tmu_inten = EXYNOS_TMU_REG_INTEN,
 184         .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
 185         .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
 186         .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
 187         .inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
 188         .inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
 189         .tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
 190         .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
 191         .emul_con = EXYNOS_EMUL_CON,
 192         .emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
 193         .emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
 194 };
 195
 196 #define EXYNOS4412_TMU_DATA \
 197         .threshold_falling = 10, \
 198         .trigger_levels[0] = 70, \
 199         .trigger_levels[1] = 95, \
 200         .trigger_levels[2] = 110, \
 201         .trigger_levels[3] = 120, \
 202         .trigger_enable[0] = true, \
 203         .trigger_enable[1] = true, \
 204         .trigger_enable[2] = true, \
 205         .trigger_enable[3] = false, \
 206         .trigger_type[0] = THROTTLE_ACTIVE, \
 207         .trigger_type[1] = THROTTLE_ACTIVE, \
 208         .trigger_type[2] = SW_TRIP, \
 209         .trigger_type[3] = HW_TRIP, \
 210         .max_trigger_level = 4, \
 211         .non_hw_trigger_levels = 3, \
 212         .gain = 8, \
 213         .reference_voltage = 16, \
 214         .noise_cancel_mode = 4, \
 215         .cal_type = TYPE_ONE_POINT_TRIMMING, \
 216         .efuse_value = 55, \
 217         .min_efuse_value = 40, \
 218         .max_efuse_value = 100, \
 219         .first_point_trim = 25, \
 220         .second_point_trim = 85, \
 221         .default_temp_offset = 50, \
 222         .freq_tab[0] = { \
 223                 .freq_clip_max = 1400 * 1000, \
 224                 .temp_level = 70, \
 225         }, \
 226         .freq_tab[1] = { \
 227                 .freq_clip_max = 400 * 1000, \
 228                 .temp_level = 95, \
 229         }, \
 230         .freq_tab_count = 2, \
 231         .triminfo_reload[0] = EXYNOS_TRIMINFO_RELOAD_ENABLE, \
 232         .registers = &exynos4412_tmu_registers, \
 233         .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
 234                         TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
 235                         TMU_SUPPORT_EMUL_TIME)
 236 #endif
 237
 238 #if defined(CONFIG_SOC_EXYNOS4412)
 239 struct exynos_tmu_init_data const exynos4412_default_tmu_data = {
 240         .tmu_data = {
 241                 {
 242                         EXYNOS4412_TMU_DATA,
 243                         .type = SOC_ARCH_EXYNOS4412,
 244                         .test_mux = EXYNOS4412_MUX_ADDR_VALUE,
 245                 },
 246         },
 247         .tmu_count = 1,
 248 };
 249 #endif
 250
 251 #if defined(CONFIG_SOC_EXYNOS5250)
 252 struct exynos_tmu_init_data const exynos5250_default_tmu_data = {
 253         .tmu_data = {
 254                 {
 255                         EXYNOS4412_TMU_DATA,
 256                         .type = SOC_ARCH_EXYNOS5250,
 257                 },
 258         },
 259         .tmu_count = 1,
 260 };
 261 #endif
 262
 263 #if defined(CONFIG_SOC_EXYNOS5260)
 264 static const struct exynos_tmu_registers exynos5260_tmu_registers = {
 265         .triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
 266         .tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
 267         .tmu_ctrl = EXYNOS_TMU_REG_CONTROL1,
 268         .therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
 269         .therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
 270         .therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
 271         .tmu_status = EXYNOS_TMU_REG_STATUS,
 272         .tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
 273         .threshold_th0 = EXYNOS_THD_TEMP_RISE,
 274         .threshold_th1 = EXYNOS_THD_TEMP_FALL,
 275         .tmu_inten = EXYNOS5260_TMU_REG_INTEN,
 276         .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
 277         .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
 278         .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
 279         .inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
 280         .inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
 281         .tmu_intstat = EXYNOS5260_TMU_REG_INTSTAT,
 282         .tmu_intclear = EXYNOS5260_TMU_REG_INTCLEAR,
 283         .emul_con = EXYNOS5260_EMUL_CON,
 284         .emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
 285         .emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
 286 };
 287
 288 #define __EXYNOS5260_TMU_DATA   \
 289         .threshold_falling = 10, \
 290         .trigger_levels[0] = 85, \
 291         .trigger_levels[1] = 103, \
 292         .trigger_levels[2] = 110, \
 293         .trigger_levels[3] = 120, \
 294         .trigger_enable[0] = true, \
 295         .trigger_enable[1] = true, \
 296         .trigger_enable[2] = true, \
 297         .trigger_enable[3] = false, \
 298         .trigger_type[0] = THROTTLE_ACTIVE, \
 299         .trigger_type[1] = THROTTLE_ACTIVE, \
 300         .trigger_type[2] = SW_TRIP, \
 301         .trigger_type[3] = HW_TRIP, \
 302         .max_trigger_level = 4, \
 303         .non_hw_trigger_levels = 3, \
 304         .gain = 8, \
 305         .reference_voltage = 16, \
 306         .noise_cancel_mode = 4, \
 307         .cal_type = TYPE_ONE_POINT_TRIMMING, \
 308         .efuse_value = 55, \
 309         .min_efuse_value = 40, \
 310         .max_efuse_value = 100, \
 311         .first_point_trim = 25, \
 312         .second_point_trim = 85, \
 313         .default_temp_offset = 50, \
 314         .freq_tab[0] = { \
 315                 .freq_clip_max = 800 * 1000, \
 316                 .temp_level = 85, \
 317         }, \
 318         .freq_tab[1] = { \
 319                 .freq_clip_max = 200 * 1000, \
 320                 .temp_level = 103, \
 321         }, \
 322         .freq_tab_count = 2, \
 323         .registers = &exynos5260_tmu_registers, \
 324
 325 #define EXYNOS5260_TMU_DATA \
 326         __EXYNOS5260_TMU_DATA \
 327         .type = SOC_ARCH_EXYNOS5260, \
 328         .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_FALLING_TRIP | \
 329                         TMU_SUPPORT_READY_STATUS | TMU_SUPPORT_EMUL_TIME)
 330
 331 struct exynos_tmu_init_data const exynos5260_default_tmu_data = {
 332         .tmu_data = {
 333                 { EXYNOS5260_TMU_DATA },
 334                 { EXYNOS5260_TMU_DATA },
 335                 { EXYNOS5260_TMU_DATA },
 336                 { EXYNOS5260_TMU_DATA },
 337                 { EXYNOS5260_TMU_DATA },
 338         },
 339         .tmu_count = 5,
 340 };
 341 #endif
 342
 343 #if defined(CONFIG_SOC_EXYNOS5420)
 344 static const struct exynos_tmu_registers exynos5420_tmu_registers = {
 345         .triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
 346         .tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
 347         .therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
 348         .therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
 349         .therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
 350         .tmu_status = EXYNOS_TMU_REG_STATUS,
 351         .tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
 352         .threshold_th0 = EXYNOS_THD_TEMP_RISE,
 353         .threshold_th1 = EXYNOS_THD_TEMP_FALL,
 354         .tmu_inten = EXYNOS_TMU_REG_INTEN,
 355         .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
 356         .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
 357         .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
 358         /* INTEN_RISE3 Not availble in exynos5420 */
 359         .inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
 360         .inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
 361         .tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
 362         .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
 363         .emul_con = EXYNOS_EMUL_CON,
 364         .emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
 365         .emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
 366 };
 367
 368 #define __EXYNOS5420_TMU_DATA   \
 369         .threshold_falling = 10, \
 370         .trigger_levels[0] = 85, \
 371         .trigger_levels[1] = 103, \
 372         .trigger_levels[2] = 110, \
 373         .trigger_levels[3] = 120, \
 374         .trigger_enable[0] = true, \
 375         .trigger_enable[1] = true, \
 376         .trigger_enable[2] = true, \
 377         .trigger_enable[3] = false, \
 378         .trigger_type[0] = THROTTLE_ACTIVE, \
 379         .trigger_type[1] = THROTTLE_ACTIVE, \
 380         .trigger_type[2] = SW_TRIP, \
 381         .trigger_type[3] = HW_TRIP, \
 382         .max_trigger_level = 4, \
 383         .non_hw_trigger_levels = 3, \
 384         .gain = 8, \
 385         .reference_voltage = 16, \
 386         .noise_cancel_mode = 4, \
 387         .cal_type = TYPE_ONE_POINT_TRIMMING, \
 388         .efuse_value = 55, \
 389         .min_efuse_value = 40, \
 390         .max_efuse_value = 100, \
 391         .first_point_trim = 25, \
 392         .second_point_trim = 85, \
 393         .default_temp_offset = 50, \
 394         .freq_tab[0] = { \
 395                 .freq_clip_max = 800 * 1000, \
 396                 .temp_level = 85, \
 397         }, \
 398         .freq_tab[1] = { \
 399                 .freq_clip_max = 200 * 1000, \
 400                 .temp_level = 103, \
 401         }, \
 402         .freq_tab_count = 2, \
 403         .registers = &exynos5420_tmu_registers, \
 404
 405 #define EXYNOS5420_TMU_DATA \
 406         __EXYNOS5420_TMU_DATA \
 407         .type = SOC_ARCH_EXYNOS5250, \
 408         .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_FALLING_TRIP | \
 409                         TMU_SUPPORT_READY_STATUS | TMU_SUPPORT_EMUL_TIME)
 410
 411 #define EXYNOS5420_TMU_DATA_SHARED \
 412         __EXYNOS5420_TMU_DATA \
 413         .type = SOC_ARCH_EXYNOS5420_TRIMINFO, \
 414         .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_FALLING_TRIP | \
 415                         TMU_SUPPORT_READY_STATUS | TMU_SUPPORT_EMUL_TIME | \
 416                         TMU_SUPPORT_ADDRESS_MULTIPLE)
 417
 418 struct exynos_tmu_init_data const exynos5420_default_tmu_data = {
 419         .tmu_data = {
 420                 { EXYNOS5420_TMU_DATA },
 421                 { EXYNOS5420_TMU_DATA },
 422                 { EXYNOS5420_TMU_DATA_SHARED },
 423                 { EXYNOS5420_TMU_DATA_SHARED },
 424                 { EXYNOS5420_TMU_DATA_SHARED },
 425         },
 426         .tmu_count = 5,
 427 };
 428 #endif
 429
 430 #if defined(CONFIG_SOC_EXYNOS5440)
 431 static const struct exynos_tmu_registers exynos5440_tmu_registers = {
 432         .triminfo_data = EXYNOS5440_TMU_S0_7_TRIM,
 433         .tmu_ctrl = EXYNOS5440_TMU_S0_7_CTRL,
 434         .therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
 435         .therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
 436         .therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
 437         .tmu_status = EXYNOS5440_TMU_S0_7_STATUS,
 438         .tmu_cur_temp = EXYNOS5440_TMU_S0_7_TEMP,
 439         .threshold_th0 = EXYNOS5440_TMU_S0_7_TH0,
 440         .threshold_th1 = EXYNOS5440_TMU_S0_7_TH1,
 441         .threshold_th2 = EXYNOS5440_TMU_S0_7_TH2,
 442         .threshold_th3_l0_shift = EXYNOS5440_TMU_TH_RISE4_SHIFT,
 443         .tmu_inten = EXYNOS5440_TMU_S0_7_IRQEN,
 444         .inten_rise0_shift = EXYNOS5440_TMU_INTEN_RISE0_SHIFT,
 445         .inten_rise1_shift = EXYNOS5440_TMU_INTEN_RISE1_SHIFT,
 446         .inten_rise2_shift = EXYNOS5440_TMU_INTEN_RISE2_SHIFT,
 447         .inten_rise3_shift = EXYNOS5440_TMU_INTEN_RISE3_SHIFT,
 448         .inten_fall0_shift = EXYNOS5440_TMU_INTEN_FALL0_SHIFT,
 449         .tmu_intstat = EXYNOS5440_TMU_S0_7_IRQ,
 450         .tmu_intclear = EXYNOS5440_TMU_S0_7_IRQ,
 451         .tmu_irqstatus = EXYNOS5440_TMU_IRQ_STATUS,
 452         .emul_con = EXYNOS5440_TMU_S0_7_DEBUG,
 453         .emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
 454         .tmu_pmin = EXYNOS5440_TMU_PMIN,
 455 };
 456
 457 #define EXYNOS5440_TMU_DATA \
 458         .trigger_levels[0] = 100, \
 459         .trigger_levels[4] = 105, \
 460         .trigger_enable[0] = 1, \
 461         .trigger_type[0] = SW_TRIP, \
 462         .trigger_type[4] = HW_TRIP, \
 463         .max_trigger_level = 5, \
 464         .non_hw_trigger_levels = 1, \
 465         .gain = 5, \
 466         .reference_voltage = 16, \
 467         .noise_cancel_mode = 4, \
 468         .cal_type = TYPE_ONE_POINT_TRIMMING, \
 469         .efuse_value = 0x5b2d, \
 470         .min_efuse_value = 16, \
 471         .max_efuse_value = 76, \
 472         .first_point_trim = 25, \
 473         .second_point_trim = 70, \
 474         .default_temp_offset = 25, \
 475         .type = SOC_ARCH_EXYNOS5440, \
 476         .registers = &exynos5440_tmu_registers, \
 477         .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_FALLING_TRIP | \
 478                         TMU_SUPPORT_MULTI_INST | TMU_SUPPORT_ADDRESS_MULTIPLE),
 479
 480 struct exynos_tmu_init_data const exynos5440_default_tmu_data = {
 481         .tmu_data = {
 482                 { EXYNOS5440_TMU_DATA } ,
 483                 { EXYNOS5440_TMU_DATA } ,
 484                 { EXYNOS5440_TMU_DATA } ,
 485         },
 486         .tmu_count = 3,
 487 };
 488 #endif