2 * Probe module for 8250/16550-type PCI serial ports.
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 * Copyright (C) 2001 Russell King, All Rights Reserved.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License.
12 #include <linux/module.h>
13 #include <linux/init.h>
14 #include <linux/pci.h>
15 #include <linux/string.h>
16 #include <linux/kernel.h>
17 #include <linux/slab.h>
18 #include <linux/delay.h>
19 #include <linux/tty.h>
20 #include <linux/serial_reg.h>
21 #include <linux/serial_core.h>
22 #include <linux/8250_pci.h>
23 #include <linux/bitops.h>
25 #include <asm/byteorder.h>
30 #undef SERIAL_DEBUG_PCI
33 * init function returns:
34 * > 0 - number of ports
35 * = 0 - use board->num_ports
38 struct pci_serial_quirk {
43 int (*probe)(struct pci_dev *dev);
44 int (*init)(struct pci_dev *dev);
45 int (*setup)(struct serial_private *,
46 const struct pciserial_board *,
47 struct uart_8250_port *, int);
48 void (*exit)(struct pci_dev *dev);
51 #define PCI_NUM_BAR_RESOURCES 6
53 struct serial_private {
56 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
57 struct pci_serial_quirk *quirk;
61 static int pci_default_setup(struct serial_private*,
62 const struct pciserial_board*, struct uart_8250_port *, int);
64 static void moan_device(const char *str, struct pci_dev *dev)
68 "Please send the output of lspci -vv, this\n"
69 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
70 "manufacturer and name of serial board or\n"
71 "modem board to rmk+serial@arm.linux.org.uk.\n",
72 pci_name(dev), str, dev->vendor, dev->device,
73 dev->subsystem_vendor, dev->subsystem_device);
77 setup_port(struct serial_private *priv, struct uart_8250_port *port,
78 int bar, int offset, int regshift)
80 struct pci_dev *dev = priv->dev;
81 unsigned long base, len;
83 if (bar >= PCI_NUM_BAR_RESOURCES)
86 base = pci_resource_start(dev, bar);
88 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
89 len = pci_resource_len(dev, bar);
91 if (!priv->remapped_bar[bar])
92 priv->remapped_bar[bar] = ioremap_nocache(base, len);
93 if (!priv->remapped_bar[bar])
96 port->port.iotype = UPIO_MEM;
97 port->port.iobase = 0;
98 port->port.mapbase = base + offset;
99 port->port.membase = priv->remapped_bar[bar] + offset;
100 port->port.regshift = regshift;
102 port->port.iotype = UPIO_PORT;
103 port->port.iobase = base + offset;
104 port->port.mapbase = 0;
105 port->port.membase = NULL;
106 port->port.regshift = 0;
112 * ADDI-DATA GmbH communication cards <info@addi-data.com>
114 static int addidata_apci7800_setup(struct serial_private *priv,
115 const struct pciserial_board *board,
116 struct uart_8250_port *port, int idx)
118 unsigned int bar = 0, offset = board->first_offset;
119 bar = FL_GET_BASE(board->flags);
122 offset += idx * board->uart_offset;
123 } else if ((idx >= 2) && (idx < 4)) {
125 offset += ((idx - 2) * board->uart_offset);
126 } else if ((idx >= 4) && (idx < 6)) {
128 offset += ((idx - 4) * board->uart_offset);
129 } else if (idx >= 6) {
131 offset += ((idx - 6) * board->uart_offset);
134 return setup_port(priv, port, bar, offset, board->reg_shift);
138 * AFAVLAB uses a different mixture of BARs and offsets
139 * Not that ugly ;) -- HW
142 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
143 struct uart_8250_port *port, int idx)
145 unsigned int bar, offset = board->first_offset;
147 bar = FL_GET_BASE(board->flags);
152 offset += (idx - 4) * board->uart_offset;
155 return setup_port(priv, port, bar, offset, board->reg_shift);
159 * HP's Remote Management Console. The Diva chip came in several
160 * different versions. N-class, L2000 and A500 have two Diva chips, each
161 * with 3 UARTs (the third UART on the second chip is unused). Superdome
162 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
163 * one Diva chip, but it has been expanded to 5 UARTs.
165 static int pci_hp_diva_init(struct pci_dev *dev)
169 switch (dev->subsystem_device) {
170 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
171 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
172 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
173 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
176 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
179 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
182 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
183 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
192 * HP's Diva chip puts the 4th/5th serial port further out, and
193 * some serial ports are supposed to be hidden on certain models.
196 pci_hp_diva_setup(struct serial_private *priv,
197 const struct pciserial_board *board,
198 struct uart_8250_port *port, int idx)
200 unsigned int offset = board->first_offset;
201 unsigned int bar = FL_GET_BASE(board->flags);
203 switch (priv->dev->subsystem_device) {
204 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
208 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
218 offset += idx * board->uart_offset;
220 return setup_port(priv, port, bar, offset, board->reg_shift);
224 * Added for EKF Intel i960 serial boards
226 static int pci_inteli960ni_init(struct pci_dev *dev)
228 unsigned long oldval;
230 if (!(dev->subsystem_device & 0x1000))
233 /* is firmware started? */
234 pci_read_config_dword(dev, 0x44, (void *)&oldval);
235 if (oldval == 0x00001000L) { /* RESET value */
236 printk(KERN_DEBUG "Local i960 firmware missing");
243 * Some PCI serial cards using the PLX 9050 PCI interface chip require
244 * that the card interrupt be explicitly enabled or disabled. This
245 * seems to be mainly needed on card using the PLX which also use I/O
248 static int pci_plx9050_init(struct pci_dev *dev)
253 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
254 moan_device("no memory in bar 0", dev);
259 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
260 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
263 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
264 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
266 * As the megawolf cards have the int pins active
267 * high, and have 2 UART chips, both ints must be
268 * enabled on the 9050. Also, the UARTS are set in
269 * 16450 mode by default, so we have to enable the
270 * 16C950 'enhanced' mode so that we can use the
275 * enable/disable interrupts
277 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
280 writel(irq_config, p + 0x4c);
283 * Read the register back to ensure that it took effect.
291 static void __devexit pci_plx9050_exit(struct pci_dev *dev)
295 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
301 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
306 * Read the register back to ensure that it took effect.
313 #define NI8420_INT_ENABLE_REG 0x38
314 #define NI8420_INT_ENABLE_BIT 0x2000
316 static void __devexit pci_ni8420_exit(struct pci_dev *dev)
319 unsigned long base, len;
320 unsigned int bar = 0;
322 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
323 moan_device("no memory in bar", dev);
327 base = pci_resource_start(dev, bar);
328 len = pci_resource_len(dev, bar);
329 p = ioremap_nocache(base, len);
333 /* Disable the CPU Interrupt */
334 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
335 p + NI8420_INT_ENABLE_REG);
341 #define MITE_IOWBSR1 0xc4
342 #define MITE_IOWCR1 0xf4
343 #define MITE_LCIMR1 0x08
344 #define MITE_LCIMR2 0x10
346 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
348 static void __devexit pci_ni8430_exit(struct pci_dev *dev)
351 unsigned long base, len;
352 unsigned int bar = 0;
354 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
355 moan_device("no memory in bar", dev);
359 base = pci_resource_start(dev, bar);
360 len = pci_resource_len(dev, bar);
361 p = ioremap_nocache(base, len);
365 /* Disable the CPU Interrupt */
366 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
370 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
372 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
373 struct uart_8250_port *port, int idx)
375 unsigned int bar, offset = board->first_offset;
380 /* first four channels map to 0, 0x100, 0x200, 0x300 */
381 offset += idx * board->uart_offset;
382 } else if (idx < 8) {
383 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
384 offset += idx * board->uart_offset + 0xC00;
385 } else /* we have only 8 ports on PMC-OCTALPRO */
388 return setup_port(priv, port, bar, offset, board->reg_shift);
392 * This does initialization for PMC OCTALPRO cards:
393 * maps the device memory, resets the UARTs (needed, bc
394 * if the module is removed and inserted again, the card
395 * is in the sleep mode) and enables global interrupt.
398 /* global control register offset for SBS PMC-OctalPro */
399 #define OCT_REG_CR_OFF 0x500
401 static int sbs_init(struct pci_dev *dev)
405 p = pci_ioremap_bar(dev, 0);
409 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
410 writeb(0x10, p + OCT_REG_CR_OFF);
412 writeb(0x0, p + OCT_REG_CR_OFF);
414 /* Set bit-2 (INTENABLE) of Control Register */
415 writeb(0x4, p + OCT_REG_CR_OFF);
422 * Disables the global interrupt of PMC-OctalPro
425 static void __devexit sbs_exit(struct pci_dev *dev)
429 p = pci_ioremap_bar(dev, 0);
430 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
432 writeb(0, p + OCT_REG_CR_OFF);
437 * SIIG serial cards have an PCI interface chip which also controls
438 * the UART clocking frequency. Each UART can be clocked independently
439 * (except cards equipped with 4 UARTs) and initial clocking settings
440 * are stored in the EEPROM chip. It can cause problems because this
441 * version of serial driver doesn't support differently clocked UART's
442 * on single PCI card. To prevent this, initialization functions set
443 * high frequency clocking for all UART's on given card. It is safe (I
444 * hope) because it doesn't touch EEPROM settings to prevent conflicts
445 * with other OSes (like M$ DOS).
447 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
449 * There is two family of SIIG serial cards with different PCI
450 * interface chip and different configuration methods:
451 * - 10x cards have control registers in IO and/or memory space;
452 * - 20x cards have control registers in standard PCI configuration space.
454 * Note: all 10x cards have PCI device ids 0x10..
455 * all 20x cards have PCI device ids 0x20..
457 * There are also Quartet Serial cards which use Oxford Semiconductor
458 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
460 * Note: some SIIG cards are probed by the parport_serial object.
463 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
464 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
466 static int pci_siig10x_init(struct pci_dev *dev)
471 switch (dev->device & 0xfff8) {
472 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
475 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
478 default: /* 1S1P, 4S */
483 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
487 writew(readw(p + 0x28) & data, p + 0x28);
493 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
494 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
496 static int pci_siig20x_init(struct pci_dev *dev)
500 /* Change clock frequency for the first UART. */
501 pci_read_config_byte(dev, 0x6f, &data);
502 pci_write_config_byte(dev, 0x6f, data & 0xef);
504 /* If this card has 2 UART, we have to do the same with second UART. */
505 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
506 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
507 pci_read_config_byte(dev, 0x73, &data);
508 pci_write_config_byte(dev, 0x73, data & 0xef);
513 static int pci_siig_init(struct pci_dev *dev)
515 unsigned int type = dev->device & 0xff00;
518 return pci_siig10x_init(dev);
519 else if (type == 0x2000)
520 return pci_siig20x_init(dev);
522 moan_device("Unknown SIIG card", dev);
526 static int pci_siig_setup(struct serial_private *priv,
527 const struct pciserial_board *board,
528 struct uart_8250_port *port, int idx)
530 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
534 offset = (idx - 4) * 8;
537 return setup_port(priv, port, bar, offset, 0);
541 * Timedia has an explosion of boards, and to avoid the PCI table from
542 * growing *huge*, we use this function to collapse some 70 entries
543 * in the PCI table into one, for sanity's and compactness's sake.
545 static const unsigned short timedia_single_port[] = {
546 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
549 static const unsigned short timedia_dual_port[] = {
550 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
551 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
552 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
553 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
557 static const unsigned short timedia_quad_port[] = {
558 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
559 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
560 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
564 static const unsigned short timedia_eight_port[] = {
565 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
566 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
569 static const struct timedia_struct {
571 const unsigned short *ids;
573 { 1, timedia_single_port },
574 { 2, timedia_dual_port },
575 { 4, timedia_quad_port },
576 { 8, timedia_eight_port }
580 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of
581 * listing them individually, this driver merely grabs them all with
582 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
583 * and should be left free to be claimed by parport_serial instead.
585 static int pci_timedia_probe(struct pci_dev *dev)
588 * Check the third digit of the subdevice ID
589 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
591 if ((dev->subsystem_device & 0x00f0) >= 0x70) {
593 "ignoring Timedia subdevice %04x for parport_serial\n",
594 dev->subsystem_device);
601 static int pci_timedia_init(struct pci_dev *dev)
603 const unsigned short *ids;
606 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
607 ids = timedia_data[i].ids;
608 for (j = 0; ids[j]; j++)
609 if (dev->subsystem_device == ids[j])
610 return timedia_data[i].num;
616 * Timedia/SUNIX uses a mixture of BARs and offsets
617 * Ugh, this is ugly as all hell --- TYT
620 pci_timedia_setup(struct serial_private *priv,
621 const struct pciserial_board *board,
622 struct uart_8250_port *port, int idx)
624 unsigned int bar = 0, offset = board->first_offset;
631 offset = board->uart_offset;
638 offset = board->uart_offset;
647 return setup_port(priv, port, bar, offset, board->reg_shift);
651 * Some Titan cards are also a little weird
654 titan_400l_800l_setup(struct serial_private *priv,
655 const struct pciserial_board *board,
656 struct uart_8250_port *port, int idx)
658 unsigned int bar, offset = board->first_offset;
669 offset = (idx - 2) * board->uart_offset;
672 return setup_port(priv, port, bar, offset, board->reg_shift);
675 static int pci_xircom_init(struct pci_dev *dev)
681 static int pci_ni8420_init(struct pci_dev *dev)
684 unsigned long base, len;
685 unsigned int bar = 0;
687 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
688 moan_device("no memory in bar", dev);
692 base = pci_resource_start(dev, bar);
693 len = pci_resource_len(dev, bar);
694 p = ioremap_nocache(base, len);
698 /* Enable CPU Interrupt */
699 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
700 p + NI8420_INT_ENABLE_REG);
706 #define MITE_IOWBSR1_WSIZE 0xa
707 #define MITE_IOWBSR1_WIN_OFFSET 0x800
708 #define MITE_IOWBSR1_WENAB (1 << 7)
709 #define MITE_LCIMR1_IO_IE_0 (1 << 24)
710 #define MITE_LCIMR2_SET_CPU_IE (1 << 31)
711 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
713 static int pci_ni8430_init(struct pci_dev *dev)
716 unsigned long base, len;
718 unsigned int bar = 0;
720 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
721 moan_device("no memory in bar", dev);
725 base = pci_resource_start(dev, bar);
726 len = pci_resource_len(dev, bar);
727 p = ioremap_nocache(base, len);
731 /* Set device window address and size in BAR0 */
732 device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
733 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
734 writel(device_window, p + MITE_IOWBSR1);
736 /* Set window access to go to RAMSEL IO address space */
737 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
740 /* Enable IO Bus Interrupt 0 */
741 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
743 /* Enable CPU Interrupt */
744 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
750 /* UART Port Control Register */
751 #define NI8430_PORTCON 0x0f
752 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
755 pci_ni8430_setup(struct serial_private *priv,
756 const struct pciserial_board *board,
757 struct uart_8250_port *port, int idx)
760 unsigned long base, len;
761 unsigned int bar, offset = board->first_offset;
763 if (idx >= board->num_ports)
766 bar = FL_GET_BASE(board->flags);
767 offset += idx * board->uart_offset;
769 base = pci_resource_start(priv->dev, bar);
770 len = pci_resource_len(priv->dev, bar);
771 p = ioremap_nocache(base, len);
773 /* enable the transceiver */
774 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
775 p + offset + NI8430_PORTCON);
779 return setup_port(priv, port, bar, offset, board->reg_shift);
782 static int pci_netmos_9900_setup(struct serial_private *priv,
783 const struct pciserial_board *board,
784 struct uart_8250_port *port, int idx)
788 if ((priv->dev->subsystem_device & 0xff00) == 0x3000) {
789 /* netmos apparently orders BARs by datasheet layout, so serial
790 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
794 return setup_port(priv, port, bar, 0, board->reg_shift);
796 return pci_default_setup(priv, board, port, idx);
800 /* the 99xx series comes with a range of device IDs and a variety
803 * 9900 has varying capabilities and can cascade to sub-controllers
804 * (cascading should be purely internal)
805 * 9904 is hardwired with 4 serial ports
806 * 9912 and 9922 are hardwired with 2 serial ports
808 static int pci_netmos_9900_numports(struct pci_dev *dev)
810 unsigned int c = dev->class;
812 unsigned short sub_serports;
818 } else if ((pi == 0) &&
819 (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
820 /* two possibilities: 0x30ps encodes number of parallel and
821 * serial ports, or 0x1000 indicates *something*. This is not
822 * immediately obvious, since the 2s1p+4s configuration seems
823 * to offer all functionality on functions 0..2, while still
824 * advertising the same function 3 as the 4s+2s1p config.
826 sub_serports = dev->subsystem_device & 0xf;
827 if (sub_serports > 0) {
830 printk(KERN_NOTICE "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
835 moan_device("unknown NetMos/Mostech program interface", dev);
839 static int pci_netmos_init(struct pci_dev *dev)
841 /* subdevice 0x00PS means <P> parallel, <S> serial */
842 unsigned int num_serial = dev->subsystem_device & 0xf;
844 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
845 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
848 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
849 dev->subsystem_device == 0x0299)
852 switch (dev->device) { /* FALLTHROUGH on all */
853 case PCI_DEVICE_ID_NETMOS_9904:
854 case PCI_DEVICE_ID_NETMOS_9912:
855 case PCI_DEVICE_ID_NETMOS_9922:
856 case PCI_DEVICE_ID_NETMOS_9900:
857 num_serial = pci_netmos_9900_numports(dev);
861 if (num_serial == 0 ) {
862 moan_device("unknown NetMos/Mostech device", dev);
873 * These chips are available with optionally one parallel port and up to
874 * two serial ports. Unfortunately they all have the same product id.
876 * Basic configuration is done over a region of 32 I/O ports. The base
877 * ioport is called INTA or INTC, depending on docs/other drivers.
879 * The region of the 32 I/O ports is configured in POSIO0R...
883 #define ITE_887x_MISCR 0x9c
884 #define ITE_887x_INTCBAR 0x78
885 #define ITE_887x_UARTBAR 0x7c
886 #define ITE_887x_PS0BAR 0x10
887 #define ITE_887x_POSIO0 0x60
890 #define ITE_887x_IOSIZE 32
891 /* I/O space size (bits 26-24; 8 bytes = 011b) */
892 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
893 /* I/O space size (bits 26-24; 32 bytes = 101b) */
894 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
895 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
896 #define ITE_887x_POSIO_SPEED (3 << 29)
897 /* enable IO_Space bit */
898 #define ITE_887x_POSIO_ENABLE (1 << 31)
900 static int pci_ite887x_init(struct pci_dev *dev)
902 /* inta_addr are the configuration addresses of the ITE */
903 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
906 struct resource *iobase = NULL;
907 u32 miscr, uartbar, ioport;
909 /* search for the base-ioport */
911 while (inta_addr[i] && iobase == NULL) {
912 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
914 if (iobase != NULL) {
915 /* write POSIO0R - speed | size | ioport */
916 pci_write_config_dword(dev, ITE_887x_POSIO0,
917 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
918 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
919 /* write INTCBAR - ioport */
920 pci_write_config_dword(dev, ITE_887x_INTCBAR,
922 ret = inb(inta_addr[i]);
924 /* ioport connected */
927 release_region(iobase->start, ITE_887x_IOSIZE);
934 printk(KERN_ERR "ite887x: could not find iobase\n");
938 /* start of undocumented type checking (see parport_pc.c) */
939 type = inb(iobase->start + 0x18) & 0x0f;
942 case 0x2: /* ITE8871 (1P) */
943 case 0xa: /* ITE8875 (1P) */
946 case 0xe: /* ITE8872 (2S1P) */
949 case 0x6: /* ITE8873 (1S) */
952 case 0x8: /* ITE8874 (2S) */
956 moan_device("Unknown ITE887x", dev);
960 /* configure all serial ports */
961 for (i = 0; i < ret; i++) {
962 /* read the I/O port from the device */
963 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
965 ioport &= 0x0000FF00; /* the actual base address */
966 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
967 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
968 ITE_887x_POSIO_IOSIZE_8 | ioport);
970 /* write the ioport to the UARTBAR */
971 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
972 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
973 uartbar |= (ioport << (16 * i)); /* set the ioport */
974 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
976 /* get current config */
977 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
978 /* disable interrupts (UARTx_Routing[3:0]) */
979 miscr &= ~(0xf << (12 - 4 * i));
980 /* activate the UART (UARTx_En) */
981 miscr |= 1 << (23 - i);
982 /* write new config with activated UART */
983 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
987 /* the device has no UARTs if we get here */
988 release_region(iobase->start, ITE_887x_IOSIZE);
994 static void __devexit pci_ite887x_exit(struct pci_dev *dev)
997 /* the ioport is bit 0-15 in POSIO0R */
998 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
1000 release_region(ioport, ITE_887x_IOSIZE);
1004 * Oxford Semiconductor Inc.
1005 * Check that device is part of the Tornado range of devices, then determine
1006 * the number of ports available on the device.
1008 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1011 unsigned long deviceID;
1012 unsigned int number_uarts = 0;
1014 /* OxSemi Tornado devices are all 0xCxxx */
1015 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1016 (dev->device & 0xF000) != 0xC000)
1019 p = pci_iomap(dev, 0, 5);
1023 deviceID = ioread32(p);
1024 /* Tornado device */
1025 if (deviceID == 0x07000200) {
1026 number_uarts = ioread8(p + 4);
1028 "%d ports detected on Oxford PCI Express device\n",
1031 pci_iounmap(dev, p);
1032 return number_uarts;
1035 static int pci_asix_setup(struct serial_private *priv,
1036 const struct pciserial_board *board,
1037 struct uart_8250_port *port, int idx)
1039 port->bugs |= UART_BUG_PARITY;
1040 return pci_default_setup(priv, board, port, idx);
1043 static int pci_default_setup(struct serial_private *priv,
1044 const struct pciserial_board *board,
1045 struct uart_8250_port *port, int idx)
1047 unsigned int bar, offset = board->first_offset, maxnr;
1049 bar = FL_GET_BASE(board->flags);
1050 if (board->flags & FL_BASE_BARS)
1053 offset += idx * board->uart_offset;
1055 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1056 (board->reg_shift + 3);
1058 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1061 return setup_port(priv, port, bar, offset, board->reg_shift);
1065 ce4100_serial_setup(struct serial_private *priv,
1066 const struct pciserial_board *board,
1067 struct uart_8250_port *port, int idx)
1071 ret = setup_port(priv, port, 0, 0, board->reg_shift);
1072 port->port.iotype = UPIO_MEM32;
1073 port->port.type = PORT_XSCALE;
1074 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1075 port->port.regshift = 2;
1081 pci_omegapci_setup(struct serial_private *priv,
1082 const struct pciserial_board *board,
1083 struct uart_8250_port *port, int idx)
1085 return setup_port(priv, port, 2, idx * 8, 0);
1088 static int skip_tx_en_setup(struct serial_private *priv,
1089 const struct pciserial_board *board,
1090 struct uart_8250_port *port, int idx)
1092 port->port.flags |= UPF_NO_TXEN_TEST;
1093 printk(KERN_DEBUG "serial8250: skipping TxEn test for device "
1094 "[%04x:%04x] subsystem [%04x:%04x]\n",
1097 priv->dev->subsystem_vendor,
1098 priv->dev->subsystem_device);
1100 return pci_default_setup(priv, board, port, idx);
1103 static void kt_handle_break(struct uart_port *p)
1105 struct uart_8250_port *up =
1106 container_of(p, struct uart_8250_port, port);
1108 * On receipt of a BI, serial device in Intel ME (Intel
1109 * management engine) needs to have its fifos cleared for sane
1110 * SOL (Serial Over Lan) output.
1112 serial8250_clear_and_reinit_fifos(up);
1115 static unsigned int kt_serial_in(struct uart_port *p, int offset)
1117 struct uart_8250_port *up =
1118 container_of(p, struct uart_8250_port, port);
1122 * When the Intel ME (management engine) gets reset its serial
1123 * port registers could return 0 momentarily. Functions like
1124 * serial8250_console_write, read and save the IER, perform
1125 * some operation and then restore it. In order to avoid
1126 * setting IER register inadvertently to 0, if the value read
1127 * is 0, double check with ier value in uart_8250_port and use
1128 * that instead. up->ier should be the same value as what is
1129 * currently configured.
1131 val = inb(p->iobase + offset);
1132 if (offset == UART_IER) {
1139 static int kt_serial_setup(struct serial_private *priv,
1140 const struct pciserial_board *board,
1141 struct uart_8250_port *port, int idx)
1143 port->port.flags |= UPF_BUG_THRE;
1144 port->port.serial_in = kt_serial_in;
1145 port->port.handle_break = kt_handle_break;
1146 return skip_tx_en_setup(priv, board, port, idx);
1149 static int pci_eg20t_init(struct pci_dev *dev)
1151 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1159 pci_xr17c154_setup(struct serial_private *priv,
1160 const struct pciserial_board *board,
1161 struct uart_8250_port *port, int idx)
1163 port->port.flags |= UPF_EXAR_EFR;
1164 return pci_default_setup(priv, board, port, idx);
1167 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
1168 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
1169 #define PCI_DEVICE_ID_OCTPRO 0x0001
1170 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
1171 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
1172 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
1173 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
1174 #define PCI_VENDOR_ID_ADVANTECH 0x13fe
1175 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1176 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1177 #define PCI_DEVICE_ID_TITAN_200I 0x8028
1178 #define PCI_DEVICE_ID_TITAN_400I 0x8048
1179 #define PCI_DEVICE_ID_TITAN_800I 0x8088
1180 #define PCI_DEVICE_ID_TITAN_800EH 0xA007
1181 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008
1182 #define PCI_DEVICE_ID_TITAN_400EH 0xA009
1183 #define PCI_DEVICE_ID_TITAN_100E 0xA010
1184 #define PCI_DEVICE_ID_TITAN_200E 0xA012
1185 #define PCI_DEVICE_ID_TITAN_400E 0xA013
1186 #define PCI_DEVICE_ID_TITAN_800E 0xA014
1187 #define PCI_DEVICE_ID_TITAN_200EI 0xA016
1188 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017
1189 #define PCI_DEVICE_ID_TITAN_400V3 0xA310
1190 #define PCI_DEVICE_ID_TITAN_410V3 0xA312
1191 #define PCI_DEVICE_ID_TITAN_800V3 0xA314
1192 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315
1193 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
1194 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
1195 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
1196 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
1197 #define PCI_VENDOR_ID_AGESTAR 0x5372
1198 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872
1199 #define PCI_VENDOR_ID_ASIX 0x9710
1201 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1202 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1205 * Master list of serial port init/setup/exit quirks.
1206 * This does not describe the general nature of the port.
1207 * (ie, baud base, number and location of ports, etc)
1209 * This list is ordered alphabetically by vendor then device.
1210 * Specific entries must come before more generic entries.
1212 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
1214 * ADDI-DATA GmbH communication cards <info@addi-data.com>
1217 .vendor = PCI_VENDOR_ID_ADDIDATA_OLD,
1218 .device = PCI_DEVICE_ID_ADDIDATA_APCI7800,
1219 .subvendor = PCI_ANY_ID,
1220 .subdevice = PCI_ANY_ID,
1221 .setup = addidata_apci7800_setup,
1224 * AFAVLAB cards - these may be called via parport_serial
1225 * It is not clear whether this applies to all products.
1228 .vendor = PCI_VENDOR_ID_AFAVLAB,
1229 .device = PCI_ANY_ID,
1230 .subvendor = PCI_ANY_ID,
1231 .subdevice = PCI_ANY_ID,
1232 .setup = afavlab_setup,
1238 .vendor = PCI_VENDOR_ID_HP,
1239 .device = PCI_DEVICE_ID_HP_DIVA,
1240 .subvendor = PCI_ANY_ID,
1241 .subdevice = PCI_ANY_ID,
1242 .init = pci_hp_diva_init,
1243 .setup = pci_hp_diva_setup,
1249 .vendor = PCI_VENDOR_ID_INTEL,
1250 .device = PCI_DEVICE_ID_INTEL_80960_RP,
1251 .subvendor = 0xe4bf,
1252 .subdevice = PCI_ANY_ID,
1253 .init = pci_inteli960ni_init,
1254 .setup = pci_default_setup,
1257 .vendor = PCI_VENDOR_ID_INTEL,
1258 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
1259 .subvendor = PCI_ANY_ID,
1260 .subdevice = PCI_ANY_ID,
1261 .setup = skip_tx_en_setup,
1264 .vendor = PCI_VENDOR_ID_INTEL,
1265 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
1266 .subvendor = PCI_ANY_ID,
1267 .subdevice = PCI_ANY_ID,
1268 .setup = skip_tx_en_setup,
1271 .vendor = PCI_VENDOR_ID_INTEL,
1272 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
1273 .subvendor = PCI_ANY_ID,
1274 .subdevice = PCI_ANY_ID,
1275 .setup = skip_tx_en_setup,
1278 .vendor = PCI_VENDOR_ID_INTEL,
1279 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
1280 .subvendor = PCI_ANY_ID,
1281 .subdevice = PCI_ANY_ID,
1282 .setup = ce4100_serial_setup,
1285 .vendor = PCI_VENDOR_ID_INTEL,
1286 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
1287 .subvendor = PCI_ANY_ID,
1288 .subdevice = PCI_ANY_ID,
1289 .setup = kt_serial_setup,
1295 .vendor = PCI_VENDOR_ID_ITE,
1296 .device = PCI_DEVICE_ID_ITE_8872,
1297 .subvendor = PCI_ANY_ID,
1298 .subdevice = PCI_ANY_ID,
1299 .init = pci_ite887x_init,
1300 .setup = pci_default_setup,
1301 .exit = __devexit_p(pci_ite887x_exit),
1304 * National Instruments
1307 .vendor = PCI_VENDOR_ID_NI,
1308 .device = PCI_DEVICE_ID_NI_PCI23216,
1309 .subvendor = PCI_ANY_ID,
1310 .subdevice = PCI_ANY_ID,
1311 .init = pci_ni8420_init,
1312 .setup = pci_default_setup,
1313 .exit = __devexit_p(pci_ni8420_exit),
1316 .vendor = PCI_VENDOR_ID_NI,
1317 .device = PCI_DEVICE_ID_NI_PCI2328,
1318 .subvendor = PCI_ANY_ID,
1319 .subdevice = PCI_ANY_ID,
1320 .init = pci_ni8420_init,
1321 .setup = pci_default_setup,
1322 .exit = __devexit_p(pci_ni8420_exit),
1325 .vendor = PCI_VENDOR_ID_NI,
1326 .device = PCI_DEVICE_ID_NI_PCI2324,
1327 .subvendor = PCI_ANY_ID,
1328 .subdevice = PCI_ANY_ID,
1329 .init = pci_ni8420_init,
1330 .setup = pci_default_setup,
1331 .exit = __devexit_p(pci_ni8420_exit),
1334 .vendor = PCI_VENDOR_ID_NI,
1335 .device = PCI_DEVICE_ID_NI_PCI2322,
1336 .subvendor = PCI_ANY_ID,
1337 .subdevice = PCI_ANY_ID,
1338 .init = pci_ni8420_init,
1339 .setup = pci_default_setup,
1340 .exit = __devexit_p(pci_ni8420_exit),
1343 .vendor = PCI_VENDOR_ID_NI,
1344 .device = PCI_DEVICE_ID_NI_PCI2324I,
1345 .subvendor = PCI_ANY_ID,
1346 .subdevice = PCI_ANY_ID,
1347 .init = pci_ni8420_init,
1348 .setup = pci_default_setup,
1349 .exit = __devexit_p(pci_ni8420_exit),
1352 .vendor = PCI_VENDOR_ID_NI,
1353 .device = PCI_DEVICE_ID_NI_PCI2322I,
1354 .subvendor = PCI_ANY_ID,
1355 .subdevice = PCI_ANY_ID,
1356 .init = pci_ni8420_init,
1357 .setup = pci_default_setup,
1358 .exit = __devexit_p(pci_ni8420_exit),
1361 .vendor = PCI_VENDOR_ID_NI,
1362 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
1363 .subvendor = PCI_ANY_ID,
1364 .subdevice = PCI_ANY_ID,
1365 .init = pci_ni8420_init,
1366 .setup = pci_default_setup,
1367 .exit = __devexit_p(pci_ni8420_exit),
1370 .vendor = PCI_VENDOR_ID_NI,
1371 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
1372 .subvendor = PCI_ANY_ID,
1373 .subdevice = PCI_ANY_ID,
1374 .init = pci_ni8420_init,
1375 .setup = pci_default_setup,
1376 .exit = __devexit_p(pci_ni8420_exit),
1379 .vendor = PCI_VENDOR_ID_NI,
1380 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
1381 .subvendor = PCI_ANY_ID,
1382 .subdevice = PCI_ANY_ID,
1383 .init = pci_ni8420_init,
1384 .setup = pci_default_setup,
1385 .exit = __devexit_p(pci_ni8420_exit),
1388 .vendor = PCI_VENDOR_ID_NI,
1389 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
1390 .subvendor = PCI_ANY_ID,
1391 .subdevice = PCI_ANY_ID,
1392 .init = pci_ni8420_init,
1393 .setup = pci_default_setup,
1394 .exit = __devexit_p(pci_ni8420_exit),
1397 .vendor = PCI_VENDOR_ID_NI,
1398 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
1399 .subvendor = PCI_ANY_ID,
1400 .subdevice = PCI_ANY_ID,
1401 .init = pci_ni8420_init,
1402 .setup = pci_default_setup,
1403 .exit = __devexit_p(pci_ni8420_exit),
1406 .vendor = PCI_VENDOR_ID_NI,
1407 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
1408 .subvendor = PCI_ANY_ID,
1409 .subdevice = PCI_ANY_ID,
1410 .init = pci_ni8420_init,
1411 .setup = pci_default_setup,
1412 .exit = __devexit_p(pci_ni8420_exit),
1415 .vendor = PCI_VENDOR_ID_NI,
1416 .device = PCI_ANY_ID,
1417 .subvendor = PCI_ANY_ID,
1418 .subdevice = PCI_ANY_ID,
1419 .init = pci_ni8430_init,
1420 .setup = pci_ni8430_setup,
1421 .exit = __devexit_p(pci_ni8430_exit),
1427 .vendor = PCI_VENDOR_ID_PANACOM,
1428 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
1429 .subvendor = PCI_ANY_ID,
1430 .subdevice = PCI_ANY_ID,
1431 .init = pci_plx9050_init,
1432 .setup = pci_default_setup,
1433 .exit = __devexit_p(pci_plx9050_exit),
1436 .vendor = PCI_VENDOR_ID_PANACOM,
1437 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
1438 .subvendor = PCI_ANY_ID,
1439 .subdevice = PCI_ANY_ID,
1440 .init = pci_plx9050_init,
1441 .setup = pci_default_setup,
1442 .exit = __devexit_p(pci_plx9050_exit),
1448 .vendor = PCI_VENDOR_ID_PLX,
1449 .device = PCI_DEVICE_ID_PLX_9030,
1450 .subvendor = PCI_SUBVENDOR_ID_PERLE,
1451 .subdevice = PCI_ANY_ID,
1452 .setup = pci_default_setup,
1455 .vendor = PCI_VENDOR_ID_PLX,
1456 .device = PCI_DEVICE_ID_PLX_9050,
1457 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
1458 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
1459 .init = pci_plx9050_init,
1460 .setup = pci_default_setup,
1461 .exit = __devexit_p(pci_plx9050_exit),
1464 .vendor = PCI_VENDOR_ID_PLX,
1465 .device = PCI_DEVICE_ID_PLX_9050,
1466 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
1467 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
1468 .init = pci_plx9050_init,
1469 .setup = pci_default_setup,
1470 .exit = __devexit_p(pci_plx9050_exit),
1473 .vendor = PCI_VENDOR_ID_PLX,
1474 .device = PCI_DEVICE_ID_PLX_9050,
1475 .subvendor = PCI_VENDOR_ID_PLX,
1476 .subdevice = PCI_SUBDEVICE_ID_UNKNOWN_0x1584,
1477 .init = pci_plx9050_init,
1478 .setup = pci_default_setup,
1479 .exit = __devexit_p(pci_plx9050_exit),
1482 .vendor = PCI_VENDOR_ID_PLX,
1483 .device = PCI_DEVICE_ID_PLX_ROMULUS,
1484 .subvendor = PCI_VENDOR_ID_PLX,
1485 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
1486 .init = pci_plx9050_init,
1487 .setup = pci_default_setup,
1488 .exit = __devexit_p(pci_plx9050_exit),
1491 * SBS Technologies, Inc., PMC-OCTALPRO 232
1494 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1495 .device = PCI_DEVICE_ID_OCTPRO,
1496 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1497 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
1500 .exit = __devexit_p(sbs_exit),
1503 * SBS Technologies, Inc., PMC-OCTALPRO 422
1506 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1507 .device = PCI_DEVICE_ID_OCTPRO,
1508 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1509 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
1512 .exit = __devexit_p(sbs_exit),
1515 * SBS Technologies, Inc., P-Octal 232
1518 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1519 .device = PCI_DEVICE_ID_OCTPRO,
1520 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1521 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
1524 .exit = __devexit_p(sbs_exit),
1527 * SBS Technologies, Inc., P-Octal 422
1530 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1531 .device = PCI_DEVICE_ID_OCTPRO,
1532 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1533 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
1536 .exit = __devexit_p(sbs_exit),
1539 * SIIG cards - these may be called via parport_serial
1542 .vendor = PCI_VENDOR_ID_SIIG,
1543 .device = PCI_ANY_ID,
1544 .subvendor = PCI_ANY_ID,
1545 .subdevice = PCI_ANY_ID,
1546 .init = pci_siig_init,
1547 .setup = pci_siig_setup,
1553 .vendor = PCI_VENDOR_ID_TITAN,
1554 .device = PCI_DEVICE_ID_TITAN_400L,
1555 .subvendor = PCI_ANY_ID,
1556 .subdevice = PCI_ANY_ID,
1557 .setup = titan_400l_800l_setup,
1560 .vendor = PCI_VENDOR_ID_TITAN,
1561 .device = PCI_DEVICE_ID_TITAN_800L,
1562 .subvendor = PCI_ANY_ID,
1563 .subdevice = PCI_ANY_ID,
1564 .setup = titan_400l_800l_setup,
1570 .vendor = PCI_VENDOR_ID_TIMEDIA,
1571 .device = PCI_DEVICE_ID_TIMEDIA_1889,
1572 .subvendor = PCI_VENDOR_ID_TIMEDIA,
1573 .subdevice = PCI_ANY_ID,
1574 .probe = pci_timedia_probe,
1575 .init = pci_timedia_init,
1576 .setup = pci_timedia_setup,
1579 .vendor = PCI_VENDOR_ID_TIMEDIA,
1580 .device = PCI_ANY_ID,
1581 .subvendor = PCI_ANY_ID,
1582 .subdevice = PCI_ANY_ID,
1583 .setup = pci_timedia_setup,
1589 .vendor = PCI_VENDOR_ID_EXAR,
1590 .device = PCI_DEVICE_ID_EXAR_XR17C152,
1591 .subvendor = PCI_ANY_ID,
1592 .subdevice = PCI_ANY_ID,
1593 .setup = pci_xr17c154_setup,
1596 .vendor = PCI_VENDOR_ID_EXAR,
1597 .device = PCI_DEVICE_ID_EXAR_XR17C154,
1598 .subvendor = PCI_ANY_ID,
1599 .subdevice = PCI_ANY_ID,
1600 .setup = pci_xr17c154_setup,
1603 .vendor = PCI_VENDOR_ID_EXAR,
1604 .device = PCI_DEVICE_ID_EXAR_XR17C158,
1605 .subvendor = PCI_ANY_ID,
1606 .subdevice = PCI_ANY_ID,
1607 .setup = pci_xr17c154_setup,
1613 .vendor = PCI_VENDOR_ID_XIRCOM,
1614 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
1615 .subvendor = PCI_ANY_ID,
1616 .subdevice = PCI_ANY_ID,
1617 .init = pci_xircom_init,
1618 .setup = pci_default_setup,
1621 * Netmos cards - these may be called via parport_serial
1624 .vendor = PCI_VENDOR_ID_NETMOS,
1625 .device = PCI_ANY_ID,
1626 .subvendor = PCI_ANY_ID,
1627 .subdevice = PCI_ANY_ID,
1628 .init = pci_netmos_init,
1629 .setup = pci_netmos_9900_setup,
1632 * For Oxford Semiconductor Tornado based devices
1635 .vendor = PCI_VENDOR_ID_OXSEMI,
1636 .device = PCI_ANY_ID,
1637 .subvendor = PCI_ANY_ID,
1638 .subdevice = PCI_ANY_ID,
1639 .init = pci_oxsemi_tornado_init,
1640 .setup = pci_default_setup,
1643 .vendor = PCI_VENDOR_ID_MAINPINE,
1644 .device = PCI_ANY_ID,
1645 .subvendor = PCI_ANY_ID,
1646 .subdevice = PCI_ANY_ID,
1647 .init = pci_oxsemi_tornado_init,
1648 .setup = pci_default_setup,
1651 .vendor = PCI_VENDOR_ID_DIGI,
1652 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
1653 .subvendor = PCI_SUBVENDOR_ID_IBM,
1654 .subdevice = PCI_ANY_ID,
1655 .init = pci_oxsemi_tornado_init,
1656 .setup = pci_default_setup,
1659 .vendor = PCI_VENDOR_ID_INTEL,
1661 .subvendor = PCI_ANY_ID,
1662 .subdevice = PCI_ANY_ID,
1663 .init = pci_eg20t_init,
1664 .setup = pci_default_setup,
1667 .vendor = PCI_VENDOR_ID_INTEL,
1669 .subvendor = PCI_ANY_ID,
1670 .subdevice = PCI_ANY_ID,
1671 .init = pci_eg20t_init,
1672 .setup = pci_default_setup,
1675 .vendor = PCI_VENDOR_ID_INTEL,
1677 .subvendor = PCI_ANY_ID,
1678 .subdevice = PCI_ANY_ID,
1679 .init = pci_eg20t_init,
1680 .setup = pci_default_setup,
1683 .vendor = PCI_VENDOR_ID_INTEL,
1685 .subvendor = PCI_ANY_ID,
1686 .subdevice = PCI_ANY_ID,
1687 .init = pci_eg20t_init,
1688 .setup = pci_default_setup,
1693 .subvendor = PCI_ANY_ID,
1694 .subdevice = PCI_ANY_ID,
1695 .init = pci_eg20t_init,
1696 .setup = pci_default_setup,
1701 .subvendor = PCI_ANY_ID,
1702 .subdevice = PCI_ANY_ID,
1703 .init = pci_eg20t_init,
1704 .setup = pci_default_setup,
1709 .subvendor = PCI_ANY_ID,
1710 .subdevice = PCI_ANY_ID,
1711 .init = pci_eg20t_init,
1712 .setup = pci_default_setup,
1717 .subvendor = PCI_ANY_ID,
1718 .subdevice = PCI_ANY_ID,
1719 .init = pci_eg20t_init,
1720 .setup = pci_default_setup,
1725 .subvendor = PCI_ANY_ID,
1726 .subdevice = PCI_ANY_ID,
1727 .init = pci_eg20t_init,
1728 .setup = pci_default_setup,
1731 * Cronyx Omega PCI (PLX-chip based)
1734 .vendor = PCI_VENDOR_ID_PLX,
1735 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
1736 .subvendor = PCI_ANY_ID,
1737 .subdevice = PCI_ANY_ID,
1738 .setup = pci_omegapci_setup,
1741 * ASIX devices with FIFO bug
1744 .vendor = PCI_VENDOR_ID_ASIX,
1745 .device = PCI_ANY_ID,
1746 .subvendor = PCI_ANY_ID,
1747 .subdevice = PCI_ANY_ID,
1748 .setup = pci_asix_setup,
1751 * Default "match everything" terminator entry
1754 .vendor = PCI_ANY_ID,
1755 .device = PCI_ANY_ID,
1756 .subvendor = PCI_ANY_ID,
1757 .subdevice = PCI_ANY_ID,
1758 .setup = pci_default_setup,
1762 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
1764 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
1767 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
1769 struct pci_serial_quirk *quirk;
1771 for (quirk = pci_serial_quirks; ; quirk++)
1772 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
1773 quirk_id_matches(quirk->device, dev->device) &&
1774 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
1775 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
1780 static inline int get_pci_irq(struct pci_dev *dev,
1781 const struct pciserial_board *board)
1783 if (board->flags & FL_NOIRQ)
1790 * This is the configuration table for all of the PCI serial boards
1791 * which we support. It is directly indexed by the pci_board_num_t enum
1792 * value, which is encoded in the pci_device_id PCI probe table's
1793 * driver_data member.
1795 * The makeup of these names are:
1796 * pbn_bn{_bt}_n_baud{_offsetinhex}
1798 * bn = PCI BAR number
1799 * bt = Index using PCI BARs
1800 * n = number of serial ports
1802 * offsetinhex = offset for each sequential port (in hex)
1804 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
1806 * Please note: in theory if n = 1, _bt infix should make no difference.
1807 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
1809 enum pci_board_num_t {
1829 pbn_b0_2_1843200_200,
1830 pbn_b0_4_1843200_200,
1831 pbn_b0_8_1843200_200,
1905 * Board-specific versions.
1912 pbn_oxsemi_1_4000000,
1913 pbn_oxsemi_2_4000000,
1914 pbn_oxsemi_4_4000000,
1915 pbn_oxsemi_8_4000000,
1925 pbn_exar_ibm_saturn,
1931 pbn_ADDIDATA_PCIe_1_3906250,
1932 pbn_ADDIDATA_PCIe_2_3906250,
1933 pbn_ADDIDATA_PCIe_4_3906250,
1934 pbn_ADDIDATA_PCIe_8_3906250,
1935 pbn_ce4100_1_115200,
1937 pbn_NETMOS9900_2s_115200,
1941 * uart_offset - the space between channels
1942 * reg_shift - describes how the UART registers are mapped
1943 * to PCI memory by the card.
1944 * For example IER register on SBS, Inc. PMC-OctPro is located at
1945 * offset 0x10 from the UART base, while UART_IER is defined as 1
1946 * in include/linux/serial_reg.h,
1947 * see first lines of serial_in() and serial_out() in 8250.c
1950 static struct pciserial_board pci_boards[] __devinitdata = {
1954 .base_baud = 115200,
1957 [pbn_b0_1_115200] = {
1960 .base_baud = 115200,
1963 [pbn_b0_2_115200] = {
1966 .base_baud = 115200,
1969 [pbn_b0_4_115200] = {
1972 .base_baud = 115200,
1975 [pbn_b0_5_115200] = {
1978 .base_baud = 115200,
1981 [pbn_b0_8_115200] = {
1984 .base_baud = 115200,
1987 [pbn_b0_1_921600] = {
1990 .base_baud = 921600,
1993 [pbn_b0_2_921600] = {
1996 .base_baud = 921600,
1999 [pbn_b0_4_921600] = {
2002 .base_baud = 921600,
2006 [pbn_b0_2_1130000] = {
2009 .base_baud = 1130000,
2013 [pbn_b0_4_1152000] = {
2016 .base_baud = 1152000,
2020 [pbn_b0_2_1843200] = {
2023 .base_baud = 1843200,
2026 [pbn_b0_4_1843200] = {
2029 .base_baud = 1843200,
2033 [pbn_b0_2_1843200_200] = {
2036 .base_baud = 1843200,
2037 .uart_offset = 0x200,
2039 [pbn_b0_4_1843200_200] = {
2042 .base_baud = 1843200,
2043 .uart_offset = 0x200,
2045 [pbn_b0_8_1843200_200] = {
2048 .base_baud = 1843200,
2049 .uart_offset = 0x200,
2051 [pbn_b0_1_4000000] = {
2054 .base_baud = 4000000,
2058 [pbn_b0_bt_1_115200] = {
2059 .flags = FL_BASE0|FL_BASE_BARS,
2061 .base_baud = 115200,
2064 [pbn_b0_bt_2_115200] = {
2065 .flags = FL_BASE0|FL_BASE_BARS,
2067 .base_baud = 115200,
2070 [pbn_b0_bt_4_115200] = {
2071 .flags = FL_BASE0|FL_BASE_BARS,
2073 .base_baud = 115200,
2076 [pbn_b0_bt_8_115200] = {
2077 .flags = FL_BASE0|FL_BASE_BARS,
2079 .base_baud = 115200,
2083 [pbn_b0_bt_1_460800] = {
2084 .flags = FL_BASE0|FL_BASE_BARS,
2086 .base_baud = 460800,
2089 [pbn_b0_bt_2_460800] = {
2090 .flags = FL_BASE0|FL_BASE_BARS,
2092 .base_baud = 460800,
2095 [pbn_b0_bt_4_460800] = {
2096 .flags = FL_BASE0|FL_BASE_BARS,
2098 .base_baud = 460800,
2102 [pbn_b0_bt_1_921600] = {
2103 .flags = FL_BASE0|FL_BASE_BARS,
2105 .base_baud = 921600,
2108 [pbn_b0_bt_2_921600] = {
2109 .flags = FL_BASE0|FL_BASE_BARS,
2111 .base_baud = 921600,
2114 [pbn_b0_bt_4_921600] = {
2115 .flags = FL_BASE0|FL_BASE_BARS,
2117 .base_baud = 921600,
2120 [pbn_b0_bt_8_921600] = {
2121 .flags = FL_BASE0|FL_BASE_BARS,
2123 .base_baud = 921600,
2127 [pbn_b1_1_115200] = {
2130 .base_baud = 115200,
2133 [pbn_b1_2_115200] = {
2136 .base_baud = 115200,
2139 [pbn_b1_4_115200] = {
2142 .base_baud = 115200,
2145 [pbn_b1_8_115200] = {
2148 .base_baud = 115200,
2151 [pbn_b1_16_115200] = {
2154 .base_baud = 115200,
2158 [pbn_b1_1_921600] = {
2161 .base_baud = 921600,
2164 [pbn_b1_2_921600] = {
2167 .base_baud = 921600,
2170 [pbn_b1_4_921600] = {
2173 .base_baud = 921600,
2176 [pbn_b1_8_921600] = {
2179 .base_baud = 921600,
2182 [pbn_b1_2_1250000] = {
2185 .base_baud = 1250000,
2189 [pbn_b1_bt_1_115200] = {
2190 .flags = FL_BASE1|FL_BASE_BARS,
2192 .base_baud = 115200,
2195 [pbn_b1_bt_2_115200] = {
2196 .flags = FL_BASE1|FL_BASE_BARS,
2198 .base_baud = 115200,
2201 [pbn_b1_bt_4_115200] = {
2202 .flags = FL_BASE1|FL_BASE_BARS,
2204 .base_baud = 115200,
2208 [pbn_b1_bt_2_921600] = {
2209 .flags = FL_BASE1|FL_BASE_BARS,
2211 .base_baud = 921600,
2215 [pbn_b1_1_1382400] = {
2218 .base_baud = 1382400,
2221 [pbn_b1_2_1382400] = {
2224 .base_baud = 1382400,
2227 [pbn_b1_4_1382400] = {
2230 .base_baud = 1382400,
2233 [pbn_b1_8_1382400] = {
2236 .base_baud = 1382400,
2240 [pbn_b2_1_115200] = {
2243 .base_baud = 115200,
2246 [pbn_b2_2_115200] = {
2249 .base_baud = 115200,
2252 [pbn_b2_4_115200] = {
2255 .base_baud = 115200,
2258 [pbn_b2_8_115200] = {
2261 .base_baud = 115200,
2265 [pbn_b2_1_460800] = {
2268 .base_baud = 460800,
2271 [pbn_b2_4_460800] = {
2274 .base_baud = 460800,
2277 [pbn_b2_8_460800] = {
2280 .base_baud = 460800,
2283 [pbn_b2_16_460800] = {
2286 .base_baud = 460800,
2290 [pbn_b2_1_921600] = {
2293 .base_baud = 921600,
2296 [pbn_b2_4_921600] = {
2299 .base_baud = 921600,
2302 [pbn_b2_8_921600] = {
2305 .base_baud = 921600,
2309 [pbn_b2_8_1152000] = {
2312 .base_baud = 1152000,
2316 [pbn_b2_bt_1_115200] = {
2317 .flags = FL_BASE2|FL_BASE_BARS,
2319 .base_baud = 115200,
2322 [pbn_b2_bt_2_115200] = {
2323 .flags = FL_BASE2|FL_BASE_BARS,
2325 .base_baud = 115200,
2328 [pbn_b2_bt_4_115200] = {
2329 .flags = FL_BASE2|FL_BASE_BARS,
2331 .base_baud = 115200,
2335 [pbn_b2_bt_2_921600] = {
2336 .flags = FL_BASE2|FL_BASE_BARS,
2338 .base_baud = 921600,
2341 [pbn_b2_bt_4_921600] = {
2342 .flags = FL_BASE2|FL_BASE_BARS,
2344 .base_baud = 921600,
2348 [pbn_b3_2_115200] = {
2351 .base_baud = 115200,
2354 [pbn_b3_4_115200] = {
2357 .base_baud = 115200,
2360 [pbn_b3_8_115200] = {
2363 .base_baud = 115200,
2367 [pbn_b4_bt_2_921600] = {
2370 .base_baud = 921600,
2373 [pbn_b4_bt_4_921600] = {
2376 .base_baud = 921600,
2379 [pbn_b4_bt_8_921600] = {
2382 .base_baud = 921600,
2387 * Entries following this are board-specific.
2396 .base_baud = 921600,
2397 .uart_offset = 0x400,
2401 .flags = FL_BASE2|FL_BASE_BARS,
2403 .base_baud = 921600,
2404 .uart_offset = 0x400,
2408 .flags = FL_BASE2|FL_BASE_BARS,
2410 .base_baud = 921600,
2411 .uart_offset = 0x400,
2415 /* I think this entry is broken - the first_offset looks wrong --rmk */
2416 [pbn_plx_romulus] = {
2419 .base_baud = 921600,
2420 .uart_offset = 8 << 2,
2422 .first_offset = 0x03,
2426 * This board uses the size of PCI Base region 0 to
2427 * signal now many ports are available
2430 .flags = FL_BASE0|FL_REGION_SZ_CAP,
2432 .base_baud = 115200,
2435 [pbn_oxsemi_1_4000000] = {
2438 .base_baud = 4000000,
2439 .uart_offset = 0x200,
2440 .first_offset = 0x1000,
2442 [pbn_oxsemi_2_4000000] = {
2445 .base_baud = 4000000,
2446 .uart_offset = 0x200,
2447 .first_offset = 0x1000,
2449 [pbn_oxsemi_4_4000000] = {
2452 .base_baud = 4000000,
2453 .uart_offset = 0x200,
2454 .first_offset = 0x1000,
2456 [pbn_oxsemi_8_4000000] = {
2459 .base_baud = 4000000,
2460 .uart_offset = 0x200,
2461 .first_offset = 0x1000,
2466 * EKF addition for i960 Boards form EKF with serial port.
2469 [pbn_intel_i960] = {
2472 .base_baud = 921600,
2473 .uart_offset = 8 << 2,
2475 .first_offset = 0x10000,
2478 .flags = FL_BASE0|FL_NOIRQ,
2480 .base_baud = 458333,
2483 .first_offset = 0x20178,
2487 * Computone - uses IOMEM.
2489 [pbn_computone_4] = {
2492 .base_baud = 921600,
2493 .uart_offset = 0x40,
2495 .first_offset = 0x200,
2497 [pbn_computone_6] = {
2500 .base_baud = 921600,
2501 .uart_offset = 0x40,
2503 .first_offset = 0x200,
2505 [pbn_computone_8] = {
2508 .base_baud = 921600,
2509 .uart_offset = 0x40,
2511 .first_offset = 0x200,
2516 .base_baud = 460800,
2521 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2522 * Only basic 16550A support.
2523 * XR17C15[24] are not tested, but they should work.
2525 [pbn_exar_XR17C152] = {
2528 .base_baud = 921600,
2529 .uart_offset = 0x200,
2531 [pbn_exar_XR17C154] = {
2534 .base_baud = 921600,
2535 .uart_offset = 0x200,
2537 [pbn_exar_XR17C158] = {
2540 .base_baud = 921600,
2541 .uart_offset = 0x200,
2543 [pbn_exar_ibm_saturn] = {
2546 .base_baud = 921600,
2547 .uart_offset = 0x200,
2551 * PA Semi PWRficient PA6T-1682M on-chip UART
2553 [pbn_pasemi_1682M] = {
2556 .base_baud = 8333333,
2559 * National Instruments 843x
2564 .base_baud = 3686400,
2565 .uart_offset = 0x10,
2566 .first_offset = 0x800,
2571 .base_baud = 3686400,
2572 .uart_offset = 0x10,
2573 .first_offset = 0x800,
2578 .base_baud = 3686400,
2579 .uart_offset = 0x10,
2580 .first_offset = 0x800,
2585 .base_baud = 3686400,
2586 .uart_offset = 0x10,
2587 .first_offset = 0x800,
2590 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
2592 [pbn_ADDIDATA_PCIe_1_3906250] = {
2595 .base_baud = 3906250,
2596 .uart_offset = 0x200,
2597 .first_offset = 0x1000,
2599 [pbn_ADDIDATA_PCIe_2_3906250] = {
2602 .base_baud = 3906250,
2603 .uart_offset = 0x200,
2604 .first_offset = 0x1000,
2606 [pbn_ADDIDATA_PCIe_4_3906250] = {
2609 .base_baud = 3906250,
2610 .uart_offset = 0x200,
2611 .first_offset = 0x1000,
2613 [pbn_ADDIDATA_PCIe_8_3906250] = {
2616 .base_baud = 3906250,
2617 .uart_offset = 0x200,
2618 .first_offset = 0x1000,
2620 [pbn_ce4100_1_115200] = {
2623 .base_baud = 921600,
2629 .base_baud = 115200,
2630 .uart_offset = 0x200,
2632 [pbn_NETMOS9900_2s_115200] = {
2635 .base_baud = 115200,
2639 static const struct pci_device_id softmodem_blacklist[] = {
2640 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
2641 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
2642 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
2646 * Given a complete unknown PCI device, try to use some heuristics to
2647 * guess what the configuration might be, based on the pitiful PCI
2648 * serial specs. Returns 0 on success, 1 on failure.
2650 static int __devinit
2651 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
2653 const struct pci_device_id *blacklist;
2654 int num_iomem, num_port, first_port = -1, i;
2657 * If it is not a communications device or the programming
2658 * interface is greater than 6, give up.
2660 * (Should we try to make guesses for multiport serial devices
2663 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
2664 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
2665 (dev->class & 0xff) > 6)
2669 * Do not access blacklisted devices that are known not to
2670 * feature serial ports.
2672 for (blacklist = softmodem_blacklist;
2673 blacklist < softmodem_blacklist + ARRAY_SIZE(softmodem_blacklist);
2675 if (dev->vendor == blacklist->vendor &&
2676 dev->device == blacklist->device)
2680 num_iomem = num_port = 0;
2681 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2682 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
2684 if (first_port == -1)
2687 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
2692 * If there is 1 or 0 iomem regions, and exactly one port,
2693 * use it. We guess the number of ports based on the IO
2696 if (num_iomem <= 1 && num_port == 1) {
2697 board->flags = first_port;
2698 board->num_ports = pci_resource_len(dev, first_port) / 8;
2703 * Now guess if we've got a board which indexes by BARs.
2704 * Each IO BAR should be 8 bytes, and they should follow
2709 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2710 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
2711 pci_resource_len(dev, i) == 8 &&
2712 (first_port == -1 || (first_port + num_port) == i)) {
2714 if (first_port == -1)
2720 board->flags = first_port | FL_BASE_BARS;
2721 board->num_ports = num_port;
2729 serial_pci_matches(const struct pciserial_board *board,
2730 const struct pciserial_board *guessed)
2733 board->num_ports == guessed->num_ports &&
2734 board->base_baud == guessed->base_baud &&
2735 board->uart_offset == guessed->uart_offset &&
2736 board->reg_shift == guessed->reg_shift &&
2737 board->first_offset == guessed->first_offset;
2740 struct serial_private *
2741 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
2743 struct uart_8250_port uart;
2744 struct serial_private *priv;
2745 struct pci_serial_quirk *quirk;
2746 int rc, nr_ports, i;
2748 nr_ports = board->num_ports;
2751 * Find an init and setup quirks.
2753 quirk = find_quirk(dev);
2756 * Run the new-style initialization function.
2757 * The initialization function returns:
2759 * 0 - use board->num_ports
2760 * >0 - number of ports
2763 rc = quirk->init(dev);
2772 priv = kzalloc(sizeof(struct serial_private) +
2773 sizeof(unsigned int) * nr_ports,
2776 priv = ERR_PTR(-ENOMEM);
2781 priv->quirk = quirk;
2783 memset(&uart, 0, sizeof(uart));
2784 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
2785 uart.port.uartclk = board->base_baud * 16;
2786 uart.port.irq = get_pci_irq(dev, board);
2787 uart.port.dev = &dev->dev;
2789 for (i = 0; i < nr_ports; i++) {
2790 if (quirk->setup(priv, board, &uart, i))
2793 #ifdef SERIAL_DEBUG_PCI
2794 printk(KERN_DEBUG "Setup PCI port: port %lx, irq %d, type %d\n",
2795 uart.port.iobase, uart.port.irq, uart.port.iotype);
2798 priv->line[i] = serial8250_register_8250_port(&uart);
2799 if (priv->line[i] < 0) {
2800 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
2813 EXPORT_SYMBOL_GPL(pciserial_init_ports);
2815 void pciserial_remove_ports(struct serial_private *priv)
2817 struct pci_serial_quirk *quirk;
2820 for (i = 0; i < priv->nr; i++)
2821 serial8250_unregister_port(priv->line[i]);
2823 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2824 if (priv->remapped_bar[i])
2825 iounmap(priv->remapped_bar[i]);
2826 priv->remapped_bar[i] = NULL;
2830 * Find the exit quirks.
2832 quirk = find_quirk(priv->dev);
2834 quirk->exit(priv->dev);
2838 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
2840 void pciserial_suspend_ports(struct serial_private *priv)
2844 for (i = 0; i < priv->nr; i++)
2845 if (priv->line[i] >= 0)
2846 serial8250_suspend_port(priv->line[i]);
2849 * Ensure that every init quirk is properly torn down
2851 if (priv->quirk->exit)
2852 priv->quirk->exit(priv->dev);
2854 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
2856 void pciserial_resume_ports(struct serial_private *priv)
2861 * Ensure that the board is correctly configured.
2863 if (priv->quirk->init)
2864 priv->quirk->init(priv->dev);
2866 for (i = 0; i < priv->nr; i++)
2867 if (priv->line[i] >= 0)
2868 serial8250_resume_port(priv->line[i]);
2870 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
2873 * Probe one serial board. Unfortunately, there is no rhyme nor reason
2874 * to the arrangement of serial ports on a PCI card.
2876 static int __devinit
2877 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
2879 struct pci_serial_quirk *quirk;
2880 struct serial_private *priv;
2881 const struct pciserial_board *board;
2882 struct pciserial_board tmp;
2885 quirk = find_quirk(dev);
2887 rc = quirk->probe(dev);
2892 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
2893 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
2898 board = &pci_boards[ent->driver_data];
2900 rc = pci_enable_device(dev);
2901 pci_save_state(dev);
2905 if (ent->driver_data == pbn_default) {
2907 * Use a copy of the pci_board entry for this;
2908 * avoid changing entries in the table.
2910 memcpy(&tmp, board, sizeof(struct pciserial_board));
2914 * We matched one of our class entries. Try to
2915 * determine the parameters of this board.
2917 rc = serial_pci_guess_board(dev, &tmp);
2922 * We matched an explicit entry. If we are able to
2923 * detect this boards settings with our heuristic,
2924 * then we no longer need this entry.
2926 memcpy(&tmp, &pci_boards[pbn_default],
2927 sizeof(struct pciserial_board));
2928 rc = serial_pci_guess_board(dev, &tmp);
2929 if (rc == 0 && serial_pci_matches(board, &tmp))
2930 moan_device("Redundant entry in serial pci_table.",
2934 priv = pciserial_init_ports(dev, board);
2935 if (!IS_ERR(priv)) {
2936 pci_set_drvdata(dev, priv);
2943 pci_disable_device(dev);
2947 static void __devexit pciserial_remove_one(struct pci_dev *dev)
2949 struct serial_private *priv = pci_get_drvdata(dev);
2951 pci_set_drvdata(dev, NULL);
2953 pciserial_remove_ports(priv);
2955 pci_disable_device(dev);
2959 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
2961 struct serial_private *priv = pci_get_drvdata(dev);
2964 pciserial_suspend_ports(priv);
2966 pci_save_state(dev);
2967 pci_set_power_state(dev, pci_choose_state(dev, state));
2971 static int pciserial_resume_one(struct pci_dev *dev)
2974 struct serial_private *priv = pci_get_drvdata(dev);
2976 pci_set_power_state(dev, PCI_D0);
2977 pci_restore_state(dev);
2981 * The device may have been disabled. Re-enable it.
2983 err = pci_enable_device(dev);
2984 /* FIXME: We cannot simply error out here */
2986 printk(KERN_ERR "pciserial: Unable to re-enable ports, trying to continue.\n");
2987 pciserial_resume_ports(priv);
2993 static struct pci_device_id serial_pci_tbl[] = {
2994 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
2995 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
2996 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
2998 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2999 PCI_SUBVENDOR_ID_CONNECT_TECH,
3000 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
3002 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3003 PCI_SUBVENDOR_ID_CONNECT_TECH,
3004 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
3006 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3007 PCI_SUBVENDOR_ID_CONNECT_TECH,
3008 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
3010 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3011 PCI_SUBVENDOR_ID_CONNECT_TECH,
3012 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
3014 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3015 PCI_SUBVENDOR_ID_CONNECT_TECH,
3016 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
3018 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3019 PCI_SUBVENDOR_ID_CONNECT_TECH,
3020 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
3022 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3023 PCI_SUBVENDOR_ID_CONNECT_TECH,
3024 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
3026 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3027 PCI_SUBVENDOR_ID_CONNECT_TECH,
3028 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
3030 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3031 PCI_SUBVENDOR_ID_CONNECT_TECH,
3032 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
3034 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3035 PCI_SUBVENDOR_ID_CONNECT_TECH,
3036 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
3038 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3039 PCI_SUBVENDOR_ID_CONNECT_TECH,
3040 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
3042 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3043 PCI_SUBVENDOR_ID_CONNECT_TECH,
3044 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
3046 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3047 PCI_SUBVENDOR_ID_CONNECT_TECH,
3048 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
3050 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3051 PCI_SUBVENDOR_ID_CONNECT_TECH,
3052 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
3054 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3055 PCI_SUBVENDOR_ID_CONNECT_TECH,
3056 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
3058 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3059 PCI_SUBVENDOR_ID_CONNECT_TECH,
3060 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
3062 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3063 PCI_SUBVENDOR_ID_CONNECT_TECH,
3064 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
3066 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3067 PCI_VENDOR_ID_AFAVLAB,
3068 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
3070 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3071 PCI_SUBVENDOR_ID_CONNECT_TECH,
3072 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
3073 pbn_b0_2_1843200_200 },
3074 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3075 PCI_SUBVENDOR_ID_CONNECT_TECH,
3076 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
3077 pbn_b0_4_1843200_200 },
3078 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3079 PCI_SUBVENDOR_ID_CONNECT_TECH,
3080 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
3081 pbn_b0_8_1843200_200 },
3082 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3083 PCI_SUBVENDOR_ID_CONNECT_TECH,
3084 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
3085 pbn_b0_2_1843200_200 },
3086 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3087 PCI_SUBVENDOR_ID_CONNECT_TECH,
3088 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
3089 pbn_b0_4_1843200_200 },
3090 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3091 PCI_SUBVENDOR_ID_CONNECT_TECH,
3092 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
3093 pbn_b0_8_1843200_200 },
3094 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3095 PCI_SUBVENDOR_ID_CONNECT_TECH,
3096 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
3097 pbn_b0_2_1843200_200 },
3098 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3099 PCI_SUBVENDOR_ID_CONNECT_TECH,
3100 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
3101 pbn_b0_4_1843200_200 },
3102 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3103 PCI_SUBVENDOR_ID_CONNECT_TECH,
3104 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
3105 pbn_b0_8_1843200_200 },
3106 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3107 PCI_SUBVENDOR_ID_CONNECT_TECH,
3108 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
3109 pbn_b0_2_1843200_200 },
3110 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3111 PCI_SUBVENDOR_ID_CONNECT_TECH,
3112 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
3113 pbn_b0_4_1843200_200 },
3114 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3115 PCI_SUBVENDOR_ID_CONNECT_TECH,
3116 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
3117 pbn_b0_8_1843200_200 },
3118 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3119 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
3120 0, 0, pbn_exar_ibm_saturn },
3122 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
3123 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3124 pbn_b2_bt_1_115200 },
3125 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
3126 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3127 pbn_b2_bt_2_115200 },
3128 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
3129 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3130 pbn_b2_bt_4_115200 },
3131 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
3132 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3133 pbn_b2_bt_2_115200 },
3134 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
3135 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3136 pbn_b2_bt_4_115200 },
3137 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
3138 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3140 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
3141 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3143 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
3144 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3147 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
3148 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3149 pbn_b2_bt_2_115200 },
3150 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
3151 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3152 pbn_b2_bt_2_921600 },
3154 * VScom SPCOM800, from sl@s.pl
3156 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
3157 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3159 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
3160 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3162 /* Unknown card - subdevice 0x1584 */
3163 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3165 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
3167 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3168 PCI_SUBVENDOR_ID_KEYSPAN,
3169 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
3171 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
3172 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3174 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
3175 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3177 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3178 PCI_VENDOR_ID_ESDGMBH,
3179 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
3181 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3182 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3183 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
3185 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3186 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3187 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
3189 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3190 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3191 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
3193 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3194 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3195 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
3197 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3198 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
3199 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
3201 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3202 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
3203 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
3205 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3206 PCI_SUBVENDOR_ID_EXSYS,
3207 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
3210 * Megawolf Romulus PCI Serial Card, from Mike Hudson
3213 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
3214 0x10b5, 0x106a, 0, 0,
3216 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
3217 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3219 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
3220 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3222 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
3223 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3225 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
3226 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3228 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
3229 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
3232 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3233 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
3236 { PCI_VENDOR_ID_OXSEMI, 0x9505,
3237 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3238 pbn_b0_bt_2_921600 },
3241 * The below card is a little controversial since it is the
3242 * subject of a PCI vendor/device ID clash. (See
3243 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
3244 * For now just used the hex ID 0x950a.
3246 { PCI_VENDOR_ID_OXSEMI, 0x950a,
3247 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_SERIAL, 0, 0,
3249 { PCI_VENDOR_ID_OXSEMI, 0x950a,
3250 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3252 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
3253 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
3255 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3256 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3258 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
3259 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3260 pbn_b0_bt_2_921600 },
3261 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
3262 PCI_ANY_ID , PCI_ANY_ID, 0, 0,
3266 * Oxford Semiconductor Inc. Tornado PCI express device range.
3268 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
3269 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3271 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
3272 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3274 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
3275 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3276 pbn_oxsemi_1_4000000 },
3277 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
3278 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3279 pbn_oxsemi_1_4000000 },
3280 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
3281 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3283 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
3284 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3286 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
3287 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3288 pbn_oxsemi_1_4000000 },
3289 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
3290 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3291 pbn_oxsemi_1_4000000 },
3292 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
3293 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3295 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
3296 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3298 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
3299 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3301 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
3302 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3304 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
3305 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3306 pbn_oxsemi_2_4000000 },
3307 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
3308 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3309 pbn_oxsemi_2_4000000 },
3310 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
3311 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3312 pbn_oxsemi_4_4000000 },
3313 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
3314 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3315 pbn_oxsemi_4_4000000 },
3316 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
3317 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3318 pbn_oxsemi_8_4000000 },
3319 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
3320 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3321 pbn_oxsemi_8_4000000 },
3322 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
3323 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3324 pbn_oxsemi_1_4000000 },
3325 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
3326 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3327 pbn_oxsemi_1_4000000 },
3328 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
3329 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3330 pbn_oxsemi_1_4000000 },
3331 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
3332 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3333 pbn_oxsemi_1_4000000 },
3334 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
3335 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3336 pbn_oxsemi_1_4000000 },
3337 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
3338 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3339 pbn_oxsemi_1_4000000 },
3340 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
3341 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3342 pbn_oxsemi_1_4000000 },
3343 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
3344 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3345 pbn_oxsemi_1_4000000 },
3346 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
3347 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3348 pbn_oxsemi_1_4000000 },
3349 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
3350 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3351 pbn_oxsemi_1_4000000 },
3352 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
3353 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3354 pbn_oxsemi_1_4000000 },
3355 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
3356 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3357 pbn_oxsemi_1_4000000 },
3358 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
3359 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3360 pbn_oxsemi_1_4000000 },
3361 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
3362 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3363 pbn_oxsemi_1_4000000 },
3364 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
3365 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3366 pbn_oxsemi_1_4000000 },
3367 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
3368 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3369 pbn_oxsemi_1_4000000 },
3370 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
3371 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3372 pbn_oxsemi_1_4000000 },
3373 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
3374 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3375 pbn_oxsemi_1_4000000 },
3376 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
3377 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3378 pbn_oxsemi_1_4000000 },
3379 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
3380 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3381 pbn_oxsemi_1_4000000 },
3382 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
3383 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3384 pbn_oxsemi_1_4000000 },
3385 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
3386 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3387 pbn_oxsemi_1_4000000 },
3388 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
3389 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3390 pbn_oxsemi_1_4000000 },
3391 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
3392 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3393 pbn_oxsemi_1_4000000 },
3394 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
3395 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3396 pbn_oxsemi_1_4000000 },
3397 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
3398 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3399 pbn_oxsemi_1_4000000 },
3401 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
3403 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
3404 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
3405 pbn_oxsemi_1_4000000 },
3406 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
3407 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
3408 pbn_oxsemi_2_4000000 },
3409 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
3410 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
3411 pbn_oxsemi_4_4000000 },
3412 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
3413 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
3414 pbn_oxsemi_8_4000000 },
3417 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
3419 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
3420 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
3421 pbn_oxsemi_2_4000000 },
3424 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
3425 * from skokodyn@yahoo.com
3427 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3428 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
3430 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3431 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
3433 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3434 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
3436 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3437 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
3441 * Digitan DS560-558, from jimd@esoft.com
3443 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
3444 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3448 * Titan Electronic cards
3449 * The 400L and 800L have a custom setup quirk.
3451 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
3452 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3454 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
3455 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3457 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
3458 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3460 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
3461 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3463 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
3464 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3466 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
3467 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3468 pbn_b1_bt_2_921600 },
3469 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
3470 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3471 pbn_b0_bt_4_921600 },
3472 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
3473 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3474 pbn_b0_bt_8_921600 },
3475 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
3476 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3477 pbn_b4_bt_2_921600 },
3478 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
3479 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3480 pbn_b4_bt_4_921600 },
3481 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
3482 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3483 pbn_b4_bt_8_921600 },
3484 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
3485 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3487 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
3488 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3490 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
3491 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3493 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
3494 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3495 pbn_oxsemi_1_4000000 },
3496 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
3497 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3498 pbn_oxsemi_2_4000000 },
3499 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
3500 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3501 pbn_oxsemi_4_4000000 },
3502 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
3503 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3504 pbn_oxsemi_8_4000000 },
3505 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
3506 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3507 pbn_oxsemi_2_4000000 },
3508 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
3509 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3510 pbn_oxsemi_2_4000000 },
3511 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
3512 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3514 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
3515 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3517 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
3518 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3520 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
3521 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3524 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
3525 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3527 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
3528 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3530 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
3531 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3533 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
3534 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3535 pbn_b2_bt_2_921600 },
3536 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
3537 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3538 pbn_b2_bt_2_921600 },
3539 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
3540 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3541 pbn_b2_bt_2_921600 },
3542 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
3543 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3544 pbn_b2_bt_4_921600 },
3545 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
3546 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3547 pbn_b2_bt_4_921600 },
3548 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
3549 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3550 pbn_b2_bt_4_921600 },
3551 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
3552 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3554 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
3555 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3557 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
3558 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3560 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
3561 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3562 pbn_b0_bt_2_921600 },
3563 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
3564 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3565 pbn_b0_bt_2_921600 },
3566 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
3567 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3568 pbn_b0_bt_2_921600 },
3569 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
3570 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3571 pbn_b0_bt_4_921600 },
3572 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
3573 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3574 pbn_b0_bt_4_921600 },
3575 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
3576 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3577 pbn_b0_bt_4_921600 },
3578 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
3579 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3580 pbn_b0_bt_8_921600 },
3581 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
3582 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3583 pbn_b0_bt_8_921600 },
3584 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
3585 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3586 pbn_b0_bt_8_921600 },
3589 * Computone devices submitted by Doug McNash dmcnash@computone.com
3591 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3592 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
3593 0, 0, pbn_computone_4 },
3594 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3595 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
3596 0, 0, pbn_computone_8 },
3597 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3598 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
3599 0, 0, pbn_computone_6 },
3601 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
3602 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3604 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
3605 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
3606 pbn_b0_bt_1_921600 },
3609 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
3611 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
3612 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3613 pbn_b0_bt_8_115200 },
3614 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
3615 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3616 pbn_b0_bt_8_115200 },
3618 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
3619 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3620 pbn_b0_bt_2_115200 },
3621 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
3622 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3623 pbn_b0_bt_2_115200 },
3624 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
3625 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3626 pbn_b0_bt_2_115200 },
3627 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
3628 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3629 pbn_b0_bt_2_115200 },
3630 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
3631 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3632 pbn_b0_bt_2_115200 },
3633 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
3634 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3635 pbn_b0_bt_4_460800 },
3636 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
3637 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3638 pbn_b0_bt_4_460800 },
3639 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
3640 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3641 pbn_b0_bt_2_460800 },
3642 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
3643 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3644 pbn_b0_bt_2_460800 },
3645 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
3646 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3647 pbn_b0_bt_2_460800 },
3648 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
3649 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3650 pbn_b0_bt_1_115200 },
3651 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
3652 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3653 pbn_b0_bt_1_460800 },
3656 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
3657 * Cards are identified by their subsystem vendor IDs, which
3658 * (in hex) match the model number.
3660 * Note that JC140x are RS422/485 cards which require ox950
3661 * ACR = 0x10, and as such are not currently fully supported.
3663 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3664 0x1204, 0x0004, 0, 0,
3666 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3667 0x1208, 0x0004, 0, 0,
3669 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3670 0x1402, 0x0002, 0, 0,
3671 pbn_b0_2_921600 }, */
3672 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3673 0x1404, 0x0004, 0, 0,
3674 pbn_b0_4_921600 }, */
3675 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
3676 0x1208, 0x0004, 0, 0,
3679 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
3680 0x1204, 0x0004, 0, 0,
3682 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
3683 0x1208, 0x0004, 0, 0,
3685 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
3686 0x1208, 0x0004, 0, 0,
3689 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
3691 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
3692 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3696 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
3698 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
3699 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3703 * RAStel 2 port modem, gerg@moreton.com.au
3705 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
3706 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3707 pbn_b2_bt_2_115200 },
3710 * EKF addition for i960 Boards form EKF with serial port
3712 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
3713 0xE4BF, PCI_ANY_ID, 0, 0,
3717 * Xircom Cardbus/Ethernet combos
3719 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
3720 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3723 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
3725 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
3726 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3730 * Untested PCI modems, sent in from various folks...
3734 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
3736 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
3737 0x1048, 0x1500, 0, 0,
3740 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
3747 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3748 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
3750 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3751 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3753 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
3754 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3757 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
3758 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3760 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
3761 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3763 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
3764 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3768 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3770 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3771 PCI_ANY_ID, PCI_ANY_ID,
3773 0, pbn_exar_XR17C152 },
3774 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3775 PCI_ANY_ID, PCI_ANY_ID,
3777 0, pbn_exar_XR17C154 },
3778 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3779 PCI_ANY_ID, PCI_ANY_ID,
3781 0, pbn_exar_XR17C158 },
3784 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
3786 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
3787 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3792 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
3793 PCI_ANY_ID, PCI_ANY_ID,
3795 pbn_b1_bt_1_115200 },
3800 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
3801 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
3806 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
3807 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
3810 * Perle PCI-RAS cards
3812 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3813 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
3814 0, 0, pbn_b2_4_921600 },
3815 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3816 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
3817 0, 0, pbn_b2_8_921600 },
3820 * Mainpine series cards: Fairly standard layout but fools
3821 * parts of the autodetect in some cases and uses otherwise
3822 * unmatched communications subclasses in the PCI Express case
3825 { /* RockForceDUO */
3826 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3827 PCI_VENDOR_ID_MAINPINE, 0x0200,
3828 0, 0, pbn_b0_2_115200 },
3829 { /* RockForceQUATRO */
3830 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3831 PCI_VENDOR_ID_MAINPINE, 0x0300,
3832 0, 0, pbn_b0_4_115200 },
3833 { /* RockForceDUO+ */
3834 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3835 PCI_VENDOR_ID_MAINPINE, 0x0400,
3836 0, 0, pbn_b0_2_115200 },
3837 { /* RockForceQUATRO+ */
3838 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3839 PCI_VENDOR_ID_MAINPINE, 0x0500,
3840 0, 0, pbn_b0_4_115200 },
3842 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3843 PCI_VENDOR_ID_MAINPINE, 0x0600,
3844 0, 0, pbn_b0_2_115200 },
3846 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3847 PCI_VENDOR_ID_MAINPINE, 0x0700,
3848 0, 0, pbn_b0_4_115200 },
3849 { /* RockForceOCTO+ */
3850 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3851 PCI_VENDOR_ID_MAINPINE, 0x0800,
3852 0, 0, pbn_b0_8_115200 },
3853 { /* RockForceDUO+ */
3854 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3855 PCI_VENDOR_ID_MAINPINE, 0x0C00,
3856 0, 0, pbn_b0_2_115200 },
3857 { /* RockForceQUARTRO+ */
3858 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3859 PCI_VENDOR_ID_MAINPINE, 0x0D00,
3860 0, 0, pbn_b0_4_115200 },
3861 { /* RockForceOCTO+ */
3862 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3863 PCI_VENDOR_ID_MAINPINE, 0x1D00,
3864 0, 0, pbn_b0_8_115200 },
3866 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3867 PCI_VENDOR_ID_MAINPINE, 0x2000,
3868 0, 0, pbn_b0_1_115200 },
3870 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3871 PCI_VENDOR_ID_MAINPINE, 0x2100,
3872 0, 0, pbn_b0_1_115200 },
3874 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3875 PCI_VENDOR_ID_MAINPINE, 0x2200,
3876 0, 0, pbn_b0_2_115200 },
3878 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3879 PCI_VENDOR_ID_MAINPINE, 0x2300,
3880 0, 0, pbn_b0_2_115200 },
3882 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3883 PCI_VENDOR_ID_MAINPINE, 0x2400,
3884 0, 0, pbn_b0_4_115200 },
3886 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3887 PCI_VENDOR_ID_MAINPINE, 0x2500,
3888 0, 0, pbn_b0_4_115200 },
3890 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3891 PCI_VENDOR_ID_MAINPINE, 0x2600,
3892 0, 0, pbn_b0_8_115200 },
3894 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3895 PCI_VENDOR_ID_MAINPINE, 0x2700,
3896 0, 0, pbn_b0_8_115200 },
3897 { /* IQ Express D1 */
3898 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3899 PCI_VENDOR_ID_MAINPINE, 0x3000,
3900 0, 0, pbn_b0_1_115200 },
3901 { /* IQ Express F1 */
3902 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3903 PCI_VENDOR_ID_MAINPINE, 0x3100,
3904 0, 0, pbn_b0_1_115200 },
3905 { /* IQ Express D2 */
3906 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3907 PCI_VENDOR_ID_MAINPINE, 0x3200,
3908 0, 0, pbn_b0_2_115200 },
3909 { /* IQ Express F2 */
3910 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3911 PCI_VENDOR_ID_MAINPINE, 0x3300,
3912 0, 0, pbn_b0_2_115200 },
3913 { /* IQ Express D4 */
3914 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3915 PCI_VENDOR_ID_MAINPINE, 0x3400,
3916 0, 0, pbn_b0_4_115200 },
3917 { /* IQ Express F4 */
3918 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3919 PCI_VENDOR_ID_MAINPINE, 0x3500,
3920 0, 0, pbn_b0_4_115200 },
3921 { /* IQ Express D8 */
3922 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3923 PCI_VENDOR_ID_MAINPINE, 0x3C00,
3924 0, 0, pbn_b0_8_115200 },
3925 { /* IQ Express F8 */
3926 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3927 PCI_VENDOR_ID_MAINPINE, 0x3D00,
3928 0, 0, pbn_b0_8_115200 },
3932 * PA Semi PA6T-1682M on-chip UART
3934 { PCI_VENDOR_ID_PASEMI, 0xa004,
3935 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3939 * National Instruments
3941 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
3942 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3944 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
3945 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3947 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
3948 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3949 pbn_b1_bt_4_115200 },
3950 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
3951 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3952 pbn_b1_bt_2_115200 },
3953 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
3954 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3955 pbn_b1_bt_4_115200 },
3956 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
3957 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3958 pbn_b1_bt_2_115200 },
3959 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
3960 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3962 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
3963 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3965 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
3966 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3967 pbn_b1_bt_4_115200 },
3968 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
3969 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3970 pbn_b1_bt_2_115200 },
3971 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
3972 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3973 pbn_b1_bt_4_115200 },
3974 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
3975 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3976 pbn_b1_bt_2_115200 },
3977 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
3978 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3980 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
3981 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3983 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
3984 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3986 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
3987 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3989 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
3990 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3992 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
3993 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3995 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
3996 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3998 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
3999 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4001 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
4002 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4004 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
4005 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4007 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
4008 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4010 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
4011 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4015 * ADDI-DATA GmbH communication cards <info@addi-data.com>
4017 { PCI_VENDOR_ID_ADDIDATA,
4018 PCI_DEVICE_ID_ADDIDATA_APCI7500,
4025 { PCI_VENDOR_ID_ADDIDATA,
4026 PCI_DEVICE_ID_ADDIDATA_APCI7420,
4033 { PCI_VENDOR_ID_ADDIDATA,
4034 PCI_DEVICE_ID_ADDIDATA_APCI7300,
4041 { PCI_VENDOR_ID_ADDIDATA_OLD,
4042 PCI_DEVICE_ID_ADDIDATA_APCI7800,
4049 { PCI_VENDOR_ID_ADDIDATA,
4050 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
4057 { PCI_VENDOR_ID_ADDIDATA,
4058 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
4065 { PCI_VENDOR_ID_ADDIDATA,
4066 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
4073 { PCI_VENDOR_ID_ADDIDATA,
4074 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
4081 { PCI_VENDOR_ID_ADDIDATA,
4082 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
4089 { PCI_VENDOR_ID_ADDIDATA,
4090 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
4097 { PCI_VENDOR_ID_ADDIDATA,
4098 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
4105 { PCI_VENDOR_ID_ADDIDATA,
4106 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
4111 pbn_ADDIDATA_PCIe_4_3906250 },
4113 { PCI_VENDOR_ID_ADDIDATA,
4114 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
4119 pbn_ADDIDATA_PCIe_2_3906250 },
4121 { PCI_VENDOR_ID_ADDIDATA,
4122 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
4127 pbn_ADDIDATA_PCIe_1_3906250 },
4129 { PCI_VENDOR_ID_ADDIDATA,
4130 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
4135 pbn_ADDIDATA_PCIe_8_3906250 },
4137 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
4138 PCI_VENDOR_ID_IBM, 0x0299,
4139 0, 0, pbn_b0_bt_2_115200 },
4141 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
4143 0, 0, pbn_b0_1_115200 },
4145 /* the 9901 is a rebranded 9912 */
4146 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
4148 0, 0, pbn_b0_1_115200 },
4150 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
4152 0, 0, pbn_b0_1_115200 },
4154 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
4156 0, 0, pbn_b0_1_115200 },
4158 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
4160 0, 0, pbn_b0_1_115200 },
4162 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
4164 0, 0, pbn_NETMOS9900_2s_115200 },
4167 * Best Connectivity and Rosewill PCI Multi I/O cards
4170 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4172 0, 0, pbn_b0_1_115200 },
4174 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4176 0, 0, pbn_b0_bt_2_115200 },
4178 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4180 0, 0, pbn_b0_bt_4_115200 },
4182 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
4183 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4184 pbn_ce4100_1_115200 },
4189 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
4190 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4194 * AgeStar as-prs2-009
4196 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
4197 PCI_ANY_ID, PCI_ANY_ID,
4198 0, 0, pbn_b0_bt_2_115200 },
4200 * These entries match devices with class COMMUNICATION_SERIAL,
4201 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
4203 { PCI_ANY_ID, PCI_ANY_ID,
4204 PCI_ANY_ID, PCI_ANY_ID,
4205 PCI_CLASS_COMMUNICATION_SERIAL << 8,
4206 0xffff00, pbn_default },
4207 { PCI_ANY_ID, PCI_ANY_ID,
4208 PCI_ANY_ID, PCI_ANY_ID,
4209 PCI_CLASS_COMMUNICATION_MODEM << 8,
4210 0xffff00, pbn_default },
4211 { PCI_ANY_ID, PCI_ANY_ID,
4212 PCI_ANY_ID, PCI_ANY_ID,
4213 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
4214 0xffff00, pbn_default },
4218 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
4219 pci_channel_state_t state)
4221 struct serial_private *priv = pci_get_drvdata(dev);
4223 if (state == pci_channel_io_perm_failure)
4224 return PCI_ERS_RESULT_DISCONNECT;
4227 pciserial_suspend_ports(priv);
4229 pci_disable_device(dev);
4231 return PCI_ERS_RESULT_NEED_RESET;
4234 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
4238 rc = pci_enable_device(dev);
4241 return PCI_ERS_RESULT_DISCONNECT;
4243 pci_restore_state(dev);
4244 pci_save_state(dev);
4246 return PCI_ERS_RESULT_RECOVERED;
4249 static void serial8250_io_resume(struct pci_dev *dev)
4251 struct serial_private *priv = pci_get_drvdata(dev);
4254 pciserial_resume_ports(priv);
4257 static struct pci_error_handlers serial8250_err_handler = {
4258 .error_detected = serial8250_io_error_detected,
4259 .slot_reset = serial8250_io_slot_reset,
4260 .resume = serial8250_io_resume,
4263 static struct pci_driver serial_pci_driver = {
4265 .probe = pciserial_init_one,
4266 .remove = __devexit_p(pciserial_remove_one),
4268 .suspend = pciserial_suspend_one,
4269 .resume = pciserial_resume_one,
4271 .id_table = serial_pci_tbl,
4272 .err_handler = &serial8250_err_handler,
4275 static int __init serial8250_pci_init(void)
4277 return pci_register_driver(&serial_pci_driver);
4280 static void __exit serial8250_pci_exit(void)
4282 pci_unregister_driver(&serial_pci_driver);
4285 module_init(serial8250_pci_init);
4286 module_exit(serial8250_pci_exit);
4288 MODULE_LICENSE("GPL");
4289 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
4290 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);