2 * Base port operations for 8250/16550-type serial ports
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 * Split from 8250_core.c, Copyright (C) 2001 Russell King.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * A note about mapbase / membase
14 * mapbase is the physical address of the IO port.
15 * membase is an 'ioremapped' cookie.
18 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
22 #include <linux/module.h>
23 #include <linux/moduleparam.h>
24 #include <linux/ioport.h>
25 #include <linux/init.h>
26 #include <linux/console.h>
27 #include <linux/sysrq.h>
28 #include <linux/delay.h>
29 #include <linux/platform_device.h>
30 #include <linux/tty.h>
31 #include <linux/ratelimit.h>
32 #include <linux/tty_flip.h>
33 #include <linux/serial.h>
34 #include <linux/serial_8250.h>
35 #include <linux/nmi.h>
36 #include <linux/mutex.h>
37 #include <linux/slab.h>
38 #include <linux/uaccess.h>
39 #include <linux/pm_runtime.h>
40 #include <linux/timer.h>
51 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
53 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
56 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
59 * Here we define the default xmit fifo size used for each type of UART.
61 static const struct serial8250_config uart_config[] = {
86 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
87 .rxtrig_bytes = {1, 4, 8, 14},
88 .flags = UART_CAP_FIFO,
99 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
105 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
107 .rxtrig_bytes = {8, 16, 24, 28},
108 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
114 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
116 .rxtrig_bytes = {1, 16, 32, 56},
117 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
125 .name = "16C950/954",
128 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
129 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
130 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
136 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
138 .rxtrig_bytes = {8, 16, 56, 60},
139 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
145 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
146 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
152 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
153 .flags = UART_CAP_FIFO,
159 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
160 .flags = UART_CAP_FIFO | UART_NATSEMI,
166 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
167 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
173 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
174 .flags = UART_CAP_FIFO,
180 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
181 .flags = UART_CAP_FIFO | UART_CAP_AFE,
187 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
188 .flags = UART_CAP_FIFO | UART_CAP_AFE,
194 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
196 .rxtrig_bytes = {1, 4, 8, 14},
197 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
203 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
204 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
211 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 |
213 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
220 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
221 UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00,
222 .flags = UART_CAP_FIFO,
224 [PORT_BRCM_TRUMANAGE] = {
228 .flags = UART_CAP_HFIFO,
233 [PORT_ALTR_16550_F32] = {
234 .name = "Altera 16550 FIFO32",
237 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
238 .flags = UART_CAP_FIFO | UART_CAP_AFE,
240 [PORT_ALTR_16550_F64] = {
241 .name = "Altera 16550 FIFO64",
244 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
245 .flags = UART_CAP_FIFO | UART_CAP_AFE,
247 [PORT_ALTR_16550_F128] = {
248 .name = "Altera 16550 FIFO128",
251 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
252 .flags = UART_CAP_FIFO | UART_CAP_AFE,
255 * tx_loadsz is set to 63-bytes instead of 64-bytes to implement
256 * workaround of errata A-008006 which states that tx_loadsz should
257 * be configured less than Maximum supported fifo bytes.
259 [PORT_16550A_FSL64] = {
260 .name = "16550A_FSL64",
263 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
265 .flags = UART_CAP_FIFO,
268 .name = "Palmchip BK-3103",
271 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
272 .rxtrig_bytes = {1, 4, 8, 14},
273 .flags = UART_CAP_FIFO,
277 /* Uart divisor latch read */
278 static int default_serial_dl_read(struct uart_8250_port *up)
280 return serial_in(up, UART_DLL) | serial_in(up, UART_DLM) << 8;
283 /* Uart divisor latch write */
284 static void default_serial_dl_write(struct uart_8250_port *up, int value)
286 serial_out(up, UART_DLL, value & 0xff);
287 serial_out(up, UART_DLM, value >> 8 & 0xff);
290 #ifdef CONFIG_SERIAL_8250_RT288X
292 /* Au1x00/RT288x UART hardware has a weird register layout */
293 static const s8 au_io_in_map[8] = {
301 -1, /* UART_SCR (unmapped) */
304 static const s8 au_io_out_map[8] = {
310 -1, /* UART_LSR (unmapped) */
311 -1, /* UART_MSR (unmapped) */
312 -1, /* UART_SCR (unmapped) */
315 static unsigned int au_serial_in(struct uart_port *p, int offset)
317 if (offset >= ARRAY_SIZE(au_io_in_map))
319 offset = au_io_in_map[offset];
322 return __raw_readl(p->membase + (offset << p->regshift));
325 static void au_serial_out(struct uart_port *p, int offset, int value)
327 if (offset >= ARRAY_SIZE(au_io_out_map))
329 offset = au_io_out_map[offset];
332 __raw_writel(value, p->membase + (offset << p->regshift));
335 /* Au1x00 haven't got a standard divisor latch */
336 static int au_serial_dl_read(struct uart_8250_port *up)
338 return __raw_readl(up->port.membase + 0x28);
341 static void au_serial_dl_write(struct uart_8250_port *up, int value)
343 __raw_writel(value, up->port.membase + 0x28);
348 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
350 offset = offset << p->regshift;
351 outb(p->hub6 - 1 + offset, p->iobase);
352 return inb(p->iobase + 1);
355 static void hub6_serial_out(struct uart_port *p, int offset, int value)
357 offset = offset << p->regshift;
358 outb(p->hub6 - 1 + offset, p->iobase);
359 outb(value, p->iobase + 1);
362 static unsigned int mem_serial_in(struct uart_port *p, int offset)
364 offset = offset << p->regshift;
365 return readb(p->membase + offset);
368 static void mem_serial_out(struct uart_port *p, int offset, int value)
370 offset = offset << p->regshift;
371 writeb(value, p->membase + offset);
374 static void mem16_serial_out(struct uart_port *p, int offset, int value)
376 offset = offset << p->regshift;
377 writew(value, p->membase + offset);
380 static unsigned int mem16_serial_in(struct uart_port *p, int offset)
382 offset = offset << p->regshift;
383 return readw(p->membase + offset);
386 static void mem32_serial_out(struct uart_port *p, int offset, int value)
388 offset = offset << p->regshift;
389 writel(value, p->membase + offset);
392 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
394 offset = offset << p->regshift;
395 return readl(p->membase + offset);
398 static void mem32be_serial_out(struct uart_port *p, int offset, int value)
400 offset = offset << p->regshift;
401 iowrite32be(value, p->membase + offset);
404 static unsigned int mem32be_serial_in(struct uart_port *p, int offset)
406 offset = offset << p->regshift;
407 return ioread32be(p->membase + offset);
410 static unsigned int io_serial_in(struct uart_port *p, int offset)
412 offset = offset << p->regshift;
413 return inb(p->iobase + offset);
416 static void io_serial_out(struct uart_port *p, int offset, int value)
418 offset = offset << p->regshift;
419 outb(value, p->iobase + offset);
422 static int serial8250_default_handle_irq(struct uart_port *port);
423 static int exar_handle_irq(struct uart_port *port);
425 static void set_io_from_upio(struct uart_port *p)
427 struct uart_8250_port *up = up_to_u8250p(p);
429 up->dl_read = default_serial_dl_read;
430 up->dl_write = default_serial_dl_write;
434 p->serial_in = hub6_serial_in;
435 p->serial_out = hub6_serial_out;
439 p->serial_in = mem_serial_in;
440 p->serial_out = mem_serial_out;
444 p->serial_in = mem16_serial_in;
445 p->serial_out = mem16_serial_out;
449 p->serial_in = mem32_serial_in;
450 p->serial_out = mem32_serial_out;
454 p->serial_in = mem32be_serial_in;
455 p->serial_out = mem32be_serial_out;
458 #ifdef CONFIG_SERIAL_8250_RT288X
460 p->serial_in = au_serial_in;
461 p->serial_out = au_serial_out;
462 up->dl_read = au_serial_dl_read;
463 up->dl_write = au_serial_dl_write;
468 p->serial_in = io_serial_in;
469 p->serial_out = io_serial_out;
472 /* Remember loaded iotype */
473 up->cur_iotype = p->iotype;
474 p->handle_irq = serial8250_default_handle_irq;
478 serial_port_out_sync(struct uart_port *p, int offset, int value)
486 p->serial_out(p, offset, value);
487 p->serial_in(p, UART_LCR); /* safe, no side-effects */
490 p->serial_out(p, offset, value);
497 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
499 serial_out(up, UART_SCR, offset);
500 serial_out(up, UART_ICR, value);
503 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
507 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
508 serial_out(up, UART_SCR, offset);
509 value = serial_in(up, UART_ICR);
510 serial_icr_write(up, UART_ACR, up->acr);
518 static void serial8250_clear_fifos(struct uart_8250_port *p)
520 if (p->capabilities & UART_CAP_FIFO) {
521 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
522 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
523 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
524 serial_out(p, UART_FCR, 0);
528 static inline void serial8250_em485_rts_after_send(struct uart_8250_port *p)
530 unsigned char mcr = serial_in(p, UART_MCR);
532 if (p->port.rs485.flags & SER_RS485_RTS_AFTER_SEND)
535 mcr &= ~UART_MCR_RTS;
536 serial_out(p, UART_MCR, mcr);
539 static void serial8250_em485_handle_start_tx(unsigned long arg);
540 static void serial8250_em485_handle_stop_tx(unsigned long arg);
542 void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p)
544 serial8250_clear_fifos(p);
545 serial_out(p, UART_FCR, p->fcr);
547 EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos);
549 void serial8250_rpm_get(struct uart_8250_port *p)
551 if (!(p->capabilities & UART_CAP_RPM))
553 pm_runtime_get_sync(p->port.dev);
555 EXPORT_SYMBOL_GPL(serial8250_rpm_get);
557 void serial8250_rpm_put(struct uart_8250_port *p)
559 if (!(p->capabilities & UART_CAP_RPM))
561 pm_runtime_mark_last_busy(p->port.dev);
562 pm_runtime_put_autosuspend(p->port.dev);
564 EXPORT_SYMBOL_GPL(serial8250_rpm_put);
567 * serial8250_em485_init() - put uart_8250_port into rs485 emulating
568 * @p: uart_8250_port port instance
570 * The function is used to start rs485 software emulating on the
571 * &struct uart_8250_port* @p. Namely, RTS is switched before/after
572 * transmission. The function is idempotent, so it is safe to call it
575 * The caller MUST enable interrupt on empty shift register before
576 * calling serial8250_em485_init(). This interrupt is not a part of
577 * 8250 standard, but implementation defined.
579 * The function is supposed to be called from .rs485_config callback
580 * or from any other callback protected with p->port.lock spinlock.
582 * See also serial8250_em485_destroy()
584 * Return 0 - success, -errno - otherwise
586 int serial8250_em485_init(struct uart_8250_port *p)
588 if (p->em485 != NULL)
591 p->em485 = kmalloc(sizeof(struct uart_8250_em485), GFP_KERNEL);
592 if (p->em485 == NULL)
595 setup_timer(&p->em485->stop_tx_timer,
596 serial8250_em485_handle_stop_tx, (unsigned long)p);
597 setup_timer(&p->em485->start_tx_timer,
598 serial8250_em485_handle_start_tx, (unsigned long)p);
599 p->em485->active_timer = NULL;
601 serial8250_em485_rts_after_send(p);
605 EXPORT_SYMBOL_GPL(serial8250_em485_init);
608 * serial8250_em485_destroy() - put uart_8250_port into normal state
609 * @p: uart_8250_port port instance
611 * The function is used to stop rs485 software emulating on the
612 * &struct uart_8250_port* @p. The function is idempotent, so it is safe to
613 * call it multiple times.
615 * The function is supposed to be called from .rs485_config callback
616 * or from any other callback protected with p->port.lock spinlock.
618 * See also serial8250_em485_init()
620 void serial8250_em485_destroy(struct uart_8250_port *p)
622 if (p->em485 == NULL)
625 del_timer(&p->em485->start_tx_timer);
626 del_timer(&p->em485->stop_tx_timer);
631 EXPORT_SYMBOL_GPL(serial8250_em485_destroy);
634 * These two wrappers ensure that enable_runtime_pm_tx() can be called more than
635 * once and disable_runtime_pm_tx() will still disable RPM because the fifo is
636 * empty and the HW can idle again.
638 static void serial8250_rpm_get_tx(struct uart_8250_port *p)
640 unsigned char rpm_active;
642 if (!(p->capabilities & UART_CAP_RPM))
645 rpm_active = xchg(&p->rpm_tx_active, 1);
648 pm_runtime_get_sync(p->port.dev);
651 static void serial8250_rpm_put_tx(struct uart_8250_port *p)
653 unsigned char rpm_active;
655 if (!(p->capabilities & UART_CAP_RPM))
658 rpm_active = xchg(&p->rpm_tx_active, 0);
661 pm_runtime_mark_last_busy(p->port.dev);
662 pm_runtime_put_autosuspend(p->port.dev);
666 * IER sleep support. UARTs which have EFRs need the "extended
667 * capability" bit enabled. Note that on XR16C850s, we need to
668 * reset LCR to write to IER.
670 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
672 unsigned char lcr = 0, efr = 0;
674 * Exar UARTs have a SLEEP register that enables or disables
675 * each UART to enter sleep mode separately. On the XR17V35x the
676 * register is accessible to each UART at the UART_EXAR_SLEEP
677 * offset but the UART channel may only write to the corresponding
680 serial8250_rpm_get(p);
681 if ((p->port.type == PORT_XR17V35X) ||
682 (p->port.type == PORT_XR17D15X)) {
683 serial_out(p, UART_EXAR_SLEEP, sleep ? 0xff : 0);
687 if (p->capabilities & UART_CAP_SLEEP) {
688 if (p->capabilities & UART_CAP_EFR) {
689 lcr = serial_in(p, UART_LCR);
690 efr = serial_in(p, UART_EFR);
691 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
692 serial_out(p, UART_EFR, UART_EFR_ECB);
693 serial_out(p, UART_LCR, 0);
695 serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
696 if (p->capabilities & UART_CAP_EFR) {
697 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
698 serial_out(p, UART_EFR, efr);
699 serial_out(p, UART_LCR, lcr);
703 serial8250_rpm_put(p);
706 #ifdef CONFIG_SERIAL_8250_RSA
708 * Attempts to turn on the RSA FIFO. Returns zero on failure.
709 * We set the port uart clock rate if we succeed.
711 static int __enable_rsa(struct uart_8250_port *up)
716 mode = serial_in(up, UART_RSA_MSR);
717 result = mode & UART_RSA_MSR_FIFO;
720 serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
721 mode = serial_in(up, UART_RSA_MSR);
722 result = mode & UART_RSA_MSR_FIFO;
726 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
731 static void enable_rsa(struct uart_8250_port *up)
733 if (up->port.type == PORT_RSA) {
734 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
735 spin_lock_irq(&up->port.lock);
737 spin_unlock_irq(&up->port.lock);
739 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
740 serial_out(up, UART_RSA_FRR, 0);
745 * Attempts to turn off the RSA FIFO. Returns zero on failure.
746 * It is unknown why interrupts were disabled in here. However,
747 * the caller is expected to preserve this behaviour by grabbing
748 * the spinlock before calling this function.
750 static void disable_rsa(struct uart_8250_port *up)
755 if (up->port.type == PORT_RSA &&
756 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
757 spin_lock_irq(&up->port.lock);
759 mode = serial_in(up, UART_RSA_MSR);
760 result = !(mode & UART_RSA_MSR_FIFO);
763 serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
764 mode = serial_in(up, UART_RSA_MSR);
765 result = !(mode & UART_RSA_MSR_FIFO);
769 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
770 spin_unlock_irq(&up->port.lock);
773 #endif /* CONFIG_SERIAL_8250_RSA */
776 * This is a quickie test to see how big the FIFO is.
777 * It doesn't work at all the time, more's the pity.
779 static int size_fifo(struct uart_8250_port *up)
781 unsigned char old_fcr, old_mcr, old_lcr;
782 unsigned short old_dl;
785 old_lcr = serial_in(up, UART_LCR);
786 serial_out(up, UART_LCR, 0);
787 old_fcr = serial_in(up, UART_FCR);
788 old_mcr = serial_in(up, UART_MCR);
789 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
790 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
791 serial_out(up, UART_MCR, UART_MCR_LOOP);
792 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
793 old_dl = serial_dl_read(up);
794 serial_dl_write(up, 0x0001);
795 serial_out(up, UART_LCR, 0x03);
796 for (count = 0; count < 256; count++)
797 serial_out(up, UART_TX, count);
798 mdelay(20);/* FIXME - schedule_timeout */
799 for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
800 (count < 256); count++)
801 serial_in(up, UART_RX);
802 serial_out(up, UART_FCR, old_fcr);
803 serial_out(up, UART_MCR, old_mcr);
804 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
805 serial_dl_write(up, old_dl);
806 serial_out(up, UART_LCR, old_lcr);
812 * Read UART ID using the divisor method - set DLL and DLM to zero
813 * and the revision will be in DLL and device type in DLM. We
814 * preserve the device state across this.
816 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
818 unsigned char old_lcr;
819 unsigned int id, old_dl;
821 old_lcr = serial_in(p, UART_LCR);
822 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
823 old_dl = serial_dl_read(p);
824 serial_dl_write(p, 0);
825 id = serial_dl_read(p);
826 serial_dl_write(p, old_dl);
828 serial_out(p, UART_LCR, old_lcr);
834 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
835 * When this function is called we know it is at least a StarTech
836 * 16650 V2, but it might be one of several StarTech UARTs, or one of
837 * its clones. (We treat the broken original StarTech 16650 V1 as a
838 * 16550, and why not? Startech doesn't seem to even acknowledge its
841 * What evil have men's minds wrought...
843 static void autoconfig_has_efr(struct uart_8250_port *up)
845 unsigned int id1, id2, id3, rev;
848 * Everything with an EFR has SLEEP
850 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
853 * First we check to see if it's an Oxford Semiconductor UART.
855 * If we have to do this here because some non-National
856 * Semiconductor clone chips lock up if you try writing to the
857 * LSR register (which serial_icr_read does)
861 * Check for Oxford Semiconductor 16C950.
863 * EFR [4] must be set else this test fails.
865 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
866 * claims that it's needed for 952 dual UART's (which are not
867 * recommended for new designs).
870 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
871 serial_out(up, UART_EFR, UART_EFR_ECB);
872 serial_out(up, UART_LCR, 0x00);
873 id1 = serial_icr_read(up, UART_ID1);
874 id2 = serial_icr_read(up, UART_ID2);
875 id3 = serial_icr_read(up, UART_ID3);
876 rev = serial_icr_read(up, UART_REV);
878 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
880 if (id1 == 0x16 && id2 == 0xC9 &&
881 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
882 up->port.type = PORT_16C950;
885 * Enable work around for the Oxford Semiconductor 952 rev B
886 * chip which causes it to seriously miscalculate baud rates
889 if (id3 == 0x52 && rev == 0x01)
890 up->bugs |= UART_BUG_QUOT;
895 * We check for a XR16C850 by setting DLL and DLM to 0, and then
896 * reading back DLL and DLM. The chip type depends on the DLM
898 * 0x10 - XR16C850 and the DLL contains the chip revision.
902 id1 = autoconfig_read_divisor_id(up);
903 DEBUG_AUTOCONF("850id=%04x ", id1);
906 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
907 up->port.type = PORT_16850;
912 * It wasn't an XR16C850.
914 * We distinguish between the '654 and the '650 by counting
915 * how many bytes are in the FIFO. I'm using this for now,
916 * since that's the technique that was sent to me in the
917 * serial driver update, but I'm not convinced this works.
918 * I've had problems doing this in the past. -TYT
920 if (size_fifo(up) == 64)
921 up->port.type = PORT_16654;
923 up->port.type = PORT_16650V2;
927 * We detected a chip without a FIFO. Only two fall into
928 * this category - the original 8250 and the 16450. The
929 * 16450 has a scratch register (accessible with LCR=0)
931 static void autoconfig_8250(struct uart_8250_port *up)
933 unsigned char scratch, status1, status2;
935 up->port.type = PORT_8250;
937 scratch = serial_in(up, UART_SCR);
938 serial_out(up, UART_SCR, 0xa5);
939 status1 = serial_in(up, UART_SCR);
940 serial_out(up, UART_SCR, 0x5a);
941 status2 = serial_in(up, UART_SCR);
942 serial_out(up, UART_SCR, scratch);
944 if (status1 == 0xa5 && status2 == 0x5a)
945 up->port.type = PORT_16450;
948 static int broken_efr(struct uart_8250_port *up)
951 * Exar ST16C2550 "A2" devices incorrectly detect as
952 * having an EFR, and report an ID of 0x0201. See
953 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
955 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
962 * We know that the chip has FIFOs. Does it have an EFR? The
963 * EFR is located in the same register position as the IIR and
964 * we know the top two bits of the IIR are currently set. The
965 * EFR should contain zero. Try to read the EFR.
967 static void autoconfig_16550a(struct uart_8250_port *up)
969 unsigned char status1, status2;
970 unsigned int iersave;
972 up->port.type = PORT_16550A;
973 up->capabilities |= UART_CAP_FIFO;
976 * XR17V35x UARTs have an extra divisor register, DLD
977 * that gets enabled with when DLAB is set which will
978 * cause the device to incorrectly match and assign
979 * port type to PORT_16650. The EFR for this UART is
980 * found at offset 0x09. Instead check the Deice ID (DVID)
981 * register for a 2, 4 or 8 port UART.
983 if (up->port.flags & UPF_EXAR_EFR) {
984 status1 = serial_in(up, UART_EXAR_DVID);
985 if (status1 == 0x82 || status1 == 0x84 || status1 == 0x88) {
986 DEBUG_AUTOCONF("Exar XR17V35x ");
987 up->port.type = PORT_XR17V35X;
988 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
997 * Check for presence of the EFR when DLAB is set.
998 * Only ST16C650V1 UARTs pass this test.
1000 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1001 if (serial_in(up, UART_EFR) == 0) {
1002 serial_out(up, UART_EFR, 0xA8);
1003 if (serial_in(up, UART_EFR) != 0) {
1004 DEBUG_AUTOCONF("EFRv1 ");
1005 up->port.type = PORT_16650;
1006 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
1008 serial_out(up, UART_LCR, 0);
1009 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
1011 status1 = serial_in(up, UART_IIR) >> 5;
1012 serial_out(up, UART_FCR, 0);
1013 serial_out(up, UART_LCR, 0);
1016 up->port.type = PORT_16550A_FSL64;
1018 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
1020 serial_out(up, UART_EFR, 0);
1025 * Maybe it requires 0xbf to be written to the LCR.
1026 * (other ST16C650V2 UARTs, TI16C752A, etc)
1028 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1029 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
1030 DEBUG_AUTOCONF("EFRv2 ");
1031 autoconfig_has_efr(up);
1036 * Check for a National Semiconductor SuperIO chip.
1037 * Attempt to switch to bank 2, read the value of the LOOP bit
1038 * from EXCR1. Switch back to bank 0, change it in MCR. Then
1039 * switch back to bank 2, read it from EXCR1 again and check
1040 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1042 serial_out(up, UART_LCR, 0);
1043 status1 = serial_in(up, UART_MCR);
1044 serial_out(up, UART_LCR, 0xE0);
1045 status2 = serial_in(up, 0x02); /* EXCR1 */
1047 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
1048 serial_out(up, UART_LCR, 0);
1049 serial_out(up, UART_MCR, status1 ^ UART_MCR_LOOP);
1050 serial_out(up, UART_LCR, 0xE0);
1051 status2 = serial_in(up, 0x02); /* EXCR1 */
1052 serial_out(up, UART_LCR, 0);
1053 serial_out(up, UART_MCR, status1);
1055 if ((status2 ^ status1) & UART_MCR_LOOP) {
1056 unsigned short quot;
1058 serial_out(up, UART_LCR, 0xE0);
1060 quot = serial_dl_read(up);
1063 if (ns16550a_goto_highspeed(up))
1064 serial_dl_write(up, quot);
1066 serial_out(up, UART_LCR, 0);
1068 up->port.uartclk = 921600*16;
1069 up->port.type = PORT_NS16550A;
1070 up->capabilities |= UART_NATSEMI;
1076 * No EFR. Try to detect a TI16750, which only sets bit 5 of
1077 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1078 * Try setting it with and without DLAB set. Cheap clones
1079 * set bit 5 without DLAB set.
1081 serial_out(up, UART_LCR, 0);
1082 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1083 status1 = serial_in(up, UART_IIR) >> 5;
1084 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1085 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1086 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1087 status2 = serial_in(up, UART_IIR) >> 5;
1088 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1089 serial_out(up, UART_LCR, 0);
1091 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1093 if (status1 == 6 && status2 == 7) {
1094 up->port.type = PORT_16750;
1095 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1100 * Try writing and reading the UART_IER_UUE bit (b6).
1101 * If it works, this is probably one of the Xscale platform's
1103 * We're going to explicitly set the UUE bit to 0 before
1104 * trying to write and read a 1 just to make sure it's not
1105 * already a 1 and maybe locked there before we even start start.
1107 iersave = serial_in(up, UART_IER);
1108 serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
1109 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1111 * OK it's in a known zero state, try writing and reading
1112 * without disturbing the current state of the other bits.
1114 serial_out(up, UART_IER, iersave | UART_IER_UUE);
1115 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1118 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1120 DEBUG_AUTOCONF("Xscale ");
1121 up->port.type = PORT_XSCALE;
1122 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1127 * If we got here we couldn't force the IER_UUE bit to 0.
1128 * Log it and continue.
1130 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1132 serial_out(up, UART_IER, iersave);
1135 * Exar uarts have EFR in a weird location
1137 if (up->port.flags & UPF_EXAR_EFR) {
1138 DEBUG_AUTOCONF("Exar XR17D15x ");
1139 up->port.type = PORT_XR17D15X;
1140 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
1147 * We distinguish between 16550A and U6 16550A by counting
1148 * how many bytes are in the FIFO.
1150 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1151 up->port.type = PORT_U6_16550A;
1152 up->capabilities |= UART_CAP_AFE;
1157 * This routine is called by rs_init() to initialize a specific serial
1158 * port. It determines what type of UART chip this serial port is
1159 * using: 8250, 16450, 16550, 16550A. The important question is
1160 * whether or not this UART is a 16550A or not, since this will
1161 * determine whether or not we can use its FIFO features or not.
1163 static void autoconfig(struct uart_8250_port *up)
1165 unsigned char status1, scratch, scratch2, scratch3;
1166 unsigned char save_lcr, save_mcr;
1167 struct uart_port *port = &up->port;
1168 unsigned long flags;
1169 unsigned int old_capabilities;
1171 if (!port->iobase && !port->mapbase && !port->membase)
1174 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
1175 serial_index(port), port->iobase, port->membase);
1178 * We really do need global IRQs disabled here - we're going to
1179 * be frobbing the chips IRQ enable register to see if it exists.
1181 spin_lock_irqsave(&port->lock, flags);
1183 up->capabilities = 0;
1186 if (!(port->flags & UPF_BUGGY_UART)) {
1188 * Do a simple existence test first; if we fail this,
1189 * there's no point trying anything else.
1191 * 0x80 is used as a nonsense port to prevent against
1192 * false positives due to ISA bus float. The
1193 * assumption is that 0x80 is a non-existent port;
1194 * which should be safe since include/asm/io.h also
1195 * makes this assumption.
1197 * Note: this is safe as long as MCR bit 4 is clear
1198 * and the device is in "PC" mode.
1200 scratch = serial_in(up, UART_IER);
1201 serial_out(up, UART_IER, 0);
1206 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1207 * 16C754B) allow only to modify them if an EFR bit is set.
1209 scratch2 = serial_in(up, UART_IER) & 0x0f;
1210 serial_out(up, UART_IER, 0x0F);
1214 scratch3 = serial_in(up, UART_IER) & 0x0f;
1215 serial_out(up, UART_IER, scratch);
1216 if (scratch2 != 0 || scratch3 != 0x0F) {
1218 * We failed; there's nothing here
1220 spin_unlock_irqrestore(&port->lock, flags);
1221 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1222 scratch2, scratch3);
1227 save_mcr = serial_in(up, UART_MCR);
1228 save_lcr = serial_in(up, UART_LCR);
1231 * Check to see if a UART is really there. Certain broken
1232 * internal modems based on the Rockwell chipset fail this
1233 * test, because they apparently don't implement the loopback
1234 * test mode. So this test is skipped on the COM 1 through
1235 * COM 4 ports. This *should* be safe, since no board
1236 * manufacturer would be stupid enough to design a board
1237 * that conflicts with COM 1-4 --- we hope!
1239 if (!(port->flags & UPF_SKIP_TEST)) {
1240 serial_out(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1241 status1 = serial_in(up, UART_MSR) & 0xF0;
1242 serial_out(up, UART_MCR, save_mcr);
1243 if (status1 != 0x90) {
1244 spin_unlock_irqrestore(&port->lock, flags);
1245 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1252 * We're pretty sure there's a port here. Lets find out what
1253 * type of port it is. The IIR top two bits allows us to find
1254 * out if it's 8250 or 16450, 16550, 16550A or later. This
1255 * determines what we test for next.
1257 * We also initialise the EFR (if any) to zero for later. The
1258 * EFR occupies the same register location as the FCR and IIR.
1260 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1261 serial_out(up, UART_EFR, 0);
1262 serial_out(up, UART_LCR, 0);
1264 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1265 scratch = serial_in(up, UART_IIR) >> 6;
1269 autoconfig_8250(up);
1272 port->type = PORT_UNKNOWN;
1275 port->type = PORT_16550;
1278 autoconfig_16550a(up);
1282 #ifdef CONFIG_SERIAL_8250_RSA
1284 * Only probe for RSA ports if we got the region.
1286 if (port->type == PORT_16550A && up->probe & UART_PROBE_RSA &&
1288 port->type = PORT_RSA;
1291 serial_out(up, UART_LCR, save_lcr);
1293 port->fifosize = uart_config[up->port.type].fifo_size;
1294 old_capabilities = up->capabilities;
1295 up->capabilities = uart_config[port->type].flags;
1296 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1298 if (port->type == PORT_UNKNOWN)
1304 #ifdef CONFIG_SERIAL_8250_RSA
1305 if (port->type == PORT_RSA)
1306 serial_out(up, UART_RSA_FRR, 0);
1308 serial_out(up, UART_MCR, save_mcr);
1309 serial8250_clear_fifos(up);
1310 serial_in(up, UART_RX);
1311 if (up->capabilities & UART_CAP_UUE)
1312 serial_out(up, UART_IER, UART_IER_UUE);
1314 serial_out(up, UART_IER, 0);
1317 spin_unlock_irqrestore(&port->lock, flags);
1318 if (up->capabilities != old_capabilities) {
1320 "ttyS%d: detected caps %08x should be %08x\n",
1321 serial_index(port), old_capabilities,
1325 DEBUG_AUTOCONF("iir=%d ", scratch);
1326 DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
1329 static void autoconfig_irq(struct uart_8250_port *up)
1331 struct uart_port *port = &up->port;
1332 unsigned char save_mcr, save_ier;
1333 unsigned char save_ICP = 0;
1334 unsigned int ICP = 0;
1338 if (port->flags & UPF_FOURPORT) {
1339 ICP = (port->iobase & 0xfe0) | 0x1f;
1340 save_ICP = inb_p(ICP);
1345 if (uart_console(port))
1348 /* forget possible initially masked and pending IRQ */
1349 probe_irq_off(probe_irq_on());
1350 save_mcr = serial_in(up, UART_MCR);
1351 save_ier = serial_in(up, UART_IER);
1352 serial_out(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1354 irqs = probe_irq_on();
1355 serial_out(up, UART_MCR, 0);
1357 if (port->flags & UPF_FOURPORT) {
1358 serial_out(up, UART_MCR,
1359 UART_MCR_DTR | UART_MCR_RTS);
1361 serial_out(up, UART_MCR,
1362 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1364 serial_out(up, UART_IER, 0x0f); /* enable all intrs */
1365 serial_in(up, UART_LSR);
1366 serial_in(up, UART_RX);
1367 serial_in(up, UART_IIR);
1368 serial_in(up, UART_MSR);
1369 serial_out(up, UART_TX, 0xFF);
1371 irq = probe_irq_off(irqs);
1373 serial_out(up, UART_MCR, save_mcr);
1374 serial_out(up, UART_IER, save_ier);
1376 if (port->flags & UPF_FOURPORT)
1377 outb_p(save_ICP, ICP);
1379 if (uart_console(port))
1382 port->irq = (irq > 0) ? irq : 0;
1385 static void serial8250_stop_rx(struct uart_port *port)
1387 struct uart_8250_port *up = up_to_u8250p(port);
1389 serial8250_rpm_get(up);
1391 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
1392 up->port.read_status_mask &= ~UART_LSR_DR;
1393 serial_port_out(port, UART_IER, up->ier);
1395 serial8250_rpm_put(up);
1398 static void __do_stop_tx_rs485(struct uart_8250_port *p)
1403 serial8250_em485_rts_after_send(p);
1405 * Empty the RX FIFO, we are not interested in anything
1406 * received during the half-duplex transmission.
1408 if (!(p->port.rs485.flags & SER_RS485_RX_DURING_TX))
1409 serial8250_clear_fifos(p);
1412 static void serial8250_em485_handle_stop_tx(unsigned long arg)
1414 struct uart_8250_port *p = (struct uart_8250_port *)arg;
1415 struct uart_8250_em485 *em485 = p->em485;
1416 unsigned long flags;
1418 spin_lock_irqsave(&p->port.lock, flags);
1420 em485->active_timer == &em485->stop_tx_timer) {
1421 __do_stop_tx_rs485(p);
1422 em485->active_timer = NULL;
1424 spin_unlock_irqrestore(&p->port.lock, flags);
1427 static void __stop_tx_rs485(struct uart_8250_port *p)
1429 struct uart_8250_em485 *em485 = p->em485;
1435 * __do_stop_tx_rs485 is going to set RTS according to config
1436 * AND flush RX FIFO if required.
1438 if (p->port.rs485.delay_rts_after_send > 0) {
1439 em485->active_timer = &em485->stop_tx_timer;
1440 mod_timer(&em485->stop_tx_timer, jiffies +
1441 p->port.rs485.delay_rts_after_send * HZ / 1000);
1443 __do_stop_tx_rs485(p);
1447 static inline void __do_stop_tx(struct uart_8250_port *p)
1449 if (p->ier & UART_IER_THRI) {
1450 p->ier &= ~UART_IER_THRI;
1451 serial_out(p, UART_IER, p->ier);
1452 serial8250_rpm_put_tx(p);
1456 static inline void __stop_tx(struct uart_8250_port *p)
1458 struct uart_8250_em485 *em485 = p->em485;
1461 unsigned char lsr = serial_in(p, UART_LSR);
1463 * To provide required timeing and allow FIFO transfer,
1464 * __stop_tx_rs485 must be called only when both FIFO and
1465 * shift register are empty. It is for device driver to enable
1466 * interrupt on TEMT.
1468 if ((lsr & BOTH_EMPTY) != BOTH_EMPTY)
1471 del_timer(&em485->start_tx_timer);
1472 em485->active_timer = NULL;
1478 static void serial8250_stop_tx(struct uart_port *port)
1480 struct uart_8250_port *up = up_to_u8250p(port);
1482 serial8250_rpm_get(up);
1486 * We really want to stop the transmitter from sending.
1488 if (port->type == PORT_16C950) {
1489 up->acr |= UART_ACR_TXDIS;
1490 serial_icr_write(up, UART_ACR, up->acr);
1492 serial8250_rpm_put(up);
1495 static inline void __start_tx(struct uart_port *port)
1497 struct uart_8250_port *up = up_to_u8250p(port);
1499 if (up->dma && !up->dma->tx_dma(up))
1502 if (!(up->ier & UART_IER_THRI)) {
1503 up->ier |= UART_IER_THRI;
1504 serial_port_out(port, UART_IER, up->ier);
1506 if (up->bugs & UART_BUG_TXEN) {
1509 lsr = serial_in(up, UART_LSR);
1510 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1511 if (lsr & UART_LSR_THRE)
1512 serial8250_tx_chars(up);
1517 * Re-enable the transmitter if we disabled it.
1519 if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1520 up->acr &= ~UART_ACR_TXDIS;
1521 serial_icr_write(up, UART_ACR, up->acr);
1525 static inline void start_tx_rs485(struct uart_port *port)
1527 struct uart_8250_port *up = up_to_u8250p(port);
1528 struct uart_8250_em485 *em485 = up->em485;
1531 if (!(up->port.rs485.flags & SER_RS485_RX_DURING_TX))
1532 serial8250_stop_rx(&up->port);
1534 del_timer(&em485->stop_tx_timer);
1535 em485->active_timer = NULL;
1537 mcr = serial_in(up, UART_MCR);
1538 if (!!(up->port.rs485.flags & SER_RS485_RTS_ON_SEND) !=
1539 !!(mcr & UART_MCR_RTS)) {
1540 if (up->port.rs485.flags & SER_RS485_RTS_ON_SEND)
1541 mcr |= UART_MCR_RTS;
1543 mcr &= ~UART_MCR_RTS;
1544 serial_out(up, UART_MCR, mcr);
1546 if (up->port.rs485.delay_rts_before_send > 0) {
1547 em485->active_timer = &em485->start_tx_timer;
1548 mod_timer(&em485->start_tx_timer, jiffies +
1549 up->port.rs485.delay_rts_before_send * HZ / 1000);
1557 static void serial8250_em485_handle_start_tx(unsigned long arg)
1559 struct uart_8250_port *p = (struct uart_8250_port *)arg;
1560 struct uart_8250_em485 *em485 = p->em485;
1561 unsigned long flags;
1563 spin_lock_irqsave(&p->port.lock, flags);
1565 em485->active_timer == &em485->start_tx_timer) {
1566 __start_tx(&p->port);
1567 em485->active_timer = NULL;
1569 spin_unlock_irqrestore(&p->port.lock, flags);
1572 static void serial8250_start_tx(struct uart_port *port)
1574 struct uart_8250_port *up = up_to_u8250p(port);
1575 struct uart_8250_em485 *em485 = up->em485;
1577 serial8250_rpm_get_tx(up);
1580 em485->active_timer == &em485->start_tx_timer)
1584 start_tx_rs485(port);
1589 static void serial8250_throttle(struct uart_port *port)
1591 port->throttle(port);
1594 static void serial8250_unthrottle(struct uart_port *port)
1596 port->unthrottle(port);
1599 static void serial8250_disable_ms(struct uart_port *port)
1601 struct uart_8250_port *up =
1602 container_of(port, struct uart_8250_port, port);
1604 /* no MSR capabilities */
1605 if (up->bugs & UART_BUG_NOMSR)
1608 up->ier &= ~UART_IER_MSI;
1609 serial_port_out(port, UART_IER, up->ier);
1612 static void serial8250_enable_ms(struct uart_port *port)
1614 struct uart_8250_port *up = up_to_u8250p(port);
1616 /* no MSR capabilities */
1617 if (up->bugs & UART_BUG_NOMSR)
1620 up->ier |= UART_IER_MSI;
1622 serial8250_rpm_get(up);
1623 serial_port_out(port, UART_IER, up->ier);
1624 serial8250_rpm_put(up);
1627 static void serial8250_read_char(struct uart_8250_port *up, unsigned char lsr)
1629 struct uart_port *port = &up->port;
1631 char flag = TTY_NORMAL;
1633 if (likely(lsr & UART_LSR_DR))
1634 ch = serial_in(up, UART_RX);
1637 * Intel 82571 has a Serial Over Lan device that will
1638 * set UART_LSR_BI without setting UART_LSR_DR when
1639 * it receives a break. To avoid reading from the
1640 * receive buffer without UART_LSR_DR bit set, we
1641 * just force the read character to be 0
1647 lsr |= up->lsr_saved_flags;
1648 up->lsr_saved_flags = 0;
1650 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1651 if (lsr & UART_LSR_BI) {
1652 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1655 * We do the SysRQ and SAK checking
1656 * here because otherwise the break
1657 * may get masked by ignore_status_mask
1658 * or read_status_mask.
1660 if (uart_handle_break(port))
1662 } else if (lsr & UART_LSR_PE)
1663 port->icount.parity++;
1664 else if (lsr & UART_LSR_FE)
1665 port->icount.frame++;
1666 if (lsr & UART_LSR_OE)
1667 port->icount.overrun++;
1670 * Mask off conditions which should be ignored.
1672 lsr &= port->read_status_mask;
1674 if (lsr & UART_LSR_BI) {
1675 DEBUG_INTR("handling break....");
1677 } else if (lsr & UART_LSR_PE)
1679 else if (lsr & UART_LSR_FE)
1682 if (uart_handle_sysrq_char(port, ch))
1685 uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
1689 * serial8250_rx_chars: processes according to the passed in LSR
1690 * value, and returns the remaining LSR bits not handled
1691 * by this Rx routine.
1693 unsigned char serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
1695 struct uart_port *port = &up->port;
1696 int max_count = 256;
1699 serial8250_read_char(up, lsr);
1700 if (--max_count == 0)
1702 lsr = serial_in(up, UART_LSR);
1703 } while (lsr & (UART_LSR_DR | UART_LSR_BI));
1705 tty_flip_buffer_push(&port->state->port);
1708 EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1710 void serial8250_tx_chars(struct uart_8250_port *up)
1712 struct uart_port *port = &up->port;
1713 struct circ_buf *xmit = &port->state->xmit;
1717 serial_out(up, UART_TX, port->x_char);
1722 if (uart_tx_stopped(port)) {
1723 serial8250_stop_tx(port);
1726 if (uart_circ_empty(xmit)) {
1731 count = up->tx_loadsz;
1733 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1734 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1736 if (uart_circ_empty(xmit))
1738 if ((up->capabilities & UART_CAP_HFIFO) &&
1739 (serial_in(up, UART_LSR) & BOTH_EMPTY) != BOTH_EMPTY)
1741 } while (--count > 0);
1743 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1744 uart_write_wakeup(port);
1746 DEBUG_INTR("THRE...");
1749 * With RPM enabled, we have to wait until the FIFO is empty before the
1750 * HW can go idle. So we get here once again with empty FIFO and disable
1751 * the interrupt and RPM in __stop_tx()
1753 if (uart_circ_empty(xmit) && !(up->capabilities & UART_CAP_RPM))
1756 EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1758 /* Caller holds uart port lock */
1759 unsigned int serial8250_modem_status(struct uart_8250_port *up)
1761 struct uart_port *port = &up->port;
1762 unsigned int status = serial_in(up, UART_MSR);
1764 status |= up->msr_saved_flags;
1765 up->msr_saved_flags = 0;
1766 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1767 port->state != NULL) {
1768 if (status & UART_MSR_TERI)
1770 if (status & UART_MSR_DDSR)
1772 if (status & UART_MSR_DDCD)
1773 uart_handle_dcd_change(port, status & UART_MSR_DCD);
1774 if (status & UART_MSR_DCTS)
1775 uart_handle_cts_change(port, status & UART_MSR_CTS);
1777 wake_up_interruptible(&port->state->port.delta_msr_wait);
1782 EXPORT_SYMBOL_GPL(serial8250_modem_status);
1785 * This handles the interrupt from one port.
1787 int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1789 unsigned char status;
1790 unsigned long flags;
1791 struct uart_8250_port *up = up_to_u8250p(port);
1794 if (iir & UART_IIR_NO_INT)
1797 spin_lock_irqsave(&port->lock, flags);
1799 status = serial_port_in(port, UART_LSR);
1801 DEBUG_INTR("status = %x...", status);
1803 if (status & (UART_LSR_DR | UART_LSR_BI)) {
1805 dma_err = up->dma->rx_dma(up, iir);
1807 if (!up->dma || dma_err)
1808 status = serial8250_rx_chars(up, status);
1810 serial8250_modem_status(up);
1811 if ((!up->dma || (up->dma && up->dma->tx_err)) &&
1812 (status & UART_LSR_THRE))
1813 serial8250_tx_chars(up);
1815 spin_unlock_irqrestore(&port->lock, flags);
1818 EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1820 static int serial8250_default_handle_irq(struct uart_port *port)
1822 struct uart_8250_port *up = up_to_u8250p(port);
1826 serial8250_rpm_get(up);
1828 iir = serial_port_in(port, UART_IIR);
1829 ret = serial8250_handle_irq(port, iir);
1831 serial8250_rpm_put(up);
1836 * These Exar UARTs have an extra interrupt indicator that could
1837 * fire for a few unimplemented interrupts. One of which is a
1838 * wakeup event when coming out of sleep. Put this here just
1839 * to be on the safe side that these interrupts don't go unhandled.
1841 static int exar_handle_irq(struct uart_port *port)
1843 unsigned char int0, int1, int2, int3;
1844 unsigned int iir = serial_port_in(port, UART_IIR);
1847 ret = serial8250_handle_irq(port, iir);
1849 if ((port->type == PORT_XR17V35X) ||
1850 (port->type == PORT_XR17D15X)) {
1851 int0 = serial_port_in(port, 0x80);
1852 int1 = serial_port_in(port, 0x81);
1853 int2 = serial_port_in(port, 0x82);
1854 int3 = serial_port_in(port, 0x83);
1860 static unsigned int serial8250_tx_empty(struct uart_port *port)
1862 struct uart_8250_port *up = up_to_u8250p(port);
1863 unsigned long flags;
1866 serial8250_rpm_get(up);
1868 spin_lock_irqsave(&port->lock, flags);
1869 lsr = serial_port_in(port, UART_LSR);
1870 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1871 spin_unlock_irqrestore(&port->lock, flags);
1873 serial8250_rpm_put(up);
1875 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1878 static unsigned int serial8250_get_mctrl(struct uart_port *port)
1880 struct uart_8250_port *up = up_to_u8250p(port);
1881 unsigned int status;
1884 serial8250_rpm_get(up);
1885 status = serial8250_modem_status(up);
1886 serial8250_rpm_put(up);
1889 if (status & UART_MSR_DCD)
1891 if (status & UART_MSR_RI)
1893 if (status & UART_MSR_DSR)
1895 if (status & UART_MSR_CTS)
1900 void serial8250_do_set_mctrl(struct uart_port *port, unsigned int mctrl)
1902 struct uart_8250_port *up = up_to_u8250p(port);
1903 unsigned char mcr = 0;
1905 if (mctrl & TIOCM_RTS)
1906 mcr |= UART_MCR_RTS;
1907 if (mctrl & TIOCM_DTR)
1908 mcr |= UART_MCR_DTR;
1909 if (mctrl & TIOCM_OUT1)
1910 mcr |= UART_MCR_OUT1;
1911 if (mctrl & TIOCM_OUT2)
1912 mcr |= UART_MCR_OUT2;
1913 if (mctrl & TIOCM_LOOP)
1914 mcr |= UART_MCR_LOOP;
1916 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1918 serial_port_out(port, UART_MCR, mcr);
1920 EXPORT_SYMBOL_GPL(serial8250_do_set_mctrl);
1922 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1924 if (port->set_mctrl)
1925 port->set_mctrl(port, mctrl);
1927 serial8250_do_set_mctrl(port, mctrl);
1930 static void serial8250_break_ctl(struct uart_port *port, int break_state)
1932 struct uart_8250_port *up = up_to_u8250p(port);
1933 unsigned long flags;
1935 serial8250_rpm_get(up);
1936 spin_lock_irqsave(&port->lock, flags);
1937 if (break_state == -1)
1938 up->lcr |= UART_LCR_SBC;
1940 up->lcr &= ~UART_LCR_SBC;
1941 serial_port_out(port, UART_LCR, up->lcr);
1942 spin_unlock_irqrestore(&port->lock, flags);
1943 serial8250_rpm_put(up);
1947 * Wait for transmitter & holding register to empty
1949 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
1951 unsigned int status, tmout = 10000;
1953 /* Wait up to 10ms for the character(s) to be sent. */
1955 status = serial_in(up, UART_LSR);
1957 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
1959 if ((status & bits) == bits)
1966 /* Wait up to 1s for flow control if necessary */
1967 if (up->port.flags & UPF_CONS_FLOW) {
1970 for (tmout = 1000000; tmout; tmout--) {
1971 unsigned int msr = serial_in(up, UART_MSR);
1972 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1973 if (msr & UART_MSR_CTS)
1976 touch_nmi_watchdog();
1981 #ifdef CONFIG_CONSOLE_POLL
1983 * Console polling routines for writing and reading from the uart while
1984 * in an interrupt or debug context.
1987 static int serial8250_get_poll_char(struct uart_port *port)
1989 struct uart_8250_port *up = up_to_u8250p(port);
1993 serial8250_rpm_get(up);
1995 lsr = serial_port_in(port, UART_LSR);
1997 if (!(lsr & UART_LSR_DR)) {
1998 status = NO_POLL_CHAR;
2002 status = serial_port_in(port, UART_RX);
2004 serial8250_rpm_put(up);
2009 static void serial8250_put_poll_char(struct uart_port *port,
2013 struct uart_8250_port *up = up_to_u8250p(port);
2015 serial8250_rpm_get(up);
2017 * First save the IER then disable the interrupts
2019 ier = serial_port_in(port, UART_IER);
2020 if (up->capabilities & UART_CAP_UUE)
2021 serial_port_out(port, UART_IER, UART_IER_UUE);
2023 serial_port_out(port, UART_IER, 0);
2025 wait_for_xmitr(up, BOTH_EMPTY);
2027 * Send the character out.
2029 serial_port_out(port, UART_TX, c);
2032 * Finally, wait for transmitter to become empty
2033 * and restore the IER
2035 wait_for_xmitr(up, BOTH_EMPTY);
2036 serial_port_out(port, UART_IER, ier);
2037 serial8250_rpm_put(up);
2040 #endif /* CONFIG_CONSOLE_POLL */
2042 int serial8250_do_startup(struct uart_port *port)
2044 struct uart_8250_port *up = up_to_u8250p(port);
2045 unsigned long flags;
2046 unsigned char lsr, iir;
2049 if (!port->fifosize)
2050 port->fifosize = uart_config[port->type].fifo_size;
2052 up->tx_loadsz = uart_config[port->type].tx_loadsz;
2053 if (!up->capabilities)
2054 up->capabilities = uart_config[port->type].flags;
2057 if (port->iotype != up->cur_iotype)
2058 set_io_from_upio(port);
2060 serial8250_rpm_get(up);
2061 if (port->type == PORT_16C950) {
2062 /* Wake up and initialize UART */
2064 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2065 serial_port_out(port, UART_EFR, UART_EFR_ECB);
2066 serial_port_out(port, UART_IER, 0);
2067 serial_port_out(port, UART_LCR, 0);
2068 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
2069 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2070 serial_port_out(port, UART_EFR, UART_EFR_ECB);
2071 serial_port_out(port, UART_LCR, 0);
2074 #ifdef CONFIG_SERIAL_8250_RSA
2076 * If this is an RSA port, see if we can kick it up to the
2077 * higher speed clock.
2082 if (port->type == PORT_XR17V35X) {
2084 * First enable access to IER [7:5], ISR [5:4], FCR [5:4],
2085 * MCR [7:5] and MSR [7:0]
2087 serial_port_out(port, UART_XR_EFR, UART_EFR_ECB);
2090 * Make sure all interrups are masked until initialization is
2091 * complete and the FIFOs are cleared
2093 serial_port_out(port, UART_IER, 0);
2097 * Clear the FIFO buffers and disable them.
2098 * (they will be reenabled in set_termios())
2100 serial8250_clear_fifos(up);
2103 * Clear the interrupt registers.
2105 serial_port_in(port, UART_LSR);
2106 serial_port_in(port, UART_RX);
2107 serial_port_in(port, UART_IIR);
2108 serial_port_in(port, UART_MSR);
2111 * At this point, there's no way the LSR could still be 0xff;
2112 * if it is, then bail out, because there's likely no UART
2115 if (!(port->flags & UPF_BUGGY_UART) &&
2116 (serial_port_in(port, UART_LSR) == 0xff)) {
2117 printk_ratelimited(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
2118 serial_index(port));
2124 * For a XR16C850, we need to set the trigger levels
2126 if (port->type == PORT_16850) {
2129 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
2131 fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2132 serial_port_out(port, UART_FCTR,
2133 fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2134 serial_port_out(port, UART_TRG, UART_TRG_96);
2135 serial_port_out(port, UART_FCTR,
2136 fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2137 serial_port_out(port, UART_TRG, UART_TRG_96);
2139 serial_port_out(port, UART_LCR, 0);
2145 * Test for UARTs that do not reassert THRE when the
2146 * transmitter is idle and the interrupt has already
2147 * been cleared. Real 16550s should always reassert
2148 * this interrupt whenever the transmitter is idle and
2149 * the interrupt is enabled. Delays are necessary to
2150 * allow register changes to become visible.
2152 spin_lock_irqsave(&port->lock, flags);
2153 if (up->port.irqflags & IRQF_SHARED)
2154 disable_irq_nosync(port->irq);
2156 wait_for_xmitr(up, UART_LSR_THRE);
2157 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2158 udelay(1); /* allow THRE to set */
2159 iir1 = serial_port_in(port, UART_IIR);
2160 serial_port_out(port, UART_IER, 0);
2161 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2162 udelay(1); /* allow a working UART time to re-assert THRE */
2163 iir = serial_port_in(port, UART_IIR);
2164 serial_port_out(port, UART_IER, 0);
2166 if (port->irqflags & IRQF_SHARED)
2167 enable_irq(port->irq);
2168 spin_unlock_irqrestore(&port->lock, flags);
2171 * If the interrupt is not reasserted, or we otherwise
2172 * don't trust the iir, setup a timer to kick the UART
2173 * on a regular basis.
2175 if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) ||
2176 up->port.flags & UPF_BUG_THRE) {
2177 up->bugs |= UART_BUG_THRE;
2181 retval = up->ops->setup_irq(up);
2186 * Now, initialize the UART
2188 serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
2190 spin_lock_irqsave(&port->lock, flags);
2191 if (up->port.flags & UPF_FOURPORT) {
2193 up->port.mctrl |= TIOCM_OUT1;
2196 * Most PC uarts need OUT2 raised to enable interrupts.
2199 up->port.mctrl |= TIOCM_OUT2;
2201 serial8250_set_mctrl(port, port->mctrl);
2204 * Serial over Lan (SoL) hack:
2205 * Intel 8257x Gigabit ethernet chips have a 16550 emulation, to be
2206 * used for Serial Over Lan. Those chips take a longer time than a
2207 * normal serial device to signalize that a transmission data was
2208 * queued. Due to that, the above test generally fails. One solution
2209 * would be to delay the reading of iir. However, this is not
2210 * reliable, since the timeout is variable. So, let's just don't
2211 * test if we receive TX irq. This way, we'll never enable
2214 if (up->port.flags & UPF_NO_TXEN_TEST)
2215 goto dont_test_tx_en;
2218 * Do a quick test to see if we receive an interrupt when we enable
2221 serial_port_out(port, UART_IER, UART_IER_THRI);
2222 lsr = serial_port_in(port, UART_LSR);
2223 iir = serial_port_in(port, UART_IIR);
2224 serial_port_out(port, UART_IER, 0);
2226 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2227 if (!(up->bugs & UART_BUG_TXEN)) {
2228 up->bugs |= UART_BUG_TXEN;
2229 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
2230 serial_index(port));
2233 up->bugs &= ~UART_BUG_TXEN;
2237 spin_unlock_irqrestore(&port->lock, flags);
2240 * Clear the interrupt registers again for luck, and clear the
2241 * saved flags to avoid getting false values from polling
2242 * routines or the previous session.
2244 serial_port_in(port, UART_LSR);
2245 serial_port_in(port, UART_RX);
2246 serial_port_in(port, UART_IIR);
2247 serial_port_in(port, UART_MSR);
2248 up->lsr_saved_flags = 0;
2249 up->msr_saved_flags = 0;
2252 * Request DMA channels for both RX and TX.
2255 retval = serial8250_request_dma(up);
2257 pr_warn_ratelimited("ttyS%d - failed to request DMA\n",
2258 serial_index(port));
2264 * Set the IER shadow for rx interrupts but defer actual interrupt
2265 * enable until after the FIFOs are enabled; otherwise, an already-
2266 * active sender can swamp the interrupt handler with "too much work".
2268 up->ier = UART_IER_RLSI | UART_IER_RDI;
2270 if (port->flags & UPF_FOURPORT) {
2273 * Enable interrupts on the AST Fourport board
2275 icp = (port->iobase & 0xfe0) | 0x01f;
2281 serial8250_rpm_put(up);
2284 EXPORT_SYMBOL_GPL(serial8250_do_startup);
2286 static int serial8250_startup(struct uart_port *port)
2289 return port->startup(port);
2290 return serial8250_do_startup(port);
2293 void serial8250_do_shutdown(struct uart_port *port)
2295 struct uart_8250_port *up = up_to_u8250p(port);
2296 unsigned long flags;
2298 serial8250_rpm_get(up);
2300 * Disable interrupts from this port
2302 spin_lock_irqsave(&port->lock, flags);
2304 serial_port_out(port, UART_IER, 0);
2305 spin_unlock_irqrestore(&port->lock, flags);
2307 synchronize_irq(port->irq);
2310 serial8250_release_dma(up);
2312 spin_lock_irqsave(&port->lock, flags);
2313 if (port->flags & UPF_FOURPORT) {
2314 /* reset interrupts on the AST Fourport board */
2315 inb((port->iobase & 0xfe0) | 0x1f);
2316 port->mctrl |= TIOCM_OUT1;
2318 port->mctrl &= ~TIOCM_OUT2;
2320 serial8250_set_mctrl(port, port->mctrl);
2321 spin_unlock_irqrestore(&port->lock, flags);
2324 * Disable break condition and FIFOs
2326 serial_port_out(port, UART_LCR,
2327 serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
2328 serial8250_clear_fifos(up);
2330 #ifdef CONFIG_SERIAL_8250_RSA
2332 * Reset the RSA board back to 115kbps compat mode.
2338 * Read data port to reset things, and then unlink from
2341 serial_port_in(port, UART_RX);
2342 serial8250_rpm_put(up);
2344 up->ops->release_irq(up);
2346 EXPORT_SYMBOL_GPL(serial8250_do_shutdown);
2348 static void serial8250_shutdown(struct uart_port *port)
2351 port->shutdown(port);
2353 serial8250_do_shutdown(port);
2357 * XR17V35x UARTs have an extra fractional divisor register (DLD)
2358 * Calculate divisor with extra 4-bit fractional portion
2360 static unsigned int xr17v35x_get_divisor(struct uart_8250_port *up,
2364 struct uart_port *port = &up->port;
2365 unsigned int quot_16;
2367 quot_16 = DIV_ROUND_CLOSEST(port->uartclk, baud);
2368 *frac = quot_16 & 0x0f;
2370 return quot_16 >> 4;
2373 static unsigned int serial8250_get_divisor(struct uart_8250_port *up,
2377 struct uart_port *port = &up->port;
2381 * Handle magic divisors for baud rates above baud_base on
2382 * SMSC SuperIO chips.
2385 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2386 baud == (port->uartclk/4))
2388 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2389 baud == (port->uartclk/8))
2391 else if (up->port.type == PORT_XR17V35X)
2392 quot = xr17v35x_get_divisor(up, baud, frac);
2394 quot = uart_get_divisor(port, baud);
2397 * Oxford Semi 952 rev B workaround
2399 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2405 static unsigned char serial8250_compute_lcr(struct uart_8250_port *up,
2410 switch (c_cflag & CSIZE) {
2412 cval = UART_LCR_WLEN5;
2415 cval = UART_LCR_WLEN6;
2418 cval = UART_LCR_WLEN7;
2422 cval = UART_LCR_WLEN8;
2426 if (c_cflag & CSTOPB)
2427 cval |= UART_LCR_STOP;
2428 if (c_cflag & PARENB) {
2429 cval |= UART_LCR_PARITY;
2430 if (up->bugs & UART_BUG_PARITY)
2431 up->fifo_bug = true;
2433 if (!(c_cflag & PARODD))
2434 cval |= UART_LCR_EPAR;
2436 if (c_cflag & CMSPAR)
2437 cval |= UART_LCR_SPAR;
2443 static void serial8250_set_divisor(struct uart_port *port, unsigned int baud,
2444 unsigned int quot, unsigned int quot_frac)
2446 struct uart_8250_port *up = up_to_u8250p(port);
2448 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2449 if (is_omap1510_8250(up)) {
2450 if (baud == 115200) {
2452 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1);
2454 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0);
2458 * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2459 * otherwise just set DLAB
2461 if (up->capabilities & UART_NATSEMI)
2462 serial_port_out(port, UART_LCR, 0xe0);
2464 serial_port_out(port, UART_LCR, up->lcr | UART_LCR_DLAB);
2466 serial_dl_write(up, quot);
2468 /* XR17V35x UARTs have an extra fractional divisor register (DLD) */
2469 if (up->port.type == PORT_XR17V35X)
2470 serial_port_out(port, 0x2, quot_frac);
2474 serial8250_get_baud_rate(struct uart_port *port, struct ktermios *termios,
2475 struct ktermios *old)
2477 unsigned int tolerance = port->uartclk / 100;
2480 * Ask the core to calculate the divisor for us.
2481 * Allow 1% tolerance at the upper limit so uart clks marginally
2482 * slower than nominal still match standard baud rates without
2483 * causing transmission errors.
2485 return uart_get_baud_rate(port, termios, old,
2486 port->uartclk / 16 / 0xffff,
2487 (port->uartclk + tolerance) / 16);
2491 serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2492 struct ktermios *old)
2494 struct uart_8250_port *up = up_to_u8250p(port);
2496 unsigned long flags;
2497 unsigned int baud, quot, frac = 0;
2499 cval = serial8250_compute_lcr(up, termios->c_cflag);
2501 baud = serial8250_get_baud_rate(port, termios, old);
2502 quot = serial8250_get_divisor(up, baud, &frac);
2505 * Ok, we're now changing the port state. Do it with
2506 * interrupts disabled.
2508 serial8250_rpm_get(up);
2509 spin_lock_irqsave(&port->lock, flags);
2511 up->lcr = cval; /* Save computed LCR */
2513 if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
2514 /* NOTE: If fifo_bug is not set, a user can set RX_trigger. */
2515 if ((baud < 2400 && !up->dma) || up->fifo_bug) {
2516 up->fcr &= ~UART_FCR_TRIGGER_MASK;
2517 up->fcr |= UART_FCR_TRIGGER_1;
2522 * MCR-based auto flow control. When AFE is enabled, RTS will be
2523 * deasserted when the receive FIFO contains more characters than
2524 * the trigger, or the MCR RTS bit is cleared. In the case where
2525 * the remote UART is not using CTS auto flow control, we must
2526 * have sufficient FIFO entries for the latency of the remote
2527 * UART to respond. IOW, at least 32 bytes of FIFO.
2529 if (up->capabilities & UART_CAP_AFE && port->fifosize >= 32) {
2530 up->mcr &= ~UART_MCR_AFE;
2531 if (termios->c_cflag & CRTSCTS)
2532 up->mcr |= UART_MCR_AFE;
2536 * Update the per-port timeout.
2538 uart_update_timeout(port, termios->c_cflag, baud);
2540 port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2541 if (termios->c_iflag & INPCK)
2542 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2543 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2544 port->read_status_mask |= UART_LSR_BI;
2547 * Characteres to ignore
2549 port->ignore_status_mask = 0;
2550 if (termios->c_iflag & IGNPAR)
2551 port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2552 if (termios->c_iflag & IGNBRK) {
2553 port->ignore_status_mask |= UART_LSR_BI;
2555 * If we're ignoring parity and break indicators,
2556 * ignore overruns too (for real raw support).
2558 if (termios->c_iflag & IGNPAR)
2559 port->ignore_status_mask |= UART_LSR_OE;
2563 * ignore all characters if CREAD is not set
2565 if ((termios->c_cflag & CREAD) == 0)
2566 port->ignore_status_mask |= UART_LSR_DR;
2569 * CTS flow control flag and modem status interrupts
2571 up->ier &= ~UART_IER_MSI;
2572 if (!(up->bugs & UART_BUG_NOMSR) &&
2573 UART_ENABLE_MS(&up->port, termios->c_cflag))
2574 up->ier |= UART_IER_MSI;
2575 if (up->capabilities & UART_CAP_UUE)
2576 up->ier |= UART_IER_UUE;
2577 if (up->capabilities & UART_CAP_RTOIE)
2578 up->ier |= UART_IER_RTOIE;
2580 serial_port_out(port, UART_IER, up->ier);
2582 if (up->capabilities & UART_CAP_EFR) {
2583 unsigned char efr = 0;
2585 * TI16C752/Startech hardware flow control. FIXME:
2586 * - TI16C752 requires control thresholds to be set.
2587 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2589 if (termios->c_cflag & CRTSCTS)
2590 efr |= UART_EFR_CTS;
2592 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2593 if (port->flags & UPF_EXAR_EFR)
2594 serial_port_out(port, UART_XR_EFR, efr);
2596 serial_port_out(port, UART_EFR, efr);
2599 serial8250_set_divisor(port, baud, quot, frac);
2602 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2603 * is written without DLAB set, this mode will be disabled.
2605 if (port->type == PORT_16750)
2606 serial_port_out(port, UART_FCR, up->fcr);
2608 serial_port_out(port, UART_LCR, up->lcr); /* reset DLAB */
2609 if (port->type != PORT_16750) {
2610 /* emulated UARTs (Lucent Venus 167x) need two steps */
2611 if (up->fcr & UART_FCR_ENABLE_FIFO)
2612 serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
2613 serial_port_out(port, UART_FCR, up->fcr); /* set fcr */
2615 serial8250_set_mctrl(port, port->mctrl);
2616 spin_unlock_irqrestore(&port->lock, flags);
2617 serial8250_rpm_put(up);
2619 /* Don't rewrite B0 */
2620 if (tty_termios_baud_rate(termios))
2621 tty_termios_encode_baud_rate(termios, baud, baud);
2623 EXPORT_SYMBOL(serial8250_do_set_termios);
2626 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2627 struct ktermios *old)
2629 if (port->set_termios)
2630 port->set_termios(port, termios, old);
2632 serial8250_do_set_termios(port, termios, old);
2636 serial8250_set_ldisc(struct uart_port *port, struct ktermios *termios)
2638 if (termios->c_line == N_PPS) {
2639 port->flags |= UPF_HARDPPS_CD;
2640 spin_lock_irq(&port->lock);
2641 serial8250_enable_ms(port);
2642 spin_unlock_irq(&port->lock);
2644 port->flags &= ~UPF_HARDPPS_CD;
2645 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2646 spin_lock_irq(&port->lock);
2647 serial8250_disable_ms(port);
2648 spin_unlock_irq(&port->lock);
2654 void serial8250_do_pm(struct uart_port *port, unsigned int state,
2655 unsigned int oldstate)
2657 struct uart_8250_port *p = up_to_u8250p(port);
2659 serial8250_set_sleep(p, state != 0);
2661 EXPORT_SYMBOL(serial8250_do_pm);
2664 serial8250_pm(struct uart_port *port, unsigned int state,
2665 unsigned int oldstate)
2668 port->pm(port, state, oldstate);
2670 serial8250_do_pm(port, state, oldstate);
2673 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2675 if (pt->port.mapsize)
2676 return pt->port.mapsize;
2677 if (pt->port.iotype == UPIO_AU) {
2678 if (pt->port.type == PORT_RT2880)
2682 if (is_omap1_8250(pt))
2683 return 0x16 << pt->port.regshift;
2685 return 8 << pt->port.regshift;
2689 * Resource handling.
2691 static int serial8250_request_std_resource(struct uart_8250_port *up)
2693 unsigned int size = serial8250_port_size(up);
2694 struct uart_port *port = &up->port;
2697 switch (port->iotype) {
2707 if (!request_mem_region(port->mapbase, size, "serial")) {
2712 if (port->flags & UPF_IOREMAP) {
2713 port->membase = ioremap_nocache(port->mapbase, size);
2714 if (!port->membase) {
2715 release_mem_region(port->mapbase, size);
2723 if (!request_region(port->iobase, size, "serial"))
2730 static void serial8250_release_std_resource(struct uart_8250_port *up)
2732 unsigned int size = serial8250_port_size(up);
2733 struct uart_port *port = &up->port;
2735 switch (port->iotype) {
2745 if (port->flags & UPF_IOREMAP) {
2746 iounmap(port->membase);
2747 port->membase = NULL;
2750 release_mem_region(port->mapbase, size);
2755 release_region(port->iobase, size);
2760 static void serial8250_release_port(struct uart_port *port)
2762 struct uart_8250_port *up = up_to_u8250p(port);
2764 serial8250_release_std_resource(up);
2767 static int serial8250_request_port(struct uart_port *port)
2769 struct uart_8250_port *up = up_to_u8250p(port);
2771 return serial8250_request_std_resource(up);
2774 static int fcr_get_rxtrig_bytes(struct uart_8250_port *up)
2776 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2777 unsigned char bytes;
2779 bytes = conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(up->fcr)];
2781 return bytes ? bytes : -EOPNOTSUPP;
2784 static int bytes_to_fcr_rxtrig(struct uart_8250_port *up, unsigned char bytes)
2786 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2789 if (!conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(UART_FCR_R_TRIG_00)])
2792 for (i = 1; i < UART_FCR_R_TRIG_MAX_STATE; i++) {
2793 if (bytes < conf_type->rxtrig_bytes[i])
2794 /* Use the nearest lower value */
2795 return (--i) << UART_FCR_R_TRIG_SHIFT;
2798 return UART_FCR_R_TRIG_11;
2801 static int do_get_rxtrig(struct tty_port *port)
2803 struct uart_state *state = container_of(port, struct uart_state, port);
2804 struct uart_port *uport = state->uart_port;
2805 struct uart_8250_port *up =
2806 container_of(uport, struct uart_8250_port, port);
2808 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1)
2811 return fcr_get_rxtrig_bytes(up);
2814 static int do_serial8250_get_rxtrig(struct tty_port *port)
2818 mutex_lock(&port->mutex);
2819 rxtrig_bytes = do_get_rxtrig(port);
2820 mutex_unlock(&port->mutex);
2822 return rxtrig_bytes;
2825 static ssize_t serial8250_get_attr_rx_trig_bytes(struct device *dev,
2826 struct device_attribute *attr, char *buf)
2828 struct tty_port *port = dev_get_drvdata(dev);
2831 rxtrig_bytes = do_serial8250_get_rxtrig(port);
2832 if (rxtrig_bytes < 0)
2833 return rxtrig_bytes;
2835 return snprintf(buf, PAGE_SIZE, "%d\n", rxtrig_bytes);
2838 static int do_set_rxtrig(struct tty_port *port, unsigned char bytes)
2840 struct uart_state *state = container_of(port, struct uart_state, port);
2841 struct uart_port *uport = state->uart_port;
2842 struct uart_8250_port *up =
2843 container_of(uport, struct uart_8250_port, port);
2846 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1 ||
2850 rxtrig = bytes_to_fcr_rxtrig(up, bytes);
2854 serial8250_clear_fifos(up);
2855 up->fcr &= ~UART_FCR_TRIGGER_MASK;
2856 up->fcr |= (unsigned char)rxtrig;
2857 serial_out(up, UART_FCR, up->fcr);
2861 static int do_serial8250_set_rxtrig(struct tty_port *port, unsigned char bytes)
2865 mutex_lock(&port->mutex);
2866 ret = do_set_rxtrig(port, bytes);
2867 mutex_unlock(&port->mutex);
2872 static ssize_t serial8250_set_attr_rx_trig_bytes(struct device *dev,
2873 struct device_attribute *attr, const char *buf, size_t count)
2875 struct tty_port *port = dev_get_drvdata(dev);
2876 unsigned char bytes;
2882 ret = kstrtou8(buf, 10, &bytes);
2886 ret = do_serial8250_set_rxtrig(port, bytes);
2893 static DEVICE_ATTR(rx_trig_bytes, S_IRUSR | S_IWUSR | S_IRGRP,
2894 serial8250_get_attr_rx_trig_bytes,
2895 serial8250_set_attr_rx_trig_bytes);
2897 static struct attribute *serial8250_dev_attrs[] = {
2898 &dev_attr_rx_trig_bytes.attr,
2902 static struct attribute_group serial8250_dev_attr_group = {
2903 .attrs = serial8250_dev_attrs,
2906 static void register_dev_spec_attr_grp(struct uart_8250_port *up)
2908 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2910 if (conf_type->rxtrig_bytes[0])
2911 up->port.attr_group = &serial8250_dev_attr_group;
2914 static void serial8250_config_port(struct uart_port *port, int flags)
2916 struct uart_8250_port *up = up_to_u8250p(port);
2920 * Find the region that we can probe for. This in turn
2921 * tells us whether we can probe for the type of port.
2923 ret = serial8250_request_std_resource(up);
2927 if (port->iotype != up->cur_iotype)
2928 set_io_from_upio(port);
2930 if (flags & UART_CONFIG_TYPE)
2933 /* if access method is AU, it is a 16550 with a quirk */
2934 if (port->type == PORT_16550A && port->iotype == UPIO_AU)
2935 up->bugs |= UART_BUG_NOMSR;
2937 /* HW bugs may trigger IRQ while IIR == NO_INT */
2938 if (port->type == PORT_TEGRA)
2939 up->bugs |= UART_BUG_NOMSR;
2941 if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2944 if (port->type == PORT_UNKNOWN)
2945 serial8250_release_std_resource(up);
2947 /* Fixme: probably not the best place for this */
2948 if ((port->type == PORT_XR17V35X) ||
2949 (port->type == PORT_XR17D15X))
2950 port->handle_irq = exar_handle_irq;
2952 register_dev_spec_attr_grp(up);
2953 up->fcr = uart_config[up->port.type].fcr;
2957 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2959 if (ser->irq >= nr_irqs || ser->irq < 0 ||
2960 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2961 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2962 ser->type == PORT_STARTECH)
2967 static const char *serial8250_type(struct uart_port *port)
2969 int type = port->type;
2971 if (type >= ARRAY_SIZE(uart_config))
2973 return uart_config[type].name;
2976 static const struct uart_ops serial8250_pops = {
2977 .tx_empty = serial8250_tx_empty,
2978 .set_mctrl = serial8250_set_mctrl,
2979 .get_mctrl = serial8250_get_mctrl,
2980 .stop_tx = serial8250_stop_tx,
2981 .start_tx = serial8250_start_tx,
2982 .throttle = serial8250_throttle,
2983 .unthrottle = serial8250_unthrottle,
2984 .stop_rx = serial8250_stop_rx,
2985 .enable_ms = serial8250_enable_ms,
2986 .break_ctl = serial8250_break_ctl,
2987 .startup = serial8250_startup,
2988 .shutdown = serial8250_shutdown,
2989 .set_termios = serial8250_set_termios,
2990 .set_ldisc = serial8250_set_ldisc,
2991 .pm = serial8250_pm,
2992 .type = serial8250_type,
2993 .release_port = serial8250_release_port,
2994 .request_port = serial8250_request_port,
2995 .config_port = serial8250_config_port,
2996 .verify_port = serial8250_verify_port,
2997 #ifdef CONFIG_CONSOLE_POLL
2998 .poll_get_char = serial8250_get_poll_char,
2999 .poll_put_char = serial8250_put_poll_char,
3003 void serial8250_init_port(struct uart_8250_port *up)
3005 struct uart_port *port = &up->port;
3007 spin_lock_init(&port->lock);
3008 port->ops = &serial8250_pops;
3010 up->cur_iotype = 0xFF;
3012 EXPORT_SYMBOL_GPL(serial8250_init_port);
3014 void serial8250_set_defaults(struct uart_8250_port *up)
3016 struct uart_port *port = &up->port;
3018 if (up->port.flags & UPF_FIXED_TYPE) {
3019 unsigned int type = up->port.type;
3021 if (!up->port.fifosize)
3022 up->port.fifosize = uart_config[type].fifo_size;
3024 up->tx_loadsz = uart_config[type].tx_loadsz;
3025 if (!up->capabilities)
3026 up->capabilities = uart_config[type].flags;
3029 set_io_from_upio(port);
3031 /* default dma handlers */
3033 if (!up->dma->tx_dma)
3034 up->dma->tx_dma = serial8250_tx_dma;
3035 if (!up->dma->rx_dma)
3036 up->dma->rx_dma = serial8250_rx_dma;
3039 EXPORT_SYMBOL_GPL(serial8250_set_defaults);
3041 #ifdef CONFIG_SERIAL_8250_CONSOLE
3043 static void serial8250_console_putchar(struct uart_port *port, int ch)
3045 struct uart_8250_port *up = up_to_u8250p(port);
3047 wait_for_xmitr(up, UART_LSR_THRE);
3048 serial_port_out(port, UART_TX, ch);
3052 * Restore serial console when h/w power-off detected
3054 static void serial8250_console_restore(struct uart_8250_port *up)
3056 struct uart_port *port = &up->port;
3057 struct ktermios termios;
3058 unsigned int baud, quot, frac = 0;
3060 termios.c_cflag = port->cons->cflag;
3061 if (port->state->port.tty && termios.c_cflag == 0)
3062 termios.c_cflag = port->state->port.tty->termios.c_cflag;
3064 baud = serial8250_get_baud_rate(port, &termios, NULL);
3065 quot = serial8250_get_divisor(up, baud, &frac);
3067 serial8250_set_divisor(port, baud, quot, frac);
3068 serial_port_out(port, UART_LCR, up->lcr);
3069 serial_port_out(port, UART_MCR, UART_MCR_DTR | UART_MCR_RTS);
3073 * Print a string to the serial port trying not to disturb
3074 * any possible real use of the port...
3076 * The console_lock must be held when we get here.
3078 void serial8250_console_write(struct uart_8250_port *up, const char *s,
3081 struct uart_port *port = &up->port;
3082 unsigned long flags;
3086 touch_nmi_watchdog();
3088 serial8250_rpm_get(up);
3092 else if (oops_in_progress)
3093 locked = spin_trylock_irqsave(&port->lock, flags);
3095 spin_lock_irqsave(&port->lock, flags);
3098 * First save the IER then disable the interrupts
3100 ier = serial_port_in(port, UART_IER);
3102 if (up->capabilities & UART_CAP_UUE)
3103 serial_port_out(port, UART_IER, UART_IER_UUE);
3105 serial_port_out(port, UART_IER, 0);
3107 /* check scratch reg to see if port powered off during system sleep */
3108 if (up->canary && (up->canary != serial_port_in(port, UART_SCR))) {
3109 serial8250_console_restore(up);
3113 uart_console_write(port, s, count, serial8250_console_putchar);
3116 * Finally, wait for transmitter to become empty
3117 * and restore the IER
3119 wait_for_xmitr(up, BOTH_EMPTY);
3120 serial_port_out(port, UART_IER, ier);
3123 * The receive handling will happen properly because the
3124 * receive ready bit will still be set; it is not cleared
3125 * on read. However, modem control will not, we must
3126 * call it if we have saved something in the saved flags
3127 * while processing with interrupts off.
3129 if (up->msr_saved_flags)
3130 serial8250_modem_status(up);
3133 spin_unlock_irqrestore(&port->lock, flags);
3134 serial8250_rpm_put(up);
3137 static unsigned int probe_baud(struct uart_port *port)
3139 unsigned char lcr, dll, dlm;
3142 lcr = serial_port_in(port, UART_LCR);
3143 serial_port_out(port, UART_LCR, lcr | UART_LCR_DLAB);
3144 dll = serial_port_in(port, UART_DLL);
3145 dlm = serial_port_in(port, UART_DLM);
3146 serial_port_out(port, UART_LCR, lcr);
3148 quot = (dlm << 8) | dll;
3149 return (port->uartclk / 16) / quot;
3152 int serial8250_console_setup(struct uart_port *port, char *options, bool probe)
3159 if (!port->iobase && !port->membase)
3163 uart_parse_options(options, &baud, &parity, &bits, &flow);
3165 baud = probe_baud(port);
3167 return uart_set_options(port, port->cons, baud, parity, bits, flow);
3170 #endif /* CONFIG_SERIAL_8250_CONSOLE */
3172 MODULE_LICENSE("GPL");