drivers/tty/serial/fsl_lpuart.c

   1 /*
   2  *  Freescale lpuart serial port driver
   3  *
   4  *  Copyright 2012-2014 Freescale Semiconductor, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  */
  11
  12 #if defined(CONFIG_SERIAL_FSL_LPUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  13 #define SUPPORT_SYSRQ
  14 #endif
  15
  16 #include <linux/clk.h>
  17 #include <linux/console.h>
  18 #include <linux/dma-mapping.h>
  19 #include <linux/dmaengine.h>
  20 #include <linux/dmapool.h>
  21 #include <linux/io.h>
  22 #include <linux/irq.h>
  23 #include <linux/module.h>
  24 #include <linux/of.h>
  25 #include <linux/of_device.h>
  26 #include <linux/of_dma.h>
  27 #include <linux/serial_core.h>
  28 #include <linux/slab.h>
  29 #include <linux/tty_flip.h>
  30
  31 /* All registers are 8-bit width */
  32 #define UARTBDH                 0x00
  33 #define UARTBDL                 0x01
  34 #define UARTCR1                 0x02
  35 #define UARTCR2                 0x03
  36 #define UARTSR1                 0x04
  37 #define UARTCR3                 0x06
  38 #define UARTDR                  0x07
  39 #define UARTCR4                 0x0a
  40 #define UARTCR5                 0x0b
  41 #define UARTMODEM               0x0d
  42 #define UARTPFIFO               0x10
  43 #define UARTCFIFO               0x11
  44 #define UARTSFIFO               0x12
  45 #define UARTTWFIFO              0x13
  46 #define UARTTCFIFO              0x14
  47 #define UARTRWFIFO              0x15
  48
  49 #define UARTBDH_LBKDIE          0x80
  50 #define UARTBDH_RXEDGIE         0x40
  51 #define UARTBDH_SBR_MASK        0x1f
  52
  53 #define UARTCR1_LOOPS           0x80
  54 #define UARTCR1_RSRC            0x20
  55 #define UARTCR1_M               0x10
  56 #define UARTCR1_WAKE            0x08
  57 #define UARTCR1_ILT             0x04
  58 #define UARTCR1_PE              0x02
  59 #define UARTCR1_PT              0x01
  60
  61 #define UARTCR2_TIE             0x80
  62 #define UARTCR2_TCIE            0x40
  63 #define UARTCR2_RIE             0x20
  64 #define UARTCR2_ILIE            0x10
  65 #define UARTCR2_TE              0x08
  66 #define UARTCR2_RE              0x04
  67 #define UARTCR2_RWU             0x02
  68 #define UARTCR2_SBK             0x01
  69
  70 #define UARTSR1_TDRE            0x80
  71 #define UARTSR1_TC              0x40
  72 #define UARTSR1_RDRF            0x20
  73 #define UARTSR1_IDLE            0x10
  74 #define UARTSR1_OR              0x08
  75 #define UARTSR1_NF              0x04
  76 #define UARTSR1_FE              0x02
  77 #define UARTSR1_PE              0x01
  78
  79 #define UARTCR3_R8              0x80
  80 #define UARTCR3_T8              0x40
  81 #define UARTCR3_TXDIR           0x20
  82 #define UARTCR3_TXINV           0x10
  83 #define UARTCR3_ORIE            0x08
  84 #define UARTCR3_NEIE            0x04
  85 #define UARTCR3_FEIE            0x02
  86 #define UARTCR3_PEIE            0x01
  87
  88 #define UARTCR4_MAEN1           0x80
  89 #define UARTCR4_MAEN2           0x40
  90 #define UARTCR4_M10             0x20
  91 #define UARTCR4_BRFA_MASK       0x1f
  92 #define UARTCR4_BRFA_OFF        0
  93
  94 #define UARTCR5_TDMAS           0x80
  95 #define UARTCR5_RDMAS           0x20
  96
  97 #define UARTMODEM_RXRTSE        0x08
  98 #define UARTMODEM_TXRTSPOL      0x04
  99 #define UARTMODEM_TXRTSE        0x02
 100 #define UARTMODEM_TXCTSE        0x01
 101
 102 #define UARTPFIFO_TXFE          0x80
 103 #define UARTPFIFO_FIFOSIZE_MASK 0x7
 104 #define UARTPFIFO_TXSIZE_OFF    4
 105 #define UARTPFIFO_RXFE          0x08
 106 #define UARTPFIFO_RXSIZE_OFF    0
 107
 108 #define UARTCFIFO_TXFLUSH       0x80
 109 #define UARTCFIFO_RXFLUSH       0x40
 110 #define UARTCFIFO_RXOFE         0x04
 111 #define UARTCFIFO_TXOFE         0x02
 112 #define UARTCFIFO_RXUFE         0x01
 113
 114 #define UARTSFIFO_TXEMPT        0x80
 115 #define UARTSFIFO_RXEMPT        0x40
 116 #define UARTSFIFO_RXOF          0x04
 117 #define UARTSFIFO_TXOF          0x02
 118 #define UARTSFIFO_RXUF          0x01
 119
 120 /* 32-bit register defination */
 121 #define UARTBAUD                0x00
 122 #define UARTSTAT                0x04
 123 #define UARTCTRL                0x08
 124 #define UARTDATA                0x0C
 125 #define UARTMATCH               0x10
 126 #define UARTMODIR               0x14
 127 #define UARTFIFO                0x18
 128 #define UARTWATER               0x1c
 129
 130 #define UARTBAUD_MAEN1          0x80000000
 131 #define UARTBAUD_MAEN2          0x40000000
 132 #define UARTBAUD_M10            0x20000000
 133 #define UARTBAUD_TDMAE          0x00800000
 134 #define UARTBAUD_RDMAE          0x00200000
 135 #define UARTBAUD_MATCFG         0x00400000
 136 #define UARTBAUD_BOTHEDGE       0x00020000
 137 #define UARTBAUD_RESYNCDIS      0x00010000
 138 #define UARTBAUD_LBKDIE         0x00008000
 139 #define UARTBAUD_RXEDGIE        0x00004000
 140 #define UARTBAUD_SBNS           0x00002000
 141 #define UARTBAUD_SBR            0x00000000
 142 #define UARTBAUD_SBR_MASK       0x1fff
 143
 144 #define UARTSTAT_LBKDIF         0x80000000
 145 #define UARTSTAT_RXEDGIF        0x40000000
 146 #define UARTSTAT_MSBF           0x20000000
 147 #define UARTSTAT_RXINV          0x10000000
 148 #define UARTSTAT_RWUID          0x08000000
 149 #define UARTSTAT_BRK13          0x04000000
 150 #define UARTSTAT_LBKDE          0x02000000
 151 #define UARTSTAT_RAF            0x01000000
 152 #define UARTSTAT_TDRE           0x00800000
 153 #define UARTSTAT_TC             0x00400000
 154 #define UARTSTAT_RDRF           0x00200000
 155 #define UARTSTAT_IDLE           0x00100000
 156 #define UARTSTAT_OR             0x00080000
 157 #define UARTSTAT_NF             0x00040000
 158 #define UARTSTAT_FE             0x00020000
 159 #define UARTSTAT_PE             0x00010000
 160 #define UARTSTAT_MA1F           0x00008000
 161 #define UARTSTAT_M21F           0x00004000
 162
 163 #define UARTCTRL_R8T9           0x80000000
 164 #define UARTCTRL_R9T8           0x40000000
 165 #define UARTCTRL_TXDIR          0x20000000
 166 #define UARTCTRL_TXINV          0x10000000
 167 #define UARTCTRL_ORIE           0x08000000
 168 #define UARTCTRL_NEIE           0x04000000
 169 #define UARTCTRL_FEIE           0x02000000
 170 #define UARTCTRL_PEIE           0x01000000
 171 #define UARTCTRL_TIE            0x00800000
 172 #define UARTCTRL_TCIE           0x00400000
 173 #define UARTCTRL_RIE            0x00200000
 174 #define UARTCTRL_ILIE           0x00100000
 175 #define UARTCTRL_TE             0x00080000
 176 #define UARTCTRL_RE             0x00040000
 177 #define UARTCTRL_RWU            0x00020000
 178 #define UARTCTRL_SBK            0x00010000
 179 #define UARTCTRL_MA1IE          0x00008000
 180 #define UARTCTRL_MA2IE          0x00004000
 181 #define UARTCTRL_IDLECFG        0x00000100
 182 #define UARTCTRL_LOOPS          0x00000080
 183 #define UARTCTRL_DOZEEN         0x00000040
 184 #define UARTCTRL_RSRC           0x00000020
 185 #define UARTCTRL_M              0x00000010
 186 #define UARTCTRL_WAKE           0x00000008
 187 #define UARTCTRL_ILT            0x00000004
 188 #define UARTCTRL_PE             0x00000002
 189 #define UARTCTRL_PT             0x00000001
 190
 191 #define UARTDATA_NOISY          0x00008000
 192 #define UARTDATA_PARITYE        0x00004000
 193 #define UARTDATA_FRETSC         0x00002000
 194 #define UARTDATA_RXEMPT         0x00001000
 195 #define UARTDATA_IDLINE         0x00000800
 196 #define UARTDATA_MASK           0x3ff
 197
 198 #define UARTMODIR_IREN          0x00020000
 199 #define UARTMODIR_TXCTSSRC      0x00000020
 200 #define UARTMODIR_TXCTSC        0x00000010
 201 #define UARTMODIR_RXRTSE        0x00000008
 202 #define UARTMODIR_TXRTSPOL      0x00000004
 203 #define UARTMODIR_TXRTSE        0x00000002
 204 #define UARTMODIR_TXCTSE        0x00000001
 205
 206 #define UARTFIFO_TXEMPT         0x00800000
 207 #define UARTFIFO_RXEMPT         0x00400000
 208 #define UARTFIFO_TXOF           0x00020000
 209 #define UARTFIFO_RXUF           0x00010000
 210 #define UARTFIFO_TXFLUSH        0x00008000
 211 #define UARTFIFO_RXFLUSH        0x00004000
 212 #define UARTFIFO_TXOFE          0x00000200
 213 #define UARTFIFO_RXUFE          0x00000100
 214 #define UARTFIFO_TXFE           0x00000080
 215 #define UARTFIFO_FIFOSIZE_MASK  0x7
 216 #define UARTFIFO_TXSIZE_OFF     4
 217 #define UARTFIFO_RXFE           0x00000008
 218 #define UARTFIFO_RXSIZE_OFF     0
 219
 220 #define UARTWATER_COUNT_MASK    0xff
 221 #define UARTWATER_TXCNT_OFF     8
 222 #define UARTWATER_RXCNT_OFF     24
 223 #define UARTWATER_WATER_MASK    0xff
 224 #define UARTWATER_TXWATER_OFF   0
 225 #define UARTWATER_RXWATER_OFF   16
 226
 227 /* Rx DMA timeout in ms, which is used to calculate Rx ring buffer size */
 228 #define DMA_RX_TIMEOUT          (10)
 229
 230 #define DRIVER_NAME     "fsl-lpuart"
 231 #define DEV_NAME        "ttyLP"
 232 #define UART_NR         6
 233
 234 /* IMX lpuart has four extra unused regs located at the beginning */
 235 #define IMX_REG_OFF     0x10
 236
 237 struct lpuart_port {
 238         struct uart_port        port;
 239         struct clk              *clk;
 240         unsigned int            txfifo_size;
 241         unsigned int            rxfifo_size;
 242
 243         bool                    lpuart_dma_tx_use;
 244         bool                    lpuart_dma_rx_use;
 245         struct dma_chan         *dma_tx_chan;
 246         struct dma_chan         *dma_rx_chan;
 247         struct dma_async_tx_descriptor  *dma_tx_desc;
 248         struct dma_async_tx_descriptor  *dma_rx_desc;
 249         dma_cookie_t            dma_tx_cookie;
 250         dma_cookie_t            dma_rx_cookie;
 251         unsigned int            dma_tx_bytes;
 252         unsigned int            dma_rx_bytes;
 253         bool                    dma_tx_in_progress;
 254         unsigned int            dma_rx_timeout;
 255         struct timer_list       lpuart_timer;
 256         struct scatterlist      rx_sgl, tx_sgl[2];
 257         struct circ_buf         rx_ring;
 258         int                     rx_dma_rng_buf_len;
 259         unsigned int            dma_tx_nents;
 260         wait_queue_head_t       dma_wait;
 261 };
 262
 263 struct lpuart_soc_data {
 264         char    iotype;
 265         u8      reg_off;
 266 };
 267
 268 static const struct lpuart_soc_data vf_data = {
 269         .iotype = UPIO_MEM,
 270 };
 271
 272 static const struct lpuart_soc_data ls_data = {
 273         .iotype = UPIO_MEM32BE,
 274 };
 275
 276 static struct lpuart_soc_data imx_data = {
 277         .iotype = UPIO_MEM32,
 278         .reg_off = IMX_REG_OFF,
 279 };
 280
 281 static const struct of_device_id lpuart_dt_ids[] = {
 282         { .compatible = "fsl,vf610-lpuart",     .data = &vf_data, },
 283         { .compatible = "fsl,ls1021a-lpuart",   .data = &ls_data, },
 284         { .compatible = "fsl,imx7ulp-lpuart",   .data = &imx_data, },
 285         { /* sentinel */ }
 286 };
 287 MODULE_DEVICE_TABLE(of, lpuart_dt_ids);
 288
 289 /* Forward declare this for the dma callbacks*/
 290 static void lpuart_dma_tx_complete(void *arg);
 291
 292 static inline u32 lpuart32_read(struct uart_port *port, u32 off)
 293 {
 294         switch (port->iotype) {
 295         case UPIO_MEM32:
 296                 return readl(port->membase + off);
 297         case UPIO_MEM32BE:
 298                 return ioread32be(port->membase + off);
 299         default:
 300                 return 0;
 301         }
 302 }
 303
 304 static inline void lpuart32_write(struct uart_port *port, u32 val,
 305                                   u32 off)
 306 {
 307         switch (port->iotype) {
 308         case UPIO_MEM32:
 309                 writel(val, port->membase + off);
 310                 break;
 311         case UPIO_MEM32BE:
 312                 iowrite32be(val, port->membase + off);
 313                 break;
 314         }
 315 }
 316
 317 static void lpuart_stop_tx(struct uart_port *port)
 318 {
 319         unsigned char temp;
 320
 321         temp = readb(port->membase + UARTCR2);
 322         temp &= ~(UARTCR2_TIE | UARTCR2_TCIE);
 323         writeb(temp, port->membase + UARTCR2);
 324 }
 325
 326 static void lpuart32_stop_tx(struct uart_port *port)
 327 {
 328         unsigned long temp;
 329
 330         temp = lpuart32_read(port, UARTCTRL);
 331         temp &= ~(UARTCTRL_TIE | UARTCTRL_TCIE);
 332         lpuart32_write(port, temp, UARTCTRL);
 333 }
 334
 335 static void lpuart_stop_rx(struct uart_port *port)
 336 {
 337         unsigned char temp;
 338
 339         temp = readb(port->membase + UARTCR2);
 340         writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2);
 341 }
 342
 343 static void lpuart32_stop_rx(struct uart_port *port)
 344 {
 345         unsigned long temp;
 346
 347         temp = lpuart32_read(port, UARTCTRL);
 348         lpuart32_write(port, temp & ~UARTCTRL_RE, UARTCTRL);
 349 }
 350
 351 static void lpuart_dma_tx(struct lpuart_port *sport)
 352 {
 353         struct circ_buf *xmit = &sport->port.state->xmit;
 354         struct scatterlist *sgl = sport->tx_sgl;
 355         struct device *dev = sport->port.dev;
 356         int ret;
 357
 358         if (sport->dma_tx_in_progress)
 359                 return;
 360
 361         sport->dma_tx_bytes = uart_circ_chars_pending(xmit);
 362
 363         if (xmit->tail < xmit->head || xmit->head == 0) {
 364                 sport->dma_tx_nents = 1;
 365                 sg_init_one(sgl, xmit->buf + xmit->tail, sport->dma_tx_bytes);
 366         } else {
 367                 sport->dma_tx_nents = 2;
 368                 sg_init_table(sgl, 2);
 369                 sg_set_buf(sgl, xmit->buf + xmit->tail,
 370                                 UART_XMIT_SIZE - xmit->tail);
 371                 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
 372         }
 373
 374         ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
 375         if (!ret) {
 376                 dev_err(dev, "DMA mapping error for TX.\n");
 377                 return;
 378         }
 379
 380         sport->dma_tx_desc = dmaengine_prep_slave_sg(sport->dma_tx_chan, sgl,
 381                                         sport->dma_tx_nents,
 382                                         DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
 383         if (!sport->dma_tx_desc) {
 384                 dma_unmap_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
 385                 dev_err(dev, "Cannot prepare TX slave DMA!\n");
 386                 return;
 387         }
 388
 389         sport->dma_tx_desc->callback = lpuart_dma_tx_complete;
 390         sport->dma_tx_desc->callback_param = sport;
 391         sport->dma_tx_in_progress = true;
 392         sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc);
 393         dma_async_issue_pending(sport->dma_tx_chan);
 394 }
 395
 396 static void lpuart_dma_tx_complete(void *arg)
 397 {
 398         struct lpuart_port *sport = arg;
 399         struct scatterlist *sgl = &sport->tx_sgl[0];
 400         struct circ_buf *xmit = &sport->port.state->xmit;
 401         unsigned long flags;
 402
 403         spin_lock_irqsave(&sport->port.lock, flags);
 404
 405         dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
 406
 407         xmit->tail = (xmit->tail + sport->dma_tx_bytes) & (UART_XMIT_SIZE - 1);
 408
 409         sport->port.icount.tx += sport->dma_tx_bytes;
 410         sport->dma_tx_in_progress = false;
 411         spin_unlock_irqrestore(&sport->port.lock, flags);
 412
 413         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 414                 uart_write_wakeup(&sport->port);
 415
 416         if (waitqueue_active(&sport->dma_wait)) {
 417                 wake_up(&sport->dma_wait);
 418                 return;
 419         }
 420
 421         spin_lock_irqsave(&sport->port.lock, flags);
 422
 423         if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port))
 424                 lpuart_dma_tx(sport);
 425
 426         spin_unlock_irqrestore(&sport->port.lock, flags);
 427 }
 428
 429 static int lpuart_dma_tx_request(struct uart_port *port)
 430 {
 431         struct lpuart_port *sport = container_of(port,
 432                                         struct lpuart_port, port);
 433         struct dma_slave_config dma_tx_sconfig = {};
 434         int ret;
 435
 436         dma_tx_sconfig.dst_addr = sport->port.mapbase + UARTDR;
 437         dma_tx_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 438         dma_tx_sconfig.dst_maxburst = 1;
 439         dma_tx_sconfig.direction = DMA_MEM_TO_DEV;
 440         ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig);
 441
 442         if (ret) {
 443                 dev_err(sport->port.dev,
 444                                 "DMA slave config failed, err = %d\n", ret);
 445                 return ret;
 446         }
 447
 448         return 0;
 449 }
 450
 451 static void lpuart_flush_buffer(struct uart_port *port)
 452 {
 453         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
 454
 455         if (sport->lpuart_dma_tx_use) {
 456                 if (sport->dma_tx_in_progress) {
 457                         dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0],
 458                                 sport->dma_tx_nents, DMA_TO_DEVICE);
 459                         sport->dma_tx_in_progress = false;
 460                 }
 461                 dmaengine_terminate_all(sport->dma_tx_chan);
 462         }
 463 }
 464
 465 #if defined(CONFIG_CONSOLE_POLL)
 466
 467 static int lpuart_poll_init(struct uart_port *port)
 468 {
 469         struct lpuart_port *sport = container_of(port,
 470                                         struct lpuart_port, port);
 471         unsigned long flags;
 472         unsigned char temp;
 473
 474         sport->port.fifosize = 0;
 475
 476         spin_lock_irqsave(&sport->port.lock, flags);
 477         /* Disable Rx & Tx */
 478         writeb(0, sport->port.membase + UARTCR2);
 479
 480         temp = readb(sport->port.membase + UARTPFIFO);
 481         /* Enable Rx and Tx FIFO */
 482         writeb(temp | UARTPFIFO_RXFE | UARTPFIFO_TXFE,
 483                         sport->port.membase + UARTPFIFO);
 484
 485         /* flush Tx and Rx FIFO */
 486         writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
 487                         sport->port.membase + UARTCFIFO);
 488
 489         /* explicitly clear RDRF */
 490         if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) {
 491                 readb(sport->port.membase + UARTDR);
 492                 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO);
 493         }
 494
 495         writeb(0, sport->port.membase + UARTTWFIFO);
 496         writeb(1, sport->port.membase + UARTRWFIFO);
 497
 498         /* Enable Rx and Tx */
 499         writeb(UARTCR2_RE | UARTCR2_TE, sport->port.membase + UARTCR2);
 500         spin_unlock_irqrestore(&sport->port.lock, flags);
 501
 502         return 0;
 503 }
 504
 505 static void lpuart_poll_put_char(struct uart_port *port, unsigned char c)
 506 {
 507         /* drain */
 508         while (!(readb(port->membase + UARTSR1) & UARTSR1_TDRE))
 509                 barrier();
 510
 511         writeb(c, port->membase + UARTDR);
 512 }
 513
 514 static int lpuart_poll_get_char(struct uart_port *port)
 515 {
 516         if (!(readb(port->membase + UARTSR1) & UARTSR1_RDRF))
 517                 return NO_POLL_CHAR;
 518
 519         return readb(port->membase + UARTDR);
 520 }
 521
 522 #endif
 523
 524 static inline void lpuart_transmit_buffer(struct lpuart_port *sport)
 525 {
 526         struct circ_buf *xmit = &sport->port.state->xmit;
 527
 528         while (!uart_circ_empty(xmit) &&
 529                 (readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size)) {
 530                 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR);
 531                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 532                 sport->port.icount.tx++;
 533         }
 534
 535         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 536                 uart_write_wakeup(&sport->port);
 537
 538         if (uart_circ_empty(xmit))
 539                 lpuart_stop_tx(&sport->port);
 540 }
 541
 542 static inline void lpuart32_transmit_buffer(struct lpuart_port *sport)
 543 {
 544         struct circ_buf *xmit = &sport->port.state->xmit;
 545         unsigned long txcnt;
 546
 547         txcnt = lpuart32_read(&sport->port, UARTWATER);
 548         txcnt = txcnt >> UARTWATER_TXCNT_OFF;
 549         txcnt &= UARTWATER_COUNT_MASK;
 550         while (!uart_circ_empty(xmit) && (txcnt < sport->txfifo_size)) {
 551                 lpuart32_write(&sport->port, xmit->buf[xmit->tail], UARTDATA);
 552                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 553                 sport->port.icount.tx++;
 554                 txcnt = lpuart32_read(&sport->port, UARTWATER);
 555                 txcnt = txcnt >> UARTWATER_TXCNT_OFF;
 556                 txcnt &= UARTWATER_COUNT_MASK;
 557         }
 558
 559         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 560                 uart_write_wakeup(&sport->port);
 561
 562         if (uart_circ_empty(xmit))
 563                 lpuart32_stop_tx(&sport->port);
 564 }
 565
 566 static void lpuart_start_tx(struct uart_port *port)
 567 {
 568         struct lpuart_port *sport = container_of(port,
 569                         struct lpuart_port, port);
 570         struct circ_buf *xmit = &sport->port.state->xmit;
 571         unsigned char temp;
 572
 573         temp = readb(port->membase + UARTCR2);
 574         writeb(temp | UARTCR2_TIE, port->membase + UARTCR2);
 575
 576         if (sport->lpuart_dma_tx_use) {
 577                 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port))
 578                         lpuart_dma_tx(sport);
 579         } else {
 580                 if (readb(port->membase + UARTSR1) & UARTSR1_TDRE)
 581                         lpuart_transmit_buffer(sport);
 582         }
 583 }
 584
 585 static void lpuart32_start_tx(struct uart_port *port)
 586 {
 587         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
 588         unsigned long temp;
 589
 590         temp = lpuart32_read(port, UARTCTRL);
 591         lpuart32_write(port, temp | UARTCTRL_TIE, UARTCTRL);
 592
 593         if (lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE)
 594                 lpuart32_transmit_buffer(sport);
 595 }
 596
 597 /* return TIOCSER_TEMT when transmitter is not busy */
 598 static unsigned int lpuart_tx_empty(struct uart_port *port)
 599 {
 600         struct lpuart_port *sport = container_of(port,
 601                         struct lpuart_port, port);
 602         unsigned char sr1 = readb(port->membase + UARTSR1);
 603         unsigned char sfifo = readb(port->membase + UARTSFIFO);
 604
 605         if (sport->dma_tx_in_progress)
 606                 return 0;
 607
 608         if (sr1 & UARTSR1_TC && sfifo & UARTSFIFO_TXEMPT)
 609                 return TIOCSER_TEMT;
 610
 611         return 0;
 612 }
 613
 614 static unsigned int lpuart32_tx_empty(struct uart_port *port)
 615 {
 616         return (lpuart32_read(port, UARTSTAT) & UARTSTAT_TC) ?
 617                 TIOCSER_TEMT : 0;
 618 }
 619
 620 static irqreturn_t lpuart_txint(int irq, void *dev_id)
 621 {
 622         struct lpuart_port *sport = dev_id;
 623         struct circ_buf *xmit = &sport->port.state->xmit;
 624         unsigned long flags;
 625
 626         spin_lock_irqsave(&sport->port.lock, flags);
 627         if (sport->port.x_char) {
 628                 if (sport->port.iotype & (UPIO_MEM32 | UPIO_MEM32BE))
 629                         lpuart32_write(&sport->port, sport->port.x_char, UARTDATA);
 630                 else
 631                         writeb(sport->port.x_char, sport->port.membase + UARTDR);
 632                 goto out;
 633         }
 634
 635         if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
 636                 if (sport->port.iotype & (UPIO_MEM32 | UPIO_MEM32BE))
 637                         lpuart32_stop_tx(&sport->port);
 638                 else
 639                         lpuart_stop_tx(&sport->port);
 640                 goto out;
 641         }
 642
 643         if (sport->port.iotype & (UPIO_MEM32 | UPIO_MEM32BE))
 644                 lpuart32_transmit_buffer(sport);
 645         else
 646                 lpuart_transmit_buffer(sport);
 647
 648         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 649                 uart_write_wakeup(&sport->port);
 650
 651 out:
 652         spin_unlock_irqrestore(&sport->port.lock, flags);
 653         return IRQ_HANDLED;
 654 }
 655
 656 static irqreturn_t lpuart_rxint(int irq, void *dev_id)
 657 {
 658         struct lpuart_port *sport = dev_id;
 659         unsigned int flg, ignored = 0;
 660         struct tty_port *port = &sport->port.state->port;
 661         unsigned long flags;
 662         unsigned char rx, sr;
 663
 664         spin_lock_irqsave(&sport->port.lock, flags);
 665
 666         while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) {
 667                 flg = TTY_NORMAL;
 668                 sport->port.icount.rx++;
 669                 /*
 670                  * to clear the FE, OR, NF, FE, PE flags,
 671                  * read SR1 then read DR
 672                  */
 673                 sr = readb(sport->port.membase + UARTSR1);
 674                 rx = readb(sport->port.membase + UARTDR);
 675
 676                 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
 677                         continue;
 678
 679                 if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) {
 680                         if (sr & UARTSR1_PE)
 681                                 sport->port.icount.parity++;
 682                         else if (sr & UARTSR1_FE)
 683                                 sport->port.icount.frame++;
 684
 685                         if (sr & UARTSR1_OR)
 686                                 sport->port.icount.overrun++;
 687
 688                         if (sr & sport->port.ignore_status_mask) {
 689                                 if (++ignored > 100)
 690                                         goto out;
 691                                 continue;
 692                         }
 693
 694                         sr &= sport->port.read_status_mask;
 695
 696                         if (sr & UARTSR1_PE)
 697                                 flg = TTY_PARITY;
 698                         else if (sr & UARTSR1_FE)
 699                                 flg = TTY_FRAME;
 700
 701                         if (sr & UARTSR1_OR)
 702                                 flg = TTY_OVERRUN;
 703
 704 #ifdef SUPPORT_SYSRQ
 705                         sport->port.sysrq = 0;
 706 #endif
 707                 }
 708
 709                 tty_insert_flip_char(port, rx, flg);
 710         }
 711
 712 out:
 713         spin_unlock_irqrestore(&sport->port.lock, flags);
 714
 715         tty_flip_buffer_push(port);
 716         return IRQ_HANDLED;
 717 }
 718
 719 static irqreturn_t lpuart32_rxint(int irq, void *dev_id)
 720 {
 721         struct lpuart_port *sport = dev_id;
 722         unsigned int flg, ignored = 0;
 723         struct tty_port *port = &sport->port.state->port;
 724         unsigned long flags;
 725         unsigned long rx, sr;
 726
 727         spin_lock_irqsave(&sport->port.lock, flags);
 728
 729         while (!(lpuart32_read(&sport->port, UARTFIFO) & UARTFIFO_RXEMPT)) {
 730                 flg = TTY_NORMAL;
 731                 sport->port.icount.rx++;
 732                 /*
 733                  * to clear the FE, OR, NF, FE, PE flags,
 734                  * read STAT then read DATA reg
 735                  */
 736                 sr = lpuart32_read(&sport->port, UARTSTAT);
 737                 rx = lpuart32_read(&sport->port, UARTDATA);
 738                 rx &= 0x3ff;
 739
 740                 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
 741                         continue;
 742
 743                 if (sr & (UARTSTAT_PE | UARTSTAT_OR | UARTSTAT_FE)) {
 744                         if (sr & UARTSTAT_PE)
 745                                 sport->port.icount.parity++;
 746                         else if (sr & UARTSTAT_FE)
 747                                 sport->port.icount.frame++;
 748
 749                         if (sr & UARTSTAT_OR)
 750                                 sport->port.icount.overrun++;
 751
 752                         if (sr & sport->port.ignore_status_mask) {
 753                                 if (++ignored > 100)
 754                                         goto out;
 755                                 continue;
 756                         }
 757
 758                         sr &= sport->port.read_status_mask;
 759
 760                         if (sr & UARTSTAT_PE)
 761                                 flg = TTY_PARITY;
 762                         else if (sr & UARTSTAT_FE)
 763                                 flg = TTY_FRAME;
 764
 765                         if (sr & UARTSTAT_OR)
 766                                 flg = TTY_OVERRUN;
 767
 768 #ifdef SUPPORT_SYSRQ
 769                         sport->port.sysrq = 0;
 770 #endif
 771                 }
 772
 773                 tty_insert_flip_char(port, rx, flg);
 774         }
 775
 776 out:
 777         spin_unlock_irqrestore(&sport->port.lock, flags);
 778
 779         tty_flip_buffer_push(port);
 780         return IRQ_HANDLED;
 781 }
 782
 783 static irqreturn_t lpuart_int(int irq, void *dev_id)
 784 {
 785         struct lpuart_port *sport = dev_id;
 786         unsigned char sts;
 787
 788         sts = readb(sport->port.membase + UARTSR1);
 789
 790         if (sts & UARTSR1_RDRF)
 791                 lpuart_rxint(irq, dev_id);
 792
 793         if (sts & UARTSR1_TDRE)
 794                 lpuart_txint(irq, dev_id);
 795
 796         return IRQ_HANDLED;
 797 }
 798
 799 static irqreturn_t lpuart32_int(int irq, void *dev_id)
 800 {
 801         struct lpuart_port *sport = dev_id;
 802         unsigned long sts, rxcount;
 803
 804         sts = lpuart32_read(&sport->port, UARTSTAT);
 805         rxcount = lpuart32_read(&sport->port, UARTWATER);
 806         rxcount = rxcount >> UARTWATER_RXCNT_OFF;
 807
 808         if (sts & UARTSTAT_RDRF || rxcount > 0)
 809                 lpuart32_rxint(irq, dev_id);
 810
 811         if ((sts & UARTSTAT_TDRE) &&
 812                 !(lpuart32_read(&sport->port, UARTBAUD) & UARTBAUD_TDMAE))
 813                 lpuart_txint(irq, dev_id);
 814
 815         lpuart32_write(&sport->port, sts, UARTSTAT);
 816         return IRQ_HANDLED;
 817 }
 818
 819 static void lpuart_copy_rx_to_tty(struct lpuart_port *sport)
 820 {
 821         struct tty_port *port = &sport->port.state->port;
 822         struct dma_tx_state state;
 823         enum dma_status dmastat;
 824         struct circ_buf *ring = &sport->rx_ring;
 825         unsigned long flags;
 826         int count = 0;
 827         unsigned char sr;
 828
 829         sr = readb(sport->port.membase + UARTSR1);
 830
 831         if (sr & (UARTSR1_PE | UARTSR1_FE)) {
 832                 /* Read DR to clear the error flags */
 833                 readb(sport->port.membase + UARTDR);
 834
 835                 if (sr & UARTSR1_PE)
 836                     sport->port.icount.parity++;
 837                 else if (sr & UARTSR1_FE)
 838                     sport->port.icount.frame++;
 839         }
 840
 841         async_tx_ack(sport->dma_rx_desc);
 842
 843         spin_lock_irqsave(&sport->port.lock, flags);
 844
 845         dmastat = dmaengine_tx_status(sport->dma_rx_chan,
 846                                 sport->dma_rx_cookie,
 847                                 &state);
 848
 849         if (dmastat == DMA_ERROR) {
 850                 dev_err(sport->port.dev, "Rx DMA transfer failed!\n");
 851                 spin_unlock_irqrestore(&sport->port.lock, flags);
 852                 return;
 853         }
 854
 855         /* CPU claims ownership of RX DMA buffer */
 856         dma_sync_sg_for_cpu(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
 857
 858         /*
 859          * ring->head points to the end of data already written by the DMA.
 860          * ring->tail points to the beginning of data to be read by the
 861          * framework.
 862          * The current transfer size should not be larger than the dma buffer
 863          * length.
 864          */
 865         ring->head = sport->rx_sgl.length - state.residue;
 866         BUG_ON(ring->head > sport->rx_sgl.length);
 867         /*
 868          * At this point ring->head may point to the first byte right after the
 869          * last byte of the dma buffer:
 870          * 0 <= ring->head <= sport->rx_sgl.length
 871          *
 872          * However ring->tail must always points inside the dma buffer:
 873          * 0 <= ring->tail <= sport->rx_sgl.length - 1
 874          *
 875          * Since we use a ring buffer, we have to handle the case
 876          * where head is lower than tail. In such a case, we first read from
 877          * tail to the end of the buffer then reset tail.
 878          */
 879         if (ring->head < ring->tail) {
 880                 count = sport->rx_sgl.length - ring->tail;
 881
 882                 tty_insert_flip_string(port, ring->buf + ring->tail, count);
 883                 ring->tail = 0;
 884                 sport->port.icount.rx += count;
 885         }
 886
 887         /* Finally we read data from tail to head */
 888         if (ring->tail < ring->head) {
 889                 count = ring->head - ring->tail;
 890                 tty_insert_flip_string(port, ring->buf + ring->tail, count);
 891                 /* Wrap ring->head if needed */
 892                 if (ring->head >= sport->rx_sgl.length)
 893                         ring->head = 0;
 894                 ring->tail = ring->head;
 895                 sport->port.icount.rx += count;
 896         }
 897
 898         dma_sync_sg_for_device(sport->port.dev, &sport->rx_sgl, 1,
 899                                DMA_FROM_DEVICE);
 900
 901         spin_unlock_irqrestore(&sport->port.lock, flags);
 902
 903         tty_flip_buffer_push(port);
 904         mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout);
 905 }
 906
 907 static void lpuart_dma_rx_complete(void *arg)
 908 {
 909         struct lpuart_port *sport = arg;
 910
 911         lpuart_copy_rx_to_tty(sport);
 912 }
 913
 914 static void lpuart_timer_func(unsigned long data)
 915 {
 916         struct lpuart_port *sport = (struct lpuart_port *)data;
 917
 918         lpuart_copy_rx_to_tty(sport);
 919 }
 920
 921 static inline int lpuart_start_rx_dma(struct lpuart_port *sport)
 922 {
 923         struct dma_slave_config dma_rx_sconfig = {};
 924         struct circ_buf *ring = &sport->rx_ring;
 925         int ret, nent;
 926         int bits, baud;
 927         struct tty_struct *tty = tty_port_tty_get(&sport->port.state->port);
 928         struct ktermios *termios = &tty->termios;
 929
 930         baud = tty_get_baud_rate(tty);
 931
 932         bits = (termios->c_cflag & CSIZE) == CS7 ? 9 : 10;
 933         if (termios->c_cflag & PARENB)
 934                 bits++;
 935
 936         /*
 937          * Calculate length of one DMA buffer size to keep latency below
 938          * 10ms at any baud rate.
 939          */
 940         sport->rx_dma_rng_buf_len = (DMA_RX_TIMEOUT * baud /  bits / 1000) * 2;
 941         sport->rx_dma_rng_buf_len = (1 << (fls(sport->rx_dma_rng_buf_len) - 1));
 942         if (sport->rx_dma_rng_buf_len < 16)
 943                 sport->rx_dma_rng_buf_len = 16;
 944
 945         ring->buf = kmalloc(sport->rx_dma_rng_buf_len, GFP_ATOMIC);
 946         if (!ring->buf) {
 947                 dev_err(sport->port.dev, "Ring buf alloc failed\n");
 948                 return -ENOMEM;
 949         }
 950
 951         sg_init_one(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len);
 952         sg_set_buf(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len);
 953         nent = dma_map_sg(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
 954
 955         if (!nent) {
 956                 dev_err(sport->port.dev, "DMA Rx mapping error\n");
 957                 return -EINVAL;
 958         }
 959
 960         dma_rx_sconfig.src_addr = sport->port.mapbase + UARTDR;
 961         dma_rx_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 962         dma_rx_sconfig.src_maxburst = 1;
 963         dma_rx_sconfig.direction = DMA_DEV_TO_MEM;
 964         ret = dmaengine_slave_config(sport->dma_rx_chan, &dma_rx_sconfig);
 965
 966         if (ret < 0) {
 967                 dev_err(sport->port.dev,
 968                                 "DMA Rx slave config failed, err = %d\n", ret);
 969                 return ret;
 970         }
 971
 972         sport->dma_rx_desc = dmaengine_prep_dma_cyclic(sport->dma_rx_chan,
 973                                  sg_dma_address(&sport->rx_sgl),
 974                                  sport->rx_sgl.length,
 975                                  sport->rx_sgl.length / 2,
 976                                  DMA_DEV_TO_MEM,
 977                                  DMA_PREP_INTERRUPT);
 978         if (!sport->dma_rx_desc) {
 979                 dev_err(sport->port.dev, "Cannot prepare cyclic DMA\n");
 980                 return -EFAULT;
 981         }
 982
 983         sport->dma_rx_desc->callback = lpuart_dma_rx_complete;
 984         sport->dma_rx_desc->callback_param = sport;
 985         sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc);
 986         dma_async_issue_pending(sport->dma_rx_chan);
 987
 988         writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_RDMAS,
 989                                 sport->port.membase + UARTCR5);
 990
 991         return 0;
 992 }
 993
 994 static void lpuart_dma_rx_free(struct uart_port *port)
 995 {
 996         struct lpuart_port *sport = container_of(port,
 997                                         struct lpuart_port, port);
 998
 999         if (sport->dma_rx_chan)
1000                 dmaengine_terminate_all(sport->dma_rx_chan);
1001
1002         dma_unmap_sg(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
1003         kfree(sport->rx_ring.buf);
1004         sport->rx_ring.tail = 0;
1005         sport->rx_ring.head = 0;
1006         sport->dma_rx_desc = NULL;
1007         sport->dma_rx_cookie = -EINVAL;
1008 }
1009
1010 static int lpuart_config_rs485(struct uart_port *port,
1011                         struct serial_rs485 *rs485)
1012 {
1013         struct lpuart_port *sport = container_of(port,
1014                         struct lpuart_port, port);
1015
1016         u8 modem = readb(sport->port.membase + UARTMODEM) &
1017                 ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE);
1018         writeb(modem, sport->port.membase + UARTMODEM);
1019
1020         if (rs485->flags & SER_RS485_ENABLED) {
1021                 /* Enable auto RS-485 RTS mode */
1022                 modem |= UARTMODEM_TXRTSE;
1023
1024                 /*
1025                  * RTS needs to be logic HIGH either during transer _or_ after
1026                  * transfer, other variants are not supported by the hardware.
1027                  */
1028
1029                 if (!(rs485->flags & (SER_RS485_RTS_ON_SEND |
1030                                 SER_RS485_RTS_AFTER_SEND)))
1031                         rs485->flags |= SER_RS485_RTS_ON_SEND;
1032
1033                 if (rs485->flags & SER_RS485_RTS_ON_SEND &&
1034                                 rs485->flags & SER_RS485_RTS_AFTER_SEND)
1035                         rs485->flags &= ~SER_RS485_RTS_AFTER_SEND;
1036
1037                 /*
1038                  * The hardware defaults to RTS logic HIGH while transfer.
1039                  * Switch polarity in case RTS shall be logic HIGH
1040                  * after transfer.
1041                  * Note: UART is assumed to be active high.
1042                  */
1043                 if (rs485->flags & SER_RS485_RTS_ON_SEND)
1044                         modem &= ~UARTMODEM_TXRTSPOL;
1045                 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND)
1046                         modem |= UARTMODEM_TXRTSPOL;
1047         }
1048
1049         /* Store the new configuration */
1050         sport->port.rs485 = *rs485;
1051
1052         writeb(modem, sport->port.membase + UARTMODEM);
1053         return 0;
1054 }
1055
1056 static unsigned int lpuart_get_mctrl(struct uart_port *port)
1057 {
1058         unsigned int temp = 0;
1059         unsigned char reg;
1060
1061         reg = readb(port->membase + UARTMODEM);
1062         if (reg & UARTMODEM_TXCTSE)
1063                 temp |= TIOCM_CTS;
1064
1065         if (reg & UARTMODEM_RXRTSE)
1066                 temp |= TIOCM_RTS;
1067
1068         return temp;
1069 }
1070
1071 static unsigned int lpuart32_get_mctrl(struct uart_port *port)
1072 {
1073         unsigned int temp = 0;
1074         unsigned long reg;
1075
1076         reg = lpuart32_read(port, UARTMODIR);
1077         if (reg & UARTMODIR_TXCTSE)
1078                 temp |= TIOCM_CTS;
1079
1080         if (reg & UARTMODIR_RXRTSE)
1081                 temp |= TIOCM_RTS;
1082
1083         return temp;
1084 }
1085
1086 static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1087 {
1088         unsigned char temp;
1089         struct lpuart_port *sport = container_of(port,
1090                                 struct lpuart_port, port);
1091
1092         /* Make sure RXRTSE bit is not set when RS485 is enabled */
1093         if (!(sport->port.rs485.flags & SER_RS485_ENABLED)) {
1094                 temp = readb(sport->port.membase + UARTMODEM) &
1095                         ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1096
1097                 if (mctrl & TIOCM_RTS)
1098                         temp |= UARTMODEM_RXRTSE;
1099
1100                 if (mctrl & TIOCM_CTS)
1101                         temp |= UARTMODEM_TXCTSE;
1102
1103                 writeb(temp, port->membase + UARTMODEM);
1104         }
1105 }
1106
1107 static void lpuart32_set_mctrl(struct uart_port *port, unsigned int mctrl)
1108 {
1109         unsigned long temp;
1110
1111         temp = lpuart32_read(port, UARTMODIR) &
1112                         ~(UARTMODIR_RXRTSE | UARTMODIR_TXCTSE);
1113
1114         if (mctrl & TIOCM_RTS)
1115                 temp |= UARTMODIR_RXRTSE;
1116
1117         if (mctrl & TIOCM_CTS)
1118                 temp |= UARTMODIR_TXCTSE;
1119
1120         lpuart32_write(port, temp, UARTMODIR);
1121 }
1122
1123 static void lpuart_break_ctl(struct uart_port *port, int break_state)
1124 {
1125         unsigned char temp;
1126
1127         temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK;
1128
1129         if (break_state != 0)
1130                 temp |= UARTCR2_SBK;
1131
1132         writeb(temp, port->membase + UARTCR2);
1133 }
1134
1135 static void lpuart32_break_ctl(struct uart_port *port, int break_state)
1136 {
1137         unsigned long temp;
1138
1139         temp = lpuart32_read(port, UARTCTRL) & ~UARTCTRL_SBK;
1140
1141         if (break_state != 0)
1142                 temp |= UARTCTRL_SBK;
1143
1144         lpuart32_write(port, temp, UARTCTRL);
1145 }
1146
1147 static void lpuart_setup_watermark(struct lpuart_port *sport)
1148 {
1149         unsigned char val, cr2;
1150         unsigned char cr2_saved;
1151
1152         cr2 = readb(sport->port.membase + UARTCR2);
1153         cr2_saved = cr2;
1154         cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE |
1155                         UARTCR2_RIE | UARTCR2_RE);
1156         writeb(cr2, sport->port.membase + UARTCR2);
1157
1158         val = readb(sport->port.membase + UARTPFIFO);
1159         writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE,
1160                         sport->port.membase + UARTPFIFO);
1161
1162         /* flush Tx and Rx FIFO */
1163         writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
1164                         sport->port.membase + UARTCFIFO);
1165
1166         /* explicitly clear RDRF */
1167         if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) {
1168                 readb(sport->port.membase + UARTDR);
1169                 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO);
1170         }
1171
1172         writeb(0, sport->port.membase + UARTTWFIFO);
1173         writeb(1, sport->port.membase + UARTRWFIFO);
1174
1175         /* Restore cr2 */
1176         writeb(cr2_saved, sport->port.membase + UARTCR2);
1177 }
1178
1179 static void lpuart32_setup_watermark(struct lpuart_port *sport)
1180 {
1181         unsigned long val, ctrl;
1182         unsigned long ctrl_saved;
1183
1184         ctrl = lpuart32_read(&sport->port, UARTCTRL);
1185         ctrl_saved = ctrl;
1186         ctrl &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_TE |
1187                         UARTCTRL_RIE | UARTCTRL_RE);
1188         lpuart32_write(&sport->port, ctrl, UARTCTRL);
1189
1190         /* enable FIFO mode */
1191         val = lpuart32_read(&sport->port, UARTFIFO);
1192         val |= UARTFIFO_TXFE | UARTFIFO_RXFE;
1193         val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH;
1194         lpuart32_write(&sport->port, val, UARTFIFO);
1195
1196         /* set the watermark */
1197         val = (0x1 << UARTWATER_RXWATER_OFF) | (0x0 << UARTWATER_TXWATER_OFF);
1198         lpuart32_write(&sport->port, val, UARTWATER);
1199
1200         /* Restore cr2 */
1201         lpuart32_write(&sport->port, ctrl_saved, UARTCTRL);
1202 }
1203
1204 static void rx_dma_timer_init(struct lpuart_port *sport)
1205 {
1206                 setup_timer(&sport->lpuart_timer, lpuart_timer_func,
1207                                 (unsigned long)sport);
1208                 sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout;
1209                 add_timer(&sport->lpuart_timer);
1210 }
1211
1212 static int lpuart_startup(struct uart_port *port)
1213 {
1214         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1215         int ret;
1216         unsigned long flags;
1217         unsigned char temp;
1218
1219         /* determine FIFO size and enable FIFO mode */
1220         temp = readb(sport->port.membase + UARTPFIFO);
1221
1222         sport->txfifo_size = 0x1 << (((temp >> UARTPFIFO_TXSIZE_OFF) &
1223                 UARTPFIFO_FIFOSIZE_MASK) + 1);
1224
1225         sport->port.fifosize = sport->txfifo_size;
1226
1227         sport->rxfifo_size = 0x1 << (((temp >> UARTPFIFO_RXSIZE_OFF) &
1228                 UARTPFIFO_FIFOSIZE_MASK) + 1);
1229
1230         ret = devm_request_irq(port->dev, port->irq, lpuart_int, 0,
1231                                 DRIVER_NAME, sport);
1232         if (ret)
1233                 return ret;
1234
1235         spin_lock_irqsave(&sport->port.lock, flags);
1236
1237         lpuart_setup_watermark(sport);
1238
1239         temp = readb(sport->port.membase + UARTCR2);
1240         temp |= (UARTCR2_RIE | UARTCR2_TIE | UARTCR2_RE | UARTCR2_TE);
1241         writeb(temp, sport->port.membase + UARTCR2);
1242
1243         if (sport->dma_rx_chan && !lpuart_start_rx_dma(sport)) {
1244                 /* set Rx DMA timeout */
1245                 sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT);
1246                 if (!sport->dma_rx_timeout)
1247                      sport->dma_rx_timeout = 1;
1248
1249                 sport->lpuart_dma_rx_use = true;
1250                 rx_dma_timer_init(sport);
1251         } else {
1252                 sport->lpuart_dma_rx_use = false;
1253         }
1254
1255         if (sport->dma_tx_chan && !lpuart_dma_tx_request(port)) {
1256                 init_waitqueue_head(&sport->dma_wait);
1257                 sport->lpuart_dma_tx_use = true;
1258                 temp = readb(port->membase + UARTCR5);
1259                 writeb(temp | UARTCR5_TDMAS, port->membase + UARTCR5);
1260         } else {
1261                 sport->lpuart_dma_tx_use = false;
1262         }
1263
1264         spin_unlock_irqrestore(&sport->port.lock, flags);
1265
1266         return 0;
1267 }
1268
1269 static int lpuart32_startup(struct uart_port *port)
1270 {
1271         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1272         int ret;
1273         unsigned long flags;
1274         unsigned long temp;
1275
1276         /* determine FIFO size */
1277         temp = lpuart32_read(&sport->port, UARTFIFO);
1278
1279         sport->txfifo_size = 0x1 << (((temp >> UARTFIFO_TXSIZE_OFF) &
1280                 UARTFIFO_FIFOSIZE_MASK) - 1);
1281
1282         sport->rxfifo_size = 0x1 << (((temp >> UARTFIFO_RXSIZE_OFF) &
1283                 UARTFIFO_FIFOSIZE_MASK) - 1);
1284
1285         ret = devm_request_irq(port->dev, port->irq, lpuart32_int, 0,
1286                                 DRIVER_NAME, sport);
1287         if (ret)
1288                 return ret;
1289
1290         spin_lock_irqsave(&sport->port.lock, flags);
1291
1292         lpuart32_setup_watermark(sport);
1293
1294         temp = lpuart32_read(&sport->port, UARTCTRL);
1295         temp |= (UARTCTRL_RIE | UARTCTRL_TIE | UARTCTRL_RE | UARTCTRL_TE);
1296         temp |= UARTCTRL_ILIE;
1297         lpuart32_write(&sport->port, temp, UARTCTRL);
1298
1299         spin_unlock_irqrestore(&sport->port.lock, flags);
1300         return 0;
1301 }
1302
1303 static void lpuart_shutdown(struct uart_port *port)
1304 {
1305         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1306         unsigned char temp;
1307         unsigned long flags;
1308
1309         spin_lock_irqsave(&port->lock, flags);
1310
1311         /* disable Rx/Tx and interrupts */
1312         temp = readb(port->membase + UARTCR2);
1313         temp &= ~(UARTCR2_TE | UARTCR2_RE |
1314                         UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
1315         writeb(temp, port->membase + UARTCR2);
1316
1317         spin_unlock_irqrestore(&port->lock, flags);
1318
1319         devm_free_irq(port->dev, port->irq, sport);
1320
1321         if (sport->lpuart_dma_rx_use) {
1322                 del_timer_sync(&sport->lpuart_timer);
1323                 lpuart_dma_rx_free(&sport->port);
1324         }
1325
1326         if (sport->lpuart_dma_tx_use) {
1327                 if (wait_event_interruptible(sport->dma_wait,
1328                         !sport->dma_tx_in_progress) != false) {
1329                         sport->dma_tx_in_progress = false;
1330                         dmaengine_terminate_all(sport->dma_tx_chan);
1331                 }
1332
1333                 lpuart_stop_tx(port);
1334         }
1335 }
1336
1337 static void lpuart32_shutdown(struct uart_port *port)
1338 {
1339         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1340         unsigned long temp;
1341         unsigned long flags;
1342
1343         spin_lock_irqsave(&port->lock, flags);
1344
1345         /* disable Rx/Tx and interrupts */
1346         temp = lpuart32_read(port, UARTCTRL);
1347         temp &= ~(UARTCTRL_TE | UARTCTRL_RE |
1348                         UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE);
1349         lpuart32_write(port, temp, UARTCTRL);
1350
1351         spin_unlock_irqrestore(&port->lock, flags);
1352
1353         devm_free_irq(port->dev, port->irq, sport);
1354 }
1355
1356 static void
1357 lpuart_set_termios(struct uart_port *port, struct ktermios *termios,
1358                    struct ktermios *old)
1359 {
1360         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1361         unsigned long flags;
1362         unsigned char cr1, old_cr1, old_cr2, cr3, cr4, bdh, modem;
1363         unsigned int  baud;
1364         unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1365         unsigned int sbr, brfa;
1366
1367         cr1 = old_cr1 = readb(sport->port.membase + UARTCR1);
1368         old_cr2 = readb(sport->port.membase + UARTCR2);
1369         cr3 = readb(sport->port.membase + UARTCR3);
1370         cr4 = readb(sport->port.membase + UARTCR4);
1371         bdh = readb(sport->port.membase + UARTBDH);
1372         modem = readb(sport->port.membase + UARTMODEM);
1373         /*
1374          * only support CS8 and CS7, and for CS7 must enable PE.
1375          * supported mode:
1376          *  - (7,e/o,1)
1377          *  - (8,n,1)
1378          *  - (8,m/s,1)
1379          *  - (8,e/o,1)
1380          */
1381         while ((termios->c_cflag & CSIZE) != CS8 &&
1382                 (termios->c_cflag & CSIZE) != CS7) {
1383                 termios->c_cflag &= ~CSIZE;
1384                 termios->c_cflag |= old_csize;
1385                 old_csize = CS8;
1386         }
1387
1388         if ((termios->c_cflag & CSIZE) == CS8 ||
1389                 (termios->c_cflag & CSIZE) == CS7)
1390                 cr1 = old_cr1 & ~UARTCR1_M;
1391
1392         if (termios->c_cflag & CMSPAR) {
1393                 if ((termios->c_cflag & CSIZE) != CS8) {
1394                         termios->c_cflag &= ~CSIZE;
1395                         termios->c_cflag |= CS8;
1396                 }
1397                 cr1 |= UARTCR1_M;
1398         }
1399
1400         /*
1401          * When auto RS-485 RTS mode is enabled,
1402          * hardware flow control need to be disabled.
1403          */
1404         if (sport->port.rs485.flags & SER_RS485_ENABLED)
1405                 termios->c_cflag &= ~CRTSCTS;
1406
1407         if (termios->c_cflag & CRTSCTS) {
1408                 modem |= (UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1409         } else {
1410                 termios->c_cflag &= ~CRTSCTS;
1411                 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1412         }
1413
1414         if (termios->c_cflag & CSTOPB)
1415                 termios->c_cflag &= ~CSTOPB;
1416
1417         /* parity must be enabled when CS7 to match 8-bits format */
1418         if ((termios->c_cflag & CSIZE) == CS7)
1419                 termios->c_cflag |= PARENB;
1420
1421         if ((termios->c_cflag & PARENB)) {
1422                 if (termios->c_cflag & CMSPAR) {
1423                         cr1 &= ~UARTCR1_PE;
1424                         if (termios->c_cflag & PARODD)
1425                                 cr3 |= UARTCR3_T8;
1426                         else
1427                                 cr3 &= ~UARTCR3_T8;
1428                 } else {
1429                         cr1 |= UARTCR1_PE;
1430                         if ((termios->c_cflag & CSIZE) == CS8)
1431                                 cr1 |= UARTCR1_M;
1432                         if (termios->c_cflag & PARODD)
1433                                 cr1 |= UARTCR1_PT;
1434                         else
1435                                 cr1 &= ~UARTCR1_PT;
1436                 }
1437         }
1438
1439         /* ask the core to calculate the divisor */
1440         baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1441
1442         /*
1443          * Need to update the Ring buffer length according to the selected
1444          * baud rate and restart Rx DMA path.
1445          *
1446          * Since timer function acqures sport->port.lock, need to stop before
1447          * acquring same lock because otherwise del_timer_sync() can deadlock.
1448          */
1449         if (old && sport->lpuart_dma_rx_use) {
1450                 del_timer_sync(&sport->lpuart_timer);
1451                 lpuart_dma_rx_free(&sport->port);
1452         }
1453
1454         spin_lock_irqsave(&sport->port.lock, flags);
1455
1456         sport->port.read_status_mask = 0;
1457         if (termios->c_iflag & INPCK)
1458                 sport->port.read_status_mask |= (UARTSR1_FE | UARTSR1_PE);
1459         if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1460                 sport->port.read_status_mask |= UARTSR1_FE;
1461
1462         /* characters to ignore */
1463         sport->port.ignore_status_mask = 0;
1464         if (termios->c_iflag & IGNPAR)
1465                 sport->port.ignore_status_mask |= UARTSR1_PE;
1466         if (termios->c_iflag & IGNBRK) {
1467                 sport->port.ignore_status_mask |= UARTSR1_FE;
1468                 /*
1469                  * if we're ignoring parity and break indicators,
1470                  * ignore overruns too (for real raw support).
1471                  */
1472                 if (termios->c_iflag & IGNPAR)
1473                         sport->port.ignore_status_mask |= UARTSR1_OR;
1474         }
1475
1476         /* update the per-port timeout */
1477         uart_update_timeout(port, termios->c_cflag, baud);
1478
1479         /* wait transmit engin complete */
1480         while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC))
1481                 barrier();
1482
1483         /* disable transmit and receive */
1484         writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE),
1485                         sport->port.membase + UARTCR2);
1486
1487         sbr = sport->port.uartclk / (16 * baud);
1488         brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud;
1489         bdh &= ~UARTBDH_SBR_MASK;
1490         bdh |= (sbr >> 8) & 0x1F;
1491         cr4 &= ~UARTCR4_BRFA_MASK;
1492         brfa &= UARTCR4_BRFA_MASK;
1493         writeb(cr4 | brfa, sport->port.membase + UARTCR4);
1494         writeb(bdh, sport->port.membase + UARTBDH);
1495         writeb(sbr & 0xFF, sport->port.membase + UARTBDL);
1496         writeb(cr3, sport->port.membase + UARTCR3);
1497         writeb(cr1, sport->port.membase + UARTCR1);
1498         writeb(modem, sport->port.membase + UARTMODEM);
1499
1500         /* restore control register */
1501         writeb(old_cr2, sport->port.membase + UARTCR2);
1502
1503         if (old && sport->lpuart_dma_rx_use) {
1504                 if (!lpuart_start_rx_dma(sport))
1505                         rx_dma_timer_init(sport);
1506                 else
1507                         sport->lpuart_dma_rx_use = false;
1508         }
1509
1510         spin_unlock_irqrestore(&sport->port.lock, flags);
1511 }
1512
1513 static void
1514 lpuart32_set_termios(struct uart_port *port, struct ktermios *termios,
1515                    struct ktermios *old)
1516 {
1517         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1518         unsigned long flags;
1519         unsigned long ctrl, old_ctrl, bd, modem;
1520         unsigned int  baud;
1521         unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1522         unsigned int sbr;
1523
1524         ctrl = old_ctrl = lpuart32_read(&sport->port, UARTCTRL);
1525         bd = lpuart32_read(&sport->port, UARTBAUD);
1526         modem = lpuart32_read(&sport->port, UARTMODIR);
1527         /*
1528          * only support CS8 and CS7, and for CS7 must enable PE.
1529          * supported mode:
1530          *  - (7,e/o,1)
1531          *  - (8,n,1)
1532          *  - (8,m/s,1)
1533          *  - (8,e/o,1)
1534          */
1535         while ((termios->c_cflag & CSIZE) != CS8 &&
1536                 (termios->c_cflag & CSIZE) != CS7) {
1537                 termios->c_cflag &= ~CSIZE;
1538                 termios->c_cflag |= old_csize;
1539                 old_csize = CS8;
1540         }
1541
1542         if ((termios->c_cflag & CSIZE) == CS8 ||
1543                 (termios->c_cflag & CSIZE) == CS7)
1544                 ctrl = old_ctrl & ~UARTCTRL_M;
1545
1546         if (termios->c_cflag & CMSPAR) {
1547                 if ((termios->c_cflag & CSIZE) != CS8) {
1548                         termios->c_cflag &= ~CSIZE;
1549                         termios->c_cflag |= CS8;
1550                 }
1551                 ctrl |= UARTCTRL_M;
1552         }
1553
1554         if (termios->c_cflag & CRTSCTS) {
1555                 modem |= (UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1556         } else {
1557                 termios->c_cflag &= ~CRTSCTS;
1558                 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1559         }
1560
1561         if (termios->c_cflag & CSTOPB)
1562                 termios->c_cflag &= ~CSTOPB;
1563
1564         /* parity must be enabled when CS7 to match 8-bits format */
1565         if ((termios->c_cflag & CSIZE) == CS7)
1566                 termios->c_cflag |= PARENB;
1567
1568         if ((termios->c_cflag & PARENB)) {
1569                 if (termios->c_cflag & CMSPAR) {
1570                         ctrl &= ~UARTCTRL_PE;
1571                         ctrl |= UARTCTRL_M;
1572                 } else {
1573                         ctrl |= UARTCR1_PE;
1574                         if ((termios->c_cflag & CSIZE) == CS8)
1575                                 ctrl |= UARTCTRL_M;
1576                         if (termios->c_cflag & PARODD)
1577                                 ctrl |= UARTCTRL_PT;
1578                         else
1579                                 ctrl &= ~UARTCTRL_PT;
1580                 }
1581         }
1582
1583         /* ask the core to calculate the divisor */
1584         baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1585
1586         spin_lock_irqsave(&sport->port.lock, flags);
1587
1588         sport->port.read_status_mask = 0;
1589         if (termios->c_iflag & INPCK)
1590                 sport->port.read_status_mask |= (UARTSTAT_FE | UARTSTAT_PE);
1591         if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1592                 sport->port.read_status_mask |= UARTSTAT_FE;
1593
1594         /* characters to ignore */
1595         sport->port.ignore_status_mask = 0;
1596         if (termios->c_iflag & IGNPAR)
1597                 sport->port.ignore_status_mask |= UARTSTAT_PE;
1598         if (termios->c_iflag & IGNBRK) {
1599                 sport->port.ignore_status_mask |= UARTSTAT_FE;
1600                 /*
1601                  * if we're ignoring parity and break indicators,
1602                  * ignore overruns too (for real raw support).
1603                  */
1604                 if (termios->c_iflag & IGNPAR)
1605                         sport->port.ignore_status_mask |= UARTSTAT_OR;
1606         }
1607
1608         /* update the per-port timeout */
1609         uart_update_timeout(port, termios->c_cflag, baud);
1610
1611         /* wait transmit engin complete */
1612         while (!(lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_TC))
1613                 barrier();
1614
1615         /* disable transmit and receive */
1616         lpuart32_write(&sport->port, old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE),
1617                        UARTCTRL);
1618
1619         sbr = sport->port.uartclk / (16 * baud);
1620         bd &= ~UARTBAUD_SBR_MASK;
1621         bd |= sbr & UARTBAUD_SBR_MASK;
1622         bd |= UARTBAUD_BOTHEDGE;
1623         bd &= ~(UARTBAUD_TDMAE | UARTBAUD_RDMAE);
1624         lpuart32_write(&sport->port, bd, UARTBAUD);
1625         lpuart32_write(&sport->port, modem, UARTMODIR);
1626         lpuart32_write(&sport->port, ctrl, UARTCTRL);
1627         /* restore control register */
1628
1629         spin_unlock_irqrestore(&sport->port.lock, flags);
1630 }
1631
1632 static const char *lpuart_type(struct uart_port *port)
1633 {
1634         return "FSL_LPUART";
1635 }
1636
1637 static void lpuart_release_port(struct uart_port *port)
1638 {
1639         /* nothing to do */
1640 }
1641
1642 static int lpuart_request_port(struct uart_port *port)
1643 {
1644         return  0;
1645 }
1646
1647 /* configure/autoconfigure the port */
1648 static void lpuart_config_port(struct uart_port *port, int flags)
1649 {
1650         if (flags & UART_CONFIG_TYPE)
1651                 port->type = PORT_LPUART;
1652 }
1653
1654 static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser)
1655 {
1656         int ret = 0;
1657
1658         if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART)
1659                 ret = -EINVAL;
1660         if (port->irq != ser->irq)
1661                 ret = -EINVAL;
1662         if (ser->io_type != UPIO_MEM)
1663                 ret = -EINVAL;
1664         if (port->uartclk / 16 != ser->baud_base)
1665                 ret = -EINVAL;
1666         if (port->iobase != ser->port)
1667                 ret = -EINVAL;
1668         if (ser->hub6 != 0)
1669                 ret = -EINVAL;
1670         return ret;
1671 }
1672
1673 static const struct uart_ops lpuart_pops = {
1674         .tx_empty       = lpuart_tx_empty,
1675         .set_mctrl      = lpuart_set_mctrl,
1676         .get_mctrl      = lpuart_get_mctrl,
1677         .stop_tx        = lpuart_stop_tx,
1678         .start_tx       = lpuart_start_tx,
1679         .stop_rx        = lpuart_stop_rx,
1680         .break_ctl      = lpuart_break_ctl,
1681         .startup        = lpuart_startup,
1682         .shutdown       = lpuart_shutdown,
1683         .set_termios    = lpuart_set_termios,
1684         .type           = lpuart_type,
1685         .request_port   = lpuart_request_port,
1686         .release_port   = lpuart_release_port,
1687         .config_port    = lpuart_config_port,
1688         .verify_port    = lpuart_verify_port,
1689         .flush_buffer   = lpuart_flush_buffer,
1690 #if defined(CONFIG_CONSOLE_POLL)
1691         .poll_init      = lpuart_poll_init,
1692         .poll_get_char  = lpuart_poll_get_char,
1693         .poll_put_char  = lpuart_poll_put_char,
1694 #endif
1695 };
1696
1697 static const struct uart_ops lpuart32_pops = {
1698         .tx_empty       = lpuart32_tx_empty,
1699         .set_mctrl      = lpuart32_set_mctrl,
1700         .get_mctrl      = lpuart32_get_mctrl,
1701         .stop_tx        = lpuart32_stop_tx,
1702         .start_tx       = lpuart32_start_tx,
1703         .stop_rx        = lpuart32_stop_rx,
1704         .break_ctl      = lpuart32_break_ctl,
1705         .startup        = lpuart32_startup,
1706         .shutdown       = lpuart32_shutdown,
1707         .set_termios    = lpuart32_set_termios,
1708         .type           = lpuart_type,
1709         .request_port   = lpuart_request_port,
1710         .release_port   = lpuart_release_port,
1711         .config_port    = lpuart_config_port,
1712         .verify_port    = lpuart_verify_port,
1713         .flush_buffer   = lpuart_flush_buffer,
1714 };
1715
1716 static struct lpuart_port *lpuart_ports[UART_NR];
1717
1718 #ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE
1719 static void lpuart_console_putchar(struct uart_port *port, int ch)
1720 {
1721         while (!(readb(port->membase + UARTSR1) & UARTSR1_TDRE))
1722                 barrier();
1723
1724         writeb(ch, port->membase + UARTDR);
1725 }
1726
1727 static void lpuart32_console_putchar(struct uart_port *port, int ch)
1728 {
1729         while (!(lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE))
1730                 barrier();
1731
1732         lpuart32_write(port, ch, UARTDATA);
1733 }
1734
1735 static void
1736 lpuart_console_write(struct console *co, const char *s, unsigned int count)
1737 {
1738         struct lpuart_port *sport = lpuart_ports[co->index];
1739         unsigned char  old_cr2, cr2;
1740         unsigned long flags;
1741         int locked = 1;
1742
1743         if (sport->port.sysrq || oops_in_progress)
1744                 locked = spin_trylock_irqsave(&sport->port.lock, flags);
1745         else
1746                 spin_lock_irqsave(&sport->port.lock, flags);
1747
1748         /* first save CR2 and then disable interrupts */
1749         cr2 = old_cr2 = readb(sport->port.membase + UARTCR2);
1750         cr2 |= (UARTCR2_TE |  UARTCR2_RE);
1751         cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
1752         writeb(cr2, sport->port.membase + UARTCR2);
1753
1754         uart_console_write(&sport->port, s, count, lpuart_console_putchar);
1755
1756         /* wait for transmitter finish complete and restore CR2 */
1757         while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC))
1758                 barrier();
1759
1760         writeb(old_cr2, sport->port.membase + UARTCR2);
1761
1762         if (locked)
1763                 spin_unlock_irqrestore(&sport->port.lock, flags);
1764 }
1765
1766 static void
1767 lpuart32_console_write(struct console *co, const char *s, unsigned int count)
1768 {
1769         struct lpuart_port *sport = lpuart_ports[co->index];
1770         unsigned long  old_cr, cr;
1771         unsigned long flags;
1772         int locked = 1;
1773
1774         if (sport->port.sysrq || oops_in_progress)
1775                 locked = spin_trylock_irqsave(&sport->port.lock, flags);
1776         else
1777                 spin_lock_irqsave(&sport->port.lock, flags);
1778
1779         /* first save CR2 and then disable interrupts */
1780         cr = old_cr = lpuart32_read(&sport->port, UARTCTRL);
1781         cr |= (UARTCTRL_TE |  UARTCTRL_RE);
1782         cr &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE);
1783         lpuart32_write(&sport->port, cr, UARTCTRL);
1784
1785         uart_console_write(&sport->port, s, count, lpuart32_console_putchar);
1786
1787         /* wait for transmitter finish complete and restore CR2 */
1788         while (!(lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_TC))
1789                 barrier();
1790
1791         lpuart32_write(&sport->port, old_cr, UARTCTRL);
1792
1793         if (locked)
1794                 spin_unlock_irqrestore(&sport->port.lock, flags);
1795 }
1796
1797 /*
1798  * if the port was already initialised (eg, by a boot loader),
1799  * try to determine the current setup.
1800  */
1801 static void __init
1802 lpuart_console_get_options(struct lpuart_port *sport, int *baud,
1803                            int *parity, int *bits)
1804 {
1805         unsigned char cr, bdh, bdl, brfa;
1806         unsigned int sbr, uartclk, baud_raw;
1807
1808         cr = readb(sport->port.membase + UARTCR2);
1809         cr &= UARTCR2_TE | UARTCR2_RE;
1810         if (!cr)
1811                 return;
1812
1813         /* ok, the port was enabled */
1814
1815         cr = readb(sport->port.membase + UARTCR1);
1816
1817         *parity = 'n';
1818         if (cr & UARTCR1_PE) {
1819                 if (cr & UARTCR1_PT)
1820                         *parity = 'o';
1821                 else
1822                         *parity = 'e';
1823         }
1824
1825         if (cr & UARTCR1_M)
1826                 *bits = 9;
1827         else
1828                 *bits = 8;
1829
1830         bdh = readb(sport->port.membase + UARTBDH);
1831         bdh &= UARTBDH_SBR_MASK;
1832         bdl = readb(sport->port.membase + UARTBDL);
1833         sbr = bdh;
1834         sbr <<= 8;
1835         sbr |= bdl;
1836         brfa = readb(sport->port.membase + UARTCR4);
1837         brfa &= UARTCR4_BRFA_MASK;
1838
1839         uartclk = clk_get_rate(sport->clk);
1840         /*
1841          * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
1842          */
1843         baud_raw = uartclk / (16 * (sbr + brfa / 32));
1844
1845         if (*baud != baud_raw)
1846                 printk(KERN_INFO "Serial: Console lpuart rounded baud rate"
1847                                 "from %d to %d\n", baud_raw, *baud);
1848 }
1849
1850 static void __init
1851 lpuart32_console_get_options(struct lpuart_port *sport, int *baud,
1852                            int *parity, int *bits)
1853 {
1854         unsigned long cr, bd;
1855         unsigned int sbr, uartclk, baud_raw;
1856
1857         cr = lpuart32_read(&sport->port, UARTCTRL);
1858         cr &= UARTCTRL_TE | UARTCTRL_RE;
1859         if (!cr)
1860                 return;
1861
1862         /* ok, the port was enabled */
1863
1864         cr = lpuart32_read(&sport->port, UARTCTRL);
1865
1866         *parity = 'n';
1867         if (cr & UARTCTRL_PE) {
1868                 if (cr & UARTCTRL_PT)
1869                         *parity = 'o';
1870                 else
1871                         *parity = 'e';
1872         }
1873
1874         if (cr & UARTCTRL_M)
1875                 *bits = 9;
1876         else
1877                 *bits = 8;
1878
1879         bd = lpuart32_read(&sport->port, UARTBAUD);
1880         bd &= UARTBAUD_SBR_MASK;
1881         sbr = bd;
1882         uartclk = clk_get_rate(sport->clk);
1883         /*
1884          * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
1885          */
1886         baud_raw = uartclk / (16 * sbr);
1887
1888         if (*baud != baud_raw)
1889                 printk(KERN_INFO "Serial: Console lpuart rounded baud rate"
1890                                 "from %d to %d\n", baud_raw, *baud);
1891 }
1892
1893 static int __init lpuart_console_setup(struct console *co, char *options)
1894 {
1895         struct lpuart_port *sport;
1896         int baud = 115200;
1897         int bits = 8;
1898         int parity = 'n';
1899         int flow = 'n';
1900
1901         /*
1902          * check whether an invalid uart number has been specified, and
1903          * if so, search for the first available port that does have
1904          * console support.
1905          */
1906         if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports))
1907                 co->index = 0;
1908
1909         sport = lpuart_ports[co->index];
1910         if (sport == NULL)
1911                 return -ENODEV;
1912
1913         if (options)
1914                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1915         else
1916                 if (sport->port.iotype & (UPIO_MEM32 | UPIO_MEM32BE))
1917                         lpuart32_console_get_options(sport, &baud, &parity, &bits);
1918                 else
1919                         lpuart_console_get_options(sport, &baud, &parity, &bits);
1920
1921         if (sport->port.iotype & (UPIO_MEM32 | UPIO_MEM32BE))
1922                 lpuart32_setup_watermark(sport);
1923         else
1924                 lpuart_setup_watermark(sport);
1925
1926         return uart_set_options(&sport->port, co, baud, parity, bits, flow);
1927 }
1928
1929 static struct uart_driver lpuart_reg;
1930 static struct console lpuart_console = {
1931         .name           = DEV_NAME,
1932         .write          = lpuart_console_write,
1933         .device         = uart_console_device,
1934         .setup          = lpuart_console_setup,
1935         .flags          = CON_PRINTBUFFER,
1936         .index          = -1,
1937         .data           = &lpuart_reg,
1938 };
1939
1940 static struct console lpuart32_console = {
1941         .name           = DEV_NAME,
1942         .write          = lpuart32_console_write,
1943         .device         = uart_console_device,
1944         .setup          = lpuart_console_setup,
1945         .flags          = CON_PRINTBUFFER,
1946         .index          = -1,
1947         .data           = &lpuart_reg,
1948 };
1949
1950 static void lpuart_early_write(struct console *con, const char *s, unsigned n)
1951 {
1952         struct earlycon_device *dev = con->data;
1953
1954         uart_console_write(&dev->port, s, n, lpuart_console_putchar);
1955 }
1956
1957 static void lpuart32_early_write(struct console *con, const char *s, unsigned n)
1958 {
1959         struct earlycon_device *dev = con->data;
1960
1961         uart_console_write(&dev->port, s, n, lpuart32_console_putchar);
1962 }
1963
1964 static int __init lpuart_early_console_setup(struct earlycon_device *device,
1965                                           const char *opt)
1966 {
1967         if (!device->port.membase)
1968                 return -ENODEV;
1969
1970         device->con->write = lpuart_early_write;
1971         return 0;
1972 }
1973
1974 static int __init lpuart32_early_console_setup(struct earlycon_device *device,
1975                                           const char *opt)
1976 {
1977         if (!device->port.membase)
1978                 return -ENODEV;
1979
1980         device->port.iotype = UPIO_MEM32BE;
1981         device->con->write = lpuart32_early_write;
1982         return 0;
1983 }
1984
1985 static int __init lpuart32_imx_early_console_setup(struct earlycon_device *device,
1986                                                    const char *opt)
1987 {
1988         if (!device->port.membase)
1989                 return -ENODEV;
1990
1991         device->port.iotype = UPIO_MEM32;
1992         device->port.membase += IMX_REG_OFF;
1993         device->con->write = lpuart32_early_write;
1994
1995         return 0;
1996 }
1997 OF_EARLYCON_DECLARE(lpuart, "fsl,vf610-lpuart", lpuart_early_console_setup);
1998 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup);
1999 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx7ulp-lpuart", lpuart32_imx_early_console_setup);
2000 EARLYCON_DECLARE(lpuart, lpuart_early_console_setup);
2001 EARLYCON_DECLARE(lpuart32, lpuart32_early_console_setup);
2002
2003 #define LPUART_CONSOLE  (&lpuart_console)
2004 #define LPUART32_CONSOLE        (&lpuart32_console)
2005 #else
2006 #define LPUART_CONSOLE  NULL
2007 #define LPUART32_CONSOLE        NULL
2008 #endif
2009
2010 static struct uart_driver lpuart_reg = {
2011         .owner          = THIS_MODULE,
2012         .driver_name    = DRIVER_NAME,
2013         .dev_name       = DEV_NAME,
2014         .nr             = ARRAY_SIZE(lpuart_ports),
2015         .cons           = LPUART_CONSOLE,
2016 };
2017
2018 static int lpuart_probe(struct platform_device *pdev)
2019 {
2020         const struct of_device_id *of_id = of_match_device(lpuart_dt_ids,
2021                                                            &pdev->dev);
2022         const struct lpuart_soc_data *sdata = of_id->data;
2023         struct device_node *np = pdev->dev.of_node;
2024         struct lpuart_port *sport;
2025         struct resource *res;
2026         int ret;
2027
2028         sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
2029         if (!sport)
2030                 return -ENOMEM;
2031
2032         pdev->dev.coherent_dma_mask = 0;
2033
2034         ret = of_alias_get_id(np, "serial");
2035         if (ret < 0) {
2036                 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
2037                 return ret;
2038         }
2039         sport->port.line = ret;
2040         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2041         sport->port.membase = devm_ioremap_resource(&pdev->dev, res);
2042         if (IS_ERR(sport->port.membase))
2043                 return PTR_ERR(sport->port.membase);
2044
2045         sport->port.membase += sdata->reg_off;
2046         sport->port.mapbase = res->start;
2047         sport->port.dev = &pdev->dev;
2048         sport->port.type = PORT_LPUART;
2049         ret = platform_get_irq(pdev, 0);
2050         if (ret < 0) {
2051                 dev_err(&pdev->dev, "cannot obtain irq\n");
2052                 return ret;
2053         }
2054         sport->port.irq = ret;
2055         sport->port.iotype = sdata->iotype;
2056         if (sport->port.iotype & (UPIO_MEM32 | UPIO_MEM32BE))
2057                 sport->port.ops = &lpuart32_pops;
2058         else
2059                 sport->port.ops = &lpuart_pops;
2060         sport->port.flags = UPF_BOOT_AUTOCONF;
2061
2062         sport->port.rs485_config = lpuart_config_rs485;
2063
2064         sport->clk = devm_clk_get(&pdev->dev, "ipg");
2065         if (IS_ERR(sport->clk)) {
2066                 ret = PTR_ERR(sport->clk);
2067                 dev_err(&pdev->dev, "failed to get uart clk: %d\n", ret);
2068                 return ret;
2069         }
2070
2071         ret = clk_prepare_enable(sport->clk);
2072         if (ret) {
2073                 dev_err(&pdev->dev, "failed to enable uart clk: %d\n", ret);
2074                 return ret;
2075         }
2076
2077         sport->port.uartclk = clk_get_rate(sport->clk);
2078
2079         lpuart_ports[sport->port.line] = sport;
2080
2081         platform_set_drvdata(pdev, &sport->port);
2082
2083         if (sport->port.iotype & (UPIO_MEM32 | UPIO_MEM32BE))
2084                 lpuart_reg.cons = LPUART32_CONSOLE;
2085         else
2086                 lpuart_reg.cons = LPUART_CONSOLE;
2087
2088         ret = uart_add_one_port(&lpuart_reg, &sport->port);
2089         if (ret) {
2090                 clk_disable_unprepare(sport->clk);
2091                 return ret;
2092         }
2093
2094         sport->dma_tx_chan = dma_request_slave_channel(sport->port.dev, "tx");
2095         if (!sport->dma_tx_chan)
2096                 dev_info(sport->port.dev, "DMA tx channel request failed, "
2097                                 "operating without tx DMA\n");
2098
2099         sport->dma_rx_chan = dma_request_slave_channel(sport->port.dev, "rx");
2100         if (!sport->dma_rx_chan)
2101                 dev_info(sport->port.dev, "DMA rx channel request failed, "
2102                                 "operating without rx DMA\n");
2103
2104         if (of_property_read_bool(np, "linux,rs485-enabled-at-boot-time")) {
2105                 sport->port.rs485.flags |= SER_RS485_ENABLED;
2106                 sport->port.rs485.flags |= SER_RS485_RTS_ON_SEND;
2107                 writeb(UARTMODEM_TXRTSE, sport->port.membase + UARTMODEM);
2108         }
2109
2110         return 0;
2111 }
2112
2113 static int lpuart_remove(struct platform_device *pdev)
2114 {
2115         struct lpuart_port *sport = platform_get_drvdata(pdev);
2116
2117         uart_remove_one_port(&lpuart_reg, &sport->port);
2118
2119         clk_disable_unprepare(sport->clk);
2120
2121         if (sport->dma_tx_chan)
2122                 dma_release_channel(sport->dma_tx_chan);
2123
2124         if (sport->dma_rx_chan)
2125                 dma_release_channel(sport->dma_rx_chan);
2126
2127         return 0;
2128 }
2129
2130 #ifdef CONFIG_PM_SLEEP
2131 static int lpuart_suspend(struct device *dev)
2132 {
2133         struct lpuart_port *sport = dev_get_drvdata(dev);
2134         unsigned long temp;
2135
2136         if (sport->port.iotype & (UPIO_MEM32 | UPIO_MEM32BE)) {
2137                 /* disable Rx/Tx and interrupts */
2138                 temp = lpuart32_read(&sport->port, UARTCTRL);
2139                 temp &= ~(UARTCTRL_TE | UARTCTRL_TIE | UARTCTRL_TCIE);
2140                 lpuart32_write(&sport->port, temp, UARTCTRL);
2141         } else {
2142                 /* disable Rx/Tx and interrupts */
2143                 temp = readb(sport->port.membase + UARTCR2);
2144                 temp &= ~(UARTCR2_TE | UARTCR2_TIE | UARTCR2_TCIE);
2145                 writeb(temp, sport->port.membase + UARTCR2);
2146         }
2147
2148         uart_suspend_port(&lpuart_reg, &sport->port);
2149
2150         if (sport->lpuart_dma_rx_use) {
2151                 /*
2152                  * EDMA driver during suspend will forcefully release any
2153                  * non-idle DMA channels. If port wakeup is enabled or if port
2154                  * is console port or 'no_console_suspend' is set the Rx DMA
2155                  * cannot resume as as expected, hence gracefully release the
2156                  * Rx DMA path before suspend and start Rx DMA path on resume.
2157                  */
2158                 if (sport->port.irq_wake) {
2159                         del_timer_sync(&sport->lpuart_timer);
2160                         lpuart_dma_rx_free(&sport->port);
2161                 }
2162
2163                 /* Disable Rx DMA to use UART port as wakeup source */
2164                 writeb(readb(sport->port.membase + UARTCR5) & ~UARTCR5_RDMAS,
2165                                         sport->port.membase + UARTCR5);
2166         }
2167
2168         if (sport->lpuart_dma_tx_use) {
2169                 sport->dma_tx_in_progress = false;
2170                 dmaengine_terminate_all(sport->dma_tx_chan);
2171         }
2172
2173         if (sport->port.suspended && !sport->port.irq_wake)
2174                 clk_disable_unprepare(sport->clk);
2175
2176         return 0;
2177 }
2178
2179 static int lpuart_resume(struct device *dev)
2180 {
2181         struct lpuart_port *sport = dev_get_drvdata(dev);
2182         unsigned long temp;
2183
2184         if (sport->port.suspended && !sport->port.irq_wake)
2185                 clk_prepare_enable(sport->clk);
2186
2187         if (sport->port.iotype & (UPIO_MEM32 | UPIO_MEM32BE)) {
2188                 lpuart32_setup_watermark(sport);
2189                 temp = lpuart32_read(&sport->port, UARTCTRL);
2190                 temp |= (UARTCTRL_RIE | UARTCTRL_TIE | UARTCTRL_RE |
2191                          UARTCTRL_TE | UARTCTRL_ILIE);
2192                 lpuart32_write(&sport->port, temp, UARTCTRL);
2193         } else {
2194                 lpuart_setup_watermark(sport);
2195                 temp = readb(sport->port.membase + UARTCR2);
2196                 temp |= (UARTCR2_RIE | UARTCR2_TIE | UARTCR2_RE | UARTCR2_TE);
2197                 writeb(temp, sport->port.membase + UARTCR2);
2198         }
2199
2200         if (sport->lpuart_dma_rx_use) {
2201                 if (sport->port.irq_wake) {
2202                         if (!lpuart_start_rx_dma(sport))
2203                                 rx_dma_timer_init(sport);
2204                         else
2205                                 sport->lpuart_dma_rx_use = false;
2206                 }
2207         }
2208
2209         if (sport->dma_tx_chan && !lpuart_dma_tx_request(&sport->port)) {
2210                         init_waitqueue_head(&sport->dma_wait);
2211                         sport->lpuart_dma_tx_use = true;
2212                         writeb(readb(sport->port.membase + UARTCR5) |
2213                                 UARTCR5_TDMAS, sport->port.membase + UARTCR5);
2214         } else {
2215                 sport->lpuart_dma_tx_use = false;
2216         }
2217
2218         uart_resume_port(&lpuart_reg, &sport->port);
2219
2220         return 0;
2221 }
2222 #endif
2223
2224 static SIMPLE_DEV_PM_OPS(lpuart_pm_ops, lpuart_suspend, lpuart_resume);
2225
2226 static struct platform_driver lpuart_driver = {
2227         .probe          = lpuart_probe,
2228         .remove         = lpuart_remove,
2229         .driver         = {
2230                 .name   = "fsl-lpuart",
2231                 .of_match_table = lpuart_dt_ids,
2232                 .pm     = &lpuart_pm_ops,
2233         },
2234 };
2235
2236 static int __init lpuart_serial_init(void)
2237 {
2238         int ret = uart_register_driver(&lpuart_reg);
2239
2240         if (ret)
2241                 return ret;
2242
2243         ret = platform_driver_register(&lpuart_driver);
2244         if (ret)
2245                 uart_unregister_driver(&lpuart_reg);
2246
2247         return ret;
2248 }
2249
2250 static void __exit lpuart_serial_exit(void)
2251 {
2252         platform_driver_unregister(&lpuart_driver);
2253         uart_unregister_driver(&lpuart_reg);
2254 }
2255
2256 module_init(lpuart_serial_init);
2257 module_exit(lpuart_serial_exit);
2258
2259 MODULE_DESCRIPTION("Freescale lpuart serial port driver");
2260 MODULE_LICENSE("GPL v2");