drivers/usb/dwc3/ep0.c

   1 /**
   2  * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions, and the following disclaimer,
  14  *    without modification.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  * 3. The names of the above-listed copyright holders may not be used
  19  *    to endorse or promote products derived from this software without
  20  *    specific prior written permission.
  21  *
  22  * ALTERNATIVELY, this software may be distributed under the terms of the
  23  * GNU General Public License ("GPL") version 2, as published by the Free
  24  * Software Foundation.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  27  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  28  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  29  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  30  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  31  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  32  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  33  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  34  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  35  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  36  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  37  */
  38
  39 #include <linux/kernel.h>
  40 #include <linux/slab.h>
  41 #include <linux/spinlock.h>
  42 #include <linux/platform_device.h>
  43 #include <linux/pm_runtime.h>
  44 #include <linux/interrupt.h>
  45 #include <linux/io.h>
  46 #include <linux/list.h>
  47 #include <linux/dma-mapping.h>
  48
  49 #include <linux/usb/ch9.h>
  50 #include <linux/usb/gadget.h>
  51 #include <linux/usb/composite.h>
  52
  53 #include "core.h"
  54 #include "gadget.h"
  55 #include "io.h"
  56
  57 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
  58 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
  59                 struct dwc3_ep *dep, struct dwc3_request *req);
  60
  61 static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state)
  62 {
  63         switch (state) {
  64         case EP0_UNCONNECTED:
  65                 return "Unconnected";
  66         case EP0_SETUP_PHASE:
  67                 return "Setup Phase";
  68         case EP0_DATA_PHASE:
  69                 return "Data Phase";
  70         case EP0_STATUS_PHASE:
  71                 return "Status Phase";
  72         default:
  73                 return "UNKNOWN";
  74         }
  75 }
  76
  77 static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,
  78                 u32 len, u32 type)
  79 {
  80         struct dwc3_gadget_ep_cmd_params params;
  81         struct dwc3_trb                 *trb;
  82         struct dwc3_ep                  *dep;
  83
  84         int                             ret;
  85
  86         dep = dwc->eps[epnum];
  87         if (dep->flags & DWC3_EP_BUSY) {
  88                 dev_vdbg(dwc->dev, "%s: still busy\n", dep->name);
  89                 return 0;
  90         }
  91
  92         trb = dwc->ep0_trb;
  93
  94         trb->bpl = lower_32_bits(buf_dma);
  95         trb->bph = upper_32_bits(buf_dma);
  96         trb->size = len;
  97         trb->ctrl = type;
  98
  99         trb->ctrl |= (DWC3_TRB_CTRL_HWO
 100                         | DWC3_TRB_CTRL_LST
 101                         | DWC3_TRB_CTRL_IOC
 102                         | DWC3_TRB_CTRL_ISP_IMI);
 103
 104         memset(&params, 0, sizeof(params));
 105         params.param0 = upper_32_bits(dwc->ep0_trb_addr);
 106         params.param1 = lower_32_bits(dwc->ep0_trb_addr);
 107
 108         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
 109                         DWC3_DEPCMD_STARTTRANSFER, &params);
 110         if (ret < 0) {
 111                 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
 112                 return ret;
 113         }
 114
 115         dep->flags |= DWC3_EP_BUSY;
 116         dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
 117                         dep->number);
 118
 119         dwc->ep0_next_event = DWC3_EP0_COMPLETE;
 120
 121         return 0;
 122 }
 123
 124 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
 125                 struct dwc3_request *req)
 126 {
 127         struct dwc3             *dwc = dep->dwc;
 128         int                     ret = 0;
 129
 130         req->request.actual     = 0;
 131         req->request.status     = -EINPROGRESS;
 132         req->epnum              = dep->number;
 133
 134         list_add_tail(&req->list, &dep->request_list);
 135
 136         /*
 137          * Gadget driver might not be quick enough to queue a request
 138          * before we get a Transfer Not Ready event on this endpoint.
 139          *
 140          * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
 141          * flag is set, it's telling us that as soon as Gadget queues the
 142          * required request, we should kick the transfer here because the
 143          * IRQ we were waiting for is long gone.
 144          */
 145         if (dep->flags & DWC3_EP_PENDING_REQUEST) {
 146                 unsigned        direction;
 147
 148                 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
 149
 150                 if (dwc->ep0state != EP0_DATA_PHASE) {
 151                         dev_WARN(dwc->dev, "Unexpected pending request\n");
 152                         return 0;
 153                 }
 154
 155                 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
 156
 157                 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
 158                                 DWC3_EP0_DIR_IN);
 159         } else if (dwc->delayed_status) {
 160                 dwc->delayed_status = false;
 161
 162                 if (dwc->ep0state == EP0_STATUS_PHASE)
 163                         __dwc3_ep0_do_control_status(dwc, dwc->eps[1]);
 164                 else
 165                         dev_dbg(dwc->dev, "too early for delayed status\n");
 166         }
 167
 168         return ret;
 169 }
 170
 171 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
 172                 gfp_t gfp_flags)
 173 {
 174         struct dwc3_request             *req = to_dwc3_request(request);
 175         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 176         struct dwc3                     *dwc = dep->dwc;
 177
 178         unsigned long                   flags;
 179
 180         int                             ret;
 181
 182         spin_lock_irqsave(&dwc->lock, flags);
 183         if (!dep->endpoint.desc) {
 184                 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
 185                                 request, dep->name);
 186                 ret = -ESHUTDOWN;
 187                 goto out;
 188         }
 189
 190         /* we share one TRB for ep0/1 */
 191         if (!list_empty(&dep->request_list)) {
 192                 ret = -EBUSY;
 193                 goto out;
 194         }
 195
 196         dev_vdbg(dwc->dev, "queueing request %p to %s length %d, state '%s'\n",
 197                         request, dep->name, request->length,
 198                         dwc3_ep0_state_string(dwc->ep0state));
 199
 200         ret = __dwc3_gadget_ep0_queue(dep, req);
 201
 202 out:
 203         spin_unlock_irqrestore(&dwc->lock, flags);
 204
 205         return ret;
 206 }
 207
 208 static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
 209 {
 210         struct dwc3_ep          *dep = dwc->eps[0];
 211
 212         /* stall is always issued on EP0 */
 213         __dwc3_gadget_ep_set_halt(dep, 1);
 214         dep->flags = DWC3_EP_ENABLED;
 215         dwc->delayed_status = false;
 216
 217         if (!list_empty(&dep->request_list)) {
 218                 struct dwc3_request     *req;
 219
 220                 req = next_request(&dep->request_list);
 221                 dwc3_gadget_giveback(dep, req, -ECONNRESET);
 222         }
 223
 224         dwc->ep0state = EP0_SETUP_PHASE;
 225         dwc3_ep0_out_start(dwc);
 226 }
 227
 228 int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
 229 {
 230         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 231         struct dwc3                     *dwc = dep->dwc;
 232
 233         dwc3_ep0_stall_and_restart(dwc);
 234
 235         return 0;
 236 }
 237
 238 void dwc3_ep0_out_start(struct dwc3 *dwc)
 239 {
 240         int                             ret;
 241
 242         ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8,
 243                         DWC3_TRBCTL_CONTROL_SETUP);
 244         WARN_ON(ret < 0);
 245 }
 246
 247 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
 248 {
 249         struct dwc3_ep          *dep;
 250         u32                     windex = le16_to_cpu(wIndex_le);
 251         u32                     epnum;
 252
 253         epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
 254         if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
 255                 epnum |= 1;
 256
 257         dep = dwc->eps[epnum];
 258         if (dep->flags & DWC3_EP_ENABLED)
 259                 return dep;
 260
 261         return NULL;
 262 }
 263
 264 static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
 265 {
 266 }
 267 /*
 268  * ch 9.4.5
 269  */
 270 static int dwc3_ep0_handle_status(struct dwc3 *dwc,
 271                 struct usb_ctrlrequest *ctrl)
 272 {
 273         struct dwc3_ep          *dep;
 274         u32                     recip;
 275         u32                     reg;
 276         u16                     usb_status = 0;
 277         __le16                  *response_pkt;
 278
 279         recip = ctrl->bRequestType & USB_RECIP_MASK;
 280         switch (recip) {
 281         case USB_RECIP_DEVICE:
 282                 /*
 283                  * LTM will be set once we know how to set this in HW.
 284                  */
 285                 usb_status |= dwc->is_selfpowered << USB_DEVICE_SELF_POWERED;
 286
 287                 if (dwc->speed == DWC3_DSTS_SUPERSPEED) {
 288                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 289                         if (reg & DWC3_DCTL_INITU1ENA)
 290                                 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
 291                         if (reg & DWC3_DCTL_INITU2ENA)
 292                                 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
 293                 }
 294
 295                 break;
 296
 297         case USB_RECIP_INTERFACE:
 298                 /*
 299                  * Function Remote Wake Capable D0
 300                  * Function Remote Wakeup       D1
 301                  */
 302                 break;
 303
 304         case USB_RECIP_ENDPOINT:
 305                 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
 306                 if (!dep)
 307                         return -EINVAL;
 308
 309                 if (dep->flags & DWC3_EP_STALL)
 310                         usb_status = 1 << USB_ENDPOINT_HALT;
 311                 break;
 312         default:
 313                 return -EINVAL;
 314         };
 315
 316         response_pkt = (__le16 *) dwc->setup_buf;
 317         *response_pkt = cpu_to_le16(usb_status);
 318
 319         dep = dwc->eps[0];
 320         dwc->ep0_usb_req.dep = dep;
 321         dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
 322         dwc->ep0_usb_req.request.buf = dwc->setup_buf;
 323         dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
 324
 325         return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
 326 }
 327
 328 static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
 329                 struct usb_ctrlrequest *ctrl, int set)
 330 {
 331         struct dwc3_ep          *dep;
 332         u32                     recip;
 333         u32                     wValue;
 334         u32                     wIndex;
 335         u32                     reg;
 336         int                     ret;
 337
 338         wValue = le16_to_cpu(ctrl->wValue);
 339         wIndex = le16_to_cpu(ctrl->wIndex);
 340         recip = ctrl->bRequestType & USB_RECIP_MASK;
 341         switch (recip) {
 342         case USB_RECIP_DEVICE:
 343
 344                 switch (wValue) {
 345                 case USB_DEVICE_REMOTE_WAKEUP:
 346                         break;
 347                 /*
 348                  * 9.4.1 says only only for SS, in AddressState only for
 349                  * default control pipe
 350                  */
 351                 case USB_DEVICE_U1_ENABLE:
 352                         if (dwc->dev_state != DWC3_CONFIGURED_STATE)
 353                                 return -EINVAL;
 354                         if (dwc->speed != DWC3_DSTS_SUPERSPEED)
 355                                 return -EINVAL;
 356
 357                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 358                         if (set)
 359                                 reg |= DWC3_DCTL_INITU1ENA;
 360                         else
 361                                 reg &= ~DWC3_DCTL_INITU1ENA;
 362                         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 363                         break;
 364
 365                 case USB_DEVICE_U2_ENABLE:
 366                         if (dwc->dev_state != DWC3_CONFIGURED_STATE)
 367                                 return -EINVAL;
 368                         if (dwc->speed != DWC3_DSTS_SUPERSPEED)
 369                                 return -EINVAL;
 370
 371                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 372                         if (set)
 373                                 reg |= DWC3_DCTL_INITU2ENA;
 374                         else
 375                                 reg &= ~DWC3_DCTL_INITU2ENA;
 376                         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 377                         break;
 378
 379                 case USB_DEVICE_LTM_ENABLE:
 380                         return -EINVAL;
 381                         break;
 382
 383                 case USB_DEVICE_TEST_MODE:
 384                         if ((wIndex & 0xff) != 0)
 385                                 return -EINVAL;
 386                         if (!set)
 387                                 return -EINVAL;
 388
 389                         dwc->test_mode_nr = wIndex >> 8;
 390                         dwc->test_mode = true;
 391                         break;
 392                 default:
 393                         return -EINVAL;
 394                 }
 395                 break;
 396
 397         case USB_RECIP_INTERFACE:
 398                 switch (wValue) {
 399                 case USB_INTRF_FUNC_SUSPEND:
 400                         if (wIndex & USB_INTRF_FUNC_SUSPEND_LP)
 401                                 /* XXX enable Low power suspend */
 402                                 ;
 403                         if (wIndex & USB_INTRF_FUNC_SUSPEND_RW)
 404                                 /* XXX enable remote wakeup */
 405                                 ;
 406                         break;
 407                 default:
 408                         return -EINVAL;
 409                 }
 410                 break;
 411
 412         case USB_RECIP_ENDPOINT:
 413                 switch (wValue) {
 414                 case USB_ENDPOINT_HALT:
 415                         dep = dwc3_wIndex_to_dep(dwc, wIndex);
 416                         if (!dep)
 417                                 return -EINVAL;
 418                         ret = __dwc3_gadget_ep_set_halt(dep, set);
 419                         if (ret)
 420                                 return -EINVAL;
 421                         break;
 422                 default:
 423                         return -EINVAL;
 424                 }
 425                 break;
 426
 427         default:
 428                 return -EINVAL;
 429         };
 430
 431         return 0;
 432 }
 433
 434 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 435 {
 436         u32 addr;
 437         u32 reg;
 438
 439         addr = le16_to_cpu(ctrl->wValue);
 440         if (addr > 127) {
 441                 dev_dbg(dwc->dev, "invalid device address %d\n", addr);
 442                 return -EINVAL;
 443         }
 444
 445         if (dwc->dev_state == DWC3_CONFIGURED_STATE) {
 446                 dev_dbg(dwc->dev, "trying to set address when configured\n");
 447                 return -EINVAL;
 448         }
 449
 450         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
 451         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
 452         reg |= DWC3_DCFG_DEVADDR(addr);
 453         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
 454
 455         if (addr)
 456                 dwc->dev_state = DWC3_ADDRESS_STATE;
 457         else
 458                 dwc->dev_state = DWC3_DEFAULT_STATE;
 459
 460         return 0;
 461 }
 462
 463 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 464 {
 465         int ret;
 466
 467         spin_unlock(&dwc->lock);
 468         ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
 469         spin_lock(&dwc->lock);
 470         return ret;
 471 }
 472
 473 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 474 {
 475         u32 cfg;
 476         int ret;
 477         u32 reg;
 478
 479         dwc->start_config_issued = false;
 480         cfg = le16_to_cpu(ctrl->wValue);
 481
 482         switch (dwc->dev_state) {
 483         case DWC3_DEFAULT_STATE:
 484                 return -EINVAL;
 485                 break;
 486
 487         case DWC3_ADDRESS_STATE:
 488                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 489                 /* if the cfg matches and the cfg is non zero */
 490                 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
 491                         dwc->dev_state = DWC3_CONFIGURED_STATE;
 492                         /*
 493                          * Enable transition to U1/U2 state when
 494                          * nothing is pending from application.
 495                          */
 496                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 497                         reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA);
 498                         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 499
 500                         dwc->resize_fifos = true;
 501                         dev_dbg(dwc->dev, "resize fifos flag SET\n");
 502                 }
 503                 break;
 504
 505         case DWC3_CONFIGURED_STATE:
 506                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 507                 if (!cfg)
 508                         dwc->dev_state = DWC3_ADDRESS_STATE;
 509                 break;
 510         default:
 511                 ret = -EINVAL;
 512         }
 513         return ret;
 514 }
 515
 516 static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req)
 517 {
 518         struct dwc3_ep  *dep = to_dwc3_ep(ep);
 519         struct dwc3     *dwc = dep->dwc;
 520
 521         u32             param = 0;
 522         u32             reg;
 523
 524         struct timing {
 525                 u8      u1sel;
 526                 u8      u1pel;
 527                 u16     u2sel;
 528                 u16     u2pel;
 529         } __packed timing;
 530
 531         int             ret;
 532
 533         memcpy(&timing, req->buf, sizeof(timing));
 534
 535         dwc->u1sel = timing.u1sel;
 536         dwc->u1pel = timing.u1pel;
 537         dwc->u2sel = le16_to_cpu(timing.u2sel);
 538         dwc->u2pel = le16_to_cpu(timing.u2pel);
 539
 540         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 541         if (reg & DWC3_DCTL_INITU2ENA)
 542                 param = dwc->u2pel;
 543         if (reg & DWC3_DCTL_INITU1ENA)
 544                 param = dwc->u1pel;
 545
 546         /*
 547          * According to Synopsys Databook, if parameter is
 548          * greater than 125, a value of zero should be
 549          * programmed in the register.
 550          */
 551         if (param > 125)
 552                 param = 0;
 553
 554         /* now that we have the time, issue DGCMD Set Sel */
 555         ret = dwc3_send_gadget_generic_command(dwc,
 556                         DWC3_DGCMD_SET_PERIODIC_PAR, param);
 557         WARN_ON(ret < 0);
 558 }
 559
 560 static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 561 {
 562         struct dwc3_ep  *dep;
 563         u16             wLength;
 564         u16             wValue;
 565
 566         if (dwc->dev_state == DWC3_DEFAULT_STATE)
 567                 return -EINVAL;
 568
 569         wValue = le16_to_cpu(ctrl->wValue);
 570         wLength = le16_to_cpu(ctrl->wLength);
 571
 572         if (wLength != 6) {
 573                 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n",
 574                                 wLength);
 575                 return -EINVAL;
 576         }
 577
 578         /*
 579          * To handle Set SEL we need to receive 6 bytes from Host. So let's
 580          * queue a usb_request for 6 bytes.
 581          *
 582          * Remember, though, this controller can't handle non-wMaxPacketSize
 583          * aligned transfers on the OUT direction, so we queue a request for
 584          * wMaxPacketSize instead.
 585          */
 586         dep = dwc->eps[0];
 587         dwc->ep0_usb_req.dep = dep;
 588         dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
 589         dwc->ep0_usb_req.request.buf = dwc->setup_buf;
 590         dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
 591
 592         return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
 593 }
 594
 595 static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 596 {
 597         u16             wLength;
 598         u16             wValue;
 599         u16             wIndex;
 600
 601         wValue = le16_to_cpu(ctrl->wValue);
 602         wLength = le16_to_cpu(ctrl->wLength);
 603         wIndex = le16_to_cpu(ctrl->wIndex);
 604
 605         if (wIndex || wLength)
 606                 return -EINVAL;
 607
 608         /*
 609          * REVISIT It's unclear from Databook what to do with this
 610          * value. For now, just cache it.
 611          */
 612         dwc->isoch_delay = wValue;
 613
 614         return 0;
 615 }
 616
 617 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 618 {
 619         int ret;
 620
 621         switch (ctrl->bRequest) {
 622         case USB_REQ_GET_STATUS:
 623                 dev_vdbg(dwc->dev, "USB_REQ_GET_STATUS\n");
 624                 ret = dwc3_ep0_handle_status(dwc, ctrl);
 625                 break;
 626         case USB_REQ_CLEAR_FEATURE:
 627                 dev_vdbg(dwc->dev, "USB_REQ_CLEAR_FEATURE\n");
 628                 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
 629                 break;
 630         case USB_REQ_SET_FEATURE:
 631                 dev_vdbg(dwc->dev, "USB_REQ_SET_FEATURE\n");
 632                 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
 633                 break;
 634         case USB_REQ_SET_ADDRESS:
 635                 dev_vdbg(dwc->dev, "USB_REQ_SET_ADDRESS\n");
 636                 ret = dwc3_ep0_set_address(dwc, ctrl);
 637                 break;
 638         case USB_REQ_SET_CONFIGURATION:
 639                 dev_vdbg(dwc->dev, "USB_REQ_SET_CONFIGURATION\n");
 640                 ret = dwc3_ep0_set_config(dwc, ctrl);
 641                 break;
 642         case USB_REQ_SET_SEL:
 643                 dev_vdbg(dwc->dev, "USB_REQ_SET_SEL\n");
 644                 ret = dwc3_ep0_set_sel(dwc, ctrl);
 645                 break;
 646         case USB_REQ_SET_ISOCH_DELAY:
 647                 dev_vdbg(dwc->dev, "USB_REQ_SET_ISOCH_DELAY\n");
 648                 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
 649                 break;
 650         default:
 651                 dev_vdbg(dwc->dev, "Forwarding to gadget driver\n");
 652                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 653                 break;
 654         };
 655
 656         return ret;
 657 }
 658
 659 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
 660                 const struct dwc3_event_depevt *event)
 661 {
 662         struct usb_ctrlrequest *ctrl = dwc->ctrl_req;
 663         int ret = -EINVAL;
 664         u32 len;
 665
 666         if (!dwc->gadget_driver)
 667                 goto out;
 668
 669         len = le16_to_cpu(ctrl->wLength);
 670         if (!len) {
 671                 dwc->three_stage_setup = false;
 672                 dwc->ep0_expect_in = false;
 673                 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
 674         } else {
 675                 dwc->three_stage_setup = true;
 676                 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
 677                 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
 678         }
 679
 680         if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
 681                 ret = dwc3_ep0_std_request(dwc, ctrl);
 682         else
 683                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 684
 685         if (ret == USB_GADGET_DELAYED_STATUS)
 686                 dwc->delayed_status = true;
 687
 688 out:
 689         if (ret < 0)
 690                 dwc3_ep0_stall_and_restart(dwc);
 691 }
 692
 693 static void dwc3_ep0_complete_data(struct dwc3 *dwc,
 694                 const struct dwc3_event_depevt *event)
 695 {
 696         struct dwc3_request     *r = NULL;
 697         struct usb_request      *ur;
 698         struct dwc3_trb         *trb;
 699         struct dwc3_ep          *ep0;
 700         u32                     transferred;
 701         u32                     length;
 702         u8                      epnum;
 703
 704         epnum = event->endpoint_number;
 705         ep0 = dwc->eps[0];
 706
 707         dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
 708
 709         r = next_request(&ep0->request_list);
 710         ur = &r->request;
 711
 712         trb = dwc->ep0_trb;
 713         length = trb->size & DWC3_TRB_SIZE_MASK;
 714
 715         if (dwc->ep0_bounced) {
 716                 unsigned transfer_size = ur->length;
 717                 unsigned maxp = ep0->endpoint.maxpacket;
 718
 719                 transfer_size += (maxp - (transfer_size % maxp));
 720                 transferred = min_t(u32, ur->length,
 721                                 transfer_size - length);
 722                 memcpy(ur->buf, dwc->ep0_bounce, transferred);
 723         } else {
 724                 transferred = ur->length - length;
 725         }
 726
 727         ur->actual += transferred;
 728
 729         if ((epnum & 1) && ur->actual < ur->length) {
 730                 /* for some reason we did not get everything out */
 731
 732                 dwc3_ep0_stall_and_restart(dwc);
 733         } else {
 734                 /*
 735                  * handle the case where we have to send a zero packet. This
 736                  * seems to be case when req.length > maxpacket. Could it be?
 737                  */
 738                 if (r)
 739                         dwc3_gadget_giveback(ep0, r, 0);
 740         }
 741 }
 742
 743 static void dwc3_ep0_complete_status(struct dwc3 *dwc,
 744                 const struct dwc3_event_depevt *event)
 745 {
 746         struct dwc3_request     *r;
 747         struct dwc3_ep          *dep;
 748
 749         dep = dwc->eps[0];
 750
 751         if (!list_empty(&dep->request_list)) {
 752                 r = next_request(&dep->request_list);
 753
 754                 dwc3_gadget_giveback(dep, r, 0);
 755         }
 756
 757         if (dwc->test_mode) {
 758                 int ret;
 759
 760                 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
 761                 if (ret < 0) {
 762                         dev_dbg(dwc->dev, "Invalid Test #%d\n",
 763                                         dwc->test_mode_nr);
 764                         dwc3_ep0_stall_and_restart(dwc);
 765                         return;
 766                 }
 767         }
 768
 769         dwc->ep0state = EP0_SETUP_PHASE;
 770         dwc3_ep0_out_start(dwc);
 771 }
 772
 773 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
 774                         const struct dwc3_event_depevt *event)
 775 {
 776         struct dwc3_ep          *dep = dwc->eps[event->endpoint_number];
 777
 778         dep->flags &= ~DWC3_EP_BUSY;
 779         dep->resource_index = 0;
 780         dwc->setup_packet_pending = false;
 781
 782         switch (dwc->ep0state) {
 783         case EP0_SETUP_PHASE:
 784                 dev_vdbg(dwc->dev, "Inspecting Setup Bytes\n");
 785                 dwc3_ep0_inspect_setup(dwc, event);
 786                 break;
 787
 788         case EP0_DATA_PHASE:
 789                 dev_vdbg(dwc->dev, "Data Phase\n");
 790                 dwc3_ep0_complete_data(dwc, event);
 791                 break;
 792
 793         case EP0_STATUS_PHASE:
 794                 dev_vdbg(dwc->dev, "Status Phase\n");
 795                 dwc3_ep0_complete_status(dwc, event);
 796                 break;
 797         default:
 798                 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
 799         }
 800 }
 801
 802 static void dwc3_ep0_do_control_setup(struct dwc3 *dwc,
 803                 const struct dwc3_event_depevt *event)
 804 {
 805         dwc3_ep0_out_start(dwc);
 806 }
 807
 808 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
 809                 struct dwc3_ep *dep, struct dwc3_request *req)
 810 {
 811         int                     ret;
 812
 813         req->direction = !!dep->number;
 814
 815         if (req->request.length == 0) {
 816                 ret = dwc3_ep0_start_trans(dwc, dep->number,
 817                                 dwc->ctrl_req_addr, 0,
 818                                 DWC3_TRBCTL_CONTROL_DATA);
 819         } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket)
 820                         && (dep->number == 0)) {
 821                 u32             transfer_size;
 822
 823                 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
 824                                 dep->number);
 825                 if (ret) {
 826                         dev_dbg(dwc->dev, "failed to map request\n");
 827                         return;
 828                 }
 829
 830                 WARN_ON(req->request.length > DWC3_EP0_BOUNCE_SIZE);
 831
 832                 transfer_size = roundup(req->request.length,
 833                                 (u32) dep->endpoint.maxpacket);
 834
 835                 dwc->ep0_bounced = true;
 836
 837                 /*
 838                  * REVISIT in case request length is bigger than
 839                  * DWC3_EP0_BOUNCE_SIZE we will need two chained
 840                  * TRBs to handle the transfer.
 841                  */
 842                 ret = dwc3_ep0_start_trans(dwc, dep->number,
 843                                 dwc->ep0_bounce_addr, transfer_size,
 844                                 DWC3_TRBCTL_CONTROL_DATA);
 845         } else {
 846                 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
 847                                 dep->number);
 848                 if (ret) {
 849                         dev_dbg(dwc->dev, "failed to map request\n");
 850                         return;
 851                 }
 852
 853                 ret = dwc3_ep0_start_trans(dwc, dep->number, req->request.dma,
 854                                 req->request.length, DWC3_TRBCTL_CONTROL_DATA);
 855         }
 856
 857         WARN_ON(ret < 0);
 858 }
 859
 860 static void dwc3_ep0_do_control_data(struct dwc3 *dwc,
 861                 const struct dwc3_event_depevt *event)
 862 {
 863         struct dwc3_ep          *dep;
 864         struct dwc3_request     *req;
 865
 866         dep = dwc->eps[0];
 867
 868         if (list_empty(&dep->request_list)) {
 869                 dev_vdbg(dwc->dev, "pending request for EP0 Data phase\n");
 870                 dep->flags |= DWC3_EP_PENDING_REQUEST;
 871
 872                 if (event->endpoint_number)
 873                         dep->flags |= DWC3_EP0_DIR_IN;
 874                 return;
 875         }
 876
 877         req = next_request(&dep->request_list);
 878         dep = dwc->eps[event->endpoint_number];
 879
 880         __dwc3_ep0_do_control_data(dwc, dep, req);
 881 }
 882
 883 static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
 884 {
 885         struct dwc3             *dwc = dep->dwc;
 886         u32                     type;
 887
 888         type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
 889                 : DWC3_TRBCTL_CONTROL_STATUS2;
 890
 891         return dwc3_ep0_start_trans(dwc, dep->number,
 892                         dwc->ctrl_req_addr, 0, type);
 893 }
 894
 895 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep)
 896 {
 897         if (dwc->resize_fifos) {
 898                 dev_dbg(dwc->dev, "starting to resize fifos\n");
 899                 dwc3_gadget_resize_tx_fifos(dwc);
 900                 dwc->resize_fifos = 0;
 901         }
 902
 903         WARN_ON(dwc3_ep0_start_control_status(dep));
 904 }
 905
 906 static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
 907                 const struct dwc3_event_depevt *event)
 908 {
 909         struct dwc3_ep          *dep = dwc->eps[event->endpoint_number];
 910
 911         __dwc3_ep0_do_control_status(dwc, dep);
 912 }
 913
 914 static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
 915                 const struct dwc3_event_depevt *event)
 916 {
 917         dwc->setup_packet_pending = true;
 918
 919         /*
 920          * This part is very tricky: If we have just handled
 921          * XferNotReady(Setup) and we're now expecting a
 922          * XferComplete but, instead, we receive another
 923          * XferNotReady(Setup), we should STALL and restart
 924          * the state machine.
 925          *
 926          * In all other cases, we just continue waiting
 927          * for the XferComplete event.
 928          *
 929          * We are a little bit unsafe here because we're
 930          * not trying to ensure that last event was, indeed,
 931          * XferNotReady(Setup).
 932          *
 933          * Still, we don't expect any condition where that
 934          * should happen and, even if it does, it would be
 935          * another error condition.
 936          */
 937         if (dwc->ep0_next_event == DWC3_EP0_COMPLETE) {
 938                 switch (event->status) {
 939                 case DEPEVT_STATUS_CONTROL_SETUP:
 940                         dev_vdbg(dwc->dev, "Unexpected XferNotReady(Setup)\n");
 941                         dwc3_ep0_stall_and_restart(dwc);
 942                         break;
 943                 case DEPEVT_STATUS_CONTROL_DATA:
 944                         /* FALLTHROUGH */
 945                 case DEPEVT_STATUS_CONTROL_STATUS:
 946                         /* FALLTHROUGH */
 947                 default:
 948                         dev_vdbg(dwc->dev, "waiting for XferComplete\n");
 949                 }
 950
 951                 return;
 952         }
 953
 954         switch (event->status) {
 955         case DEPEVT_STATUS_CONTROL_SETUP:
 956                 dev_vdbg(dwc->dev, "Control Setup\n");
 957
 958                 dwc->ep0state = EP0_SETUP_PHASE;
 959
 960                 dwc3_ep0_do_control_setup(dwc, event);
 961                 break;
 962
 963         case DEPEVT_STATUS_CONTROL_DATA:
 964                 dev_vdbg(dwc->dev, "Control Data\n");
 965
 966                 dwc->ep0state = EP0_DATA_PHASE;
 967
 968                 if (dwc->ep0_next_event != DWC3_EP0_NRDY_DATA) {
 969                         dev_vdbg(dwc->dev, "Expected %d got %d\n",
 970                                         dwc->ep0_next_event,
 971                                         DWC3_EP0_NRDY_DATA);
 972
 973                         dwc3_ep0_stall_and_restart(dwc);
 974                         return;
 975                 }
 976
 977                 /*
 978                  * One of the possible error cases is when Host _does_
 979                  * request for Data Phase, but it does so on the wrong
 980                  * direction.
 981                  *
 982                  * Here, we already know ep0_next_event is DATA (see above),
 983                  * so we only need to check for direction.
 984                  */
 985                 if (dwc->ep0_expect_in != event->endpoint_number) {
 986                         dev_vdbg(dwc->dev, "Wrong direction for Data phase\n");
 987                         dwc3_ep0_stall_and_restart(dwc);
 988                         return;
 989                 }
 990
 991                 dwc3_ep0_do_control_data(dwc, event);
 992                 break;
 993
 994         case DEPEVT_STATUS_CONTROL_STATUS:
 995                 dev_vdbg(dwc->dev, "Control Status\n");
 996
 997                 dwc->ep0state = EP0_STATUS_PHASE;
 998
 999                 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS) {
1000                         dev_vdbg(dwc->dev, "Expected %d got %d\n",
1001                                         dwc->ep0_next_event,
1002                                         DWC3_EP0_NRDY_STATUS);
1003
1004                         dwc3_ep0_stall_and_restart(dwc);
1005                         return;
1006                 }
1007
1008                 if (dwc->delayed_status) {
1009                         WARN_ON_ONCE(event->endpoint_number != 1);
1010                         dev_vdbg(dwc->dev, "Mass Storage delayed status\n");
1011                         return;
1012                 }
1013
1014                 dwc3_ep0_do_control_status(dwc, event);
1015         }
1016 }
1017
1018 void dwc3_ep0_interrupt(struct dwc3 *dwc,
1019                 const struct dwc3_event_depevt *event)
1020 {
1021         u8                      epnum = event->endpoint_number;
1022
1023         dev_dbg(dwc->dev, "%s while ep%d%s in state '%s'\n",
1024                         dwc3_ep_event_string(event->endpoint_event),
1025                         epnum >> 1, (epnum & 1) ? "in" : "out",
1026                         dwc3_ep0_state_string(dwc->ep0state));
1027
1028         switch (event->endpoint_event) {
1029         case DWC3_DEPEVT_XFERCOMPLETE:
1030                 dwc3_ep0_xfer_complete(dwc, event);
1031                 break;
1032
1033         case DWC3_DEPEVT_XFERNOTREADY:
1034                 dwc3_ep0_xfernotready(dwc, event);
1035                 break;
1036
1037         case DWC3_DEPEVT_XFERINPROGRESS:
1038         case DWC3_DEPEVT_RXTXFIFOEVT:
1039         case DWC3_DEPEVT_STREAMEVT:
1040         case DWC3_DEPEVT_EPCMDCMPLT:
1041                 break;
1042         }
1043 }