drivers/usb/dwc3/gadget.c

   1 /**
   2  * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * This program is free software: you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2  of
  11  * the License as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/delay.h>
  21 #include <linux/slab.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/pm_runtime.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/io.h>
  27 #include <linux/list.h>
  28 #include <linux/dma-mapping.h>
  29
  30 #include <linux/usb/ch9.h>
  31 #include <linux/usb/gadget.h>
  32
  33 #include "debug.h"
  34 #include "core.h"
  35 #include "gadget.h"
  36 #include "io.h"
  37
  38 /**
  39  * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
  40  * @dwc: pointer to our context structure
  41  * @mode: the mode to set (J, K SE0 NAK, Force Enable)
  42  *
  43  * Caller should take care of locking. This function will
  44  * return 0 on success or -EINVAL if wrong Test Selector
  45  * is passed
  46  */
  47 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
  48 {
  49         u32             reg;
  50
  51         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  52         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
  53
  54         switch (mode) {
  55         case TEST_J:
  56         case TEST_K:
  57         case TEST_SE0_NAK:
  58         case TEST_PACKET:
  59         case TEST_FORCE_EN:
  60                 reg |= mode << 1;
  61                 break;
  62         default:
  63                 return -EINVAL;
  64         }
  65
  66         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  67
  68         return 0;
  69 }
  70
  71 /**
  72  * dwc3_gadget_get_link_state - Gets current state of USB Link
  73  * @dwc: pointer to our context structure
  74  *
  75  * Caller should take care of locking. This function will
  76  * return the link state on success (>= 0) or -ETIMEDOUT.
  77  */
  78 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
  79 {
  80         u32             reg;
  81
  82         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
  83
  84         return DWC3_DSTS_USBLNKST(reg);
  85 }
  86
  87 /**
  88  * dwc3_gadget_set_link_state - Sets USB Link to a particular State
  89  * @dwc: pointer to our context structure
  90  * @state: the state to put link into
  91  *
  92  * Caller should take care of locking. This function will
  93  * return 0 on success or -ETIMEDOUT.
  94  */
  95 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
  96 {
  97         int             retries = 10000;
  98         u32             reg;
  99
 100         /*
 101          * Wait until device controller is ready. Only applies to 1.94a and
 102          * later RTL.
 103          */
 104         if (dwc->revision >= DWC3_REVISION_194A) {
 105                 while (--retries) {
 106                         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 107                         if (reg & DWC3_DSTS_DCNRD)
 108                                 udelay(5);
 109                         else
 110                                 break;
 111                 }
 112
 113                 if (retries <= 0)
 114                         return -ETIMEDOUT;
 115         }
 116
 117         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 118         reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
 119
 120         /* set requested state */
 121         reg |= DWC3_DCTL_ULSTCHNGREQ(state);
 122         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 123
 124         /*
 125          * The following code is racy when called from dwc3_gadget_wakeup,
 126          * and is not needed, at least on newer versions
 127          */
 128         if (dwc->revision >= DWC3_REVISION_194A)
 129                 return 0;
 130
 131         /* wait for a change in DSTS */
 132         retries = 10000;
 133         while (--retries) {
 134                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 135
 136                 if (DWC3_DSTS_USBLNKST(reg) == state)
 137                         return 0;
 138
 139                 udelay(5);
 140         }
 141
 142         dwc3_trace(trace_dwc3_gadget,
 143                         "link state change request timed out");
 144
 145         return -ETIMEDOUT;
 146 }
 147
 148 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
 149                 int status)
 150 {
 151         struct dwc3                     *dwc = dep->dwc;
 152         int                             i;
 153
 154         if (req->started) {
 155                 i = 0;
 156                 do {
 157                         dep->trb_dequeue++;
 158                         /*
 159                          * Skip LINK TRB. We can't use req->trb and check for
 160                          * DWC3_TRBCTL_LINK_TRB because it points the TRB we
 161                          * just completed (not the LINK TRB).
 162                          */
 163                         if (((dep->trb_dequeue % DWC3_TRB_NUM) ==
 164                                 DWC3_TRB_NUM - 1) &&
 165                                 usb_endpoint_xfer_isoc(dep->endpoint.desc))
 166                                 dep->trb_dequeue++;
 167                 } while(++i < req->request.num_mapped_sgs);
 168                 req->started = false;
 169         }
 170         list_del(&req->list);
 171         req->trb = NULL;
 172
 173         if (req->request.status == -EINPROGRESS)
 174                 req->request.status = status;
 175
 176         if (dwc->ep0_bounced && dep->number == 0)
 177                 dwc->ep0_bounced = false;
 178         else
 179                 usb_gadget_unmap_request(&dwc->gadget, &req->request,
 180                                 req->direction);
 181
 182         trace_dwc3_gadget_giveback(req);
 183
 184         spin_unlock(&dwc->lock);
 185         usb_gadget_giveback_request(&dep->endpoint, &req->request);
 186         spin_lock(&dwc->lock);
 187 }
 188
 189 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
 190 {
 191         u32             timeout = 500;
 192         u32             reg;
 193
 194         trace_dwc3_gadget_generic_cmd(cmd, param);
 195
 196         dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
 197         dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
 198
 199         do {
 200                 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
 201                 if (!(reg & DWC3_DGCMD_CMDACT)) {
 202                         dwc3_trace(trace_dwc3_gadget,
 203                                         "Command Complete --> %d",
 204                                         DWC3_DGCMD_STATUS(reg));
 205                         if (DWC3_DGCMD_STATUS(reg))
 206                                 return -EINVAL;
 207                         return 0;
 208                 }
 209
 210                 /*
 211                  * We can't sleep here, because it's also called from
 212                  * interrupt context.
 213                  */
 214                 timeout--;
 215                 if (!timeout) {
 216                         dwc3_trace(trace_dwc3_gadget,
 217                                         "Command Timed Out");
 218                         return -ETIMEDOUT;
 219                 }
 220                 udelay(1);
 221         } while (1);
 222 }
 223
 224 static int __dwc3_gadget_wakeup(struct dwc3 *dwc);
 225
 226 int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
 227                 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
 228 {
 229         struct dwc3_ep          *dep = dwc->eps[ep];
 230         u32                     timeout = 500;
 231         u32                     reg;
 232
 233         int                     susphy = false;
 234         int                     ret = -EINVAL;
 235
 236         trace_dwc3_gadget_ep_cmd(dep, cmd, params);
 237
 238         /*
 239          * Synopsys Databook 2.60a states, on section 6.3.2.5.[1-8], that if
 240          * we're issuing an endpoint command, we must check if
 241          * GUSB2PHYCFG.SUSPHY bit is set. If it is, then we need to clear it.
 242          *
 243          * We will also set SUSPHY bit to what it was before returning as stated
 244          * by the same section on Synopsys databook.
 245          */
 246         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 247         if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
 248                 susphy = true;
 249                 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 250                 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 251         }
 252
 253         if (cmd == DWC3_DEPCMD_STARTTRANSFER) {
 254                 int             needs_wakeup;
 255
 256                 needs_wakeup = (dwc->link_state == DWC3_LINK_STATE_U1 ||
 257                                 dwc->link_state == DWC3_LINK_STATE_U2 ||
 258                                 dwc->link_state == DWC3_LINK_STATE_U3);
 259
 260                 if (unlikely(needs_wakeup)) {
 261                         ret = __dwc3_gadget_wakeup(dwc);
 262                         dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
 263                                         ret);
 264                 }
 265         }
 266
 267         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
 268         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
 269         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
 270
 271         dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
 272         do {
 273                 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
 274                 if (!(reg & DWC3_DEPCMD_CMDACT)) {
 275                         dwc3_trace(trace_dwc3_gadget,
 276                                         "Command Complete --> %d",
 277                                         DWC3_DEPCMD_STATUS(reg));
 278                         if (DWC3_DEPCMD_STATUS(reg))
 279                                 break;
 280                         ret = 0;
 281                         break;
 282                 }
 283
 284                 /*
 285                  * We can't sleep here, because it is also called from
 286                  * interrupt context.
 287                  */
 288                 timeout--;
 289                 if (!timeout) {
 290                         dwc3_trace(trace_dwc3_gadget,
 291                                         "Command Timed Out");
 292                         ret = -ETIMEDOUT;
 293                         break;
 294                 }
 295
 296                 udelay(1);
 297         } while (1);
 298
 299         if (unlikely(susphy)) {
 300                 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 301                 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
 302                 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 303         }
 304
 305         return ret;
 306 }
 307
 308 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
 309                 struct dwc3_trb *trb)
 310 {
 311         u32             offset = (char *) trb - (char *) dep->trb_pool;
 312
 313         return dep->trb_pool_dma + offset;
 314 }
 315
 316 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
 317 {
 318         struct dwc3             *dwc = dep->dwc;
 319
 320         if (dep->trb_pool)
 321                 return 0;
 322
 323         dep->trb_pool = dma_alloc_coherent(dwc->dev,
 324                         sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
 325                         &dep->trb_pool_dma, GFP_KERNEL);
 326         if (!dep->trb_pool) {
 327                 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
 328                                 dep->name);
 329                 return -ENOMEM;
 330         }
 331
 332         return 0;
 333 }
 334
 335 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
 336 {
 337         struct dwc3             *dwc = dep->dwc;
 338
 339         dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
 340                         dep->trb_pool, dep->trb_pool_dma);
 341
 342         dep->trb_pool = NULL;
 343         dep->trb_pool_dma = 0;
 344 }
 345
 346 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep);
 347
 348 /**
 349  * dwc3_gadget_start_config - Configure EP resources
 350  * @dwc: pointer to our controller context structure
 351  * @dep: endpoint that is being enabled
 352  *
 353  * The assignment of transfer resources cannot perfectly follow the
 354  * data book due to the fact that the controller driver does not have
 355  * all knowledge of the configuration in advance. It is given this
 356  * information piecemeal by the composite gadget framework after every
 357  * SET_CONFIGURATION and SET_INTERFACE. Trying to follow the databook
 358  * programming model in this scenario can cause errors. For two
 359  * reasons:
 360  *
 361  * 1) The databook says to do DEPSTARTCFG for every SET_CONFIGURATION
 362  * and SET_INTERFACE (8.1.5). This is incorrect in the scenario of
 363  * multiple interfaces.
 364  *
 365  * 2) The databook does not mention doing more DEPXFERCFG for new
 366  * endpoint on alt setting (8.1.6).
 367  *
 368  * The following simplified method is used instead:
 369  *
 370  * All hardware endpoints can be assigned a transfer resource and this
 371  * setting will stay persistent until either a core reset or
 372  * hibernation. So whenever we do a DEPSTARTCFG(0) we can go ahead and
 373  * do DEPXFERCFG for every hardware endpoint as well. We are
 374  * guaranteed that there are as many transfer resources as endpoints.
 375  *
 376  * This function is called for each endpoint when it is being enabled
 377  * but is triggered only when called for EP0-out, which always happens
 378  * first, and which should only happen in one of the above conditions.
 379  */
 380 static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
 381 {
 382         struct dwc3_gadget_ep_cmd_params params;
 383         u32                     cmd;
 384         int                     i;
 385         int                     ret;
 386
 387         if (dep->number)
 388                 return 0;
 389
 390         memset(&params, 0x00, sizeof(params));
 391         cmd = DWC3_DEPCMD_DEPSTARTCFG;
 392
 393         ret = dwc3_send_gadget_ep_cmd(dwc, 0, cmd, &params);
 394         if (ret)
 395                 return ret;
 396
 397         for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
 398                 struct dwc3_ep *dep = dwc->eps[i];
 399
 400                 if (!dep)
 401                         continue;
 402
 403                 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
 404                 if (ret)
 405                         return ret;
 406         }
 407
 408         return 0;
 409 }
 410
 411 static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
 412                 const struct usb_endpoint_descriptor *desc,
 413                 const struct usb_ss_ep_comp_descriptor *comp_desc,
 414                 bool ignore, bool restore)
 415 {
 416         struct dwc3_gadget_ep_cmd_params params;
 417
 418         memset(&params, 0x00, sizeof(params));
 419
 420         params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
 421                 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
 422
 423         /* Burst size is only needed in SuperSpeed mode */
 424         if (dwc->gadget.speed >= USB_SPEED_SUPER) {
 425                 u32 burst = dep->endpoint.maxburst - 1;
 426
 427                 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst);
 428         }
 429
 430         if (ignore)
 431                 params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM;
 432
 433         if (restore) {
 434                 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
 435                 params.param2 |= dep->saved_state;
 436         }
 437
 438         params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
 439                 | DWC3_DEPCFG_XFER_NOT_READY_EN;
 440
 441         if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
 442                 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
 443                         | DWC3_DEPCFG_STREAM_EVENT_EN;
 444                 dep->stream_capable = true;
 445         }
 446
 447         if (!usb_endpoint_xfer_control(desc))
 448                 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
 449
 450         /*
 451          * We are doing 1:1 mapping for endpoints, meaning
 452          * Physical Endpoints 2 maps to Logical Endpoint 2 and
 453          * so on. We consider the direction bit as part of the physical
 454          * endpoint number. So USB endpoint 0x81 is 0x03.
 455          */
 456         params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
 457
 458         /*
 459          * We must use the lower 16 TX FIFOs even though
 460          * HW might have more
 461          */
 462         if (dep->direction)
 463                 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
 464
 465         if (desc->bInterval) {
 466                 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
 467                 dep->interval = 1 << (desc->bInterval - 1);
 468         }
 469
 470         return dwc3_send_gadget_ep_cmd(dwc, dep->number,
 471                         DWC3_DEPCMD_SETEPCONFIG, &params);
 472 }
 473
 474 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
 475 {
 476         struct dwc3_gadget_ep_cmd_params params;
 477
 478         memset(&params, 0x00, sizeof(params));
 479
 480         params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
 481
 482         return dwc3_send_gadget_ep_cmd(dwc, dep->number,
 483                         DWC3_DEPCMD_SETTRANSFRESOURCE, &params);
 484 }
 485
 486 /**
 487  * __dwc3_gadget_ep_enable - Initializes a HW endpoint
 488  * @dep: endpoint to be initialized
 489  * @desc: USB Endpoint Descriptor
 490  *
 491  * Caller should take care of locking
 492  */
 493 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
 494                 const struct usb_endpoint_descriptor *desc,
 495                 const struct usb_ss_ep_comp_descriptor *comp_desc,
 496                 bool ignore, bool restore)
 497 {
 498         struct dwc3             *dwc = dep->dwc;
 499         u32                     reg;
 500         int                     ret;
 501
 502         dwc3_trace(trace_dwc3_gadget, "Enabling %s", dep->name);
 503
 504         if (!(dep->flags & DWC3_EP_ENABLED)) {
 505                 ret = dwc3_gadget_start_config(dwc, dep);
 506                 if (ret)
 507                         return ret;
 508         }
 509
 510         ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore,
 511                         restore);
 512         if (ret)
 513                 return ret;
 514
 515         if (!(dep->flags & DWC3_EP_ENABLED)) {
 516                 struct dwc3_trb *trb_st_hw;
 517                 struct dwc3_trb *trb_link;
 518
 519                 dep->endpoint.desc = desc;
 520                 dep->comp_desc = comp_desc;
 521                 dep->type = usb_endpoint_type(desc);
 522                 dep->flags |= DWC3_EP_ENABLED;
 523
 524                 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 525                 reg |= DWC3_DALEPENA_EP(dep->number);
 526                 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 527
 528                 if (!usb_endpoint_xfer_isoc(desc))
 529                         goto out;
 530
 531                 /* Link TRB for ISOC. The HWO bit is never reset */
 532                 trb_st_hw = &dep->trb_pool[0];
 533
 534                 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
 535                 memset(trb_link, 0, sizeof(*trb_link));
 536
 537                 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 538                 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 539                 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
 540                 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
 541         }
 542
 543 out:
 544         switch (usb_endpoint_type(desc)) {
 545         case USB_ENDPOINT_XFER_CONTROL:
 546                 /* don't change name */
 547                 break;
 548         case USB_ENDPOINT_XFER_ISOC:
 549                 strlcat(dep->name, "-isoc", sizeof(dep->name));
 550                 break;
 551         case USB_ENDPOINT_XFER_BULK:
 552                 strlcat(dep->name, "-bulk", sizeof(dep->name));
 553                 break;
 554         case USB_ENDPOINT_XFER_INT:
 555                 strlcat(dep->name, "-int", sizeof(dep->name));
 556                 break;
 557         default:
 558                 dev_err(dwc->dev, "invalid endpoint transfer type\n");
 559         }
 560
 561         return 0;
 562 }
 563
 564 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
 565 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
 566 {
 567         struct dwc3_request             *req;
 568
 569         if (!list_empty(&dep->started_list)) {
 570                 dwc3_stop_active_transfer(dwc, dep->number, true);
 571
 572                 /* - giveback all requests to gadget driver */
 573                 while (!list_empty(&dep->started_list)) {
 574                         req = next_request(&dep->started_list);
 575
 576                         dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 577                 }
 578         }
 579
 580         while (!list_empty(&dep->pending_list)) {
 581                 req = next_request(&dep->pending_list);
 582
 583                 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 584         }
 585 }
 586
 587 /**
 588  * __dwc3_gadget_ep_disable - Disables a HW endpoint
 589  * @dep: the endpoint to disable
 590  *
 591  * This function also removes requests which are currently processed ny the
 592  * hardware and those which are not yet scheduled.
 593  * Caller should take care of locking.
 594  */
 595 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
 596 {
 597         struct dwc3             *dwc = dep->dwc;
 598         u32                     reg;
 599
 600         dwc3_trace(trace_dwc3_gadget, "Disabling %s", dep->name);
 601
 602         dwc3_remove_requests(dwc, dep);
 603
 604         /* make sure HW endpoint isn't stalled */
 605         if (dep->flags & DWC3_EP_STALL)
 606                 __dwc3_gadget_ep_set_halt(dep, 0, false);
 607
 608         reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 609         reg &= ~DWC3_DALEPENA_EP(dep->number);
 610         dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 611
 612         dep->stream_capable = false;
 613         dep->endpoint.desc = NULL;
 614         dep->comp_desc = NULL;
 615         dep->type = 0;
 616         dep->flags = 0;
 617
 618         snprintf(dep->name, sizeof(dep->name), "ep%d%s",
 619                         dep->number >> 1,
 620                         (dep->number & 1) ? "in" : "out");
 621
 622         return 0;
 623 }
 624
 625 /* -------------------------------------------------------------------------- */
 626
 627 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
 628                 const struct usb_endpoint_descriptor *desc)
 629 {
 630         return -EINVAL;
 631 }
 632
 633 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
 634 {
 635         return -EINVAL;
 636 }
 637
 638 /* -------------------------------------------------------------------------- */
 639
 640 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
 641                 const struct usb_endpoint_descriptor *desc)
 642 {
 643         struct dwc3_ep                  *dep;
 644         struct dwc3                     *dwc;
 645         unsigned long                   flags;
 646         int                             ret;
 647
 648         if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
 649                 pr_debug("dwc3: invalid parameters\n");
 650                 return -EINVAL;
 651         }
 652
 653         if (!desc->wMaxPacketSize) {
 654                 pr_debug("dwc3: missing wMaxPacketSize\n");
 655                 return -EINVAL;
 656         }
 657
 658         dep = to_dwc3_ep(ep);
 659         dwc = dep->dwc;
 660
 661         if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
 662                                         "%s is already enabled\n",
 663                                         dep->name))
 664                 return 0;
 665
 666         spin_lock_irqsave(&dwc->lock, flags);
 667         ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false, false);
 668         spin_unlock_irqrestore(&dwc->lock, flags);
 669
 670         return ret;
 671 }
 672
 673 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
 674 {
 675         struct dwc3_ep                  *dep;
 676         struct dwc3                     *dwc;
 677         unsigned long                   flags;
 678         int                             ret;
 679
 680         if (!ep) {
 681                 pr_debug("dwc3: invalid parameters\n");
 682                 return -EINVAL;
 683         }
 684
 685         dep = to_dwc3_ep(ep);
 686         dwc = dep->dwc;
 687
 688         if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
 689                                         "%s is already disabled\n",
 690                                         dep->name))
 691                 return 0;
 692
 693         spin_lock_irqsave(&dwc->lock, flags);
 694         ret = __dwc3_gadget_ep_disable(dep);
 695         spin_unlock_irqrestore(&dwc->lock, flags);
 696
 697         return ret;
 698 }
 699
 700 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
 701         gfp_t gfp_flags)
 702 {
 703         struct dwc3_request             *req;
 704         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 705
 706         req = kzalloc(sizeof(*req), gfp_flags);
 707         if (!req)
 708                 return NULL;
 709
 710         req->epnum      = dep->number;
 711         req->dep        = dep;
 712
 713         trace_dwc3_alloc_request(req);
 714
 715         return &req->request;
 716 }
 717
 718 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
 719                 struct usb_request *request)
 720 {
 721         struct dwc3_request             *req = to_dwc3_request(request);
 722
 723         trace_dwc3_free_request(req);
 724         kfree(req);
 725 }
 726
 727 /**
 728  * dwc3_prepare_one_trb - setup one TRB from one request
 729  * @dep: endpoint for which this request is prepared
 730  * @req: dwc3_request pointer
 731  */
 732 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
 733                 struct dwc3_request *req, dma_addr_t dma,
 734                 unsigned length, unsigned last, unsigned chain, unsigned node)
 735 {
 736         struct dwc3_trb         *trb;
 737
 738         dwc3_trace(trace_dwc3_gadget, "%s: req %p dma %08llx length %d%s%s",
 739                         dep->name, req, (unsigned long long) dma,
 740                         length, last ? " last" : "",
 741                         chain ? " chain" : "");
 742
 743
 744         trb = &dep->trb_pool[dep->trb_enqueue % DWC3_TRB_NUM];
 745
 746         if (!req->trb) {
 747                 dwc3_gadget_move_started_request(req);
 748                 req->trb = trb;
 749                 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
 750                 req->first_trb_index = dep->trb_enqueue % DWC3_TRB_NUM;
 751         }
 752
 753         dep->trb_enqueue++;
 754         /* Skip the LINK-TRB on ISOC */
 755         if (((dep->trb_enqueue % DWC3_TRB_NUM) == DWC3_TRB_NUM - 1) &&
 756                         usb_endpoint_xfer_isoc(dep->endpoint.desc))
 757                 dep->trb_enqueue++;
 758
 759         trb->size = DWC3_TRB_SIZE_LENGTH(length);
 760         trb->bpl = lower_32_bits(dma);
 761         trb->bph = upper_32_bits(dma);
 762
 763         switch (usb_endpoint_type(dep->endpoint.desc)) {
 764         case USB_ENDPOINT_XFER_CONTROL:
 765                 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
 766                 break;
 767
 768         case USB_ENDPOINT_XFER_ISOC:
 769                 if (!node)
 770                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
 771                 else
 772                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
 773
 774                 /* always enable Interrupt on Missed ISOC */
 775                 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
 776                 break;
 777
 778         case USB_ENDPOINT_XFER_BULK:
 779         case USB_ENDPOINT_XFER_INT:
 780                 trb->ctrl = DWC3_TRBCTL_NORMAL;
 781                 break;
 782         default:
 783                 /*
 784                  * This is only possible with faulty memory because we
 785                  * checked it already :)
 786                  */
 787                 BUG();
 788         }
 789
 790         /* always enable Continue on Short Packet */
 791         trb->ctrl |= DWC3_TRB_CTRL_CSP;
 792
 793         if (!req->request.no_interrupt)
 794                 trb->ctrl |= DWC3_TRB_CTRL_IOC | DWC3_TRB_CTRL_ISP_IMI;
 795
 796         if (last)
 797                 trb->ctrl |= DWC3_TRB_CTRL_LST;
 798
 799         if (chain)
 800                 trb->ctrl |= DWC3_TRB_CTRL_CHN;
 801
 802         if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
 803                 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
 804
 805         trb->ctrl |= DWC3_TRB_CTRL_HWO;
 806
 807         trace_dwc3_prepare_trb(dep, trb);
 808 }
 809
 810 /*
 811  * dwc3_prepare_trbs - setup TRBs from requests
 812  * @dep: endpoint for which requests are being prepared
 813  * @starting: true if the endpoint is idle and no requests are queued.
 814  *
 815  * The function goes through the requests list and sets up TRBs for the
 816  * transfers. The function returns once there are no more TRBs available or
 817  * it runs out of requests.
 818  */
 819 static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
 820 {
 821         struct dwc3_request     *req, *n;
 822         u32                     trbs_left;
 823         u32                     max;
 824         unsigned int            last_one = 0;
 825
 826         BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
 827
 828         /* the first request must not be queued */
 829         trbs_left = (dep->trb_dequeue - dep->trb_enqueue) % DWC3_TRB_NUM;
 830
 831         /* Can't wrap around on a non-isoc EP since there's no link TRB */
 832         if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
 833                 max = DWC3_TRB_NUM - (dep->trb_enqueue % DWC3_TRB_NUM);
 834                 if (trbs_left > max)
 835                         trbs_left = max;
 836         }
 837
 838         /*
 839          * If busy & slot are equal than it is either full or empty. If we are
 840          * starting to process requests then we are empty. Otherwise we are
 841          * full and don't do anything
 842          */
 843         if (!trbs_left) {
 844                 if (!starting)
 845                         return;
 846                 trbs_left = DWC3_TRB_NUM;
 847                 /*
 848                  * In case we start from scratch, we queue the ISOC requests
 849                  * starting from slot 1. This is done because we use ring
 850                  * buffer and have no LST bit to stop us. Instead, we place
 851                  * IOC bit every TRB_NUM/4. We try to avoid having an interrupt
 852                  * after the first request so we start at slot 1 and have
 853                  * 7 requests proceed before we hit the first IOC.
 854                  * Other transfer types don't use the ring buffer and are
 855                  * processed from the first TRB until the last one. Since we
 856                  * don't wrap around we have to start at the beginning.
 857                  */
 858                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
 859                         dep->trb_dequeue = 1;
 860                         dep->trb_enqueue = 1;
 861                 } else {
 862                         dep->trb_dequeue = 0;
 863                         dep->trb_enqueue = 0;
 864                 }
 865         }
 866
 867         /* The last TRB is a link TRB, not used for xfer */
 868         if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc))
 869                 return;
 870
 871         list_for_each_entry_safe(req, n, &dep->pending_list, list) {
 872                 unsigned        length;
 873                 dma_addr_t      dma;
 874                 last_one = false;
 875
 876                 if (req->request.num_mapped_sgs > 0) {
 877                         struct usb_request *request = &req->request;
 878                         struct scatterlist *sg = request->sg;
 879                         struct scatterlist *s;
 880                         int             i;
 881
 882                         for_each_sg(sg, s, request->num_mapped_sgs, i) {
 883                                 unsigned chain = true;
 884
 885                                 length = sg_dma_len(s);
 886                                 dma = sg_dma_address(s);
 887
 888                                 if (i == (request->num_mapped_sgs - 1) ||
 889                                                 sg_is_last(s)) {
 890                                         if (list_empty(&dep->pending_list))
 891                                                 last_one = true;
 892                                         chain = false;
 893                                 }
 894
 895                                 trbs_left--;
 896                                 if (!trbs_left)
 897                                         last_one = true;
 898
 899                                 if (last_one)
 900                                         chain = false;
 901
 902                                 dwc3_prepare_one_trb(dep, req, dma, length,
 903                                                 last_one, chain, i);
 904
 905                                 if (last_one)
 906                                         break;
 907                         }
 908
 909                         if (last_one)
 910                                 break;
 911                 } else {
 912                         dma = req->request.dma;
 913                         length = req->request.length;
 914                         trbs_left--;
 915
 916                         if (!trbs_left)
 917                                 last_one = 1;
 918
 919                         /* Is this the last request? */
 920                         if (list_is_last(&req->list, &dep->pending_list))
 921                                 last_one = 1;
 922
 923                         dwc3_prepare_one_trb(dep, req, dma, length,
 924                                         last_one, false, 0);
 925
 926                         if (last_one)
 927                                 break;
 928                 }
 929         }
 930 }
 931
 932 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
 933                 int start_new)
 934 {
 935         struct dwc3_gadget_ep_cmd_params params;
 936         struct dwc3_request             *req;
 937         struct dwc3                     *dwc = dep->dwc;
 938         int                             ret;
 939         u32                             cmd;
 940
 941         if (start_new && (dep->flags & DWC3_EP_BUSY)) {
 942                 dwc3_trace(trace_dwc3_gadget, "%s: endpoint busy", dep->name);
 943                 return -EBUSY;
 944         }
 945
 946         /*
 947          * If we are getting here after a short-out-packet we don't enqueue any
 948          * new requests as we try to set the IOC bit only on the last request.
 949          */
 950         if (start_new) {
 951                 if (list_empty(&dep->started_list))
 952                         dwc3_prepare_trbs(dep, start_new);
 953
 954                 /* req points to the first request which will be sent */
 955                 req = next_request(&dep->started_list);
 956         } else {
 957                 dwc3_prepare_trbs(dep, start_new);
 958
 959                 /*
 960                  * req points to the first request where HWO changed from 0 to 1
 961                  */
 962                 req = next_request(&dep->started_list);
 963         }
 964         if (!req) {
 965                 dep->flags |= DWC3_EP_PENDING_REQUEST;
 966                 return 0;
 967         }
 968
 969         memset(&params, 0, sizeof(params));
 970
 971         if (start_new) {
 972                 params.param0 = upper_32_bits(req->trb_dma);
 973                 params.param1 = lower_32_bits(req->trb_dma);
 974                 cmd = DWC3_DEPCMD_STARTTRANSFER;
 975         } else {
 976                 cmd = DWC3_DEPCMD_UPDATETRANSFER;
 977         }
 978
 979         cmd |= DWC3_DEPCMD_PARAM(cmd_param);
 980         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
 981         if (ret < 0) {
 982                 /*
 983                  * FIXME we need to iterate over the list of requests
 984                  * here and stop, unmap, free and del each of the linked
 985                  * requests instead of what we do now.
 986                  */
 987                 usb_gadget_unmap_request(&dwc->gadget, &req->request,
 988                                 req->direction);
 989                 list_del(&req->list);
 990                 return ret;
 991         }
 992
 993         dep->flags |= DWC3_EP_BUSY;
 994
 995         if (start_new) {
 996                 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
 997                                 dep->number);
 998                 WARN_ON_ONCE(!dep->resource_index);
 999         }
1000
1001         return 0;
1002 }
1003
1004 static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1005                 struct dwc3_ep *dep, u32 cur_uf)
1006 {
1007         u32 uf;
1008
1009         if (list_empty(&dep->pending_list)) {
1010                 dwc3_trace(trace_dwc3_gadget,
1011                                 "ISOC ep %s run out for requests",
1012                                 dep->name);
1013                 dep->flags |= DWC3_EP_PENDING_REQUEST;
1014                 return;
1015         }
1016
1017         /* 4 micro frames in the future */
1018         uf = cur_uf + dep->interval * 4;
1019
1020         __dwc3_gadget_kick_transfer(dep, uf, 1);
1021 }
1022
1023 static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1024                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1025 {
1026         u32 cur_uf, mask;
1027
1028         mask = ~(dep->interval - 1);
1029         cur_uf = event->parameters & mask;
1030
1031         __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1032 }
1033
1034 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1035 {
1036         struct dwc3             *dwc = dep->dwc;
1037         int                     ret;
1038
1039         if (!dep->endpoint.desc) {
1040                 dwc3_trace(trace_dwc3_gadget,
1041                                 "trying to queue request %p to disabled %s\n",
1042                                 &req->request, dep->endpoint.name);
1043                 return -ESHUTDOWN;
1044         }
1045
1046         if (WARN(req->dep != dep, "request %p belongs to '%s'\n",
1047                                 &req->request, req->dep->name)) {
1048                 dwc3_trace(trace_dwc3_gadget, "request %p belongs to '%s'\n",
1049                                 &req->request, req->dep->name);
1050                 return -EINVAL;
1051         }
1052
1053         req->request.actual     = 0;
1054         req->request.status     = -EINPROGRESS;
1055         req->direction          = dep->direction;
1056         req->epnum              = dep->number;
1057
1058         trace_dwc3_ep_queue(req);
1059
1060         /*
1061          * We only add to our list of requests now and
1062          * start consuming the list once we get XferNotReady
1063          * IRQ.
1064          *
1065          * That way, we avoid doing anything that we don't need
1066          * to do now and defer it until the point we receive a
1067          * particular token from the Host side.
1068          *
1069          * This will also avoid Host cancelling URBs due to too
1070          * many NAKs.
1071          */
1072         ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1073                         dep->direction);
1074         if (ret)
1075                 return ret;
1076
1077         list_add_tail(&req->list, &dep->pending_list);
1078
1079         /*
1080          * If there are no pending requests and the endpoint isn't already
1081          * busy, we will just start the request straight away.
1082          *
1083          * This will save one IRQ (XFER_NOT_READY) and possibly make it a
1084          * little bit faster.
1085          */
1086         if (!usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1087                         !usb_endpoint_xfer_int(dep->endpoint.desc) &&
1088                         !(dep->flags & DWC3_EP_BUSY)) {
1089                 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1090                 goto out;
1091         }
1092
1093         /*
1094          * There are a few special cases:
1095          *
1096          * 1. XferNotReady with empty list of requests. We need to kick the
1097          *    transfer here in that situation, otherwise we will be NAKing
1098          *    forever. If we get XferNotReady before gadget driver has a
1099          *    chance to queue a request, we will ACK the IRQ but won't be
1100          *    able to receive the data until the next request is queued.
1101          *    The following code is handling exactly that.
1102          *
1103          */
1104         if (dep->flags & DWC3_EP_PENDING_REQUEST) {
1105                 /*
1106                  * If xfernotready is already elapsed and it is a case
1107                  * of isoc transfer, then issue END TRANSFER, so that
1108                  * you can receive xfernotready again and can have
1109                  * notion of current microframe.
1110                  */
1111                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1112                         if (list_empty(&dep->started_list)) {
1113                                 dwc3_stop_active_transfer(dwc, dep->number, true);
1114                                 dep->flags = DWC3_EP_ENABLED;
1115                         }
1116                         return 0;
1117                 }
1118
1119                 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1120                 if (!ret)
1121                         dep->flags &= ~DWC3_EP_PENDING_REQUEST;
1122
1123                 goto out;
1124         }
1125
1126         /*
1127          * 2. XferInProgress on Isoc EP with an active transfer. We need to
1128          *    kick the transfer here after queuing a request, otherwise the
1129          *    core may not see the modified TRB(s).
1130          */
1131         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1132                         (dep->flags & DWC3_EP_BUSY) &&
1133                         !(dep->flags & DWC3_EP_MISSED_ISOC)) {
1134                 WARN_ON_ONCE(!dep->resource_index);
1135                 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index,
1136                                 false);
1137                 goto out;
1138         }
1139
1140         /*
1141          * 4. Stream Capable Bulk Endpoints. We need to start the transfer
1142          * right away, otherwise host will not know we have streams to be
1143          * handled.
1144          */
1145         if (dep->stream_capable)
1146                 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1147
1148 out:
1149         if (ret && ret != -EBUSY)
1150                 dwc3_trace(trace_dwc3_gadget,
1151                                 "%s: failed to kick transfers\n",
1152                                 dep->name);
1153         if (ret == -EBUSY)
1154                 ret = 0;
1155
1156         return ret;
1157 }
1158
1159 static void __dwc3_gadget_ep_zlp_complete(struct usb_ep *ep,
1160                 struct usb_request *request)
1161 {
1162         dwc3_gadget_ep_free_request(ep, request);
1163 }
1164
1165 static int __dwc3_gadget_ep_queue_zlp(struct dwc3 *dwc, struct dwc3_ep *dep)
1166 {
1167         struct dwc3_request             *req;
1168         struct usb_request              *request;
1169         struct usb_ep                   *ep = &dep->endpoint;
1170
1171         dwc3_trace(trace_dwc3_gadget, "queueing ZLP\n");
1172         request = dwc3_gadget_ep_alloc_request(ep, GFP_ATOMIC);
1173         if (!request)
1174                 return -ENOMEM;
1175
1176         request->length = 0;
1177         request->buf = dwc->zlp_buf;
1178         request->complete = __dwc3_gadget_ep_zlp_complete;
1179
1180         req = to_dwc3_request(request);
1181
1182         return __dwc3_gadget_ep_queue(dep, req);
1183 }
1184
1185 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1186         gfp_t gfp_flags)
1187 {
1188         struct dwc3_request             *req = to_dwc3_request(request);
1189         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1190         struct dwc3                     *dwc = dep->dwc;
1191
1192         unsigned long                   flags;
1193
1194         int                             ret;
1195
1196         spin_lock_irqsave(&dwc->lock, flags);
1197         ret = __dwc3_gadget_ep_queue(dep, req);
1198
1199         /*
1200          * Okay, here's the thing, if gadget driver has requested for a ZLP by
1201          * setting request->zero, instead of doing magic, we will just queue an
1202          * extra usb_request ourselves so that it gets handled the same way as
1203          * any other request.
1204          */
1205         if (ret == 0 && request->zero && request->length &&
1206             (request->length % ep->maxpacket == 0))
1207                 ret = __dwc3_gadget_ep_queue_zlp(dwc, dep);
1208
1209         spin_unlock_irqrestore(&dwc->lock, flags);
1210
1211         return ret;
1212 }
1213
1214 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1215                 struct usb_request *request)
1216 {
1217         struct dwc3_request             *req = to_dwc3_request(request);
1218         struct dwc3_request             *r = NULL;
1219
1220         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1221         struct dwc3                     *dwc = dep->dwc;
1222
1223         unsigned long                   flags;
1224         int                             ret = 0;
1225
1226         trace_dwc3_ep_dequeue(req);
1227
1228         spin_lock_irqsave(&dwc->lock, flags);
1229
1230         list_for_each_entry(r, &dep->pending_list, list) {
1231                 if (r == req)
1232                         break;
1233         }
1234
1235         if (r != req) {
1236                 list_for_each_entry(r, &dep->started_list, list) {
1237                         if (r == req)
1238                                 break;
1239                 }
1240                 if (r == req) {
1241                         /* wait until it is processed */
1242                         dwc3_stop_active_transfer(dwc, dep->number, true);
1243                         goto out1;
1244                 }
1245                 dev_err(dwc->dev, "request %p was not queued to %s\n",
1246                                 request, ep->name);
1247                 ret = -EINVAL;
1248                 goto out0;
1249         }
1250
1251 out1:
1252         /* giveback the request */
1253         dwc3_gadget_giveback(dep, req, -ECONNRESET);
1254
1255 out0:
1256         spin_unlock_irqrestore(&dwc->lock, flags);
1257
1258         return ret;
1259 }
1260
1261 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1262 {
1263         struct dwc3_gadget_ep_cmd_params        params;
1264         struct dwc3                             *dwc = dep->dwc;
1265         int                                     ret;
1266
1267         if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1268                 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1269                 return -EINVAL;
1270         }
1271
1272         memset(&params, 0x00, sizeof(params));
1273
1274         if (value) {
1275                 if (!protocol && ((dep->direction && dep->flags & DWC3_EP_BUSY) ||
1276                                 (!list_empty(&dep->started_list) ||
1277                                  !list_empty(&dep->pending_list)))) {
1278                         dwc3_trace(trace_dwc3_gadget,
1279                                         "%s: pending request, cannot halt\n",
1280                                         dep->name);
1281                         return -EAGAIN;
1282                 }
1283
1284                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1285                         DWC3_DEPCMD_SETSTALL, &params);
1286                 if (ret)
1287                         dev_err(dwc->dev, "failed to set STALL on %s\n",
1288                                         dep->name);
1289                 else
1290                         dep->flags |= DWC3_EP_STALL;
1291         } else {
1292                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1293                         DWC3_DEPCMD_CLEARSTALL, &params);
1294                 if (ret)
1295                         dev_err(dwc->dev, "failed to clear STALL on %s\n",
1296                                         dep->name);
1297                 else
1298                         dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1299         }
1300
1301         return ret;
1302 }
1303
1304 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1305 {
1306         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1307         struct dwc3                     *dwc = dep->dwc;
1308
1309         unsigned long                   flags;
1310
1311         int                             ret;
1312
1313         spin_lock_irqsave(&dwc->lock, flags);
1314         ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1315         spin_unlock_irqrestore(&dwc->lock, flags);
1316
1317         return ret;
1318 }
1319
1320 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1321 {
1322         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1323         struct dwc3                     *dwc = dep->dwc;
1324         unsigned long                   flags;
1325         int                             ret;
1326
1327         spin_lock_irqsave(&dwc->lock, flags);
1328         dep->flags |= DWC3_EP_WEDGE;
1329
1330         if (dep->number == 0 || dep->number == 1)
1331                 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1332         else
1333                 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1334         spin_unlock_irqrestore(&dwc->lock, flags);
1335
1336         return ret;
1337 }
1338
1339 /* -------------------------------------------------------------------------- */
1340
1341 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1342         .bLength        = USB_DT_ENDPOINT_SIZE,
1343         .bDescriptorType = USB_DT_ENDPOINT,
1344         .bmAttributes   = USB_ENDPOINT_XFER_CONTROL,
1345 };
1346
1347 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1348         .enable         = dwc3_gadget_ep0_enable,
1349         .disable        = dwc3_gadget_ep0_disable,
1350         .alloc_request  = dwc3_gadget_ep_alloc_request,
1351         .free_request   = dwc3_gadget_ep_free_request,
1352         .queue          = dwc3_gadget_ep0_queue,
1353         .dequeue        = dwc3_gadget_ep_dequeue,
1354         .set_halt       = dwc3_gadget_ep0_set_halt,
1355         .set_wedge      = dwc3_gadget_ep_set_wedge,
1356 };
1357
1358 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1359         .enable         = dwc3_gadget_ep_enable,
1360         .disable        = dwc3_gadget_ep_disable,
1361         .alloc_request  = dwc3_gadget_ep_alloc_request,
1362         .free_request   = dwc3_gadget_ep_free_request,
1363         .queue          = dwc3_gadget_ep_queue,
1364         .dequeue        = dwc3_gadget_ep_dequeue,
1365         .set_halt       = dwc3_gadget_ep_set_halt,
1366         .set_wedge      = dwc3_gadget_ep_set_wedge,
1367 };
1368
1369 /* -------------------------------------------------------------------------- */
1370
1371 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1372 {
1373         struct dwc3             *dwc = gadget_to_dwc(g);
1374         u32                     reg;
1375
1376         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1377         return DWC3_DSTS_SOFFN(reg);
1378 }
1379
1380 static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
1381 {
1382         unsigned long           timeout;
1383
1384         int                     ret;
1385         u32                     reg;
1386
1387         u8                      link_state;
1388         u8                      speed;
1389
1390         /*
1391          * According to the Databook Remote wakeup request should
1392          * be issued only when the device is in early suspend state.
1393          *
1394          * We can check that via USB Link State bits in DSTS register.
1395          */
1396         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1397
1398         speed = reg & DWC3_DSTS_CONNECTSPD;
1399         if ((speed == DWC3_DSTS_SUPERSPEED) ||
1400             (speed == DWC3_DSTS_SUPERSPEED_PLUS)) {
1401                 dwc3_trace(trace_dwc3_gadget, "no wakeup on SuperSpeed\n");
1402                 return -EINVAL;
1403         }
1404
1405         link_state = DWC3_DSTS_USBLNKST(reg);
1406
1407         switch (link_state) {
1408         case DWC3_LINK_STATE_RX_DET:    /* in HS, means Early Suspend */
1409         case DWC3_LINK_STATE_U3:        /* in HS, means SUSPEND */
1410                 break;
1411         default:
1412                 dwc3_trace(trace_dwc3_gadget,
1413                                 "can't wakeup from '%s'\n",
1414                                 dwc3_gadget_link_string(link_state));
1415                 return -EINVAL;
1416         }
1417
1418         ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1419         if (ret < 0) {
1420                 dev_err(dwc->dev, "failed to put link in Recovery\n");
1421                 return ret;
1422         }
1423
1424         /* Recent versions do this automatically */
1425         if (dwc->revision < DWC3_REVISION_194A) {
1426                 /* write zeroes to Link Change Request */
1427                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1428                 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1429                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1430         }
1431
1432         /* poll until Link State changes to ON */
1433         timeout = jiffies + msecs_to_jiffies(100);
1434
1435         while (!time_after(jiffies, timeout)) {
1436                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1437
1438                 /* in HS, means ON */
1439                 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1440                         break;
1441         }
1442
1443         if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1444                 dev_err(dwc->dev, "failed to send remote wakeup\n");
1445                 return -EINVAL;
1446         }
1447
1448         return 0;
1449 }
1450
1451 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1452 {
1453         struct dwc3             *dwc = gadget_to_dwc(g);
1454         unsigned long           flags;
1455         int                     ret;
1456
1457         spin_lock_irqsave(&dwc->lock, flags);
1458         ret = __dwc3_gadget_wakeup(dwc);
1459         spin_unlock_irqrestore(&dwc->lock, flags);
1460
1461         return ret;
1462 }
1463
1464 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1465                 int is_selfpowered)
1466 {
1467         struct dwc3             *dwc = gadget_to_dwc(g);
1468         unsigned long           flags;
1469
1470         spin_lock_irqsave(&dwc->lock, flags);
1471         g->is_selfpowered = !!is_selfpowered;
1472         spin_unlock_irqrestore(&dwc->lock, flags);
1473
1474         return 0;
1475 }
1476
1477 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1478 {
1479         u32                     reg;
1480         u32                     timeout = 500;
1481
1482         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1483         if (is_on) {
1484                 if (dwc->revision <= DWC3_REVISION_187A) {
1485                         reg &= ~DWC3_DCTL_TRGTULST_MASK;
1486                         reg |= DWC3_DCTL_TRGTULST_RX_DET;
1487                 }
1488
1489                 if (dwc->revision >= DWC3_REVISION_194A)
1490                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
1491                 reg |= DWC3_DCTL_RUN_STOP;
1492
1493                 if (dwc->has_hibernation)
1494                         reg |= DWC3_DCTL_KEEP_CONNECT;
1495
1496                 dwc->pullups_connected = true;
1497         } else {
1498                 reg &= ~DWC3_DCTL_RUN_STOP;
1499
1500                 if (dwc->has_hibernation && !suspend)
1501                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
1502
1503                 dwc->pullups_connected = false;
1504         }
1505
1506         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1507
1508         do {
1509                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1510                 if (is_on) {
1511                         if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1512                                 break;
1513                 } else {
1514                         if (reg & DWC3_DSTS_DEVCTRLHLT)
1515                                 break;
1516                 }
1517                 timeout--;
1518                 if (!timeout)
1519                         return -ETIMEDOUT;
1520                 udelay(1);
1521         } while (1);
1522
1523         dwc3_trace(trace_dwc3_gadget, "gadget %s data soft-%s",
1524                         dwc->gadget_driver
1525                         ? dwc->gadget_driver->function : "no-function",
1526                         is_on ? "connect" : "disconnect");
1527
1528         return 0;
1529 }
1530
1531 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1532 {
1533         struct dwc3             *dwc = gadget_to_dwc(g);
1534         unsigned long           flags;
1535         int                     ret;
1536
1537         is_on = !!is_on;
1538
1539         spin_lock_irqsave(&dwc->lock, flags);
1540         ret = dwc3_gadget_run_stop(dwc, is_on, false);
1541         spin_unlock_irqrestore(&dwc->lock, flags);
1542
1543         return ret;
1544 }
1545
1546 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1547 {
1548         u32                     reg;
1549
1550         /* Enable all but Start and End of Frame IRQs */
1551         reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1552                         DWC3_DEVTEN_EVNTOVERFLOWEN |
1553                         DWC3_DEVTEN_CMDCMPLTEN |
1554                         DWC3_DEVTEN_ERRTICERREN |
1555                         DWC3_DEVTEN_WKUPEVTEN |
1556                         DWC3_DEVTEN_ULSTCNGEN |
1557                         DWC3_DEVTEN_CONNECTDONEEN |
1558                         DWC3_DEVTEN_USBRSTEN |
1559                         DWC3_DEVTEN_DISCONNEVTEN);
1560
1561         dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1562 }
1563
1564 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1565 {
1566         /* mask all interrupts */
1567         dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1568 }
1569
1570 static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
1571 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
1572
1573 static int dwc3_gadget_start(struct usb_gadget *g,
1574                 struct usb_gadget_driver *driver)
1575 {
1576         struct dwc3             *dwc = gadget_to_dwc(g);
1577         struct dwc3_ep          *dep;
1578         unsigned long           flags;
1579         int                     ret = 0;
1580         int                     irq;
1581         u32                     reg;
1582
1583         irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1584         ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
1585                         IRQF_SHARED, "dwc3", dwc->ev_buf);
1586         if (ret) {
1587                 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1588                                 irq, ret);
1589                 goto err0;
1590         }
1591
1592         spin_lock_irqsave(&dwc->lock, flags);
1593
1594         if (dwc->gadget_driver) {
1595                 dev_err(dwc->dev, "%s is already bound to %s\n",
1596                                 dwc->gadget.name,
1597                                 dwc->gadget_driver->driver.name);
1598                 ret = -EBUSY;
1599                 goto err1;
1600         }
1601
1602         dwc->gadget_driver      = driver;
1603
1604         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1605         reg &= ~(DWC3_DCFG_SPEED_MASK);
1606
1607         /**
1608          * WORKAROUND: DWC3 revision < 2.20a have an issue
1609          * which would cause metastability state on Run/Stop
1610          * bit if we try to force the IP to USB2-only mode.
1611          *
1612          * Because of that, we cannot configure the IP to any
1613          * speed other than the SuperSpeed
1614          *
1615          * Refers to:
1616          *
1617          * STAR#9000525659: Clock Domain Crossing on DCTL in
1618          * USB 2.0 Mode
1619          */
1620         if (dwc->revision < DWC3_REVISION_220A) {
1621                 reg |= DWC3_DCFG_SUPERSPEED;
1622         } else {
1623                 switch (dwc->maximum_speed) {
1624                 case USB_SPEED_LOW:
1625                         reg |= DWC3_DSTS_LOWSPEED;
1626                         break;
1627                 case USB_SPEED_FULL:
1628                         reg |= DWC3_DSTS_FULLSPEED1;
1629                         break;
1630                 case USB_SPEED_HIGH:
1631                         reg |= DWC3_DSTS_HIGHSPEED;
1632                         break;
1633                 case USB_SPEED_SUPER_PLUS:
1634                         reg |= DWC3_DSTS_SUPERSPEED_PLUS;
1635                         break;
1636                 default:
1637                         dev_err(dwc->dev, "invalid dwc->maximum_speed (%d)\n",
1638                                 dwc->maximum_speed);
1639                         /* fall through */
1640                 case USB_SPEED_SUPER:
1641                         reg |= DWC3_DCFG_SUPERSPEED;
1642                         break;
1643                 }
1644         }
1645         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1646
1647         /* Start with SuperSpeed Default */
1648         dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1649
1650         dep = dwc->eps[0];
1651         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1652                         false);
1653         if (ret) {
1654                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1655                 goto err2;
1656         }
1657
1658         dep = dwc->eps[1];
1659         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1660                         false);
1661         if (ret) {
1662                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1663                 goto err3;
1664         }
1665
1666         /* begin to receive SETUP packets */
1667         dwc->ep0state = EP0_SETUP_PHASE;
1668         dwc3_ep0_out_start(dwc);
1669
1670         dwc3_gadget_enable_irq(dwc);
1671
1672         spin_unlock_irqrestore(&dwc->lock, flags);
1673
1674         return 0;
1675
1676 err3:
1677         __dwc3_gadget_ep_disable(dwc->eps[0]);
1678
1679 err2:
1680         dwc->gadget_driver = NULL;
1681
1682 err1:
1683         spin_unlock_irqrestore(&dwc->lock, flags);
1684
1685         free_irq(irq, dwc->ev_buf);
1686
1687 err0:
1688         return ret;
1689 }
1690
1691 static int dwc3_gadget_stop(struct usb_gadget *g)
1692 {
1693         struct dwc3             *dwc = gadget_to_dwc(g);
1694         unsigned long           flags;
1695         int                     irq;
1696
1697         spin_lock_irqsave(&dwc->lock, flags);
1698
1699         dwc3_gadget_disable_irq(dwc);
1700         __dwc3_gadget_ep_disable(dwc->eps[0]);
1701         __dwc3_gadget_ep_disable(dwc->eps[1]);
1702
1703         dwc->gadget_driver      = NULL;
1704
1705         spin_unlock_irqrestore(&dwc->lock, flags);
1706
1707         irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1708         free_irq(irq, dwc->ev_buf);
1709
1710         return 0;
1711 }
1712
1713 static const struct usb_gadget_ops dwc3_gadget_ops = {
1714         .get_frame              = dwc3_gadget_get_frame,
1715         .wakeup                 = dwc3_gadget_wakeup,
1716         .set_selfpowered        = dwc3_gadget_set_selfpowered,
1717         .pullup                 = dwc3_gadget_pullup,
1718         .udc_start              = dwc3_gadget_start,
1719         .udc_stop               = dwc3_gadget_stop,
1720 };
1721
1722 /* -------------------------------------------------------------------------- */
1723
1724 static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
1725                 u8 num, u32 direction)
1726 {
1727         struct dwc3_ep                  *dep;
1728         u8                              i;
1729
1730         for (i = 0; i < num; i++) {
1731                 u8 epnum = (i << 1) | (!!direction);
1732
1733                 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1734                 if (!dep)
1735                         return -ENOMEM;
1736
1737                 dep->dwc = dwc;
1738                 dep->number = epnum;
1739                 dep->direction = !!direction;
1740                 dwc->eps[epnum] = dep;
1741
1742                 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1743                                 (epnum & 1) ? "in" : "out");
1744
1745                 dep->endpoint.name = dep->name;
1746
1747                 dwc3_trace(trace_dwc3_gadget, "initializing %s", dep->name);
1748
1749                 if (epnum == 0 || epnum == 1) {
1750                         usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
1751                         dep->endpoint.maxburst = 1;
1752                         dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1753                         if (!epnum)
1754                                 dwc->gadget.ep0 = &dep->endpoint;
1755                 } else {
1756                         int             ret;
1757
1758                         usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
1759                         dep->endpoint.max_streams = 15;
1760                         dep->endpoint.ops = &dwc3_gadget_ep_ops;
1761                         list_add_tail(&dep->endpoint.ep_list,
1762                                         &dwc->gadget.ep_list);
1763
1764                         ret = dwc3_alloc_trb_pool(dep);
1765                         if (ret)
1766                                 return ret;
1767                 }
1768
1769                 if (epnum == 0 || epnum == 1) {
1770                         dep->endpoint.caps.type_control = true;
1771                 } else {
1772                         dep->endpoint.caps.type_iso = true;
1773                         dep->endpoint.caps.type_bulk = true;
1774                         dep->endpoint.caps.type_int = true;
1775                 }
1776
1777                 dep->endpoint.caps.dir_in = !!direction;
1778                 dep->endpoint.caps.dir_out = !direction;
1779
1780                 INIT_LIST_HEAD(&dep->pending_list);
1781                 INIT_LIST_HEAD(&dep->started_list);
1782         }
1783
1784         return 0;
1785 }
1786
1787 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1788 {
1789         int                             ret;
1790
1791         INIT_LIST_HEAD(&dwc->gadget.ep_list);
1792
1793         ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0);
1794         if (ret < 0) {
1795                 dwc3_trace(trace_dwc3_gadget,
1796                                 "failed to allocate OUT endpoints");
1797                 return ret;
1798         }
1799
1800         ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1);
1801         if (ret < 0) {
1802                 dwc3_trace(trace_dwc3_gadget,
1803                                 "failed to allocate IN endpoints");
1804                 return ret;
1805         }
1806
1807         return 0;
1808 }
1809
1810 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1811 {
1812         struct dwc3_ep                  *dep;
1813         u8                              epnum;
1814
1815         for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1816                 dep = dwc->eps[epnum];
1817                 if (!dep)
1818                         continue;
1819                 /*
1820                  * Physical endpoints 0 and 1 are special; they form the
1821                  * bi-directional USB endpoint 0.
1822                  *
1823                  * For those two physical endpoints, we don't allocate a TRB
1824                  * pool nor do we add them the endpoints list. Due to that, we
1825                  * shouldn't do these two operations otherwise we would end up
1826                  * with all sorts of bugs when removing dwc3.ko.
1827                  */
1828                 if (epnum != 0 && epnum != 1) {
1829                         dwc3_free_trb_pool(dep);
1830                         list_del(&dep->endpoint.ep_list);
1831                 }
1832
1833                 kfree(dep);
1834         }
1835 }
1836
1837 /* -------------------------------------------------------------------------- */
1838
1839 static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
1840                 struct dwc3_request *req, struct dwc3_trb *trb,
1841                 const struct dwc3_event_depevt *event, int status)
1842 {
1843         unsigned int            count;
1844         unsigned int            s_pkt = 0;
1845         unsigned int            trb_status;
1846
1847         trace_dwc3_complete_trb(dep, trb);
1848
1849         if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1850                 /*
1851                  * We continue despite the error. There is not much we
1852                  * can do. If we don't clean it up we loop forever. If
1853                  * we skip the TRB then it gets overwritten after a
1854                  * while since we use them in a ring buffer. A BUG()
1855                  * would help. Lets hope that if this occurs, someone
1856                  * fixes the root cause instead of looking away :)
1857                  */
1858                 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1859                                 dep->name, trb);
1860         count = trb->size & DWC3_TRB_SIZE_MASK;
1861
1862         if (dep->direction) {
1863                 if (count) {
1864                         trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
1865                         if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
1866                                 dwc3_trace(trace_dwc3_gadget,
1867                                                 "%s: incomplete IN transfer\n",
1868                                                 dep->name);
1869                                 /*
1870                                  * If missed isoc occurred and there is
1871                                  * no request queued then issue END
1872                                  * TRANSFER, so that core generates
1873                                  * next xfernotready and we will issue
1874                                  * a fresh START TRANSFER.
1875                                  * If there are still queued request
1876                                  * then wait, do not issue either END
1877                                  * or UPDATE TRANSFER, just attach next
1878                                  * request in pending_list during
1879                                  * giveback.If any future queued request
1880                                  * is successfully transferred then we
1881                                  * will issue UPDATE TRANSFER for all
1882                                  * request in the pending_list.
1883                                  */
1884                                 dep->flags |= DWC3_EP_MISSED_ISOC;
1885                         } else {
1886                                 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1887                                                 dep->name);
1888                                 status = -ECONNRESET;
1889                         }
1890                 } else {
1891                         dep->flags &= ~DWC3_EP_MISSED_ISOC;
1892                 }
1893         } else {
1894                 if (count && (event->status & DEPEVT_STATUS_SHORT))
1895                         s_pkt = 1;
1896         }
1897
1898         /*
1899          * We assume here we will always receive the entire data block
1900          * which we should receive. Meaning, if we program RX to
1901          * receive 4K but we receive only 2K, we assume that's all we
1902          * should receive and we simply bounce the request back to the
1903          * gadget driver for further processing.
1904          */
1905         req->request.actual += req->request.length - count;
1906         if (s_pkt)
1907                 return 1;
1908         if ((event->status & DEPEVT_STATUS_LST) &&
1909                         (trb->ctrl & (DWC3_TRB_CTRL_LST |
1910                                 DWC3_TRB_CTRL_HWO)))
1911                 return 1;
1912         if ((event->status & DEPEVT_STATUS_IOC) &&
1913                         (trb->ctrl & DWC3_TRB_CTRL_IOC))
1914                 return 1;
1915         return 0;
1916 }
1917
1918 static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1919                 const struct dwc3_event_depevt *event, int status)
1920 {
1921         struct dwc3_request     *req;
1922         struct dwc3_trb         *trb;
1923         unsigned int            slot;
1924         unsigned int            i;
1925         int                     ret;
1926
1927         do {
1928                 req = next_request(&dep->started_list);
1929                 if (WARN_ON_ONCE(!req))
1930                         return 1;
1931
1932                 i = 0;
1933                 do {
1934                         slot = req->first_trb_index + i;
1935                         if ((slot == DWC3_TRB_NUM - 1) &&
1936                                 usb_endpoint_xfer_isoc(dep->endpoint.desc))
1937                                 slot++;
1938                         slot %= DWC3_TRB_NUM;
1939                         trb = &dep->trb_pool[slot];
1940
1941                         ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
1942                                         event, status);
1943                         if (ret)
1944                                 break;
1945                 } while (++i < req->request.num_mapped_sgs);
1946
1947                 dwc3_gadget_giveback(dep, req, status);
1948
1949                 if (ret)
1950                         break;
1951         } while (1);
1952
1953         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1954                         list_empty(&dep->started_list)) {
1955                 if (list_empty(&dep->pending_list)) {
1956                         /*
1957                          * If there is no entry in request list then do
1958                          * not issue END TRANSFER now. Just set PENDING
1959                          * flag, so that END TRANSFER is issued when an
1960                          * entry is added into request list.
1961                          */
1962                         dep->flags = DWC3_EP_PENDING_REQUEST;
1963                 } else {
1964                         dwc3_stop_active_transfer(dwc, dep->number, true);
1965                         dep->flags = DWC3_EP_ENABLED;
1966                 }
1967                 return 1;
1968         }
1969
1970         return 1;
1971 }
1972
1973 static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
1974                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1975 {
1976         unsigned                status = 0;
1977         int                     clean_busy;
1978         u32                     is_xfer_complete;
1979
1980         is_xfer_complete = (event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE);
1981
1982         if (event->status & DEPEVT_STATUS_BUSERR)
1983                 status = -ECONNRESET;
1984
1985         clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
1986         if (clean_busy && (is_xfer_complete ||
1987                                 usb_endpoint_xfer_isoc(dep->endpoint.desc)))
1988                 dep->flags &= ~DWC3_EP_BUSY;
1989
1990         /*
1991          * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
1992          * See dwc3_gadget_linksts_change_interrupt() for 1st half.
1993          */
1994         if (dwc->revision < DWC3_REVISION_183A) {
1995                 u32             reg;
1996                 int             i;
1997
1998                 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
1999                         dep = dwc->eps[i];
2000
2001                         if (!(dep->flags & DWC3_EP_ENABLED))
2002                                 continue;
2003
2004                         if (!list_empty(&dep->started_list))
2005                                 return;
2006                 }
2007
2008                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2009                 reg |= dwc->u1u2;
2010                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2011
2012                 dwc->u1u2 = 0;
2013         }
2014
2015         if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2016                 int ret;
2017
2018                 ret = __dwc3_gadget_kick_transfer(dep, 0, is_xfer_complete);
2019                 if (!ret || ret == -EBUSY)
2020                         return;
2021         }
2022 }
2023
2024 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
2025                 const struct dwc3_event_depevt *event)
2026 {
2027         struct dwc3_ep          *dep;
2028         u8                      epnum = event->endpoint_number;
2029
2030         dep = dwc->eps[epnum];
2031
2032         if (!(dep->flags & DWC3_EP_ENABLED))
2033                 return;
2034
2035         if (epnum == 0 || epnum == 1) {
2036                 dwc3_ep0_interrupt(dwc, event);
2037                 return;
2038         }
2039
2040         switch (event->endpoint_event) {
2041         case DWC3_DEPEVT_XFERCOMPLETE:
2042                 dep->resource_index = 0;
2043
2044                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2045                         dwc3_trace(trace_dwc3_gadget,
2046                                         "%s is an Isochronous endpoint\n",
2047                                         dep->name);
2048                         return;
2049                 }
2050
2051                 dwc3_endpoint_transfer_complete(dwc, dep, event);
2052                 break;
2053         case DWC3_DEPEVT_XFERINPROGRESS:
2054                 dwc3_endpoint_transfer_complete(dwc, dep, event);
2055                 break;
2056         case DWC3_DEPEVT_XFERNOTREADY:
2057                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2058                         dwc3_gadget_start_isoc(dwc, dep, event);
2059                 } else {
2060                         int active;
2061                         int ret;
2062
2063                         active = event->status & DEPEVT_STATUS_TRANSFER_ACTIVE;
2064
2065                         dwc3_trace(trace_dwc3_gadget, "%s: reason %s",
2066                                         dep->name, active ? "Transfer Active"
2067                                         : "Transfer Not Active");
2068
2069                         ret = __dwc3_gadget_kick_transfer(dep, 0, !active);
2070                         if (!ret || ret == -EBUSY)
2071                                 return;
2072
2073                         dwc3_trace(trace_dwc3_gadget,
2074                                         "%s: failed to kick transfers\n",
2075                                         dep->name);
2076                 }
2077
2078                 break;
2079         case DWC3_DEPEVT_STREAMEVT:
2080                 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
2081                         dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
2082                                         dep->name);
2083                         return;
2084                 }
2085
2086                 switch (event->status) {
2087                 case DEPEVT_STREAMEVT_FOUND:
2088                         dwc3_trace(trace_dwc3_gadget,
2089                                         "Stream %d found and started",
2090                                         event->parameters);
2091
2092                         break;
2093                 case DEPEVT_STREAMEVT_NOTFOUND:
2094                         /* FALLTHROUGH */
2095                 default:
2096                         dwc3_trace(trace_dwc3_gadget,
2097                                         "unable to find suitable stream\n");
2098                 }
2099                 break;
2100         case DWC3_DEPEVT_RXTXFIFOEVT:
2101                 dwc3_trace(trace_dwc3_gadget, "%s FIFO Overrun\n", dep->name);
2102                 break;
2103         case DWC3_DEPEVT_EPCMDCMPLT:
2104                 dwc3_trace(trace_dwc3_gadget, "Endpoint Command Complete");
2105                 break;
2106         }
2107 }
2108
2109 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2110 {
2111         if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2112                 spin_unlock(&dwc->lock);
2113                 dwc->gadget_driver->disconnect(&dwc->gadget);
2114                 spin_lock(&dwc->lock);
2115         }
2116 }
2117
2118 static void dwc3_suspend_gadget(struct dwc3 *dwc)
2119 {
2120         if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
2121                 spin_unlock(&dwc->lock);
2122                 dwc->gadget_driver->suspend(&dwc->gadget);
2123                 spin_lock(&dwc->lock);
2124         }
2125 }
2126
2127 static void dwc3_resume_gadget(struct dwc3 *dwc)
2128 {
2129         if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2130                 spin_unlock(&dwc->lock);
2131                 dwc->gadget_driver->resume(&dwc->gadget);
2132                 spin_lock(&dwc->lock);
2133         }
2134 }
2135
2136 static void dwc3_reset_gadget(struct dwc3 *dwc)
2137 {
2138         if (!dwc->gadget_driver)
2139                 return;
2140
2141         if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2142                 spin_unlock(&dwc->lock);
2143                 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
2144                 spin_lock(&dwc->lock);
2145         }
2146 }
2147
2148 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
2149 {
2150         struct dwc3_ep *dep;
2151         struct dwc3_gadget_ep_cmd_params params;
2152         u32 cmd;
2153         int ret;
2154
2155         dep = dwc->eps[epnum];
2156
2157         if (!dep->resource_index)
2158                 return;
2159
2160         /*
2161          * NOTICE: We are violating what the Databook says about the
2162          * EndTransfer command. Ideally we would _always_ wait for the
2163          * EndTransfer Command Completion IRQ, but that's causing too
2164          * much trouble synchronizing between us and gadget driver.
2165          *
2166          * We have discussed this with the IP Provider and it was
2167          * suggested to giveback all requests here, but give HW some
2168          * extra time to synchronize with the interconnect. We're using
2169          * an arbitrary 100us delay for that.
2170          *
2171          * Note also that a similar handling was tested by Synopsys
2172          * (thanks a lot Paul) and nothing bad has come out of it.
2173          * In short, what we're doing is:
2174          *
2175          * - Issue EndTransfer WITH CMDIOC bit set
2176          * - Wait 100us
2177          */
2178
2179         cmd = DWC3_DEPCMD_ENDTRANSFER;
2180         cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2181         cmd |= DWC3_DEPCMD_CMDIOC;
2182         cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2183         memset(&params, 0, sizeof(params));
2184         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
2185         WARN_ON_ONCE(ret);
2186         dep->resource_index = 0;
2187         dep->flags &= ~DWC3_EP_BUSY;
2188         udelay(100);
2189 }
2190
2191 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2192 {
2193         u32 epnum;
2194
2195         for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2196                 struct dwc3_ep *dep;
2197
2198                 dep = dwc->eps[epnum];
2199                 if (!dep)
2200                         continue;
2201
2202                 if (!(dep->flags & DWC3_EP_ENABLED))
2203                         continue;
2204
2205                 dwc3_remove_requests(dwc, dep);
2206         }
2207 }
2208
2209 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2210 {
2211         u32 epnum;
2212
2213         for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2214                 struct dwc3_ep *dep;
2215                 struct dwc3_gadget_ep_cmd_params params;
2216                 int ret;
2217
2218                 dep = dwc->eps[epnum];
2219                 if (!dep)
2220                         continue;
2221
2222                 if (!(dep->flags & DWC3_EP_STALL))
2223                         continue;
2224
2225                 dep->flags &= ~DWC3_EP_STALL;
2226
2227                 memset(&params, 0, sizeof(params));
2228                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
2229                                 DWC3_DEPCMD_CLEARSTALL, &params);
2230                 WARN_ON_ONCE(ret);
2231         }
2232 }
2233
2234 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2235 {
2236         int                     reg;
2237
2238         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2239         reg &= ~DWC3_DCTL_INITU1ENA;
2240         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2241
2242         reg &= ~DWC3_DCTL_INITU2ENA;
2243         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2244
2245         dwc3_disconnect_gadget(dwc);
2246
2247         dwc->gadget.speed = USB_SPEED_UNKNOWN;
2248         dwc->setup_packet_pending = false;
2249         usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
2250 }
2251
2252 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2253 {
2254         u32                     reg;
2255
2256         /*
2257          * WORKAROUND: DWC3 revisions <1.88a have an issue which
2258          * would cause a missing Disconnect Event if there's a
2259          * pending Setup Packet in the FIFO.
2260          *
2261          * There's no suggested workaround on the official Bug
2262          * report, which states that "unless the driver/application
2263          * is doing any special handling of a disconnect event,
2264          * there is no functional issue".
2265          *
2266          * Unfortunately, it turns out that we _do_ some special
2267          * handling of a disconnect event, namely complete all
2268          * pending transfers, notify gadget driver of the
2269          * disconnection, and so on.
2270          *
2271          * Our suggested workaround is to follow the Disconnect
2272          * Event steps here, instead, based on a setup_packet_pending
2273          * flag. Such flag gets set whenever we have a SETUP_PENDING
2274          * status for EP0 TRBs and gets cleared on XferComplete for the
2275          * same endpoint.
2276          *
2277          * Refers to:
2278          *
2279          * STAR#9000466709: RTL: Device : Disconnect event not
2280          * generated if setup packet pending in FIFO
2281          */
2282         if (dwc->revision < DWC3_REVISION_188A) {
2283                 if (dwc->setup_packet_pending)
2284                         dwc3_gadget_disconnect_interrupt(dwc);
2285         }
2286
2287         dwc3_reset_gadget(dwc);
2288
2289         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2290         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2291         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2292         dwc->test_mode = false;
2293
2294         dwc3_stop_active_transfers(dwc);
2295         dwc3_clear_stall_all_ep(dwc);
2296
2297         /* Reset device address to zero */
2298         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2299         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2300         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2301 }
2302
2303 static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
2304 {
2305         u32 reg;
2306         u32 usb30_clock = DWC3_GCTL_CLK_BUS;
2307
2308         /*
2309          * We change the clock only at SS but I dunno why I would want to do
2310          * this. Maybe it becomes part of the power saving plan.
2311          */
2312
2313         if ((speed != DWC3_DSTS_SUPERSPEED) &&
2314             (speed != DWC3_DSTS_SUPERSPEED_PLUS))
2315                 return;
2316
2317         /*
2318          * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2319          * each time on Connect Done.
2320          */
2321         if (!usb30_clock)
2322                 return;
2323
2324         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2325         reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2326         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2327 }
2328
2329 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2330 {
2331         struct dwc3_ep          *dep;
2332         int                     ret;
2333         u32                     reg;
2334         u8                      speed;
2335
2336         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2337         speed = reg & DWC3_DSTS_CONNECTSPD;
2338         dwc->speed = speed;
2339
2340         dwc3_update_ram_clk_sel(dwc, speed);
2341
2342         switch (speed) {
2343         case DWC3_DCFG_SUPERSPEED_PLUS:
2344                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2345                 dwc->gadget.ep0->maxpacket = 512;
2346                 dwc->gadget.speed = USB_SPEED_SUPER_PLUS;
2347                 break;
2348         case DWC3_DCFG_SUPERSPEED:
2349                 /*
2350                  * WORKAROUND: DWC3 revisions <1.90a have an issue which
2351                  * would cause a missing USB3 Reset event.
2352                  *
2353                  * In such situations, we should force a USB3 Reset
2354                  * event by calling our dwc3_gadget_reset_interrupt()
2355                  * routine.
2356                  *
2357                  * Refers to:
2358                  *
2359                  * STAR#9000483510: RTL: SS : USB3 reset event may
2360                  * not be generated always when the link enters poll
2361                  */
2362                 if (dwc->revision < DWC3_REVISION_190A)
2363                         dwc3_gadget_reset_interrupt(dwc);
2364
2365                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2366                 dwc->gadget.ep0->maxpacket = 512;
2367                 dwc->gadget.speed = USB_SPEED_SUPER;
2368                 break;
2369         case DWC3_DCFG_HIGHSPEED:
2370                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2371                 dwc->gadget.ep0->maxpacket = 64;
2372                 dwc->gadget.speed = USB_SPEED_HIGH;
2373                 break;
2374         case DWC3_DCFG_FULLSPEED2:
2375         case DWC3_DCFG_FULLSPEED1:
2376                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2377                 dwc->gadget.ep0->maxpacket = 64;
2378                 dwc->gadget.speed = USB_SPEED_FULL;
2379                 break;
2380         case DWC3_DCFG_LOWSPEED:
2381                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2382                 dwc->gadget.ep0->maxpacket = 8;
2383                 dwc->gadget.speed = USB_SPEED_LOW;
2384                 break;
2385         }
2386
2387         /* Enable USB2 LPM Capability */
2388
2389         if ((dwc->revision > DWC3_REVISION_194A) &&
2390             (speed != DWC3_DCFG_SUPERSPEED) &&
2391             (speed != DWC3_DCFG_SUPERSPEED_PLUS)) {
2392                 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2393                 reg |= DWC3_DCFG_LPM_CAP;
2394                 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2395
2396                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2397                 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2398
2399                 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2400
2401                 /*
2402                  * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2403                  * DCFG.LPMCap is set, core responses with an ACK and the
2404                  * BESL value in the LPM token is less than or equal to LPM
2405                  * NYET threshold.
2406                  */
2407                 WARN_ONCE(dwc->revision < DWC3_REVISION_240A
2408                                 && dwc->has_lpm_erratum,
2409                                 "LPM Erratum not available on dwc3 revisisions < 2.40a\n");
2410
2411                 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2412                         reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2413
2414                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2415         } else {
2416                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2417                 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2418                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2419         }
2420
2421         dep = dwc->eps[0];
2422         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2423                         false);
2424         if (ret) {
2425                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2426                 return;
2427         }
2428
2429         dep = dwc->eps[1];
2430         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2431                         false);
2432         if (ret) {
2433                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2434                 return;
2435         }
2436
2437         /*
2438          * Configure PHY via GUSB3PIPECTLn if required.
2439          *
2440          * Update GTXFIFOSIZn
2441          *
2442          * In both cases reset values should be sufficient.
2443          */
2444 }
2445
2446 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2447 {
2448         /*
2449          * TODO take core out of low power mode when that's
2450          * implemented.
2451          */
2452
2453         if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2454                 spin_unlock(&dwc->lock);
2455                 dwc->gadget_driver->resume(&dwc->gadget);
2456                 spin_lock(&dwc->lock);
2457         }
2458 }
2459
2460 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2461                 unsigned int evtinfo)
2462 {
2463         enum dwc3_link_state    next = evtinfo & DWC3_LINK_STATE_MASK;
2464         unsigned int            pwropt;
2465
2466         /*
2467          * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2468          * Hibernation mode enabled which would show up when device detects
2469          * host-initiated U3 exit.
2470          *
2471          * In that case, device will generate a Link State Change Interrupt
2472          * from U3 to RESUME which is only necessary if Hibernation is
2473          * configured in.
2474          *
2475          * There are no functional changes due to such spurious event and we
2476          * just need to ignore it.
2477          *
2478          * Refers to:
2479          *
2480          * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2481          * operational mode
2482          */
2483         pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2484         if ((dwc->revision < DWC3_REVISION_250A) &&
2485                         (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2486                 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2487                                 (next == DWC3_LINK_STATE_RESUME)) {
2488                         dwc3_trace(trace_dwc3_gadget,
2489                                         "ignoring transition U3 -> Resume");
2490                         return;
2491                 }
2492         }
2493
2494         /*
2495          * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2496          * on the link partner, the USB session might do multiple entry/exit
2497          * of low power states before a transfer takes place.
2498          *
2499          * Due to this problem, we might experience lower throughput. The
2500          * suggested workaround is to disable DCTL[12:9] bits if we're
2501          * transitioning from U1/U2 to U0 and enable those bits again
2502          * after a transfer completes and there are no pending transfers
2503          * on any of the enabled endpoints.
2504          *
2505          * This is the first half of that workaround.
2506          *
2507          * Refers to:
2508          *
2509          * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2510          * core send LGO_Ux entering U0
2511          */
2512         if (dwc->revision < DWC3_REVISION_183A) {
2513                 if (next == DWC3_LINK_STATE_U0) {
2514                         u32     u1u2;
2515                         u32     reg;
2516
2517                         switch (dwc->link_state) {
2518                         case DWC3_LINK_STATE_U1:
2519                         case DWC3_LINK_STATE_U2:
2520                                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2521                                 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2522                                                 | DWC3_DCTL_ACCEPTU2ENA
2523                                                 | DWC3_DCTL_INITU1ENA
2524                                                 | DWC3_DCTL_ACCEPTU1ENA);
2525
2526                                 if (!dwc->u1u2)
2527                                         dwc->u1u2 = reg & u1u2;
2528
2529                                 reg &= ~u1u2;
2530
2531                                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2532                                 break;
2533                         default:
2534                                 /* do nothing */
2535                                 break;
2536                         }
2537                 }
2538         }
2539
2540         switch (next) {
2541         case DWC3_LINK_STATE_U1:
2542                 if (dwc->speed == USB_SPEED_SUPER)
2543                         dwc3_suspend_gadget(dwc);
2544                 break;
2545         case DWC3_LINK_STATE_U2:
2546         case DWC3_LINK_STATE_U3:
2547                 dwc3_suspend_gadget(dwc);
2548                 break;
2549         case DWC3_LINK_STATE_RESUME:
2550                 dwc3_resume_gadget(dwc);
2551                 break;
2552         default:
2553                 /* do nothing */
2554                 break;
2555         }
2556
2557         dwc->link_state = next;
2558 }
2559
2560 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2561                 unsigned int evtinfo)
2562 {
2563         unsigned int is_ss = evtinfo & BIT(4);
2564
2565         /**
2566          * WORKAROUND: DWC3 revison 2.20a with hibernation support
2567          * have a known issue which can cause USB CV TD.9.23 to fail
2568          * randomly.
2569          *
2570          * Because of this issue, core could generate bogus hibernation
2571          * events which SW needs to ignore.
2572          *
2573          * Refers to:
2574          *
2575          * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2576          * Device Fallback from SuperSpeed
2577          */
2578         if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2579                 return;
2580
2581         /* enter hibernation here */
2582 }
2583
2584 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2585                 const struct dwc3_event_devt *event)
2586 {
2587         switch (event->type) {
2588         case DWC3_DEVICE_EVENT_DISCONNECT:
2589                 dwc3_gadget_disconnect_interrupt(dwc);
2590                 break;
2591         case DWC3_DEVICE_EVENT_RESET:
2592                 dwc3_gadget_reset_interrupt(dwc);
2593                 break;
2594         case DWC3_DEVICE_EVENT_CONNECT_DONE:
2595                 dwc3_gadget_conndone_interrupt(dwc);
2596                 break;
2597         case DWC3_DEVICE_EVENT_WAKEUP:
2598                 dwc3_gadget_wakeup_interrupt(dwc);
2599                 break;
2600         case DWC3_DEVICE_EVENT_HIBER_REQ:
2601                 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
2602                                         "unexpected hibernation event\n"))
2603                         break;
2604
2605                 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2606                 break;
2607         case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2608                 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2609                 break;
2610         case DWC3_DEVICE_EVENT_EOPF:
2611                 dwc3_trace(trace_dwc3_gadget, "End of Periodic Frame");
2612                 break;
2613         case DWC3_DEVICE_EVENT_SOF:
2614                 dwc3_trace(trace_dwc3_gadget, "Start of Periodic Frame");
2615                 break;
2616         case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2617                 dwc3_trace(trace_dwc3_gadget, "Erratic Error");
2618                 break;
2619         case DWC3_DEVICE_EVENT_CMD_CMPL:
2620                 dwc3_trace(trace_dwc3_gadget, "Command Complete");
2621                 break;
2622         case DWC3_DEVICE_EVENT_OVERFLOW:
2623                 dwc3_trace(trace_dwc3_gadget, "Overflow");
2624                 break;
2625         default:
2626                 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2627         }
2628 }
2629
2630 static void dwc3_process_event_entry(struct dwc3 *dwc,
2631                 const union dwc3_event *event)
2632 {
2633         trace_dwc3_event(event->raw);
2634
2635         /* Endpoint IRQ, handle it and return early */
2636         if (event->type.is_devspec == 0) {
2637                 /* depevt */
2638                 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2639         }
2640
2641         switch (event->type.type) {
2642         case DWC3_EVENT_TYPE_DEV:
2643                 dwc3_gadget_interrupt(dwc, &event->devt);
2644                 break;
2645         /* REVISIT what to do with Carkit and I2C events ? */
2646         default:
2647                 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2648         }
2649 }
2650
2651 static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
2652 {
2653         struct dwc3 *dwc = evt->dwc;
2654         irqreturn_t ret = IRQ_NONE;
2655         int left;
2656         u32 reg;
2657
2658         left = evt->count;
2659
2660         if (!(evt->flags & DWC3_EVENT_PENDING))
2661                 return IRQ_NONE;
2662
2663         while (left > 0) {
2664                 union dwc3_event event;
2665
2666                 event.raw = *(u32 *) (evt->buf + evt->lpos);
2667
2668                 dwc3_process_event_entry(dwc, &event);
2669
2670                 /*
2671                  * FIXME we wrap around correctly to the next entry as
2672                  * almost all entries are 4 bytes in size. There is one
2673                  * entry which has 12 bytes which is a regular entry
2674                  * followed by 8 bytes data. ATM I don't know how
2675                  * things are organized if we get next to the a
2676                  * boundary so I worry about that once we try to handle
2677                  * that.
2678                  */
2679                 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2680                 left -= 4;
2681
2682                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 4);
2683         }
2684
2685         evt->count = 0;
2686         evt->flags &= ~DWC3_EVENT_PENDING;
2687         ret = IRQ_HANDLED;
2688
2689         /* Unmask interrupt */
2690         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
2691         reg &= ~DWC3_GEVNTSIZ_INTMASK;
2692         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
2693
2694         return ret;
2695 }
2696
2697 static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
2698 {
2699         struct dwc3_event_buffer *evt = _evt;
2700         struct dwc3 *dwc = evt->dwc;
2701         unsigned long flags;
2702         irqreturn_t ret = IRQ_NONE;
2703
2704         spin_lock_irqsave(&dwc->lock, flags);
2705         ret = dwc3_process_event_buf(evt);
2706         spin_unlock_irqrestore(&dwc->lock, flags);
2707
2708         return ret;
2709 }
2710
2711 static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
2712 {
2713         struct dwc3 *dwc = evt->dwc;
2714         u32 count;
2715         u32 reg;
2716
2717         count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
2718         count &= DWC3_GEVNTCOUNT_MASK;
2719         if (!count)
2720                 return IRQ_NONE;
2721
2722         evt->count = count;
2723         evt->flags |= DWC3_EVENT_PENDING;
2724
2725         /* Mask interrupt */
2726         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
2727         reg |= DWC3_GEVNTSIZ_INTMASK;
2728         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
2729
2730         return IRQ_WAKE_THREAD;
2731 }
2732
2733 static irqreturn_t dwc3_interrupt(int irq, void *_evt)
2734 {
2735         struct dwc3_event_buffer        *evt = _evt;
2736
2737         return dwc3_check_event_buf(evt);
2738 }
2739
2740 /**
2741  * dwc3_gadget_init - Initializes gadget related registers
2742  * @dwc: pointer to our controller context structure
2743  *
2744  * Returns 0 on success otherwise negative errno.
2745  */
2746 int dwc3_gadget_init(struct dwc3 *dwc)
2747 {
2748         int                                     ret;
2749
2750         dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2751                         &dwc->ctrl_req_addr, GFP_KERNEL);
2752         if (!dwc->ctrl_req) {
2753                 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2754                 ret = -ENOMEM;
2755                 goto err0;
2756         }
2757
2758         dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb) * 2,
2759                         &dwc->ep0_trb_addr, GFP_KERNEL);
2760         if (!dwc->ep0_trb) {
2761                 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2762                 ret = -ENOMEM;
2763                 goto err1;
2764         }
2765
2766         dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
2767         if (!dwc->setup_buf) {
2768                 ret = -ENOMEM;
2769                 goto err2;
2770         }
2771
2772         dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
2773                         DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,
2774                         GFP_KERNEL);
2775         if (!dwc->ep0_bounce) {
2776                 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2777                 ret = -ENOMEM;
2778                 goto err3;
2779         }
2780
2781         dwc->zlp_buf = kzalloc(DWC3_ZLP_BUF_SIZE, GFP_KERNEL);
2782         if (!dwc->zlp_buf) {
2783                 ret = -ENOMEM;
2784                 goto err4;
2785         }
2786
2787         dwc->gadget.ops                 = &dwc3_gadget_ops;
2788         dwc->gadget.speed               = USB_SPEED_UNKNOWN;
2789         dwc->gadget.sg_supported        = true;
2790         dwc->gadget.name                = "dwc3-gadget";
2791         dwc->gadget.is_otg              = dwc->dr_mode == USB_DR_MODE_OTG;
2792
2793         /*
2794          * FIXME We might be setting max_speed to <SUPER, however versions
2795          * <2.20a of dwc3 have an issue with metastability (documented
2796          * elsewhere in this driver) which tells us we can't set max speed to
2797          * anything lower than SUPER.
2798          *
2799          * Because gadget.max_speed is only used by composite.c and function
2800          * drivers (i.e. it won't go into dwc3's registers) we are allowing this
2801          * to happen so we avoid sending SuperSpeed Capability descriptor
2802          * together with our BOS descriptor as that could confuse host into
2803          * thinking we can handle super speed.
2804          *
2805          * Note that, in fact, we won't even support GetBOS requests when speed
2806          * is less than super speed because we don't have means, yet, to tell
2807          * composite.c that we are USB 2.0 + LPM ECN.
2808          */
2809         if (dwc->revision < DWC3_REVISION_220A)
2810                 dwc3_trace(trace_dwc3_gadget,
2811                                 "Changing max_speed on rev %08x\n",
2812                                 dwc->revision);
2813
2814         dwc->gadget.max_speed           = dwc->maximum_speed;
2815
2816         /*
2817          * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
2818          * on ep out.
2819          */
2820         dwc->gadget.quirk_ep_out_aligned_size = true;
2821
2822         /*
2823          * REVISIT: Here we should clear all pending IRQs to be
2824          * sure we're starting from a well known location.
2825          */
2826
2827         ret = dwc3_gadget_init_endpoints(dwc);
2828         if (ret)
2829                 goto err5;
2830
2831         ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2832         if (ret) {
2833                 dev_err(dwc->dev, "failed to register udc\n");
2834                 goto err5;
2835         }
2836
2837         return 0;
2838
2839 err5:
2840         kfree(dwc->zlp_buf);
2841
2842 err4:
2843         dwc3_gadget_free_endpoints(dwc);
2844         dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2845                         dwc->ep0_bounce, dwc->ep0_bounce_addr);
2846
2847 err3:
2848         kfree(dwc->setup_buf);
2849
2850 err2:
2851         dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2852                         dwc->ep0_trb, dwc->ep0_trb_addr);
2853
2854 err1:
2855         dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2856                         dwc->ctrl_req, dwc->ctrl_req_addr);
2857
2858 err0:
2859         return ret;
2860 }
2861
2862 /* -------------------------------------------------------------------------- */
2863
2864 void dwc3_gadget_exit(struct dwc3 *dwc)
2865 {
2866         usb_del_gadget_udc(&dwc->gadget);
2867
2868         dwc3_gadget_free_endpoints(dwc);
2869
2870         dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2871                         dwc->ep0_bounce, dwc->ep0_bounce_addr);
2872
2873         kfree(dwc->setup_buf);
2874         kfree(dwc->zlp_buf);
2875
2876         dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2877                         dwc->ep0_trb, dwc->ep0_trb_addr);
2878
2879         dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2880                         dwc->ctrl_req, dwc->ctrl_req_addr);
2881 }
2882
2883 int dwc3_gadget_suspend(struct dwc3 *dwc)
2884 {
2885         if (dwc->pullups_connected) {
2886                 dwc3_gadget_disable_irq(dwc);
2887                 dwc3_gadget_run_stop(dwc, true, true);
2888         }
2889
2890         __dwc3_gadget_ep_disable(dwc->eps[0]);
2891         __dwc3_gadget_ep_disable(dwc->eps[1]);
2892
2893         dwc->dcfg = dwc3_readl(dwc->regs, DWC3_DCFG);
2894
2895         return 0;
2896 }
2897
2898 int dwc3_gadget_resume(struct dwc3 *dwc)
2899 {
2900         struct dwc3_ep          *dep;
2901         int                     ret;
2902
2903         /* Start with SuperSpeed Default */
2904         dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2905
2906         dep = dwc->eps[0];
2907         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
2908                         false);
2909         if (ret)
2910                 goto err0;
2911
2912         dep = dwc->eps[1];
2913         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
2914                         false);
2915         if (ret)
2916                 goto err1;
2917
2918         /* begin to receive SETUP packets */
2919         dwc->ep0state = EP0_SETUP_PHASE;
2920         dwc3_ep0_out_start(dwc);
2921
2922         dwc3_writel(dwc->regs, DWC3_DCFG, dwc->dcfg);
2923
2924         if (dwc->pullups_connected) {
2925                 dwc3_gadget_enable_irq(dwc);
2926                 dwc3_gadget_run_stop(dwc, true, false);
2927         }
2928
2929         return 0;
2930
2931 err1:
2932         __dwc3_gadget_ep_disable(dwc->eps[0]);
2933
2934 err0:
2935         return ret;
2936 }