2 * Copyright (c) 2015 Google, Inc
3 * Copyright (c) 2011 The Chromium OS Authors.
4 * Copyright (C) 2009 NVIDIA, Corporation
5 * Copyright (C) 2007-2008 SMSC (Steve Glendinning)
7 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/unaligned.h>
16 #include <linux/mii.h>
17 #include "usb_ether.h"
19 /* SMSC LAN95xx based USB 2.0 Ethernet Devices */
22 #define LED_GPIO_CFG (0x24)
23 #define LED_GPIO_CFG_SPD_LED (0x01000000)
24 #define LED_GPIO_CFG_LNK_LED (0x00100000)
25 #define LED_GPIO_CFG_FDX_LED (0x00010000)
27 /* Tx command words */
28 #define TX_CMD_A_FIRST_SEG_ 0x00002000
29 #define TX_CMD_A_LAST_SEG_ 0x00001000
32 #define RX_STS_FL_ 0x3FFF0000 /* Frame Length */
33 #define RX_STS_ES_ 0x00008000 /* Error Summary */
41 #define TX_CFG_ON_ 0x00000004
44 #define HW_CFG_BIR_ 0x00001000
45 #define HW_CFG_RXDOFF_ 0x00000600
46 #define HW_CFG_MEF_ 0x00000020
47 #define HW_CFG_BCE_ 0x00000002
48 #define HW_CFG_LRST_ 0x00000008
51 #define PM_CTL_PHY_RST_ 0x00000010
56 * Hi watermark = 15.5Kb (~10 mtu pkts)
57 * low watermark = 3k (~2 mtu pkts)
58 * backpressure duration = ~ 350us
59 * Apply FC on any frame.
61 #define AFC_CFG_DEFAULT 0x00F830A1
64 #define E2P_CMD_BUSY_ 0x80000000
65 #define E2P_CMD_READ_ 0x00000000
66 #define E2P_CMD_TIMEOUT_ 0x00000400
67 #define E2P_CMD_LOADED_ 0x00000200
68 #define E2P_CMD_ADDR_ 0x000001FF
72 #define BURST_CAP 0x38
74 #define INT_EP_CTL 0x68
75 #define INT_EP_CTL_PHY_INT_ 0x00008000
77 #define BULK_IN_DLY 0x6C
81 #define MAC_CR_MCPAS_ 0x00080000
82 #define MAC_CR_PRMS_ 0x00040000
83 #define MAC_CR_HPFILT_ 0x00002000
84 #define MAC_CR_TXEN_ 0x00000008
85 #define MAC_CR_RXEN_ 0x00000004
91 #define MII_ADDR 0x114
92 #define MII_WRITE_ 0x02
93 #define MII_BUSY_ 0x01
94 #define MII_READ_ 0x00 /* ~of MII Write bit */
96 #define MII_DATA 0x118
103 #define Tx_COE_EN_ 0x00010000
104 #define Rx_COE_EN_ 0x00000001
106 /* Vendor-specific PHY Definitions */
107 #define PHY_INT_SRC 29
109 #define PHY_INT_MASK 30
110 #define PHY_INT_MASK_ANEG_COMP_ ((u16)0x0040)
111 #define PHY_INT_MASK_LINK_DOWN_ ((u16)0x0010)
112 #define PHY_INT_MASK_DEFAULT_ (PHY_INT_MASK_ANEG_COMP_ | \
113 PHY_INT_MASK_LINK_DOWN_)
115 /* USB Vendor Requests */
116 #define USB_VENDOR_REQUEST_WRITE_REGISTER 0xA0
117 #define USB_VENDOR_REQUEST_READ_REGISTER 0xA1
119 /* Some extra defines */
120 #define HS_USB_PKT_SIZE 512
121 #define FS_USB_PKT_SIZE 64
122 #define DEFAULT_HS_BURST_CAP_SIZE (16 * 1024 + 5 * HS_USB_PKT_SIZE)
123 #define DEFAULT_FS_BURST_CAP_SIZE (6 * 1024 + 33 * FS_USB_PKT_SIZE)
124 #define DEFAULT_BULK_IN_DELAY 0x00002000
125 #define MAX_SINGLE_PACKET_SIZE 2048
126 #define EEPROM_MAC_OFFSET 0x01
127 #define SMSC95XX_INTERNAL_PHY_ID 1
128 #define ETH_P_8021Q 0x8100 /* 802.1Q VLAN Extended Header */
131 #define SMSC95XX_BASE_NAME "sms"
132 #define USB_CTRL_SET_TIMEOUT 5000
133 #define USB_CTRL_GET_TIMEOUT 5000
134 #define USB_BULK_SEND_TIMEOUT 5000
135 #define USB_BULK_RECV_TIMEOUT 5000
137 #define RX_URB_SIZE 2048
138 #define PHY_CONNECT_TIMEOUT 5000
142 #ifndef CONFIG_DM_ETH
144 static int curr_eth_dev; /* index for name of next device detected */
148 struct smsc95xx_private {
150 struct ueth_data ueth;
152 size_t rx_urb_size; /* maximum USB URB size */
153 u32 mac_cr; /* MAC control register value */
154 int have_hwaddr; /* 1 if we have a hardware MAC address */
158 * Smsc95xx infrastructure commands
160 static int smsc95xx_write_reg(struct usb_device *udev, u32 index, u32 data)
163 ALLOC_CACHE_ALIGN_BUFFER(u32, tmpbuf, 1);
168 len = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
169 USB_VENDOR_REQUEST_WRITE_REGISTER,
170 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
171 0, index, tmpbuf, sizeof(data),
172 USB_CTRL_SET_TIMEOUT);
173 if (len != sizeof(data)) {
174 debug("smsc95xx_write_reg failed: index=%d, data=%d, len=%d",
181 static int smsc95xx_read_reg(struct usb_device *udev, u32 index, u32 *data)
184 ALLOC_CACHE_ALIGN_BUFFER(u32, tmpbuf, 1);
186 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
187 USB_VENDOR_REQUEST_READ_REGISTER,
188 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
189 0, index, tmpbuf, sizeof(data),
190 USB_CTRL_GET_TIMEOUT);
192 if (len != sizeof(data)) {
193 debug("smsc95xx_read_reg failed: index=%d, len=%d",
202 /* Loop until the read is completed with timeout */
203 static int smsc95xx_phy_wait_not_busy(struct usb_device *udev)
205 unsigned long start_time = get_timer(0);
209 smsc95xx_read_reg(udev, MII_ADDR, &val);
210 if (!(val & MII_BUSY_))
212 } while (get_timer(start_time) < 1000);
217 static int smsc95xx_mdio_read(struct usb_device *udev, int phy_id, int idx)
221 /* confirm MII not busy */
222 if (smsc95xx_phy_wait_not_busy(udev)) {
223 debug("MII is busy in smsc95xx_mdio_read\n");
227 /* set the address, index & direction (read from PHY) */
228 addr = (phy_id << 11) | (idx << 6) | MII_READ_;
229 smsc95xx_write_reg(udev, MII_ADDR, addr);
231 if (smsc95xx_phy_wait_not_busy(udev)) {
232 debug("Timed out reading MII reg %02X\n", idx);
236 smsc95xx_read_reg(udev, MII_DATA, &val);
238 return (u16)(val & 0xFFFF);
241 static void smsc95xx_mdio_write(struct usb_device *udev, int phy_id, int idx,
246 /* confirm MII not busy */
247 if (smsc95xx_phy_wait_not_busy(udev)) {
248 debug("MII is busy in smsc95xx_mdio_write\n");
253 smsc95xx_write_reg(udev, MII_DATA, val);
255 /* set the address, index & direction (write to PHY) */
256 addr = (phy_id << 11) | (idx << 6) | MII_WRITE_;
257 smsc95xx_write_reg(udev, MII_ADDR, addr);
259 if (smsc95xx_phy_wait_not_busy(udev))
260 debug("Timed out writing MII reg %02X\n", idx);
263 static int smsc95xx_eeprom_confirm_not_busy(struct usb_device *udev)
265 unsigned long start_time = get_timer(0);
269 smsc95xx_read_reg(udev, E2P_CMD, &val);
270 if (!(val & E2P_CMD_BUSY_))
273 } while (get_timer(start_time) < 1 * 1000 * 1000);
275 debug("EEPROM is busy\n");
279 static int smsc95xx_wait_eeprom(struct usb_device *udev)
281 unsigned long start_time = get_timer(0);
285 smsc95xx_read_reg(udev, E2P_CMD, &val);
286 if (!(val & E2P_CMD_BUSY_) || (val & E2P_CMD_TIMEOUT_))
289 } while (get_timer(start_time) < 1 * 1000 * 1000);
291 if (val & (E2P_CMD_TIMEOUT_ | E2P_CMD_BUSY_)) {
292 debug("EEPROM read operation timeout\n");
298 static int smsc95xx_read_eeprom(struct usb_device *udev, u32 offset, u32 length,
304 ret = smsc95xx_eeprom_confirm_not_busy(udev);
308 for (i = 0; i < length; i++) {
309 val = E2P_CMD_BUSY_ | E2P_CMD_READ_ | (offset & E2P_CMD_ADDR_);
310 smsc95xx_write_reg(udev, E2P_CMD, val);
312 ret = smsc95xx_wait_eeprom(udev);
316 smsc95xx_read_reg(udev, E2P_DATA, &val);
317 data[i] = val & 0xFF;
324 * mii_nway_restart - restart NWay (autonegotiation) for this interface
326 * Returns 0 on success, negative on error.
328 static int mii_nway_restart(struct usb_device *udev, struct ueth_data *dev)
333 /* if autoneg is off, it's an error */
334 bmcr = smsc95xx_mdio_read(udev, dev->phy_id, MII_BMCR);
336 if (bmcr & BMCR_ANENABLE) {
337 bmcr |= BMCR_ANRESTART;
338 smsc95xx_mdio_write(udev, dev->phy_id, MII_BMCR, bmcr);
344 static int smsc95xx_phy_initialize(struct usb_device *udev,
345 struct ueth_data *dev)
347 smsc95xx_mdio_write(udev, dev->phy_id, MII_BMCR, BMCR_RESET);
348 smsc95xx_mdio_write(udev, dev->phy_id, MII_ADVERTISE,
349 ADVERTISE_ALL | ADVERTISE_CSMA |
350 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
353 smsc95xx_mdio_read(udev, dev->phy_id, PHY_INT_SRC);
355 smsc95xx_mdio_write(udev, dev->phy_id, PHY_INT_MASK,
356 PHY_INT_MASK_DEFAULT_);
357 mii_nway_restart(udev, dev);
359 debug("phy initialised succesfully\n");
363 static int smsc95xx_init_mac_address(unsigned char *enetaddr,
364 struct usb_device *udev)
368 /* try reading mac address from EEPROM */
369 ret = smsc95xx_read_eeprom(udev, EEPROM_MAC_OFFSET, ETH_ALEN, enetaddr);
373 if (is_valid_ethaddr(enetaddr)) {
374 /* eeprom values are valid so use them */
375 debug("MAC address read from EEPROM\n");
380 * No eeprom, or eeprom values are invalid. Generating a random MAC
381 * address is not safe. Just return an error.
383 debug("Invalid MAC address read from EEPROM\n");
388 static int smsc95xx_write_hwaddr_common(struct usb_device *udev,
389 struct smsc95xx_private *priv,
390 unsigned char *enetaddr)
392 u32 addr_lo = __get_unaligned_le32(&enetaddr[0]);
393 u32 addr_hi = __get_unaligned_le16(&enetaddr[4]);
396 /* set hardware address */
397 debug("** %s()\n", __func__);
398 ret = smsc95xx_write_reg(udev, ADDRL, addr_lo);
402 ret = smsc95xx_write_reg(udev, ADDRH, addr_hi);
406 debug("MAC %pM\n", enetaddr);
407 priv->have_hwaddr = 1;
412 /* Enable or disable Tx & Rx checksum offload engines */
413 static int smsc95xx_set_csums(struct usb_device *udev, int use_tx_csum,
417 int ret = smsc95xx_read_reg(udev, COE_CR, &read_buf);
422 read_buf |= Tx_COE_EN_;
424 read_buf &= ~Tx_COE_EN_;
427 read_buf |= Rx_COE_EN_;
429 read_buf &= ~Rx_COE_EN_;
431 ret = smsc95xx_write_reg(udev, COE_CR, read_buf);
435 debug("COE_CR = 0x%08x\n", read_buf);
439 static void smsc95xx_set_multicast(struct smsc95xx_private *priv)
441 /* No multicast in u-boot */
442 priv->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
445 /* starts the TX path */
446 static void smsc95xx_start_tx_path(struct usb_device *udev,
447 struct smsc95xx_private *priv)
451 /* Enable Tx at MAC */
452 priv->mac_cr |= MAC_CR_TXEN_;
454 smsc95xx_write_reg(udev, MAC_CR, priv->mac_cr);
456 /* Enable Tx at SCSRs */
457 reg_val = TX_CFG_ON_;
458 smsc95xx_write_reg(udev, TX_CFG, reg_val);
461 /* Starts the Receive path */
462 static void smsc95xx_start_rx_path(struct usb_device *udev,
463 struct smsc95xx_private *priv)
465 priv->mac_cr |= MAC_CR_RXEN_;
466 smsc95xx_write_reg(udev, MAC_CR, priv->mac_cr);
469 static int smsc95xx_init_common(struct usb_device *udev, struct ueth_data *dev,
470 struct smsc95xx_private *priv,
471 unsigned char *enetaddr)
478 #define TIMEOUT_RESOLUTION 50 /* ms */
481 debug("** %s()\n", __func__);
482 dev->phy_id = SMSC95XX_INTERNAL_PHY_ID; /* fixed phy id */
484 write_buf = HW_CFG_LRST_;
485 ret = smsc95xx_write_reg(udev, HW_CFG, write_buf);
491 ret = smsc95xx_read_reg(udev, HW_CFG, &read_buf);
496 } while ((read_buf & HW_CFG_LRST_) && (timeout < 100));
498 if (timeout >= 100) {
499 debug("timeout waiting for completion of Lite Reset\n");
503 write_buf = PM_CTL_PHY_RST_;
504 ret = smsc95xx_write_reg(udev, PM_CTRL, write_buf);
510 ret = smsc95xx_read_reg(udev, PM_CTRL, &read_buf);
515 } while ((read_buf & PM_CTL_PHY_RST_) && (timeout < 100));
516 if (timeout >= 100) {
517 debug("timeout waiting for PHY Reset\n");
520 if (!priv->have_hwaddr && smsc95xx_init_mac_address(enetaddr, udev) ==
522 priv->have_hwaddr = 1;
523 if (!priv->have_hwaddr) {
524 puts("Error: SMSC95xx: No MAC address set - set usbethaddr\n");
525 return -EADDRNOTAVAIL;
527 ret = smsc95xx_write_hwaddr_common(udev, priv, enetaddr);
531 ret = smsc95xx_read_reg(udev, HW_CFG, &read_buf);
534 debug("Read Value from HW_CFG : 0x%08x\n", read_buf);
536 read_buf |= HW_CFG_BIR_;
537 ret = smsc95xx_write_reg(udev, HW_CFG, read_buf);
541 ret = smsc95xx_read_reg(udev, HW_CFG, &read_buf);
544 debug("Read Value from HW_CFG after writing "
545 "HW_CFG_BIR_: 0x%08x\n", read_buf);
548 if (dev->pusb_dev->speed == USB_SPEED_HIGH) {
549 burst_cap = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE;
550 priv->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE;
552 burst_cap = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE;
553 priv->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE;
557 priv->rx_urb_size = MAX_SINGLE_PACKET_SIZE;
559 debug("rx_urb_size=%ld\n", (ulong)priv->rx_urb_size);
561 ret = smsc95xx_write_reg(udev, BURST_CAP, burst_cap);
565 ret = smsc95xx_read_reg(udev, BURST_CAP, &read_buf);
568 debug("Read Value from BURST_CAP after writing: 0x%08x\n", read_buf);
570 read_buf = DEFAULT_BULK_IN_DELAY;
571 ret = smsc95xx_write_reg(udev, BULK_IN_DLY, read_buf);
575 ret = smsc95xx_read_reg(udev, BULK_IN_DLY, &read_buf);
578 debug("Read Value from BULK_IN_DLY after writing: "
579 "0x%08x\n", read_buf);
581 ret = smsc95xx_read_reg(udev, HW_CFG, &read_buf);
584 debug("Read Value from HW_CFG: 0x%08x\n", read_buf);
587 read_buf |= (HW_CFG_MEF_ | HW_CFG_BCE_);
589 read_buf &= ~HW_CFG_RXDOFF_;
591 #define NET_IP_ALIGN 0
592 read_buf |= NET_IP_ALIGN << 9;
594 ret = smsc95xx_write_reg(udev, HW_CFG, read_buf);
598 ret = smsc95xx_read_reg(udev, HW_CFG, &read_buf);
601 debug("Read Value from HW_CFG after writing: 0x%08x\n", read_buf);
603 write_buf = 0xFFFFFFFF;
604 ret = smsc95xx_write_reg(udev, INT_STS, write_buf);
608 ret = smsc95xx_read_reg(udev, ID_REV, &read_buf);
611 debug("ID_REV = 0x%08x\n", read_buf);
613 /* Configure GPIO pins as LED outputs */
614 write_buf = LED_GPIO_CFG_SPD_LED | LED_GPIO_CFG_LNK_LED |
615 LED_GPIO_CFG_FDX_LED;
616 ret = smsc95xx_write_reg(udev, LED_GPIO_CFG, write_buf);
619 debug("LED_GPIO_CFG set\n");
623 ret = smsc95xx_write_reg(udev, FLOW, write_buf);
627 read_buf = AFC_CFG_DEFAULT;
628 ret = smsc95xx_write_reg(udev, AFC_CFG, read_buf);
632 ret = smsc95xx_read_reg(udev, MAC_CR, &priv->mac_cr);
636 /* Init Rx. Set Vlan */
637 write_buf = (u32)ETH_P_8021Q;
638 ret = smsc95xx_write_reg(udev, VLAN1, write_buf);
642 /* Disable checksum offload engines */
643 ret = smsc95xx_set_csums(udev, 0, 0);
645 debug("Failed to set csum offload: %d\n", ret);
648 smsc95xx_set_multicast(priv);
650 ret = smsc95xx_phy_initialize(udev, dev);
653 ret = smsc95xx_read_reg(udev, INT_EP_CTL, &read_buf);
657 /* enable PHY interrupts */
658 read_buf |= INT_EP_CTL_PHY_INT_;
660 ret = smsc95xx_write_reg(udev, INT_EP_CTL, read_buf);
664 smsc95xx_start_tx_path(udev, priv);
665 smsc95xx_start_rx_path(udev, priv);
669 link_detected = smsc95xx_mdio_read(udev, dev->phy_id, MII_BMSR)
671 if (!link_detected) {
673 printf("Waiting for Ethernet connection... ");
674 udelay(TIMEOUT_RESOLUTION * 1000);
675 timeout += TIMEOUT_RESOLUTION;
677 } while (!link_detected && timeout < PHY_CONNECT_TIMEOUT);
682 printf("unable to connect.\n");
688 static int smsc95xx_send_common(struct ueth_data *dev, void *packet, int length)
694 ALLOC_CACHE_ALIGN_BUFFER(unsigned char, msg,
695 PKTSIZE + sizeof(tx_cmd_a) + sizeof(tx_cmd_b));
697 debug("** %s(), len %d, buf %#x\n", __func__, length, (int)msg);
698 if (length > PKTSIZE)
701 tx_cmd_a = (u32)length | TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_;
702 tx_cmd_b = (u32)length;
703 cpu_to_le32s(&tx_cmd_a);
704 cpu_to_le32s(&tx_cmd_b);
706 /* prepend cmd_a and cmd_b */
707 memcpy(msg, &tx_cmd_a, sizeof(tx_cmd_a));
708 memcpy(msg + sizeof(tx_cmd_a), &tx_cmd_b, sizeof(tx_cmd_b));
709 memcpy(msg + sizeof(tx_cmd_a) + sizeof(tx_cmd_b), (void *)packet,
711 err = usb_bulk_msg(dev->pusb_dev,
712 usb_sndbulkpipe(dev->pusb_dev, dev->ep_out),
714 length + sizeof(tx_cmd_a) + sizeof(tx_cmd_b),
716 USB_BULK_SEND_TIMEOUT);
717 debug("Tx: len = %u, actual = %u, err = %d\n",
718 length + sizeof(tx_cmd_a) + sizeof(tx_cmd_b),
724 #ifndef CONFIG_DM_ETH
728 static int smsc95xx_init(struct eth_device *eth, bd_t *bd)
730 struct ueth_data *dev = (struct ueth_data *)eth->priv;
731 struct usb_device *udev = dev->pusb_dev;
732 struct smsc95xx_private *priv =
733 (struct smsc95xx_private *)dev->dev_priv;
735 return smsc95xx_init_common(udev, dev, priv, eth->enetaddr);
738 static int smsc95xx_send(struct eth_device *eth, void *packet, int length)
740 struct ueth_data *dev = (struct ueth_data *)eth->priv;
742 return smsc95xx_send_common(dev, packet, length);
745 static int smsc95xx_recv(struct eth_device *eth)
747 struct ueth_data *dev = (struct ueth_data *)eth->priv;
748 DEFINE_CACHE_ALIGN_BUFFER(unsigned char, recv_buf, RX_URB_SIZE);
749 unsigned char *buf_ptr;
755 debug("** %s()\n", __func__);
756 err = usb_bulk_msg(dev->pusb_dev,
757 usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in),
758 (void *)recv_buf, RX_URB_SIZE, &actual_len,
759 USB_BULK_RECV_TIMEOUT);
760 debug("Rx: len = %u, actual = %u, err = %d\n", RX_URB_SIZE,
763 debug("Rx: failed to receive\n");
766 if (actual_len > RX_URB_SIZE) {
767 debug("Rx: received too many bytes %d\n", actual_len);
772 while (actual_len > 0) {
774 * 1st 4 bytes contain the length of the actual data plus error
775 * info. Extract data length.
777 if (actual_len < sizeof(packet_len)) {
778 debug("Rx: incomplete packet length\n");
781 memcpy(&packet_len, buf_ptr, sizeof(packet_len));
782 le32_to_cpus(&packet_len);
783 if (packet_len & RX_STS_ES_) {
784 debug("Rx: Error header=%#x", packet_len);
787 packet_len = ((packet_len & RX_STS_FL_) >> 16);
789 if (packet_len > actual_len - sizeof(packet_len)) {
790 debug("Rx: too large packet: %d\n", packet_len);
794 /* Notify net stack */
795 net_process_received_packet(buf_ptr + sizeof(packet_len),
798 /* Adjust for next iteration */
799 actual_len -= sizeof(packet_len) + packet_len;
800 buf_ptr += sizeof(packet_len) + packet_len;
801 cur_buf_align = (int)buf_ptr - (int)recv_buf;
803 if (cur_buf_align & 0x03) {
804 int align = 4 - (cur_buf_align & 0x03);
813 static void smsc95xx_halt(struct eth_device *eth)
815 debug("** %s()\n", __func__);
818 static int smsc95xx_write_hwaddr(struct eth_device *eth)
820 struct ueth_data *dev = eth->priv;
821 struct usb_device *udev = dev->pusb_dev;
822 struct smsc95xx_private *priv = dev->dev_priv;
824 return smsc95xx_write_hwaddr_common(udev, priv, eth->enetaddr);
828 * SMSC probing functions
830 void smsc95xx_eth_before_probe(void)
835 struct smsc95xx_dongle {
836 unsigned short vendor;
837 unsigned short product;
840 static const struct smsc95xx_dongle smsc95xx_dongles[] = {
841 { 0x0424, 0xec00 }, /* LAN9512/LAN9514 Ethernet */
842 { 0x0424, 0x9500 }, /* LAN9500 Ethernet */
843 { 0x0424, 0x9730 }, /* LAN9730 Ethernet (HSIC) */
844 { 0x0424, 0x9900 }, /* SMSC9500 USB Ethernet Device (SAL10) */
845 { 0x0424, 0x9e00 }, /* LAN9500A Ethernet */
846 { 0x0000, 0x0000 } /* END - Do not remove */
849 /* Probe to see if a new device is actually an SMSC device */
850 int smsc95xx_eth_probe(struct usb_device *dev, unsigned int ifnum,
851 struct ueth_data *ss)
853 struct usb_interface *iface;
854 struct usb_interface_descriptor *iface_desc;
857 /* let's examine the device now */
858 iface = &dev->config.if_desc[ifnum];
859 iface_desc = &dev->config.if_desc[ifnum].desc;
861 for (i = 0; smsc95xx_dongles[i].vendor != 0; i++) {
862 if (dev->descriptor.idVendor == smsc95xx_dongles[i].vendor &&
863 dev->descriptor.idProduct == smsc95xx_dongles[i].product)
864 /* Found a supported dongle */
867 if (smsc95xx_dongles[i].vendor == 0)
870 /* At this point, we know we've got a live one */
871 debug("\n\nUSB Ethernet device detected\n");
872 memset(ss, '\0', sizeof(struct ueth_data));
874 /* Initialize the ueth_data structure with some useful info */
877 ss->subclass = iface_desc->bInterfaceSubClass;
878 ss->protocol = iface_desc->bInterfaceProtocol;
881 * We are expecting a minimum of 3 endpoints - in, out (bulk), and int.
882 * We will ignore any others.
884 for (i = 0; i < iface_desc->bNumEndpoints; i++) {
885 /* is it an BULK endpoint? */
886 if ((iface->ep_desc[i].bmAttributes &
887 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK) {
888 if (iface->ep_desc[i].bEndpointAddress & USB_DIR_IN)
890 iface->ep_desc[i].bEndpointAddress &
891 USB_ENDPOINT_NUMBER_MASK;
894 iface->ep_desc[i].bEndpointAddress &
895 USB_ENDPOINT_NUMBER_MASK;
898 /* is it an interrupt endpoint? */
899 if ((iface->ep_desc[i].bmAttributes &
900 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) {
901 ss->ep_int = iface->ep_desc[i].bEndpointAddress &
902 USB_ENDPOINT_NUMBER_MASK;
903 ss->irqinterval = iface->ep_desc[i].bInterval;
906 debug("Endpoints In %d Out %d Int %d\n",
907 ss->ep_in, ss->ep_out, ss->ep_int);
909 /* Do some basic sanity checks, and bail if we find a problem */
910 if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) ||
911 !ss->ep_in || !ss->ep_out || !ss->ep_int) {
912 debug("Problems with device\n");
915 dev->privptr = (void *)ss;
917 /* alloc driver private */
918 ss->dev_priv = calloc(1, sizeof(struct smsc95xx_private));
925 int smsc95xx_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
926 struct eth_device *eth)
928 debug("** %s()\n", __func__);
930 debug("%s: missing parameter.\n", __func__);
933 sprintf(eth->name, "%s%d", SMSC95XX_BASE_NAME, curr_eth_dev++);
934 eth->init = smsc95xx_init;
935 eth->send = smsc95xx_send;
936 eth->recv = smsc95xx_recv;
937 eth->halt = smsc95xx_halt;
938 eth->write_hwaddr = smsc95xx_write_hwaddr;
942 #endif /* !CONFIG_DM_ETH */
945 static int smsc95xx_eth_start(struct udevice *dev)
947 struct usb_device *udev = dev_get_parentdata(dev);
948 struct smsc95xx_private *priv = dev_get_priv(dev);
949 struct eth_pdata *pdata = dev_get_platdata(dev);
951 /* Driver-model Ethernet ensures we have this */
952 priv->have_hwaddr = 1;
954 return smsc95xx_init_common(udev, &priv->ueth, priv, pdata->enetaddr);
957 void smsc95xx_eth_stop(struct udevice *dev)
959 debug("** %s()\n", __func__);
962 int smsc95xx_eth_send(struct udevice *dev, void *packet, int length)
964 struct smsc95xx_private *priv = dev_get_priv(dev);
966 return smsc95xx_send_common(&priv->ueth, packet, length);
969 int smsc95xx_eth_recv(struct udevice *dev, int flags, uchar **packetp)
971 struct smsc95xx_private *priv = dev_get_priv(dev);
972 struct ueth_data *ueth = &priv->ueth;
977 len = usb_ether_get_rx_bytes(ueth, &ptr);
978 debug("%s: first try, len=%d\n", __func__, len);
980 if (!(flags & ETH_RECV_CHECK_DEVICE))
982 ret = usb_ether_receive(ueth, RX_URB_SIZE);
986 len = usb_ether_get_rx_bytes(ueth, &ptr);
987 debug("%s: second try, len=%d\n", __func__, len);
991 * 1st 4 bytes contain the length of the actual data plus error info.
992 * Extract data length.
994 if (len < sizeof(packet_len)) {
995 debug("Rx: incomplete packet length\n");
998 memcpy(&packet_len, ptr, sizeof(packet_len));
999 le32_to_cpus(&packet_len);
1000 if (packet_len & RX_STS_ES_) {
1001 debug("Rx: Error header=%#x", packet_len);
1004 packet_len = ((packet_len & RX_STS_FL_) >> 16);
1006 if (packet_len > len - sizeof(packet_len)) {
1007 debug("Rx: too large packet: %d\n", packet_len);
1011 *packetp = ptr + sizeof(packet_len);
1015 usb_ether_advance_rxbuf(ueth, -1);
1019 static int smsc95xx_free_pkt(struct udevice *dev, uchar *packet, int packet_len)
1021 struct smsc95xx_private *priv = dev_get_priv(dev);
1023 packet_len = ALIGN(packet_len, 4);
1024 usb_ether_advance_rxbuf(&priv->ueth, sizeof(u32) + packet_len);
1029 int smsc95xx_write_hwaddr(struct udevice *dev)
1031 struct usb_device *udev = dev_get_parentdata(dev);
1032 struct eth_pdata *pdata = dev_get_platdata(dev);
1033 struct smsc95xx_private *priv = dev_get_priv(dev);
1035 return smsc95xx_write_hwaddr_common(udev, priv, pdata->enetaddr);
1038 static int smsc95xx_eth_probe(struct udevice *dev)
1040 struct smsc95xx_private *priv = dev_get_priv(dev);
1041 struct ueth_data *ueth = &priv->ueth;
1043 return usb_ether_register(dev, ueth, RX_URB_SIZE);
1046 static const struct eth_ops smsc95xx_eth_ops = {
1047 .start = smsc95xx_eth_start,
1048 .send = smsc95xx_eth_send,
1049 .recv = smsc95xx_eth_recv,
1050 .free_pkt = smsc95xx_free_pkt,
1051 .stop = smsc95xx_eth_stop,
1052 .write_hwaddr = smsc95xx_write_hwaddr,
1055 U_BOOT_DRIVER(smsc95xx_eth) = {
1056 .name = "smsc95xx_eth",
1058 .probe = smsc95xx_eth_probe,
1059 .ops = &smsc95xx_eth_ops,
1060 .priv_auto_alloc_size = sizeof(struct smsc95xx_private),
1061 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
1064 static const struct usb_device_id smsc95xx_eth_id_table[] = {
1065 { USB_DEVICE(0x05ac, 0x1402) },
1066 { USB_DEVICE(0x0424, 0xec00) }, /* LAN9512/LAN9514 Ethernet */
1067 { USB_DEVICE(0x0424, 0x9500) }, /* LAN9500 Ethernet */
1068 { USB_DEVICE(0x0424, 0x9730) }, /* LAN9730 Ethernet (HSIC) */
1069 { USB_DEVICE(0x0424, 0x9900) }, /* SMSC9500 USB Ethernet (SAL10) */
1070 { USB_DEVICE(0x0424, 0x9e00) }, /* LAN9500A Ethernet */
1071 { } /* Terminating entry */
1074 U_BOOT_USB_DEVICE(smsc95xx_eth, smsc95xx_eth_id_table);