2 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
3 * Copyright (C) 2010 Freescale Semiconductor, Inc.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 #include <linux/compiler.h>
20 #include <usb/ehci-fsl.h>
22 #include <asm/arch/imx-regs.h>
23 #include <asm/arch/clock.h>
24 #include <asm/arch/mx5x_pins.h>
27 #include "ehci-core.h"
29 #define MX5_USBOTHER_REGS_OFFSET 0x800
32 #define MXC_OTG_OFFSET 0
33 #define MXC_H1_OFFSET 0x200
34 #define MXC_H2_OFFSET 0x400
36 #define MXC_USBCTRL_OFFSET 0
37 #define MXC_USB_PHY_CTR_FUNC_OFFSET 0x8
38 #define MXC_USB_PHY_CTR_FUNC2_OFFSET 0xc
39 #define MXC_USB_CTRL_1_OFFSET 0x10
40 #define MXC_USBH2CTRL_OFFSET 0x14
43 #define MXC_OTG_UCTRL_OWIE_BIT (1 << 27) /* OTG wakeup intr enable */
44 #define MXC_OTG_UCTRL_OPM_BIT (1 << 24) /* OTG power mask */
45 #define MXC_H1_UCTRL_H1UIE_BIT (1 << 12) /* Host1 ULPI interrupt enable */
46 #define MXC_H1_UCTRL_H1WIE_BIT (1 << 11) /* HOST1 wakeup intr enable */
47 #define MXC_H1_UCTRL_H1PM_BIT (1 << 8) /* HOST1 power mask */
49 /* USB_PHY_CTRL_FUNC */
50 #define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable Overcurrent Event */
51 #define MXC_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event */
54 #define MXC_H2_UCTRL_H2UIE_BIT (1 << 8)
55 #define MXC_H2_UCTRL_H2WIE_BIT (1 << 7)
56 #define MXC_H2_UCTRL_H2PM_BIT (1 << 4)
59 #define MXC_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
61 int mxc_set_usbcontrol(int port, unsigned int flags)
64 void __iomem *usb_base = (void __iomem *)OTG_BASE_ADDR;
65 void __iomem *usbother_base;
68 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
71 case 0: /* OTG port */
72 if (flags & MXC_EHCI_INTERNAL_PHY) {
73 v = __raw_readl(usbother_base +
74 MXC_USB_PHY_CTR_FUNC_OFFSET);
75 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
76 /* OC/USBPWR is not used */
77 v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;
79 /* OC/USBPWR is used */
80 v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT;
81 __raw_writel(v, usbother_base +
82 MXC_USB_PHY_CTR_FUNC_OFFSET);
84 v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
85 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
86 v |= MXC_OTG_UCTRL_OPM_BIT;
88 v &= ~MXC_OTG_UCTRL_OPM_BIT;
89 __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
92 case 1: /* Host 1 Host ULPI */
94 /* The clock for the USBH1 ULPI port will come externally
96 v = __raw_readl(usbother_base + MXC_USB_CTRL_1_OFFSET);
97 __raw_writel(v | MXC_USB_CTRL_UH1_EXT_CLK_EN, usbother_base +
98 MXC_USB_CTRL_1_OFFSET);
101 v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
102 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
103 v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used */
105 v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used */
106 __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
108 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
109 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
110 v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */
112 v |= MXC_H1_OC_DIS_BIT; /* OC is not used */
113 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
116 case 2: /* Host 2 ULPI */
117 v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET);
118 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
119 v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used */
121 v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used */
123 __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);
130 int ehci_hcd_init(void)
132 struct usb_ehci *ehci;
134 struct clkctl *sc_regs = (struct clkctl *)CCM_BASE_ADDR;
137 reg = __raw_readl(&sc_regs->cscmr1) & ~(1 << 26);
138 /* derive USB PHY clock multiplexer from PLL3 */
140 __raw_writel(reg, &sc_regs->cscmr1);
144 enable_usboh3_clk(1);
146 enable_usb_phy2_clk(1);
149 /* do board specific initialization */
150 board_ehci_hcd_init(CONFIG_MXC_USB_PORT);
152 ehci = (struct usb_ehci *)(OTG_BASE_ADDR +
153 (0x200 * CONFIG_MXC_USB_PORT));
154 hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
155 hcor = (struct ehci_hcor *)((uint32_t)hccr +
156 HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
157 setbits_le32(&ehci->usbmode, CM_HOST);
159 __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
160 setbits_le32(&ehci->portsc, USB_EN);
162 mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS);
169 int ehci_hcd_stop(void)