2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <linux/usb.h>
24 #include <linux/pci.h>
25 #include <linux/slab.h>
26 #include <linux/dmapool.h>
31 * Allocates a generic ring segment from the ring pool, sets the dma address,
32 * initializes the segment to zero, and sets the private next pointer to NULL.
35 * "All components of all Command and Transfer TRBs shall be initialized to '0'"
37 static struct xhci_segment *xhci_segment_alloc(struct xhci_hcd *xhci,
38 unsigned int cycle_state, gfp_t flags)
40 struct xhci_segment *seg;
44 seg = kzalloc(sizeof *seg, flags);
48 seg->trbs = dma_pool_alloc(xhci->segment_pool, flags, &dma);
54 memset(seg->trbs, 0, SEGMENT_SIZE);
55 /* If the cycle state is 0, set the cycle bit to 1 for all the TRBs */
56 if (cycle_state == 0) {
57 for (i = 0; i < TRBS_PER_SEGMENT; i++)
58 seg->trbs[i].link.control |= TRB_CYCLE;
66 static void xhci_segment_free(struct xhci_hcd *xhci, struct xhci_segment *seg)
69 dma_pool_free(xhci->segment_pool, seg->trbs, seg->dma);
75 static void xhci_free_segments_for_ring(struct xhci_hcd *xhci,
76 struct xhci_segment *first)
78 struct xhci_segment *seg;
81 while (seg != first) {
82 struct xhci_segment *next = seg->next;
83 xhci_segment_free(xhci, seg);
86 xhci_segment_free(xhci, first);
90 * Make the prev segment point to the next segment.
92 * Change the last TRB in the prev segment to be a Link TRB which points to the
93 * DMA address of the next segment. The caller needs to set any Link TRB
94 * related flags, such as End TRB, Toggle Cycle, and no snoop.
96 static void xhci_link_segments(struct xhci_hcd *xhci, struct xhci_segment *prev,
97 struct xhci_segment *next, enum xhci_ring_type type)
104 if (type != TYPE_EVENT) {
105 prev->trbs[TRBS_PER_SEGMENT-1].link.segment_ptr =
106 cpu_to_le64(next->dma);
108 /* Set the last TRB in the segment to have a TRB type ID of Link TRB */
109 val = le32_to_cpu(prev->trbs[TRBS_PER_SEGMENT-1].link.control);
110 val &= ~TRB_TYPE_BITMASK;
111 val |= TRB_TYPE(TRB_LINK);
112 /* Always set the chain bit with 0.95 hardware */
113 /* Set chain bit for isoc rings on AMD 0.96 host */
114 if (xhci_link_trb_quirk(xhci) ||
115 (type == TYPE_ISOC &&
116 (xhci->quirks & XHCI_AMD_0x96_HOST)))
118 prev->trbs[TRBS_PER_SEGMENT-1].link.control = cpu_to_le32(val);
123 * Link the ring to the new segments.
124 * Set Toggle Cycle for the new ring if needed.
126 static void xhci_link_rings(struct xhci_hcd *xhci, struct xhci_ring *ring,
127 struct xhci_segment *first, struct xhci_segment *last,
128 unsigned int num_segs)
130 struct xhci_segment *next;
132 if (!ring || !first || !last)
135 next = ring->enq_seg->next;
136 xhci_link_segments(xhci, ring->enq_seg, first, ring->type);
137 xhci_link_segments(xhci, last, next, ring->type);
138 ring->num_segs += num_segs;
139 ring->num_trbs_free += (TRBS_PER_SEGMENT - 1) * num_segs;
141 if (ring->type != TYPE_EVENT && ring->enq_seg == ring->last_seg) {
142 ring->last_seg->trbs[TRBS_PER_SEGMENT-1].link.control
143 &= ~cpu_to_le32(LINK_TOGGLE);
144 last->trbs[TRBS_PER_SEGMENT-1].link.control
145 |= cpu_to_le32(LINK_TOGGLE);
146 ring->last_seg = last;
150 /* XXX: Do we need the hcd structure in all these functions? */
151 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring)
157 xhci_free_segments_for_ring(xhci, ring->first_seg);
162 static void xhci_initialize_ring_info(struct xhci_ring *ring,
163 unsigned int cycle_state)
165 /* The ring is empty, so the enqueue pointer == dequeue pointer */
166 ring->enqueue = ring->first_seg->trbs;
167 ring->enq_seg = ring->first_seg;
168 ring->dequeue = ring->enqueue;
169 ring->deq_seg = ring->first_seg;
170 /* The ring is initialized to 0. The producer must write 1 to the cycle
171 * bit to handover ownership of the TRB, so PCS = 1. The consumer must
172 * compare CCS to the cycle bit to check ownership, so CCS = 1.
174 * New rings are initialized with cycle state equal to 1; if we are
175 * handling ring expansion, set the cycle state equal to the old ring.
177 ring->cycle_state = cycle_state;
178 /* Not necessary for new rings, but needed for re-initialized rings */
179 ring->enq_updates = 0;
180 ring->deq_updates = 0;
183 * Each segment has a link TRB, and leave an extra TRB for SW
186 ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1;
189 /* Allocate segments and link them for a ring */
190 static int xhci_alloc_segments_for_ring(struct xhci_hcd *xhci,
191 struct xhci_segment **first, struct xhci_segment **last,
192 unsigned int num_segs, unsigned int cycle_state,
193 enum xhci_ring_type type, gfp_t flags)
195 struct xhci_segment *prev;
197 prev = xhci_segment_alloc(xhci, cycle_state, flags);
203 while (num_segs > 0) {
204 struct xhci_segment *next;
206 next = xhci_segment_alloc(xhci, cycle_state, flags);
208 xhci_free_segments_for_ring(xhci, *first);
211 xhci_link_segments(xhci, prev, next, type);
216 xhci_link_segments(xhci, prev, *first, type);
223 * Create a new ring with zero or more segments.
225 * Link each segment together into a ring.
226 * Set the end flag and the cycle toggle bit on the last segment.
227 * See section 4.9.1 and figures 15 and 16.
229 static struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci,
230 unsigned int num_segs, unsigned int cycle_state,
231 enum xhci_ring_type type, gfp_t flags)
233 struct xhci_ring *ring;
236 ring = kzalloc(sizeof *(ring), flags);
240 ring->num_segs = num_segs;
241 INIT_LIST_HEAD(&ring->td_list);
246 ret = xhci_alloc_segments_for_ring(xhci, &ring->first_seg,
247 &ring->last_seg, num_segs, cycle_state, type, flags);
251 /* Only event ring does not use link TRB */
252 if (type != TYPE_EVENT) {
253 /* See section 4.9.2.1 and 6.4.4.1 */
254 ring->last_seg->trbs[TRBS_PER_SEGMENT - 1].link.control |=
255 cpu_to_le32(LINK_TOGGLE);
257 xhci_initialize_ring_info(ring, cycle_state);
261 xhci_ring_free(xhci, ring);
265 void xhci_free_or_cache_endpoint_ring(struct xhci_hcd *xhci,
266 struct xhci_virt_device *virt_dev,
267 unsigned int ep_index)
271 rings_cached = virt_dev->num_rings_cached;
272 if (rings_cached < XHCI_MAX_RINGS_CACHED) {
273 virt_dev->ring_cache[rings_cached] =
274 virt_dev->eps[ep_index].ring;
275 virt_dev->num_rings_cached++;
276 xhci_dbg(xhci, "Cached old ring, "
277 "%d ring%s cached\n",
278 virt_dev->num_rings_cached,
279 (virt_dev->num_rings_cached > 1) ? "s" : "");
281 xhci_ring_free(xhci, virt_dev->eps[ep_index].ring);
282 xhci_dbg(xhci, "Ring cache full (%d rings), "
284 virt_dev->num_rings_cached);
286 virt_dev->eps[ep_index].ring = NULL;
289 /* Zero an endpoint ring (except for link TRBs) and move the enqueue and dequeue
290 * pointers to the beginning of the ring.
292 static void xhci_reinit_cached_ring(struct xhci_hcd *xhci,
293 struct xhci_ring *ring, unsigned int cycle_state,
294 enum xhci_ring_type type)
296 struct xhci_segment *seg = ring->first_seg;
301 sizeof(union xhci_trb)*TRBS_PER_SEGMENT);
302 if (cycle_state == 0) {
303 for (i = 0; i < TRBS_PER_SEGMENT; i++)
304 seg->trbs[i].link.control |= TRB_CYCLE;
306 /* All endpoint rings have link TRBs */
307 xhci_link_segments(xhci, seg, seg->next, type);
309 } while (seg != ring->first_seg);
311 xhci_initialize_ring_info(ring, cycle_state);
312 /* td list should be empty since all URBs have been cancelled,
313 * but just in case...
315 INIT_LIST_HEAD(&ring->td_list);
319 * Expand an existing ring.
320 * Look for a cached ring or allocate a new ring which has same segment numbers
321 * and link the two rings.
323 int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring,
324 unsigned int num_trbs, gfp_t flags)
326 struct xhci_segment *first;
327 struct xhci_segment *last;
328 unsigned int num_segs;
329 unsigned int num_segs_needed;
332 num_segs_needed = (num_trbs + (TRBS_PER_SEGMENT - 1) - 1) /
333 (TRBS_PER_SEGMENT - 1);
335 /* Allocate number of segments we needed, or double the ring size */
336 num_segs = ring->num_segs > num_segs_needed ?
337 ring->num_segs : num_segs_needed;
339 ret = xhci_alloc_segments_for_ring(xhci, &first, &last,
340 num_segs, ring->cycle_state, ring->type, flags);
344 xhci_link_rings(xhci, ring, first, last, num_segs);
345 xhci_dbg(xhci, "ring expansion succeed, now has %d segments\n",
351 #define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32)
353 static struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci,
354 int type, gfp_t flags)
356 struct xhci_container_ctx *ctx = kzalloc(sizeof(*ctx), flags);
360 BUG_ON((type != XHCI_CTX_TYPE_DEVICE) && (type != XHCI_CTX_TYPE_INPUT));
362 ctx->size = HCC_64BYTE_CONTEXT(xhci->hcc_params) ? 2048 : 1024;
363 if (type == XHCI_CTX_TYPE_INPUT)
364 ctx->size += CTX_SIZE(xhci->hcc_params);
366 ctx->bytes = dma_pool_alloc(xhci->device_pool, flags, &ctx->dma);
367 memset(ctx->bytes, 0, ctx->size);
371 static void xhci_free_container_ctx(struct xhci_hcd *xhci,
372 struct xhci_container_ctx *ctx)
376 dma_pool_free(xhci->device_pool, ctx->bytes, ctx->dma);
380 struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_hcd *xhci,
381 struct xhci_container_ctx *ctx)
383 BUG_ON(ctx->type != XHCI_CTX_TYPE_INPUT);
384 return (struct xhci_input_control_ctx *)ctx->bytes;
387 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci,
388 struct xhci_container_ctx *ctx)
390 if (ctx->type == XHCI_CTX_TYPE_DEVICE)
391 return (struct xhci_slot_ctx *)ctx->bytes;
393 return (struct xhci_slot_ctx *)
394 (ctx->bytes + CTX_SIZE(xhci->hcc_params));
397 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci,
398 struct xhci_container_ctx *ctx,
399 unsigned int ep_index)
401 /* increment ep index by offset of start of ep ctx array */
403 if (ctx->type == XHCI_CTX_TYPE_INPUT)
406 return (struct xhci_ep_ctx *)
407 (ctx->bytes + (ep_index * CTX_SIZE(xhci->hcc_params)));
411 /***************** Streams structures manipulation *************************/
413 static void xhci_free_stream_ctx(struct xhci_hcd *xhci,
414 unsigned int num_stream_ctxs,
415 struct xhci_stream_ctx *stream_ctx, dma_addr_t dma)
417 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
419 if (num_stream_ctxs > MEDIUM_STREAM_ARRAY_SIZE)
420 dma_free_coherent(&pdev->dev,
421 sizeof(struct xhci_stream_ctx)*num_stream_ctxs,
423 else if (num_stream_ctxs <= SMALL_STREAM_ARRAY_SIZE)
424 return dma_pool_free(xhci->small_streams_pool,
427 return dma_pool_free(xhci->medium_streams_pool,
432 * The stream context array for each endpoint with bulk streams enabled can
433 * vary in size, based on:
434 * - how many streams the endpoint supports,
435 * - the maximum primary stream array size the host controller supports,
436 * - and how many streams the device driver asks for.
438 * The stream context array must be a power of 2, and can be as small as
439 * 64 bytes or as large as 1MB.
441 static struct xhci_stream_ctx *xhci_alloc_stream_ctx(struct xhci_hcd *xhci,
442 unsigned int num_stream_ctxs, dma_addr_t *dma,
445 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
447 if (num_stream_ctxs > MEDIUM_STREAM_ARRAY_SIZE)
448 return dma_alloc_coherent(&pdev->dev,
449 sizeof(struct xhci_stream_ctx)*num_stream_ctxs,
451 else if (num_stream_ctxs <= SMALL_STREAM_ARRAY_SIZE)
452 return dma_pool_alloc(xhci->small_streams_pool,
455 return dma_pool_alloc(xhci->medium_streams_pool,
459 struct xhci_ring *xhci_dma_to_transfer_ring(
460 struct xhci_virt_ep *ep,
463 if (ep->ep_state & EP_HAS_STREAMS)
464 return radix_tree_lookup(&ep->stream_info->trb_address_map,
465 address >> SEGMENT_SHIFT);
469 /* Only use this when you know stream_info is valid */
470 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
471 static struct xhci_ring *dma_to_stream_ring(
472 struct xhci_stream_info *stream_info,
475 return radix_tree_lookup(&stream_info->trb_address_map,
476 address >> SEGMENT_SHIFT);
478 #endif /* CONFIG_USB_XHCI_HCD_DEBUGGING */
480 struct xhci_ring *xhci_stream_id_to_ring(
481 struct xhci_virt_device *dev,
482 unsigned int ep_index,
483 unsigned int stream_id)
485 struct xhci_virt_ep *ep = &dev->eps[ep_index];
489 if (!ep->stream_info)
492 if (stream_id > ep->stream_info->num_streams)
494 return ep->stream_info->stream_rings[stream_id];
497 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
498 static int xhci_test_radix_tree(struct xhci_hcd *xhci,
499 unsigned int num_streams,
500 struct xhci_stream_info *stream_info)
503 struct xhci_ring *cur_ring;
506 for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
507 struct xhci_ring *mapped_ring;
508 int trb_size = sizeof(union xhci_trb);
510 cur_ring = stream_info->stream_rings[cur_stream];
511 for (addr = cur_ring->first_seg->dma;
512 addr < cur_ring->first_seg->dma + SEGMENT_SIZE;
514 mapped_ring = dma_to_stream_ring(stream_info, addr);
515 if (cur_ring != mapped_ring) {
516 xhci_warn(xhci, "WARN: DMA address 0x%08llx "
517 "didn't map to stream ID %u; "
518 "mapped to ring %p\n",
519 (unsigned long long) addr,
525 /* One TRB after the end of the ring segment shouldn't return a
526 * pointer to the current ring (although it may be a part of a
529 mapped_ring = dma_to_stream_ring(stream_info, addr);
530 if (mapped_ring != cur_ring) {
531 /* One TRB before should also fail */
532 addr = cur_ring->first_seg->dma - trb_size;
533 mapped_ring = dma_to_stream_ring(stream_info, addr);
535 if (mapped_ring == cur_ring) {
536 xhci_warn(xhci, "WARN: Bad DMA address 0x%08llx "
537 "mapped to valid stream ID %u; "
538 "mapped ring = %p\n",
539 (unsigned long long) addr,
547 #endif /* CONFIG_USB_XHCI_HCD_DEBUGGING */
550 * Change an endpoint's internal structure so it supports stream IDs. The
551 * number of requested streams includes stream 0, which cannot be used by device
554 * The number of stream contexts in the stream context array may be bigger than
555 * the number of streams the driver wants to use. This is because the number of
556 * stream context array entries must be a power of two.
558 * We need a radix tree for mapping physical addresses of TRBs to which stream
559 * ID they belong to. We need to do this because the host controller won't tell
560 * us which stream ring the TRB came from. We could store the stream ID in an
561 * event data TRB, but that doesn't help us for the cancellation case, since the
562 * endpoint may stop before it reaches that event data TRB.
564 * The radix tree maps the upper portion of the TRB DMA address to a ring
565 * segment that has the same upper portion of DMA addresses. For example, say I
566 * have segments of size 1KB, that are always 64-byte aligned. A segment may
567 * start at 0x10c91000 and end at 0x10c913f0. If I use the upper 10 bits, the
568 * key to the stream ID is 0x43244. I can use the DMA address of the TRB to
569 * pass the radix tree a key to get the right stream ID:
571 * 0x10c90fff >> 10 = 0x43243
572 * 0x10c912c0 >> 10 = 0x43244
573 * 0x10c91400 >> 10 = 0x43245
575 * Obviously, only those TRBs with DMA addresses that are within the segment
576 * will make the radix tree return the stream ID for that ring.
578 * Caveats for the radix tree:
580 * The radix tree uses an unsigned long as a key pair. On 32-bit systems, an
581 * unsigned long will be 32-bits; on a 64-bit system an unsigned long will be
582 * 64-bits. Since we only request 32-bit DMA addresses, we can use that as the
583 * key on 32-bit or 64-bit systems (it would also be fine if we asked for 64-bit
584 * PCI DMA addresses on a 64-bit system). There might be a problem on 32-bit
585 * extended systems (where the DMA address can be bigger than 32-bits),
586 * if we allow the PCI dma mask to be bigger than 32-bits. So don't do that.
588 struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
589 unsigned int num_stream_ctxs,
590 unsigned int num_streams, gfp_t mem_flags)
592 struct xhci_stream_info *stream_info;
594 struct xhci_ring *cur_ring;
599 xhci_dbg(xhci, "Allocating %u streams and %u "
600 "stream context array entries.\n",
601 num_streams, num_stream_ctxs);
602 if (xhci->cmd_ring_reserved_trbs == MAX_RSVD_CMD_TRBS) {
603 xhci_dbg(xhci, "Command ring has no reserved TRBs available\n");
606 xhci->cmd_ring_reserved_trbs++;
608 stream_info = kzalloc(sizeof(struct xhci_stream_info), mem_flags);
612 stream_info->num_streams = num_streams;
613 stream_info->num_stream_ctxs = num_stream_ctxs;
615 /* Initialize the array of virtual pointers to stream rings. */
616 stream_info->stream_rings = kzalloc(
617 sizeof(struct xhci_ring *)*num_streams,
619 if (!stream_info->stream_rings)
622 /* Initialize the array of DMA addresses for stream rings for the HW. */
623 stream_info->stream_ctx_array = xhci_alloc_stream_ctx(xhci,
624 num_stream_ctxs, &stream_info->ctx_array_dma,
626 if (!stream_info->stream_ctx_array)
628 memset(stream_info->stream_ctx_array, 0,
629 sizeof(struct xhci_stream_ctx)*num_stream_ctxs);
631 /* Allocate everything needed to free the stream rings later */
632 stream_info->free_streams_command =
633 xhci_alloc_command(xhci, true, true, mem_flags);
634 if (!stream_info->free_streams_command)
637 INIT_RADIX_TREE(&stream_info->trb_address_map, GFP_ATOMIC);
639 /* Allocate rings for all the streams that the driver will use,
640 * and add their segment DMA addresses to the radix tree.
641 * Stream 0 is reserved.
643 for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
644 stream_info->stream_rings[cur_stream] =
645 xhci_ring_alloc(xhci, 2, 1, TYPE_STREAM, mem_flags);
646 cur_ring = stream_info->stream_rings[cur_stream];
649 cur_ring->stream_id = cur_stream;
650 /* Set deq ptr, cycle bit, and stream context type */
651 addr = cur_ring->first_seg->dma |
652 SCT_FOR_CTX(SCT_PRI_TR) |
653 cur_ring->cycle_state;
654 stream_info->stream_ctx_array[cur_stream].stream_ring =
656 xhci_dbg(xhci, "Setting stream %d ring ptr to 0x%08llx\n",
657 cur_stream, (unsigned long long) addr);
659 key = (unsigned long)
660 (cur_ring->first_seg->dma >> SEGMENT_SHIFT);
661 ret = radix_tree_insert(&stream_info->trb_address_map,
664 xhci_ring_free(xhci, cur_ring);
665 stream_info->stream_rings[cur_stream] = NULL;
669 /* Leave the other unused stream ring pointers in the stream context
670 * array initialized to zero. This will cause the xHC to give us an
671 * error if the device asks for a stream ID we don't have setup (if it
672 * was any other way, the host controller would assume the ring is
673 * "empty" and wait forever for data to be queued to that stream ID).
676 /* Do a little test on the radix tree to make sure it returns the
679 if (xhci_test_radix_tree(xhci, num_streams, stream_info))
686 for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
687 cur_ring = stream_info->stream_rings[cur_stream];
689 addr = cur_ring->first_seg->dma;
690 radix_tree_delete(&stream_info->trb_address_map,
691 addr >> SEGMENT_SHIFT);
692 xhci_ring_free(xhci, cur_ring);
693 stream_info->stream_rings[cur_stream] = NULL;
696 xhci_free_command(xhci, stream_info->free_streams_command);
698 kfree(stream_info->stream_rings);
702 xhci->cmd_ring_reserved_trbs--;
706 * Sets the MaxPStreams field and the Linear Stream Array field.
707 * Sets the dequeue pointer to the stream context array.
709 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
710 struct xhci_ep_ctx *ep_ctx,
711 struct xhci_stream_info *stream_info)
713 u32 max_primary_streams;
714 /* MaxPStreams is the number of stream context array entries, not the
715 * number we're actually using. Must be in 2^(MaxPstreams + 1) format.
716 * fls(0) = 0, fls(0x1) = 1, fls(0x10) = 2, fls(0x100) = 3, etc.
718 max_primary_streams = fls(stream_info->num_stream_ctxs) - 2;
719 xhci_dbg(xhci, "Setting number of stream ctx array entries to %u\n",
720 1 << (max_primary_streams + 1));
721 ep_ctx->ep_info &= cpu_to_le32(~EP_MAXPSTREAMS_MASK);
722 ep_ctx->ep_info |= cpu_to_le32(EP_MAXPSTREAMS(max_primary_streams)
724 ep_ctx->deq = cpu_to_le64(stream_info->ctx_array_dma);
728 * Sets the MaxPStreams field and the Linear Stream Array field to 0.
729 * Reinstalls the "normal" endpoint ring (at its previous dequeue mark,
730 * not at the beginning of the ring).
732 void xhci_setup_no_streams_ep_input_ctx(struct xhci_hcd *xhci,
733 struct xhci_ep_ctx *ep_ctx,
734 struct xhci_virt_ep *ep)
737 ep_ctx->ep_info &= cpu_to_le32(~(EP_MAXPSTREAMS_MASK | EP_HAS_LSA));
738 addr = xhci_trb_virt_to_dma(ep->ring->deq_seg, ep->ring->dequeue);
739 ep_ctx->deq = cpu_to_le64(addr | ep->ring->cycle_state);
742 /* Frees all stream contexts associated with the endpoint,
744 * Caller should fix the endpoint context streams fields.
746 void xhci_free_stream_info(struct xhci_hcd *xhci,
747 struct xhci_stream_info *stream_info)
750 struct xhci_ring *cur_ring;
756 for (cur_stream = 1; cur_stream < stream_info->num_streams;
758 cur_ring = stream_info->stream_rings[cur_stream];
760 addr = cur_ring->first_seg->dma;
761 radix_tree_delete(&stream_info->trb_address_map,
762 addr >> SEGMENT_SHIFT);
763 xhci_ring_free(xhci, cur_ring);
764 stream_info->stream_rings[cur_stream] = NULL;
767 xhci_free_command(xhci, stream_info->free_streams_command);
768 xhci->cmd_ring_reserved_trbs--;
769 if (stream_info->stream_ctx_array)
770 xhci_free_stream_ctx(xhci,
771 stream_info->num_stream_ctxs,
772 stream_info->stream_ctx_array,
773 stream_info->ctx_array_dma);
776 kfree(stream_info->stream_rings);
781 /***************** Device context manipulation *************************/
783 static void xhci_init_endpoint_timer(struct xhci_hcd *xhci,
784 struct xhci_virt_ep *ep)
786 init_timer(&ep->stop_cmd_timer);
787 ep->stop_cmd_timer.data = (unsigned long) ep;
788 ep->stop_cmd_timer.function = xhci_stop_endpoint_command_watchdog;
792 static void xhci_free_tt_info(struct xhci_hcd *xhci,
793 struct xhci_virt_device *virt_dev,
796 struct list_head *tt;
797 struct list_head *tt_list_head;
798 struct list_head *tt_next;
799 struct xhci_tt_bw_info *tt_info;
801 /* If the device never made it past the Set Address stage,
802 * it may not have the real_port set correctly.
804 if (virt_dev->real_port == 0 ||
805 virt_dev->real_port > HCS_MAX_PORTS(xhci->hcs_params1)) {
806 xhci_dbg(xhci, "Bad real port.\n");
810 tt_list_head = &(xhci->rh_bw[virt_dev->real_port - 1].tts);
811 if (list_empty(tt_list_head))
814 list_for_each(tt, tt_list_head) {
815 tt_info = list_entry(tt, struct xhci_tt_bw_info, tt_list);
816 if (tt_info->slot_id == slot_id)
819 /* Cautionary measure in case the hub was disconnected before we
820 * stored the TT information.
822 if (tt_info->slot_id != slot_id)
826 tt_info = list_entry(tt, struct xhci_tt_bw_info,
828 /* Multi-TT hubs will have more than one entry */
833 if (list_empty(tt_list_head))
836 tt_info = list_entry(tt, struct xhci_tt_bw_info,
838 } while (tt_info->slot_id == slot_id);
841 int xhci_alloc_tt_info(struct xhci_hcd *xhci,
842 struct xhci_virt_device *virt_dev,
843 struct usb_device *hdev,
844 struct usb_tt *tt, gfp_t mem_flags)
846 struct xhci_tt_bw_info *tt_info;
847 unsigned int num_ports;
853 num_ports = hdev->maxchild;
855 for (i = 0; i < num_ports; i++, tt_info++) {
856 struct xhci_interval_bw_table *bw_table;
858 tt_info = kzalloc(sizeof(*tt_info), mem_flags);
861 INIT_LIST_HEAD(&tt_info->tt_list);
862 list_add(&tt_info->tt_list,
863 &xhci->rh_bw[virt_dev->real_port - 1].tts);
864 tt_info->slot_id = virt_dev->udev->slot_id;
866 tt_info->ttport = i+1;
867 bw_table = &tt_info->bw_table;
868 for (j = 0; j < XHCI_MAX_INTERVAL; j++)
869 INIT_LIST_HEAD(&bw_table->interval_bw[j].endpoints);
874 xhci_free_tt_info(xhci, virt_dev, virt_dev->udev->slot_id);
879 /* All the xhci_tds in the ring's TD list should be freed at this point.
880 * Should be called with xhci->lock held if there is any chance the TT lists
881 * will be manipulated by the configure endpoint, allocate device, or update
882 * hub functions while this function is removing the TT entries from the list.
884 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id)
886 struct xhci_virt_device *dev;
888 int old_active_eps = 0;
890 /* Slot ID 0 is reserved */
891 if (slot_id == 0 || !xhci->devs[slot_id])
894 dev = xhci->devs[slot_id];
895 xhci->dcbaa->dev_context_ptrs[slot_id] = 0;
900 old_active_eps = dev->tt_info->active_eps;
902 for (i = 0; i < 31; ++i) {
903 if (dev->eps[i].ring)
904 xhci_ring_free(xhci, dev->eps[i].ring);
905 if (dev->eps[i].stream_info)
906 xhci_free_stream_info(xhci,
907 dev->eps[i].stream_info);
908 /* Endpoints on the TT/root port lists should have been removed
909 * when usb_disable_device() was called for the device.
910 * We can't drop them anyway, because the udev might have gone
911 * away by this point, and we can't tell what speed it was.
913 if (!list_empty(&dev->eps[i].bw_endpoint_list))
914 xhci_warn(xhci, "Slot %u endpoint %u "
915 "not removed from BW list!\n",
918 /* If this is a hub, free the TT(s) from the TT list */
919 xhci_free_tt_info(xhci, dev, slot_id);
920 /* If necessary, update the number of active TTs on this root port */
921 xhci_update_tt_active_eps(xhci, dev, old_active_eps);
923 if (dev->ring_cache) {
924 for (i = 0; i < dev->num_rings_cached; i++)
925 xhci_ring_free(xhci, dev->ring_cache[i]);
926 kfree(dev->ring_cache);
930 xhci_free_container_ctx(xhci, dev->in_ctx);
932 xhci_free_container_ctx(xhci, dev->out_ctx);
934 kfree(xhci->devs[slot_id]);
935 xhci->devs[slot_id] = NULL;
938 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id,
939 struct usb_device *udev, gfp_t flags)
941 struct xhci_virt_device *dev;
944 /* Slot ID 0 is reserved */
945 if (slot_id == 0 || xhci->devs[slot_id]) {
946 xhci_warn(xhci, "Bad Slot ID %d\n", slot_id);
950 xhci->devs[slot_id] = kzalloc(sizeof(*xhci->devs[slot_id]), flags);
951 if (!xhci->devs[slot_id])
953 dev = xhci->devs[slot_id];
955 /* Allocate the (output) device context that will be used in the HC. */
956 dev->out_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_DEVICE, flags);
960 xhci_dbg(xhci, "Slot %d output ctx = 0x%llx (dma)\n", slot_id,
961 (unsigned long long)dev->out_ctx->dma);
963 /* Allocate the (input) device context for address device command */
964 dev->in_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT, flags);
968 xhci_dbg(xhci, "Slot %d input ctx = 0x%llx (dma)\n", slot_id,
969 (unsigned long long)dev->in_ctx->dma);
971 /* Initialize the cancellation list and watchdog timers for each ep */
972 for (i = 0; i < 31; i++) {
973 xhci_init_endpoint_timer(xhci, &dev->eps[i]);
974 INIT_LIST_HEAD(&dev->eps[i].cancelled_td_list);
975 INIT_LIST_HEAD(&dev->eps[i].bw_endpoint_list);
978 /* Allocate endpoint 0 ring */
979 dev->eps[0].ring = xhci_ring_alloc(xhci, 2, 1, TYPE_CTRL, flags);
980 if (!dev->eps[0].ring)
983 /* Allocate pointers to the ring cache */
984 dev->ring_cache = kzalloc(
985 sizeof(struct xhci_ring *)*XHCI_MAX_RINGS_CACHED,
987 if (!dev->ring_cache)
989 dev->num_rings_cached = 0;
991 init_completion(&dev->cmd_completion);
992 INIT_LIST_HEAD(&dev->cmd_list);
995 /* Point to output device context in dcbaa. */
996 xhci->dcbaa->dev_context_ptrs[slot_id] = cpu_to_le64(dev->out_ctx->dma);
997 xhci_dbg(xhci, "Set slot id %d dcbaa entry %p to 0x%llx\n",
999 &xhci->dcbaa->dev_context_ptrs[slot_id],
1000 le64_to_cpu(xhci->dcbaa->dev_context_ptrs[slot_id]));
1004 xhci_free_virt_device(xhci, slot_id);
1008 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
1009 struct usb_device *udev)
1011 struct xhci_virt_device *virt_dev;
1012 struct xhci_ep_ctx *ep0_ctx;
1013 struct xhci_ring *ep_ring;
1015 virt_dev = xhci->devs[udev->slot_id];
1016 ep0_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, 0);
1017 ep_ring = virt_dev->eps[0].ring;
1019 * FIXME we don't keep track of the dequeue pointer very well after a
1020 * Set TR dequeue pointer, so we're setting the dequeue pointer of the
1021 * host to our enqueue pointer. This should only be called after a
1022 * configured device has reset, so all control transfers should have
1023 * been completed or cancelled before the reset.
1025 ep0_ctx->deq = cpu_to_le64(xhci_trb_virt_to_dma(ep_ring->enq_seg,
1027 | ep_ring->cycle_state);
1031 * The xHCI roothub may have ports of differing speeds in any order in the port
1032 * status registers. xhci->port_array provides an array of the port speed for
1033 * each offset into the port status registers.
1035 * The xHCI hardware wants to know the roothub port number that the USB device
1036 * is attached to (or the roothub port its ancestor hub is attached to). All we
1037 * know is the index of that port under either the USB 2.0 or the USB 3.0
1038 * roothub, but that doesn't give us the real index into the HW port status
1039 * registers. Scan through the xHCI roothub port array, looking for the Nth
1040 * entry of the correct port speed. Return the port number of that entry.
1042 static u32 xhci_find_real_port_number(struct xhci_hcd *xhci,
1043 struct usb_device *udev)
1045 struct usb_device *top_dev;
1046 unsigned int num_similar_speed_ports;
1047 unsigned int faked_port_num;
1050 for (top_dev = udev; top_dev->parent && top_dev->parent->parent;
1051 top_dev = top_dev->parent)
1052 /* Found device below root hub */;
1053 faked_port_num = top_dev->portnum;
1054 for (i = 0, num_similar_speed_ports = 0;
1055 i < HCS_MAX_PORTS(xhci->hcs_params1); i++) {
1056 u8 port_speed = xhci->port_array[i];
1059 * Skip ports that don't have known speeds, or have duplicate
1060 * Extended Capabilities port speed entries.
1062 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
1066 * USB 3.0 ports are always under a USB 3.0 hub. USB 2.0 and
1067 * 1.1 ports are under the USB 2.0 hub. If the port speed
1068 * matches the device speed, it's a similar speed port.
1070 if ((port_speed == 0x03) == (udev->speed == USB_SPEED_SUPER))
1071 num_similar_speed_ports++;
1072 if (num_similar_speed_ports == faked_port_num)
1073 /* Roothub ports are numbered from 1 to N */
1079 /* Setup an xHCI virtual device for a Set Address command */
1080 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev)
1082 struct xhci_virt_device *dev;
1083 struct xhci_ep_ctx *ep0_ctx;
1084 struct xhci_slot_ctx *slot_ctx;
1086 struct usb_device *top_dev;
1088 dev = xhci->devs[udev->slot_id];
1089 /* Slot ID 0 is reserved */
1090 if (udev->slot_id == 0 || !dev) {
1091 xhci_warn(xhci, "Slot ID %d is not assigned to this device\n",
1095 ep0_ctx = xhci_get_ep_ctx(xhci, dev->in_ctx, 0);
1096 slot_ctx = xhci_get_slot_ctx(xhci, dev->in_ctx);
1098 /* 3) Only the control endpoint is valid - one endpoint context */
1099 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1) | udev->route);
1100 switch (udev->speed) {
1101 case USB_SPEED_SUPER:
1102 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_SS);
1104 case USB_SPEED_HIGH:
1105 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_HS);
1107 case USB_SPEED_FULL:
1108 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_FS);
1111 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_LS);
1113 case USB_SPEED_WIRELESS:
1114 xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n");
1118 /* Speed was set earlier, this shouldn't happen. */
1121 /* Find the root hub port this device is under */
1122 port_num = xhci_find_real_port_number(xhci, udev);
1125 slot_ctx->dev_info2 |= cpu_to_le32(ROOT_HUB_PORT(port_num));
1126 /* Set the port number in the virtual_device to the faked port number */
1127 for (top_dev = udev; top_dev->parent && top_dev->parent->parent;
1128 top_dev = top_dev->parent)
1129 /* Found device below root hub */;
1130 dev->fake_port = top_dev->portnum;
1131 dev->real_port = port_num;
1132 xhci_dbg(xhci, "Set root hub portnum to %d\n", port_num);
1133 xhci_dbg(xhci, "Set fake root hub portnum to %d\n", dev->fake_port);
1135 /* Find the right bandwidth table that this device will be a part of.
1136 * If this is a full speed device attached directly to a root port (or a
1137 * decendent of one), it counts as a primary bandwidth domain, not a
1138 * secondary bandwidth domain under a TT. An xhci_tt_info structure
1139 * will never be created for the HS root hub.
1141 if (!udev->tt || !udev->tt->hub->parent) {
1142 dev->bw_table = &xhci->rh_bw[port_num - 1].bw_table;
1144 struct xhci_root_port_bw_info *rh_bw;
1145 struct xhci_tt_bw_info *tt_bw;
1147 rh_bw = &xhci->rh_bw[port_num - 1];
1148 /* Find the right TT. */
1149 list_for_each_entry(tt_bw, &rh_bw->tts, tt_list) {
1150 if (tt_bw->slot_id != udev->tt->hub->slot_id)
1153 if (!dev->udev->tt->multi ||
1155 tt_bw->ttport == dev->udev->ttport)) {
1156 dev->bw_table = &tt_bw->bw_table;
1157 dev->tt_info = tt_bw;
1162 xhci_warn(xhci, "WARN: Didn't find a matching TT\n");
1165 /* Is this a LS/FS device under an external HS hub? */
1166 if (udev->tt && udev->tt->hub->parent) {
1167 slot_ctx->tt_info = cpu_to_le32(udev->tt->hub->slot_id |
1168 (udev->ttport << 8));
1169 if (udev->tt->multi)
1170 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
1172 xhci_dbg(xhci, "udev->tt = %p\n", udev->tt);
1173 xhci_dbg(xhci, "udev->ttport = 0x%x\n", udev->ttport);
1175 /* Step 4 - ring already allocated */
1177 ep0_ctx->ep_info2 = cpu_to_le32(EP_TYPE(CTRL_EP));
1179 * XXX: Not sure about wireless USB devices.
1181 switch (udev->speed) {
1182 case USB_SPEED_SUPER:
1183 ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(512));
1185 case USB_SPEED_HIGH:
1186 /* USB core guesses at a 64-byte max packet first for FS devices */
1187 case USB_SPEED_FULL:
1188 ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(64));
1191 ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(8));
1193 case USB_SPEED_WIRELESS:
1194 xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n");
1201 /* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */
1202 ep0_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(0) | ERROR_COUNT(3));
1204 ep0_ctx->deq = cpu_to_le64(dev->eps[0].ring->first_seg->dma |
1205 dev->eps[0].ring->cycle_state);
1207 /* Steps 7 and 8 were done in xhci_alloc_virt_device() */
1213 * Convert interval expressed as 2^(bInterval - 1) == interval into
1214 * straight exponent value 2^n == interval.
1217 static unsigned int xhci_parse_exponent_interval(struct usb_device *udev,
1218 struct usb_host_endpoint *ep)
1220 unsigned int interval;
1222 interval = clamp_val(ep->desc.bInterval, 1, 16) - 1;
1223 if (interval != ep->desc.bInterval - 1)
1224 dev_warn(&udev->dev,
1225 "ep %#x - rounding interval to %d %sframes\n",
1226 ep->desc.bEndpointAddress,
1228 udev->speed == USB_SPEED_FULL ? "" : "micro");
1230 if (udev->speed == USB_SPEED_FULL) {
1232 * Full speed isoc endpoints specify interval in frames,
1233 * not microframes. We are using microframes everywhere,
1234 * so adjust accordingly.
1236 interval += 3; /* 1 frame = 2^3 uframes */
1243 * Convert bInterval expressed in microframes (in 1-255 range) to exponent of
1244 * microframes, rounded down to nearest power of 2.
1246 static unsigned int xhci_microframes_to_exponent(struct usb_device *udev,
1247 struct usb_host_endpoint *ep, unsigned int desc_interval,
1248 unsigned int min_exponent, unsigned int max_exponent)
1250 unsigned int interval;
1252 interval = fls(desc_interval) - 1;
1253 interval = clamp_val(interval, min_exponent, max_exponent);
1254 if ((1 << interval) != desc_interval)
1255 dev_warn(&udev->dev,
1256 "ep %#x - rounding interval to %d microframes, ep desc says %d microframes\n",
1257 ep->desc.bEndpointAddress,
1264 static unsigned int xhci_parse_microframe_interval(struct usb_device *udev,
1265 struct usb_host_endpoint *ep)
1267 return xhci_microframes_to_exponent(udev, ep,
1268 ep->desc.bInterval, 0, 15);
1272 static unsigned int xhci_parse_frame_interval(struct usb_device *udev,
1273 struct usb_host_endpoint *ep)
1275 return xhci_microframes_to_exponent(udev, ep,
1276 ep->desc.bInterval * 8, 3, 10);
1279 /* Return the polling or NAK interval.
1281 * The polling interval is expressed in "microframes". If xHCI's Interval field
1282 * is set to N, it will service the endpoint every 2^(Interval)*125us.
1284 * The NAK interval is one NAK per 1 to 255 microframes, or no NAKs if interval
1287 static unsigned int xhci_get_endpoint_interval(struct usb_device *udev,
1288 struct usb_host_endpoint *ep)
1290 unsigned int interval = 0;
1292 switch (udev->speed) {
1293 case USB_SPEED_HIGH:
1295 if (usb_endpoint_xfer_control(&ep->desc) ||
1296 usb_endpoint_xfer_bulk(&ep->desc)) {
1297 interval = xhci_parse_microframe_interval(udev, ep);
1300 /* Fall through - SS and HS isoc/int have same decoding */
1302 case USB_SPEED_SUPER:
1303 if (usb_endpoint_xfer_int(&ep->desc) ||
1304 usb_endpoint_xfer_isoc(&ep->desc)) {
1305 interval = xhci_parse_exponent_interval(udev, ep);
1309 case USB_SPEED_FULL:
1310 if (usb_endpoint_xfer_isoc(&ep->desc)) {
1311 interval = xhci_parse_exponent_interval(udev, ep);
1315 * Fall through for interrupt endpoint interval decoding
1316 * since it uses the same rules as low speed interrupt
1321 if (usb_endpoint_xfer_int(&ep->desc) ||
1322 usb_endpoint_xfer_isoc(&ep->desc)) {
1324 interval = xhci_parse_frame_interval(udev, ep);
1331 return EP_INTERVAL(interval);
1334 /* The "Mult" field in the endpoint context is only set for SuperSpeed isoc eps.
1335 * High speed endpoint descriptors can define "the number of additional
1336 * transaction opportunities per microframe", but that goes in the Max Burst
1337 * endpoint context field.
1339 static u32 xhci_get_endpoint_mult(struct usb_device *udev,
1340 struct usb_host_endpoint *ep)
1342 if (udev->speed != USB_SPEED_SUPER ||
1343 !usb_endpoint_xfer_isoc(&ep->desc))
1345 return ep->ss_ep_comp.bmAttributes;
1348 static u32 xhci_get_endpoint_type(struct usb_device *udev,
1349 struct usb_host_endpoint *ep)
1354 in = usb_endpoint_dir_in(&ep->desc);
1355 if (usb_endpoint_xfer_control(&ep->desc)) {
1356 type = EP_TYPE(CTRL_EP);
1357 } else if (usb_endpoint_xfer_bulk(&ep->desc)) {
1359 type = EP_TYPE(BULK_IN_EP);
1361 type = EP_TYPE(BULK_OUT_EP);
1362 } else if (usb_endpoint_xfer_isoc(&ep->desc)) {
1364 type = EP_TYPE(ISOC_IN_EP);
1366 type = EP_TYPE(ISOC_OUT_EP);
1367 } else if (usb_endpoint_xfer_int(&ep->desc)) {
1369 type = EP_TYPE(INT_IN_EP);
1371 type = EP_TYPE(INT_OUT_EP);
1378 /* Return the maximum endpoint service interval time (ESIT) payload.
1379 * Basically, this is the maxpacket size, multiplied by the burst size
1382 static u32 xhci_get_max_esit_payload(struct xhci_hcd *xhci,
1383 struct usb_device *udev,
1384 struct usb_host_endpoint *ep)
1389 /* Only applies for interrupt or isochronous endpoints */
1390 if (usb_endpoint_xfer_control(&ep->desc) ||
1391 usb_endpoint_xfer_bulk(&ep->desc))
1394 if (udev->speed == USB_SPEED_SUPER)
1395 return le16_to_cpu(ep->ss_ep_comp.wBytesPerInterval);
1397 max_packet = GET_MAX_PACKET(usb_endpoint_maxp(&ep->desc));
1398 max_burst = (usb_endpoint_maxp(&ep->desc) & 0x1800) >> 11;
1399 /* A 0 in max burst means 1 transfer per ESIT */
1400 return max_packet * (max_burst + 1);
1403 /* Set up an endpoint with one ring segment. Do not allocate stream rings.
1404 * Drivers will have to call usb_alloc_streams() to do that.
1406 int xhci_endpoint_init(struct xhci_hcd *xhci,
1407 struct xhci_virt_device *virt_dev,
1408 struct usb_device *udev,
1409 struct usb_host_endpoint *ep,
1412 unsigned int ep_index;
1413 struct xhci_ep_ctx *ep_ctx;
1414 struct xhci_ring *ep_ring;
1415 unsigned int max_packet;
1416 unsigned int max_burst;
1417 enum xhci_ring_type type;
1418 u32 max_esit_payload;
1420 ep_index = xhci_get_endpoint_index(&ep->desc);
1421 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
1423 type = usb_endpoint_type(&ep->desc);
1424 /* Set up the endpoint ring */
1425 virt_dev->eps[ep_index].new_ring =
1426 xhci_ring_alloc(xhci, 2, 1, type, mem_flags);
1427 if (!virt_dev->eps[ep_index].new_ring) {
1428 /* Attempt to use the ring cache */
1429 if (virt_dev->num_rings_cached == 0)
1431 virt_dev->eps[ep_index].new_ring =
1432 virt_dev->ring_cache[virt_dev->num_rings_cached];
1433 virt_dev->ring_cache[virt_dev->num_rings_cached] = NULL;
1434 virt_dev->num_rings_cached--;
1435 xhci_reinit_cached_ring(xhci, virt_dev->eps[ep_index].new_ring,
1438 virt_dev->eps[ep_index].skip = false;
1439 ep_ring = virt_dev->eps[ep_index].new_ring;
1440 ep_ctx->deq = cpu_to_le64(ep_ring->first_seg->dma | ep_ring->cycle_state);
1442 ep_ctx->ep_info = cpu_to_le32(xhci_get_endpoint_interval(udev, ep)
1443 | EP_MULT(xhci_get_endpoint_mult(udev, ep)));
1445 /* FIXME dig Mult and streams info out of ep companion desc */
1447 /* Allow 3 retries for everything but isoc;
1448 * CErr shall be set to 0 for Isoch endpoints.
1450 if (!usb_endpoint_xfer_isoc(&ep->desc))
1451 ep_ctx->ep_info2 = cpu_to_le32(ERROR_COUNT(3));
1453 ep_ctx->ep_info2 = cpu_to_le32(ERROR_COUNT(0));
1455 ep_ctx->ep_info2 |= cpu_to_le32(xhci_get_endpoint_type(udev, ep));
1457 /* Set the max packet size and max burst */
1458 switch (udev->speed) {
1459 case USB_SPEED_SUPER:
1460 max_packet = usb_endpoint_maxp(&ep->desc);
1461 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet));
1462 /* dig out max burst from ep companion desc */
1463 max_packet = ep->ss_ep_comp.bMaxBurst;
1464 ep_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(max_packet));
1466 case USB_SPEED_HIGH:
1467 /* bits 11:12 specify the number of additional transaction
1468 * opportunities per microframe (USB 2.0, section 9.6.6)
1470 if (usb_endpoint_xfer_isoc(&ep->desc) ||
1471 usb_endpoint_xfer_int(&ep->desc)) {
1472 max_burst = (usb_endpoint_maxp(&ep->desc)
1474 ep_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(max_burst));
1477 case USB_SPEED_FULL:
1479 max_packet = GET_MAX_PACKET(usb_endpoint_maxp(&ep->desc));
1480 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet));
1485 max_esit_payload = xhci_get_max_esit_payload(xhci, udev, ep);
1486 ep_ctx->tx_info = cpu_to_le32(MAX_ESIT_PAYLOAD_FOR_EP(max_esit_payload));
1489 * XXX no idea how to calculate the average TRB buffer length for bulk
1490 * endpoints, as the driver gives us no clue how big each scatter gather
1491 * list entry (or buffer) is going to be.
1493 * For isochronous and interrupt endpoints, we set it to the max
1494 * available, until we have new API in the USB core to allow drivers to
1495 * declare how much bandwidth they actually need.
1497 * Normally, it would be calculated by taking the total of the buffer
1498 * lengths in the TD and then dividing by the number of TRBs in a TD,
1499 * including link TRBs, No-op TRBs, and Event data TRBs. Since we don't
1500 * use Event Data TRBs, and we don't chain in a link TRB on short
1501 * transfers, we're basically dividing by 1.
1503 * xHCI 1.0 specification indicates that the Average TRB Length should
1504 * be set to 8 for control endpoints.
1506 if (usb_endpoint_xfer_control(&ep->desc) && xhci->hci_version == 0x100)
1507 ep_ctx->tx_info |= cpu_to_le32(AVG_TRB_LENGTH_FOR_EP(8));
1510 cpu_to_le32(AVG_TRB_LENGTH_FOR_EP(max_esit_payload));
1512 /* FIXME Debug endpoint context */
1516 void xhci_endpoint_zero(struct xhci_hcd *xhci,
1517 struct xhci_virt_device *virt_dev,
1518 struct usb_host_endpoint *ep)
1520 unsigned int ep_index;
1521 struct xhci_ep_ctx *ep_ctx;
1523 ep_index = xhci_get_endpoint_index(&ep->desc);
1524 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
1526 ep_ctx->ep_info = 0;
1527 ep_ctx->ep_info2 = 0;
1529 ep_ctx->tx_info = 0;
1530 /* Don't free the endpoint ring until the set interface or configuration
1535 void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info)
1537 bw_info->ep_interval = 0;
1539 bw_info->num_packets = 0;
1540 bw_info->max_packet_size = 0;
1542 bw_info->max_esit_payload = 0;
1545 void xhci_update_bw_info(struct xhci_hcd *xhci,
1546 struct xhci_container_ctx *in_ctx,
1547 struct xhci_input_control_ctx *ctrl_ctx,
1548 struct xhci_virt_device *virt_dev)
1550 struct xhci_bw_info *bw_info;
1551 struct xhci_ep_ctx *ep_ctx;
1552 unsigned int ep_type;
1555 for (i = 1; i < 31; ++i) {
1556 bw_info = &virt_dev->eps[i].bw_info;
1558 /* We can't tell what endpoint type is being dropped, but
1559 * unconditionally clearing the bandwidth info for non-periodic
1560 * endpoints should be harmless because the info will never be
1561 * set in the first place.
1563 if (!EP_IS_ADDED(ctrl_ctx, i) && EP_IS_DROPPED(ctrl_ctx, i)) {
1564 /* Dropped endpoint */
1565 xhci_clear_endpoint_bw_info(bw_info);
1569 if (EP_IS_ADDED(ctrl_ctx, i)) {
1570 ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, i);
1571 ep_type = CTX_TO_EP_TYPE(le32_to_cpu(ep_ctx->ep_info2));
1573 /* Ignore non-periodic endpoints */
1574 if (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
1575 ep_type != ISOC_IN_EP &&
1576 ep_type != INT_IN_EP)
1579 /* Added or changed endpoint */
1580 bw_info->ep_interval = CTX_TO_EP_INTERVAL(
1581 le32_to_cpu(ep_ctx->ep_info));
1582 /* Number of packets and mult are zero-based in the
1583 * input context, but we want one-based for the
1586 bw_info->mult = CTX_TO_EP_MULT(
1587 le32_to_cpu(ep_ctx->ep_info)) + 1;
1588 bw_info->num_packets = CTX_TO_MAX_BURST(
1589 le32_to_cpu(ep_ctx->ep_info2)) + 1;
1590 bw_info->max_packet_size = MAX_PACKET_DECODED(
1591 le32_to_cpu(ep_ctx->ep_info2));
1592 bw_info->type = ep_type;
1593 bw_info->max_esit_payload = CTX_TO_MAX_ESIT_PAYLOAD(
1594 le32_to_cpu(ep_ctx->tx_info));
1599 /* Copy output xhci_ep_ctx to the input xhci_ep_ctx copy.
1600 * Useful when you want to change one particular aspect of the endpoint and then
1601 * issue a configure endpoint command.
1603 void xhci_endpoint_copy(struct xhci_hcd *xhci,
1604 struct xhci_container_ctx *in_ctx,
1605 struct xhci_container_ctx *out_ctx,
1606 unsigned int ep_index)
1608 struct xhci_ep_ctx *out_ep_ctx;
1609 struct xhci_ep_ctx *in_ep_ctx;
1611 out_ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1612 in_ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
1614 in_ep_ctx->ep_info = out_ep_ctx->ep_info;
1615 in_ep_ctx->ep_info2 = out_ep_ctx->ep_info2;
1616 in_ep_ctx->deq = out_ep_ctx->deq;
1617 in_ep_ctx->tx_info = out_ep_ctx->tx_info;
1620 /* Copy output xhci_slot_ctx to the input xhci_slot_ctx.
1621 * Useful when you want to change one particular aspect of the endpoint and then
1622 * issue a configure endpoint command. Only the context entries field matters,
1623 * but we'll copy the whole thing anyway.
1625 void xhci_slot_copy(struct xhci_hcd *xhci,
1626 struct xhci_container_ctx *in_ctx,
1627 struct xhci_container_ctx *out_ctx)
1629 struct xhci_slot_ctx *in_slot_ctx;
1630 struct xhci_slot_ctx *out_slot_ctx;
1632 in_slot_ctx = xhci_get_slot_ctx(xhci, in_ctx);
1633 out_slot_ctx = xhci_get_slot_ctx(xhci, out_ctx);
1635 in_slot_ctx->dev_info = out_slot_ctx->dev_info;
1636 in_slot_ctx->dev_info2 = out_slot_ctx->dev_info2;
1637 in_slot_ctx->tt_info = out_slot_ctx->tt_info;
1638 in_slot_ctx->dev_state = out_slot_ctx->dev_state;
1641 /* Set up the scratchpad buffer array and scratchpad buffers, if needed. */
1642 static int scratchpad_alloc(struct xhci_hcd *xhci, gfp_t flags)
1645 struct device *dev = xhci_to_hcd(xhci)->self.controller;
1646 int num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2);
1648 xhci_dbg(xhci, "Allocating %d scratchpad buffers\n", num_sp);
1653 xhci->scratchpad = kzalloc(sizeof(*xhci->scratchpad), flags);
1654 if (!xhci->scratchpad)
1657 xhci->scratchpad->sp_array = dma_alloc_coherent(dev,
1658 num_sp * sizeof(u64),
1659 &xhci->scratchpad->sp_dma, flags);
1660 if (!xhci->scratchpad->sp_array)
1663 xhci->scratchpad->sp_buffers = kzalloc(sizeof(void *) * num_sp, flags);
1664 if (!xhci->scratchpad->sp_buffers)
1667 xhci->scratchpad->sp_dma_buffers =
1668 kzalloc(sizeof(dma_addr_t) * num_sp, flags);
1670 if (!xhci->scratchpad->sp_dma_buffers)
1673 xhci->dcbaa->dev_context_ptrs[0] = cpu_to_le64(xhci->scratchpad->sp_dma);
1674 for (i = 0; i < num_sp; i++) {
1676 void *buf = dma_alloc_coherent(dev, xhci->page_size, &dma,
1681 xhci->scratchpad->sp_array[i] = dma;
1682 xhci->scratchpad->sp_buffers[i] = buf;
1683 xhci->scratchpad->sp_dma_buffers[i] = dma;
1689 for (i = i - 1; i >= 0; i--) {
1690 dma_free_coherent(dev, xhci->page_size,
1691 xhci->scratchpad->sp_buffers[i],
1692 xhci->scratchpad->sp_dma_buffers[i]);
1694 kfree(xhci->scratchpad->sp_dma_buffers);
1697 kfree(xhci->scratchpad->sp_buffers);
1700 dma_free_coherent(dev, num_sp * sizeof(u64),
1701 xhci->scratchpad->sp_array,
1702 xhci->scratchpad->sp_dma);
1705 kfree(xhci->scratchpad);
1706 xhci->scratchpad = NULL;
1712 static void scratchpad_free(struct xhci_hcd *xhci)
1716 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
1718 if (!xhci->scratchpad)
1721 num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2);
1723 for (i = 0; i < num_sp; i++) {
1724 dma_free_coherent(&pdev->dev, xhci->page_size,
1725 xhci->scratchpad->sp_buffers[i],
1726 xhci->scratchpad->sp_dma_buffers[i]);
1728 kfree(xhci->scratchpad->sp_dma_buffers);
1729 kfree(xhci->scratchpad->sp_buffers);
1730 dma_free_coherent(&pdev->dev, num_sp * sizeof(u64),
1731 xhci->scratchpad->sp_array,
1732 xhci->scratchpad->sp_dma);
1733 kfree(xhci->scratchpad);
1734 xhci->scratchpad = NULL;
1737 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
1738 bool allocate_in_ctx, bool allocate_completion,
1741 struct xhci_command *command;
1743 command = kzalloc(sizeof(*command), mem_flags);
1747 if (allocate_in_ctx) {
1749 xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT,
1751 if (!command->in_ctx) {
1757 if (allocate_completion) {
1758 command->completion =
1759 kzalloc(sizeof(struct completion), mem_flags);
1760 if (!command->completion) {
1761 xhci_free_container_ctx(xhci, command->in_ctx);
1765 init_completion(command->completion);
1768 command->status = 0;
1769 INIT_LIST_HEAD(&command->cmd_list);
1773 void xhci_urb_free_priv(struct xhci_hcd *xhci, struct urb_priv *urb_priv)
1776 kfree(urb_priv->td[0]);
1781 void xhci_free_command(struct xhci_hcd *xhci,
1782 struct xhci_command *command)
1784 xhci_free_container_ctx(xhci,
1786 kfree(command->completion);
1790 void xhci_mem_cleanup(struct xhci_hcd *xhci)
1792 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
1793 struct dev_info *dev_info, *next;
1794 struct list_head *tt_list_head;
1795 struct list_head *tt;
1796 struct list_head *endpoints;
1797 struct list_head *ep, *q;
1798 struct xhci_tt_bw_info *tt_info;
1799 struct xhci_interval_bw_table *bwt;
1800 struct xhci_virt_ep *virt_ep;
1802 unsigned long flags;
1806 /* Free the Event Ring Segment Table and the actual Event Ring */
1807 size = sizeof(struct xhci_erst_entry)*(xhci->erst.num_entries);
1808 if (xhci->erst.entries)
1809 dma_free_coherent(&pdev->dev, size,
1810 xhci->erst.entries, xhci->erst.erst_dma_addr);
1811 xhci->erst.entries = NULL;
1812 xhci_dbg(xhci, "Freed ERST\n");
1813 if (xhci->event_ring)
1814 xhci_ring_free(xhci, xhci->event_ring);
1815 xhci->event_ring = NULL;
1816 xhci_dbg(xhci, "Freed event ring\n");
1818 if (xhci->lpm_command)
1819 xhci_free_command(xhci, xhci->lpm_command);
1820 xhci->cmd_ring_reserved_trbs = 0;
1822 xhci_ring_free(xhci, xhci->cmd_ring);
1823 xhci->cmd_ring = NULL;
1824 xhci_dbg(xhci, "Freed command ring\n");
1826 for (i = 1; i < MAX_HC_SLOTS; ++i)
1827 xhci_free_virt_device(xhci, i);
1829 if (xhci->segment_pool)
1830 dma_pool_destroy(xhci->segment_pool);
1831 xhci->segment_pool = NULL;
1832 xhci_dbg(xhci, "Freed segment pool\n");
1834 if (xhci->device_pool)
1835 dma_pool_destroy(xhci->device_pool);
1836 xhci->device_pool = NULL;
1837 xhci_dbg(xhci, "Freed device context pool\n");
1839 if (xhci->small_streams_pool)
1840 dma_pool_destroy(xhci->small_streams_pool);
1841 xhci->small_streams_pool = NULL;
1842 xhci_dbg(xhci, "Freed small stream array pool\n");
1844 if (xhci->medium_streams_pool)
1845 dma_pool_destroy(xhci->medium_streams_pool);
1846 xhci->medium_streams_pool = NULL;
1847 xhci_dbg(xhci, "Freed medium stream array pool\n");
1850 dma_free_coherent(&pdev->dev, sizeof(*xhci->dcbaa),
1851 xhci->dcbaa, xhci->dcbaa->dma);
1854 scratchpad_free(xhci);
1856 spin_lock_irqsave(&xhci->lock, flags);
1857 list_for_each_entry_safe(dev_info, next, &xhci->lpm_failed_devs, list) {
1858 list_del(&dev_info->list);
1861 spin_unlock_irqrestore(&xhci->lock, flags);
1863 bwt = &xhci->rh_bw->bw_table;
1864 for (i = 0; i < XHCI_MAX_INTERVAL; i++) {
1865 endpoints = &bwt->interval_bw[i].endpoints;
1866 list_for_each_safe(ep, q, endpoints) {
1867 virt_ep = list_entry(ep, struct xhci_virt_ep, bw_endpoint_list);
1868 list_del(&virt_ep->bw_endpoint_list);
1873 tt_list_head = &xhci->rh_bw->tts;
1874 list_for_each_safe(tt, q, tt_list_head) {
1875 tt_info = list_entry(tt, struct xhci_tt_bw_info, tt_list);
1880 xhci->num_usb2_ports = 0;
1881 xhci->num_usb3_ports = 0;
1882 xhci->num_active_eps = 0;
1883 kfree(xhci->usb2_ports);
1884 kfree(xhci->usb3_ports);
1885 kfree(xhci->port_array);
1888 xhci->page_size = 0;
1889 xhci->page_shift = 0;
1890 xhci->bus_state[0].bus_suspended = 0;
1891 xhci->bus_state[1].bus_suspended = 0;
1894 static int xhci_test_trb_in_td(struct xhci_hcd *xhci,
1895 struct xhci_segment *input_seg,
1896 union xhci_trb *start_trb,
1897 union xhci_trb *end_trb,
1898 dma_addr_t input_dma,
1899 struct xhci_segment *result_seg,
1900 char *test_name, int test_number)
1902 unsigned long long start_dma;
1903 unsigned long long end_dma;
1904 struct xhci_segment *seg;
1906 start_dma = xhci_trb_virt_to_dma(input_seg, start_trb);
1907 end_dma = xhci_trb_virt_to_dma(input_seg, end_trb);
1909 seg = trb_in_td(input_seg, start_trb, end_trb, input_dma);
1910 if (seg != result_seg) {
1911 xhci_warn(xhci, "WARN: %s TRB math test %d failed!\n",
1912 test_name, test_number);
1913 xhci_warn(xhci, "Tested TRB math w/ seg %p and "
1914 "input DMA 0x%llx\n",
1916 (unsigned long long) input_dma);
1917 xhci_warn(xhci, "starting TRB %p (0x%llx DMA), "
1918 "ending TRB %p (0x%llx DMA)\n",
1919 start_trb, start_dma,
1921 xhci_warn(xhci, "Expected seg %p, got seg %p\n",
1928 /* TRB math checks for xhci_trb_in_td(), using the command and event rings. */
1929 static int xhci_check_trb_in_td_math(struct xhci_hcd *xhci, gfp_t mem_flags)
1932 dma_addr_t input_dma;
1933 struct xhci_segment *result_seg;
1934 } simple_test_vector [] = {
1935 /* A zeroed DMA field should fail */
1937 /* One TRB before the ring start should fail */
1938 { xhci->event_ring->first_seg->dma - 16, NULL },
1939 /* One byte before the ring start should fail */
1940 { xhci->event_ring->first_seg->dma - 1, NULL },
1941 /* Starting TRB should succeed */
1942 { xhci->event_ring->first_seg->dma, xhci->event_ring->first_seg },
1943 /* Ending TRB should succeed */
1944 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16,
1945 xhci->event_ring->first_seg },
1946 /* One byte after the ring end should fail */
1947 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16 + 1, NULL },
1948 /* One TRB after the ring end should fail */
1949 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT)*16, NULL },
1950 /* An address of all ones should fail */
1951 { (dma_addr_t) (~0), NULL },
1954 struct xhci_segment *input_seg;
1955 union xhci_trb *start_trb;
1956 union xhci_trb *end_trb;
1957 dma_addr_t input_dma;
1958 struct xhci_segment *result_seg;
1959 } complex_test_vector [] = {
1960 /* Test feeding a valid DMA address from a different ring */
1961 { .input_seg = xhci->event_ring->first_seg,
1962 .start_trb = xhci->event_ring->first_seg->trbs,
1963 .end_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
1964 .input_dma = xhci->cmd_ring->first_seg->dma,
1967 /* Test feeding a valid end TRB from a different ring */
1968 { .input_seg = xhci->event_ring->first_seg,
1969 .start_trb = xhci->event_ring->first_seg->trbs,
1970 .end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
1971 .input_dma = xhci->cmd_ring->first_seg->dma,
1974 /* Test feeding a valid start and end TRB from a different ring */
1975 { .input_seg = xhci->event_ring->first_seg,
1976 .start_trb = xhci->cmd_ring->first_seg->trbs,
1977 .end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
1978 .input_dma = xhci->cmd_ring->first_seg->dma,
1981 /* TRB in this ring, but after this TD */
1982 { .input_seg = xhci->event_ring->first_seg,
1983 .start_trb = &xhci->event_ring->first_seg->trbs[0],
1984 .end_trb = &xhci->event_ring->first_seg->trbs[3],
1985 .input_dma = xhci->event_ring->first_seg->dma + 4*16,
1988 /* TRB in this ring, but before this TD */
1989 { .input_seg = xhci->event_ring->first_seg,
1990 .start_trb = &xhci->event_ring->first_seg->trbs[3],
1991 .end_trb = &xhci->event_ring->first_seg->trbs[6],
1992 .input_dma = xhci->event_ring->first_seg->dma + 2*16,
1995 /* TRB in this ring, but after this wrapped TD */
1996 { .input_seg = xhci->event_ring->first_seg,
1997 .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
1998 .end_trb = &xhci->event_ring->first_seg->trbs[1],
1999 .input_dma = xhci->event_ring->first_seg->dma + 2*16,
2002 /* TRB in this ring, but before this wrapped TD */
2003 { .input_seg = xhci->event_ring->first_seg,
2004 .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
2005 .end_trb = &xhci->event_ring->first_seg->trbs[1],
2006 .input_dma = xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 4)*16,
2009 /* TRB not in this ring, and we have a wrapped TD */
2010 { .input_seg = xhci->event_ring->first_seg,
2011 .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
2012 .end_trb = &xhci->event_ring->first_seg->trbs[1],
2013 .input_dma = xhci->cmd_ring->first_seg->dma + 2*16,
2018 unsigned int num_tests;
2021 num_tests = ARRAY_SIZE(simple_test_vector);
2022 for (i = 0; i < num_tests; i++) {
2023 ret = xhci_test_trb_in_td(xhci,
2024 xhci->event_ring->first_seg,
2025 xhci->event_ring->first_seg->trbs,
2026 &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
2027 simple_test_vector[i].input_dma,
2028 simple_test_vector[i].result_seg,
2034 num_tests = ARRAY_SIZE(complex_test_vector);
2035 for (i = 0; i < num_tests; i++) {
2036 ret = xhci_test_trb_in_td(xhci,
2037 complex_test_vector[i].input_seg,
2038 complex_test_vector[i].start_trb,
2039 complex_test_vector[i].end_trb,
2040 complex_test_vector[i].input_dma,
2041 complex_test_vector[i].result_seg,
2046 xhci_dbg(xhci, "TRB math tests passed.\n");
2050 static void xhci_set_hc_event_deq(struct xhci_hcd *xhci)
2055 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2056 xhci->event_ring->dequeue);
2057 if (deq == 0 && !in_interrupt())
2058 xhci_warn(xhci, "WARN something wrong with SW event ring "
2060 /* Update HC event ring dequeue pointer */
2061 temp = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2062 temp &= ERST_PTR_MASK;
2063 /* Don't clear the EHB bit (which is RW1C) because
2064 * there might be more events to service.
2067 xhci_dbg(xhci, "// Write event ring dequeue pointer, "
2068 "preserving EHB bit\n");
2069 xhci_write_64(xhci, ((u64) deq & (u64) ~ERST_PTR_MASK) | temp,
2070 &xhci->ir_set->erst_dequeue);
2073 static void xhci_add_in_port(struct xhci_hcd *xhci, unsigned int num_ports,
2074 __le32 __iomem *addr, u8 major_revision)
2076 u32 temp, port_offset, port_count;
2079 if (major_revision > 0x03) {
2080 xhci_warn(xhci, "Ignoring unknown port speed, "
2081 "Ext Cap %p, revision = 0x%x\n",
2082 addr, major_revision);
2083 /* Ignoring port protocol we can't understand. FIXME */
2087 /* Port offset and count in the third dword, see section 7.2 */
2088 temp = xhci_readl(xhci, addr + 2);
2089 port_offset = XHCI_EXT_PORT_OFF(temp);
2090 port_count = XHCI_EXT_PORT_COUNT(temp);
2091 xhci_dbg(xhci, "Ext Cap %p, port offset = %u, "
2092 "count = %u, revision = 0x%x\n",
2093 addr, port_offset, port_count, major_revision);
2094 /* Port count includes the current port offset */
2095 if (port_offset == 0 || (port_offset + port_count - 1) > num_ports)
2096 /* WTF? "Valid values are ‘1’ to MaxPorts" */
2099 /* Check the host's USB2 LPM capability */
2100 if ((xhci->hci_version == 0x96) && (major_revision != 0x03) &&
2101 (temp & XHCI_L1C)) {
2102 xhci_dbg(xhci, "xHCI 0.96: support USB2 software lpm\n");
2103 xhci->sw_lpm_support = 1;
2106 if ((xhci->hci_version >= 0x100) && (major_revision != 0x03)) {
2107 xhci_dbg(xhci, "xHCI 1.0: support USB2 software lpm\n");
2108 xhci->sw_lpm_support = 1;
2109 if (temp & XHCI_HLC) {
2110 xhci_dbg(xhci, "xHCI 1.0: support USB2 hardware lpm\n");
2111 xhci->hw_lpm_support = 1;
2116 for (i = port_offset; i < (port_offset + port_count); i++) {
2117 /* Duplicate entry. Ignore the port if the revisions differ. */
2118 if (xhci->port_array[i] != 0) {
2119 xhci_warn(xhci, "Duplicate port entry, Ext Cap %p,"
2120 " port %u\n", addr, i);
2121 xhci_warn(xhci, "Port was marked as USB %u, "
2122 "duplicated as USB %u\n",
2123 xhci->port_array[i], major_revision);
2124 /* Only adjust the roothub port counts if we haven't
2125 * found a similar duplicate.
2127 if (xhci->port_array[i] != major_revision &&
2128 xhci->port_array[i] != DUPLICATE_ENTRY) {
2129 if (xhci->port_array[i] == 0x03)
2130 xhci->num_usb3_ports--;
2132 xhci->num_usb2_ports--;
2133 xhci->port_array[i] = DUPLICATE_ENTRY;
2135 /* FIXME: Should we disable the port? */
2138 xhci->port_array[i] = major_revision;
2139 if (major_revision == 0x03)
2140 xhci->num_usb3_ports++;
2142 xhci->num_usb2_ports++;
2144 /* FIXME: Should we disable ports not in the Extended Capabilities? */
2148 * Scan the Extended Capabilities for the "Supported Protocol Capabilities" that
2149 * specify what speeds each port is supposed to be. We can't count on the port
2150 * speed bits in the PORTSC register being correct until a device is connected,
2151 * but we need to set up the two fake roothubs with the correct number of USB
2152 * 3.0 and USB 2.0 ports at host controller initialization time.
2154 static int xhci_setup_port_arrays(struct xhci_hcd *xhci, gfp_t flags)
2156 __le32 __iomem *addr;
2158 unsigned int num_ports;
2159 int i, j, port_index;
2161 addr = &xhci->cap_regs->hcc_params;
2162 offset = XHCI_HCC_EXT_CAPS(xhci_readl(xhci, addr));
2164 xhci_err(xhci, "No Extended Capability registers, "
2165 "unable to set up roothub.\n");
2169 num_ports = HCS_MAX_PORTS(xhci->hcs_params1);
2170 xhci->port_array = kzalloc(sizeof(*xhci->port_array)*num_ports, flags);
2171 if (!xhci->port_array)
2174 xhci->rh_bw = kzalloc(sizeof(*xhci->rh_bw)*num_ports, flags);
2177 for (i = 0; i < num_ports; i++) {
2178 struct xhci_interval_bw_table *bw_table;
2180 INIT_LIST_HEAD(&xhci->rh_bw[i].tts);
2181 bw_table = &xhci->rh_bw[i].bw_table;
2182 for (j = 0; j < XHCI_MAX_INTERVAL; j++)
2183 INIT_LIST_HEAD(&bw_table->interval_bw[j].endpoints);
2187 * For whatever reason, the first capability offset is from the
2188 * capability register base, not from the HCCPARAMS register.
2189 * See section 5.3.6 for offset calculation.
2191 addr = &xhci->cap_regs->hc_capbase + offset;
2195 cap_id = xhci_readl(xhci, addr);
2196 if (XHCI_EXT_CAPS_ID(cap_id) == XHCI_EXT_CAPS_PROTOCOL)
2197 xhci_add_in_port(xhci, num_ports, addr,
2198 (u8) XHCI_EXT_PORT_MAJOR(cap_id));
2199 offset = XHCI_EXT_CAPS_NEXT(cap_id);
2200 if (!offset || (xhci->num_usb2_ports + xhci->num_usb3_ports)
2204 * Once you're into the Extended Capabilities, the offset is
2205 * always relative to the register holding the offset.
2210 if (xhci->num_usb2_ports == 0 && xhci->num_usb3_ports == 0) {
2211 xhci_warn(xhci, "No ports on the roothubs?\n");
2214 xhci_dbg(xhci, "Found %u USB 2.0 ports and %u USB 3.0 ports.\n",
2215 xhci->num_usb2_ports, xhci->num_usb3_ports);
2217 /* Place limits on the number of roothub ports so that the hub
2218 * descriptors aren't longer than the USB core will allocate.
2220 if (xhci->num_usb3_ports > 15) {
2221 xhci_dbg(xhci, "Limiting USB 3.0 roothub ports to 15.\n");
2222 xhci->num_usb3_ports = 15;
2224 if (xhci->num_usb2_ports > USB_MAXCHILDREN) {
2225 xhci_dbg(xhci, "Limiting USB 2.0 roothub ports to %u.\n",
2227 xhci->num_usb2_ports = USB_MAXCHILDREN;
2231 * Note we could have all USB 3.0 ports, or all USB 2.0 ports.
2232 * Not sure how the USB core will handle a hub with no ports...
2234 if (xhci->num_usb2_ports) {
2235 xhci->usb2_ports = kmalloc(sizeof(*xhci->usb2_ports)*
2236 xhci->num_usb2_ports, flags);
2237 if (!xhci->usb2_ports)
2241 for (i = 0; i < num_ports; i++) {
2242 if (xhci->port_array[i] == 0x03 ||
2243 xhci->port_array[i] == 0 ||
2244 xhci->port_array[i] == DUPLICATE_ENTRY)
2247 xhci->usb2_ports[port_index] =
2248 &xhci->op_regs->port_status_base +
2250 xhci_dbg(xhci, "USB 2.0 port at index %u, "
2252 xhci->usb2_ports[port_index]);
2254 if (port_index == xhci->num_usb2_ports)
2258 if (xhci->num_usb3_ports) {
2259 xhci->usb3_ports = kmalloc(sizeof(*xhci->usb3_ports)*
2260 xhci->num_usb3_ports, flags);
2261 if (!xhci->usb3_ports)
2265 for (i = 0; i < num_ports; i++)
2266 if (xhci->port_array[i] == 0x03) {
2267 xhci->usb3_ports[port_index] =
2268 &xhci->op_regs->port_status_base +
2270 xhci_dbg(xhci, "USB 3.0 port at index %u, "
2272 xhci->usb3_ports[port_index]);
2274 if (port_index == xhci->num_usb3_ports)
2281 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
2284 struct device *dev = xhci_to_hcd(xhci)->self.controller;
2285 unsigned int val, val2;
2287 struct xhci_segment *seg;
2288 u32 page_size, temp;
2291 page_size = xhci_readl(xhci, &xhci->op_regs->page_size);
2292 xhci_dbg(xhci, "Supported page size register = 0x%x\n", page_size);
2293 for (i = 0; i < 16; i++) {
2294 if ((0x1 & page_size) != 0)
2296 page_size = page_size >> 1;
2299 xhci_dbg(xhci, "Supported page size of %iK\n", (1 << (i+12)) / 1024);
2301 xhci_warn(xhci, "WARN: no supported page size\n");
2302 /* Use 4K pages, since that's common and the minimum the HC supports */
2303 xhci->page_shift = 12;
2304 xhci->page_size = 1 << xhci->page_shift;
2305 xhci_dbg(xhci, "HCD page size set to %iK\n", xhci->page_size / 1024);
2308 * Program the Number of Device Slots Enabled field in the CONFIG
2309 * register with the max value of slots the HC can handle.
2311 val = HCS_MAX_SLOTS(xhci_readl(xhci, &xhci->cap_regs->hcs_params1));
2312 xhci_dbg(xhci, "// xHC can handle at most %d device slots.\n",
2313 (unsigned int) val);
2314 val2 = xhci_readl(xhci, &xhci->op_regs->config_reg);
2315 val |= (val2 & ~HCS_SLOTS_MASK);
2316 xhci_dbg(xhci, "// Setting Max device slots reg = 0x%x.\n",
2317 (unsigned int) val);
2318 xhci_writel(xhci, val, &xhci->op_regs->config_reg);
2321 * Section 5.4.8 - doorbell array must be
2322 * "physically contiguous and 64-byte (cache line) aligned".
2324 xhci->dcbaa = dma_alloc_coherent(dev, sizeof(*xhci->dcbaa), &dma,
2328 memset(xhci->dcbaa, 0, sizeof *(xhci->dcbaa));
2329 xhci->dcbaa->dma = dma;
2330 xhci_dbg(xhci, "// Device context base array address = 0x%llx (DMA), %p (virt)\n",
2331 (unsigned long long)xhci->dcbaa->dma, xhci->dcbaa);
2332 xhci_write_64(xhci, dma, &xhci->op_regs->dcbaa_ptr);
2335 * Initialize the ring segment pool. The ring must be a contiguous
2336 * structure comprised of TRBs. The TRBs must be 16 byte aligned,
2337 * however, the command ring segment needs 64-byte aligned segments,
2338 * so we pick the greater alignment need.
2340 xhci->segment_pool = dma_pool_create("xHCI ring segments", dev,
2341 SEGMENT_SIZE, 64, xhci->page_size);
2343 /* See Table 46 and Note on Figure 55 */
2344 xhci->device_pool = dma_pool_create("xHCI input/output contexts", dev,
2345 2112, 64, xhci->page_size);
2346 if (!xhci->segment_pool || !xhci->device_pool)
2349 /* Linear stream context arrays don't have any boundary restrictions,
2350 * and only need to be 16-byte aligned.
2352 xhci->small_streams_pool =
2353 dma_pool_create("xHCI 256 byte stream ctx arrays",
2354 dev, SMALL_STREAM_ARRAY_SIZE, 16, 0);
2355 xhci->medium_streams_pool =
2356 dma_pool_create("xHCI 1KB stream ctx arrays",
2357 dev, MEDIUM_STREAM_ARRAY_SIZE, 16, 0);
2358 /* Any stream context array bigger than MEDIUM_STREAM_ARRAY_SIZE
2359 * will be allocated with dma_alloc_coherent()
2362 if (!xhci->small_streams_pool || !xhci->medium_streams_pool)
2365 /* Set up the command ring to have one segments for now. */
2366 xhci->cmd_ring = xhci_ring_alloc(xhci, 1, 1, TYPE_COMMAND, flags);
2367 if (!xhci->cmd_ring)
2369 xhci_dbg(xhci, "Allocated command ring at %p\n", xhci->cmd_ring);
2370 xhci_dbg(xhci, "First segment DMA is 0x%llx\n",
2371 (unsigned long long)xhci->cmd_ring->first_seg->dma);
2373 /* Set the address in the Command Ring Control register */
2374 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
2375 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
2376 (xhci->cmd_ring->first_seg->dma & (u64) ~CMD_RING_RSVD_BITS) |
2377 xhci->cmd_ring->cycle_state;
2378 xhci_dbg(xhci, "// Setting command ring address to 0x%x\n", val);
2379 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
2380 xhci_dbg_cmd_ptrs(xhci);
2382 xhci->lpm_command = xhci_alloc_command(xhci, true, true, flags);
2383 if (!xhci->lpm_command)
2386 /* Reserve one command ring TRB for disabling LPM.
2387 * Since the USB core grabs the shared usb_bus bandwidth mutex before
2388 * disabling LPM, we only need to reserve one TRB for all devices.
2390 xhci->cmd_ring_reserved_trbs++;
2392 val = xhci_readl(xhci, &xhci->cap_regs->db_off);
2394 xhci_dbg(xhci, "// Doorbell array is located at offset 0x%x"
2395 " from cap regs base addr\n", val);
2396 xhci->dba = (void __iomem *) xhci->cap_regs + val;
2397 xhci_dbg_regs(xhci);
2398 xhci_print_run_regs(xhci);
2399 /* Set ir_set to interrupt register set 0 */
2400 xhci->ir_set = &xhci->run_regs->ir_set[0];
2403 * Event ring setup: Allocate a normal ring, but also setup
2404 * the event ring segment table (ERST). Section 4.9.3.
2406 xhci_dbg(xhci, "// Allocating event ring\n");
2407 xhci->event_ring = xhci_ring_alloc(xhci, ERST_NUM_SEGS, 1, TYPE_EVENT,
2409 if (!xhci->event_ring)
2411 if (xhci_check_trb_in_td_math(xhci, flags) < 0)
2414 xhci->erst.entries = dma_alloc_coherent(dev,
2415 sizeof(struct xhci_erst_entry) * ERST_NUM_SEGS, &dma,
2417 if (!xhci->erst.entries)
2419 xhci_dbg(xhci, "// Allocated event ring segment table at 0x%llx\n",
2420 (unsigned long long)dma);
2422 memset(xhci->erst.entries, 0, sizeof(struct xhci_erst_entry)*ERST_NUM_SEGS);
2423 xhci->erst.num_entries = ERST_NUM_SEGS;
2424 xhci->erst.erst_dma_addr = dma;
2425 xhci_dbg(xhci, "Set ERST to 0; private num segs = %i, virt addr = %p, dma addr = 0x%llx\n",
2426 xhci->erst.num_entries,
2428 (unsigned long long)xhci->erst.erst_dma_addr);
2430 /* set ring base address and size for each segment table entry */
2431 for (val = 0, seg = xhci->event_ring->first_seg; val < ERST_NUM_SEGS; val++) {
2432 struct xhci_erst_entry *entry = &xhci->erst.entries[val];
2433 entry->seg_addr = cpu_to_le64(seg->dma);
2434 entry->seg_size = cpu_to_le32(TRBS_PER_SEGMENT);
2439 /* set ERST count with the number of entries in the segment table */
2440 val = xhci_readl(xhci, &xhci->ir_set->erst_size);
2441 val &= ERST_SIZE_MASK;
2442 val |= ERST_NUM_SEGS;
2443 xhci_dbg(xhci, "// Write ERST size = %i to ir_set 0 (some bits preserved)\n",
2445 xhci_writel(xhci, val, &xhci->ir_set->erst_size);
2447 xhci_dbg(xhci, "// Set ERST entries to point to event ring.\n");
2448 /* set the segment table base address */
2449 xhci_dbg(xhci, "// Set ERST base address for ir_set 0 = 0x%llx\n",
2450 (unsigned long long)xhci->erst.erst_dma_addr);
2451 val_64 = xhci_read_64(xhci, &xhci->ir_set->erst_base);
2452 val_64 &= ERST_PTR_MASK;
2453 val_64 |= (xhci->erst.erst_dma_addr & (u64) ~ERST_PTR_MASK);
2454 xhci_write_64(xhci, val_64, &xhci->ir_set->erst_base);
2456 /* Set the event ring dequeue address */
2457 xhci_set_hc_event_deq(xhci);
2458 xhci_dbg(xhci, "Wrote ERST address to ir_set 0.\n");
2459 xhci_print_ir_set(xhci, 0);
2462 * XXX: Might need to set the Interrupter Moderation Register to
2463 * something other than the default (~1ms minimum between interrupts).
2464 * See section 5.5.1.2.
2466 init_completion(&xhci->addr_dev);
2467 for (i = 0; i < MAX_HC_SLOTS; ++i)
2468 xhci->devs[i] = NULL;
2469 for (i = 0; i < USB_MAXCHILDREN; ++i) {
2470 xhci->bus_state[0].resume_done[i] = 0;
2471 xhci->bus_state[1].resume_done[i] = 0;
2474 if (scratchpad_alloc(xhci, flags))
2476 if (xhci_setup_port_arrays(xhci, flags))
2479 INIT_LIST_HEAD(&xhci->lpm_failed_devs);
2481 /* Enable USB 3.0 device notifications for function remote wake, which
2482 * is necessary for allowing USB 3.0 devices to do remote wakeup from
2483 * U3 (device suspend).
2485 temp = xhci_readl(xhci, &xhci->op_regs->dev_notification);
2486 temp &= ~DEV_NOTE_MASK;
2487 temp |= DEV_NOTE_FWAKE;
2488 xhci_writel(xhci, temp, &xhci->op_regs->dev_notification);
2493 xhci_warn(xhci, "Couldn't initialize memory\n");
2496 xhci_mem_cleanup(xhci);