drivers/usb/musb/musb_cppi41.c

   1 #include <linux/device.h>
   2 #include <linux/dma-mapping.h>
   3 #include <linux/dmaengine.h>
   4 #include <linux/sizes.h>
   5 #include <linux/platform_device.h>
   6 #include <linux/of.h>
   7
   8 #include "musb_core.h"
   9
  10 #define RNDIS_REG(x) (0x80 + ((x - 1) * 4))
  11
  12 #define EP_MODE_AUTOREG_NONE            0
  13 #define EP_MODE_AUTOREG_ALL_NEOP        1
  14 #define EP_MODE_AUTOREG_ALWAYS          3
  15
  16 #define EP_MODE_DMA_TRANSPARENT         0
  17 #define EP_MODE_DMA_RNDIS               1
  18 #define EP_MODE_DMA_GEN_RNDIS           3
  19
  20 #define USB_CTRL_TX_MODE        0x70
  21 #define USB_CTRL_RX_MODE        0x74
  22 #define USB_CTRL_AUTOREQ        0xd0
  23 #define USB_TDOWN               0xd8
  24
  25 struct cppi41_dma_channel {
  26         struct dma_channel channel;
  27         struct cppi41_dma_controller *controller;
  28         struct musb_hw_ep *hw_ep;
  29         struct dma_chan *dc;
  30         dma_cookie_t cookie;
  31         u8 port_num;
  32         u8 is_tx;
  33         u8 is_allocated;
  34         u8 usb_toggle;
  35
  36         dma_addr_t buf_addr;
  37         u32 total_len;
  38         u32 prog_len;
  39         u32 transferred;
  40         u32 packet_sz;
  41         struct list_head tx_check;
  42         int tx_zlp;
  43 };
  44
  45 #define MUSB_DMA_NUM_CHANNELS 15
  46
  47 struct cppi41_dma_controller {
  48         struct dma_controller controller;
  49         struct cppi41_dma_channel rx_channel[MUSB_DMA_NUM_CHANNELS];
  50         struct cppi41_dma_channel tx_channel[MUSB_DMA_NUM_CHANNELS];
  51         struct musb *musb;
  52         struct hrtimer early_tx;
  53         struct list_head early_tx_list;
  54         u32 rx_mode;
  55         u32 tx_mode;
  56         u32 auto_req;
  57 };
  58
  59 static void save_rx_toggle(struct cppi41_dma_channel *cppi41_channel)
  60 {
  61         u16 csr;
  62         u8 toggle;
  63
  64         if (cppi41_channel->is_tx)
  65                 return;
  66         if (!is_host_active(cppi41_channel->controller->musb))
  67                 return;
  68
  69         csr = musb_readw(cppi41_channel->hw_ep->regs, MUSB_RXCSR);
  70         toggle = csr & MUSB_RXCSR_H_DATATOGGLE ? 1 : 0;
  71
  72         cppi41_channel->usb_toggle = toggle;
  73 }
  74
  75 static void update_rx_toggle(struct cppi41_dma_channel *cppi41_channel)
  76 {
  77         struct musb_hw_ep *hw_ep = cppi41_channel->hw_ep;
  78         struct musb *musb = hw_ep->musb;
  79         u16 csr;
  80         u8 toggle;
  81
  82         if (cppi41_channel->is_tx)
  83                 return;
  84         if (!is_host_active(musb))
  85                 return;
  86
  87         musb_ep_select(musb->mregs, hw_ep->epnum);
  88         csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
  89         toggle = csr & MUSB_RXCSR_H_DATATOGGLE ? 1 : 0;
  90
  91         /*
  92          * AM335x Advisory 1.0.13: Due to internal synchronisation error the
  93          * data toggle may reset from DATA1 to DATA0 during receiving data from
  94          * more than one endpoint.
  95          */
  96         if (!toggle && toggle == cppi41_channel->usb_toggle) {
  97                 csr |= MUSB_RXCSR_H_DATATOGGLE | MUSB_RXCSR_H_WR_DATATOGGLE;
  98                 musb_writew(cppi41_channel->hw_ep->regs, MUSB_RXCSR, csr);
  99                 dev_dbg(cppi41_channel->controller->musb->controller,
 100                                 "Restoring DATA1 toggle.\n");
 101         }
 102
 103         cppi41_channel->usb_toggle = toggle;
 104 }
 105
 106 static bool musb_is_tx_fifo_empty(struct musb_hw_ep *hw_ep)
 107 {
 108         u8              epnum = hw_ep->epnum;
 109         struct musb     *musb = hw_ep->musb;
 110         void __iomem    *epio = musb->endpoints[epnum].regs;
 111         u16             csr;
 112
 113         musb_ep_select(musb->mregs, hw_ep->epnum);
 114         csr = musb_readw(epio, MUSB_TXCSR);
 115         if (csr & MUSB_TXCSR_TXPKTRDY)
 116                 return false;
 117         return true;
 118 }
 119
 120 static void cppi41_dma_callback(void *private_data);
 121
 122 static void cppi41_trans_done(struct cppi41_dma_channel *cppi41_channel)
 123 {
 124         struct musb_hw_ep *hw_ep = cppi41_channel->hw_ep;
 125         struct musb *musb = hw_ep->musb;
 126         void __iomem *epio = hw_ep->regs;
 127         u16 csr;
 128
 129         if (!cppi41_channel->prog_len ||
 130             (cppi41_channel->channel.status == MUSB_DMA_STATUS_FREE)) {
 131
 132                 /* done, complete */
 133                 cppi41_channel->channel.actual_len =
 134                         cppi41_channel->transferred;
 135                 cppi41_channel->channel.status = MUSB_DMA_STATUS_FREE;
 136                 cppi41_channel->channel.rx_packet_done = true;
 137
 138                 /*
 139                  * transmit ZLP using PIO mode for transfers which size is
 140                  * multiple of EP packet size.
 141                  */
 142                 if (cppi41_channel->tx_zlp && (cppi41_channel->transferred %
 143                                         cppi41_channel->packet_sz) == 0) {
 144                         musb_ep_select(musb->mregs, hw_ep->epnum);
 145                         csr = MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY;
 146                         musb_writew(epio, MUSB_TXCSR, csr);
 147                 }
 148                 musb_dma_completion(musb, hw_ep->epnum, cppi41_channel->is_tx);
 149         } else {
 150                 /* next iteration, reload */
 151                 struct dma_chan *dc = cppi41_channel->dc;
 152                 struct dma_async_tx_descriptor *dma_desc;
 153                 enum dma_transfer_direction direction;
 154                 u32 remain_bytes;
 155
 156                 cppi41_channel->buf_addr += cppi41_channel->packet_sz;
 157
 158                 remain_bytes = cppi41_channel->total_len;
 159                 remain_bytes -= cppi41_channel->transferred;
 160                 remain_bytes = min(remain_bytes, cppi41_channel->packet_sz);
 161                 cppi41_channel->prog_len = remain_bytes;
 162
 163                 direction = cppi41_channel->is_tx ? DMA_MEM_TO_DEV
 164                         : DMA_DEV_TO_MEM;
 165                 dma_desc = dmaengine_prep_slave_single(dc,
 166                                 cppi41_channel->buf_addr,
 167                                 remain_bytes,
 168                                 direction,
 169                                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 170                 if (WARN_ON(!dma_desc))
 171                         return;
 172
 173                 dma_desc->callback = cppi41_dma_callback;
 174                 dma_desc->callback_param = &cppi41_channel->channel;
 175                 cppi41_channel->cookie = dma_desc->tx_submit(dma_desc);
 176                 dma_async_issue_pending(dc);
 177
 178                 if (!cppi41_channel->is_tx) {
 179                         musb_ep_select(musb->mregs, hw_ep->epnum);
 180                         csr = musb_readw(epio, MUSB_RXCSR);
 181                         csr |= MUSB_RXCSR_H_REQPKT;
 182                         musb_writew(epio, MUSB_RXCSR, csr);
 183                 }
 184         }
 185 }
 186
 187 static enum hrtimer_restart cppi41_recheck_tx_req(struct hrtimer *timer)
 188 {
 189         struct cppi41_dma_controller *controller;
 190         struct cppi41_dma_channel *cppi41_channel, *n;
 191         struct musb *musb;
 192         unsigned long flags;
 193         enum hrtimer_restart ret = HRTIMER_NORESTART;
 194
 195         controller = container_of(timer, struct cppi41_dma_controller,
 196                         early_tx);
 197         musb = controller->musb;
 198
 199         spin_lock_irqsave(&musb->lock, flags);
 200         list_for_each_entry_safe(cppi41_channel, n, &controller->early_tx_list,
 201                         tx_check) {
 202                 bool empty;
 203                 struct musb_hw_ep *hw_ep = cppi41_channel->hw_ep;
 204
 205                 empty = musb_is_tx_fifo_empty(hw_ep);
 206                 if (empty) {
 207                         list_del_init(&cppi41_channel->tx_check);
 208                         cppi41_trans_done(cppi41_channel);
 209                 }
 210         }
 211
 212         if (!list_empty(&controller->early_tx_list)) {
 213                 ret = HRTIMER_RESTART;
 214                 hrtimer_forward_now(&controller->early_tx,
 215                                 ktime_set(0, 20 * NSEC_PER_USEC));
 216         }
 217
 218         spin_unlock_irqrestore(&musb->lock, flags);
 219         return ret;
 220 }
 221
 222 static void cppi41_dma_callback(void *private_data)
 223 {
 224         struct dma_channel *channel = private_data;
 225         struct cppi41_dma_channel *cppi41_channel = channel->private_data;
 226         struct musb_hw_ep *hw_ep = cppi41_channel->hw_ep;
 227         struct musb *musb = hw_ep->musb;
 228         unsigned long flags;
 229         struct dma_tx_state txstate;
 230         u32 transferred;
 231         bool empty;
 232
 233         spin_lock_irqsave(&musb->lock, flags);
 234
 235         dmaengine_tx_status(cppi41_channel->dc, cppi41_channel->cookie,
 236                         &txstate);
 237         transferred = cppi41_channel->prog_len - txstate.residue;
 238         cppi41_channel->transferred += transferred;
 239
 240         dev_dbg(musb->controller, "DMA transfer done on hw_ep=%d bytes=%d/%d\n",
 241                 hw_ep->epnum, cppi41_channel->transferred,
 242                 cppi41_channel->total_len);
 243
 244         update_rx_toggle(cppi41_channel);
 245
 246         if (cppi41_channel->transferred == cppi41_channel->total_len ||
 247                         transferred < cppi41_channel->packet_sz)
 248                 cppi41_channel->prog_len = 0;
 249
 250         empty = musb_is_tx_fifo_empty(hw_ep);
 251         if (empty) {
 252                 cppi41_trans_done(cppi41_channel);
 253         } else {
 254                 struct cppi41_dma_controller *controller;
 255                 /*
 256                  * On AM335x it has been observed that the TX interrupt fires
 257                  * too early that means the TXFIFO is not yet empty but the DMA
 258                  * engine says that it is done with the transfer. We don't
 259                  * receive a FIFO empty interrupt so the only thing we can do is
 260                  * to poll for the bit. On HS it usually takes 2us, on FS around
 261                  * 110us - 150us depending on the transfer size.
 262                  * We spin on HS (no longer than than 25us and setup a timer on
 263                  * FS to check for the bit and complete the transfer.
 264                  */
 265                 controller = cppi41_channel->controller;
 266
 267                 if (musb->g.speed == USB_SPEED_HIGH) {
 268                         unsigned wait = 25;
 269
 270                         do {
 271                                 empty = musb_is_tx_fifo_empty(hw_ep);
 272                                 if (empty)
 273                                         break;
 274                                 wait--;
 275                                 if (!wait)
 276                                         break;
 277                                 udelay(1);
 278                         } while (1);
 279
 280                         empty = musb_is_tx_fifo_empty(hw_ep);
 281                         if (empty) {
 282                                 cppi41_trans_done(cppi41_channel);
 283                                 goto out;
 284                         }
 285                 }
 286                 list_add_tail(&cppi41_channel->tx_check,
 287                                 &controller->early_tx_list);
 288                 if (!hrtimer_is_queued(&controller->early_tx)) {
 289                         unsigned long usecs = cppi41_channel->total_len / 10;
 290
 291                         hrtimer_start_range_ns(&controller->early_tx,
 292                                 ktime_set(0, usecs * NSEC_PER_USEC),
 293                                 20 * NSEC_PER_USEC,
 294                                 HRTIMER_MODE_REL);
 295                 }
 296         }
 297 out:
 298         spin_unlock_irqrestore(&musb->lock, flags);
 299 }
 300
 301 static u32 update_ep_mode(unsigned ep, unsigned mode, u32 old)
 302 {
 303         unsigned shift;
 304
 305         shift = (ep - 1) * 2;
 306         old &= ~(3 << shift);
 307         old |= mode << shift;
 308         return old;
 309 }
 310
 311 static void cppi41_set_dma_mode(struct cppi41_dma_channel *cppi41_channel,
 312                 unsigned mode)
 313 {
 314         struct cppi41_dma_controller *controller = cppi41_channel->controller;
 315         u32 port;
 316         u32 new_mode;
 317         u32 old_mode;
 318
 319         if (cppi41_channel->is_tx)
 320                 old_mode = controller->tx_mode;
 321         else
 322                 old_mode = controller->rx_mode;
 323         port = cppi41_channel->port_num;
 324         new_mode = update_ep_mode(port, mode, old_mode);
 325
 326         if (new_mode == old_mode)
 327                 return;
 328         if (cppi41_channel->is_tx) {
 329                 controller->tx_mode = new_mode;
 330                 musb_writel(controller->musb->ctrl_base, USB_CTRL_TX_MODE,
 331                                 new_mode);
 332         } else {
 333                 controller->rx_mode = new_mode;
 334                 musb_writel(controller->musb->ctrl_base, USB_CTRL_RX_MODE,
 335                                 new_mode);
 336         }
 337 }
 338
 339 static void cppi41_set_autoreq_mode(struct cppi41_dma_channel *cppi41_channel,
 340                 unsigned mode)
 341 {
 342         struct cppi41_dma_controller *controller = cppi41_channel->controller;
 343         u32 port;
 344         u32 new_mode;
 345         u32 old_mode;
 346
 347         old_mode = controller->auto_req;
 348         port = cppi41_channel->port_num;
 349         new_mode = update_ep_mode(port, mode, old_mode);
 350
 351         if (new_mode == old_mode)
 352                 return;
 353         controller->auto_req = new_mode;
 354         musb_writel(controller->musb->ctrl_base, USB_CTRL_AUTOREQ, new_mode);
 355 }
 356
 357 static bool cppi41_configure_channel(struct dma_channel *channel,
 358                                 u16 packet_sz, u8 mode,
 359                                 dma_addr_t dma_addr, u32 len)
 360 {
 361         struct cppi41_dma_channel *cppi41_channel = channel->private_data;
 362         struct dma_chan *dc = cppi41_channel->dc;
 363         struct dma_async_tx_descriptor *dma_desc;
 364         enum dma_transfer_direction direction;
 365         struct musb *musb = cppi41_channel->controller->musb;
 366         unsigned use_gen_rndis = 0;
 367
 368         dev_dbg(musb->controller,
 369                 "configure ep%d/%x packet_sz=%d, mode=%d, dma_addr=0x%llx, len=%d is_tx=%d\n",
 370                 cppi41_channel->port_num, RNDIS_REG(cppi41_channel->port_num),
 371                 packet_sz, mode, (unsigned long long) dma_addr,
 372                 len, cppi41_channel->is_tx);
 373
 374         cppi41_channel->buf_addr = dma_addr;
 375         cppi41_channel->total_len = len;
 376         cppi41_channel->transferred = 0;
 377         cppi41_channel->packet_sz = packet_sz;
 378         cppi41_channel->tx_zlp = (cppi41_channel->is_tx && mode) ? 1 : 0;
 379
 380         /*
 381          * Due to AM335x' Advisory 1.0.13 we are not allowed to transfer more
 382          * than max packet size at a time.
 383          */
 384         if (cppi41_channel->is_tx)
 385                 use_gen_rndis = 1;
 386
 387         if (use_gen_rndis) {
 388                 /* RNDIS mode */
 389                 if (len > packet_sz) {
 390                         musb_writel(musb->ctrl_base,
 391                                 RNDIS_REG(cppi41_channel->port_num), len);
 392                         /* gen rndis */
 393                         cppi41_set_dma_mode(cppi41_channel,
 394                                         EP_MODE_DMA_GEN_RNDIS);
 395
 396                         /* auto req */
 397                         cppi41_set_autoreq_mode(cppi41_channel,
 398                                         EP_MODE_AUTOREG_ALL_NEOP);
 399                 } else {
 400                         musb_writel(musb->ctrl_base,
 401                                         RNDIS_REG(cppi41_channel->port_num), 0);
 402                         cppi41_set_dma_mode(cppi41_channel,
 403                                         EP_MODE_DMA_TRANSPARENT);
 404                         cppi41_set_autoreq_mode(cppi41_channel,
 405                                         EP_MODE_AUTOREG_NONE);
 406                 }
 407         } else {
 408                 /* fallback mode */
 409                 cppi41_set_dma_mode(cppi41_channel, EP_MODE_DMA_TRANSPARENT);
 410                 cppi41_set_autoreq_mode(cppi41_channel, EP_MODE_AUTOREG_NONE);
 411                 len = min_t(u32, packet_sz, len);
 412         }
 413         cppi41_channel->prog_len = len;
 414         direction = cppi41_channel->is_tx ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
 415         dma_desc = dmaengine_prep_slave_single(dc, dma_addr, len, direction,
 416                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 417         if (!dma_desc)
 418                 return false;
 419
 420         dma_desc->callback = cppi41_dma_callback;
 421         dma_desc->callback_param = channel;
 422         cppi41_channel->cookie = dma_desc->tx_submit(dma_desc);
 423         cppi41_channel->channel.rx_packet_done = false;
 424
 425         save_rx_toggle(cppi41_channel);
 426         dma_async_issue_pending(dc);
 427         return true;
 428 }
 429
 430 static struct dma_channel *cppi41_dma_channel_allocate(struct dma_controller *c,
 431                                 struct musb_hw_ep *hw_ep, u8 is_tx)
 432 {
 433         struct cppi41_dma_controller *controller = container_of(c,
 434                         struct cppi41_dma_controller, controller);
 435         struct cppi41_dma_channel *cppi41_channel = NULL;
 436         u8 ch_num = hw_ep->epnum - 1;
 437
 438         if (ch_num >= MUSB_DMA_NUM_CHANNELS)
 439                 return NULL;
 440
 441         if (is_tx)
 442                 cppi41_channel = &controller->tx_channel[ch_num];
 443         else
 444                 cppi41_channel = &controller->rx_channel[ch_num];
 445
 446         if (!cppi41_channel->dc)
 447                 return NULL;
 448
 449         if (cppi41_channel->is_allocated)
 450                 return NULL;
 451
 452         cppi41_channel->hw_ep = hw_ep;
 453         cppi41_channel->is_allocated = 1;
 454
 455         return &cppi41_channel->channel;
 456 }
 457
 458 static void cppi41_dma_channel_release(struct dma_channel *channel)
 459 {
 460         struct cppi41_dma_channel *cppi41_channel = channel->private_data;
 461
 462         if (cppi41_channel->is_allocated) {
 463                 cppi41_channel->is_allocated = 0;
 464                 channel->status = MUSB_DMA_STATUS_FREE;
 465                 channel->actual_len = 0;
 466         }
 467 }
 468
 469 static int cppi41_dma_channel_program(struct dma_channel *channel,
 470                                 u16 packet_sz, u8 mode,
 471                                 dma_addr_t dma_addr, u32 len)
 472 {
 473         int ret;
 474         struct cppi41_dma_channel *cppi41_channel = channel->private_data;
 475         int hb_mult = 0;
 476
 477         BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN ||
 478                 channel->status == MUSB_DMA_STATUS_BUSY);
 479
 480         if (is_host_active(cppi41_channel->controller->musb)) {
 481                 if (cppi41_channel->is_tx)
 482                         hb_mult = cppi41_channel->hw_ep->out_qh->hb_mult;
 483                 else
 484                         hb_mult = cppi41_channel->hw_ep->in_qh->hb_mult;
 485         }
 486
 487         channel->status = MUSB_DMA_STATUS_BUSY;
 488         channel->actual_len = 0;
 489
 490         if (hb_mult)
 491                 packet_sz = hb_mult * (packet_sz & 0x7FF);
 492
 493         ret = cppi41_configure_channel(channel, packet_sz, mode, dma_addr, len);
 494         if (!ret)
 495                 channel->status = MUSB_DMA_STATUS_FREE;
 496
 497         return ret;
 498 }
 499
 500 static int cppi41_is_compatible(struct dma_channel *channel, u16 maxpacket,
 501                 void *buf, u32 length)
 502 {
 503         struct cppi41_dma_channel *cppi41_channel = channel->private_data;
 504         struct cppi41_dma_controller *controller = cppi41_channel->controller;
 505         struct musb *musb = controller->musb;
 506
 507         if (is_host_active(musb)) {
 508                 WARN_ON(1);
 509                 return 1;
 510         }
 511         if (cppi41_channel->hw_ep->ep_in.type != USB_ENDPOINT_XFER_BULK)
 512                 return 0;
 513         if (cppi41_channel->is_tx)
 514                 return 1;
 515         /* AM335x Advisory 1.0.13. No workaround for device RX mode */
 516         return 0;
 517 }
 518
 519 static int cppi41_dma_channel_abort(struct dma_channel *channel)
 520 {
 521         struct cppi41_dma_channel *cppi41_channel = channel->private_data;
 522         struct cppi41_dma_controller *controller = cppi41_channel->controller;
 523         struct musb *musb = controller->musb;
 524         void __iomem *epio = cppi41_channel->hw_ep->regs;
 525         int tdbit;
 526         int ret;
 527         unsigned is_tx;
 528         u16 csr;
 529
 530         is_tx = cppi41_channel->is_tx;
 531         dev_dbg(musb->controller, "abort channel=%d, is_tx=%d\n",
 532                         cppi41_channel->port_num, is_tx);
 533
 534         if (cppi41_channel->channel.status == MUSB_DMA_STATUS_FREE)
 535                 return 0;
 536
 537         list_del_init(&cppi41_channel->tx_check);
 538         if (is_tx) {
 539                 csr = musb_readw(epio, MUSB_TXCSR);
 540                 csr &= ~MUSB_TXCSR_DMAENAB;
 541                 musb_writew(epio, MUSB_TXCSR, csr);
 542         } else {
 543                 csr = musb_readw(epio, MUSB_RXCSR);
 544                 csr &= ~(MUSB_RXCSR_H_REQPKT | MUSB_RXCSR_DMAENAB);
 545                 musb_writew(epio, MUSB_RXCSR, csr);
 546
 547                 csr = musb_readw(epio, MUSB_RXCSR);
 548                 if (csr & MUSB_RXCSR_RXPKTRDY) {
 549                         csr |= MUSB_RXCSR_FLUSHFIFO;
 550                         musb_writew(epio, MUSB_RXCSR, csr);
 551                         musb_writew(epio, MUSB_RXCSR, csr);
 552                 }
 553         }
 554
 555         tdbit = 1 << cppi41_channel->port_num;
 556         if (is_tx)
 557                 tdbit <<= 16;
 558
 559         do {
 560                 musb_writel(musb->ctrl_base, USB_TDOWN, tdbit);
 561                 ret = dmaengine_terminate_all(cppi41_channel->dc);
 562         } while (ret == -EAGAIN);
 563
 564         musb_writel(musb->ctrl_base, USB_TDOWN, tdbit);
 565
 566         if (is_tx) {
 567                 csr = musb_readw(epio, MUSB_TXCSR);
 568                 if (csr & MUSB_TXCSR_TXPKTRDY) {
 569                         csr |= MUSB_TXCSR_FLUSHFIFO;
 570                         musb_writew(epio, MUSB_TXCSR, csr);
 571                 }
 572         }
 573
 574         cppi41_channel->channel.status = MUSB_DMA_STATUS_FREE;
 575         return 0;
 576 }
 577
 578 static void cppi41_release_all_dma_chans(struct cppi41_dma_controller *ctrl)
 579 {
 580         struct dma_chan *dc;
 581         int i;
 582
 583         for (i = 0; i < MUSB_DMA_NUM_CHANNELS; i++) {
 584                 dc = ctrl->tx_channel[i].dc;
 585                 if (dc)
 586                         dma_release_channel(dc);
 587                 dc = ctrl->rx_channel[i].dc;
 588                 if (dc)
 589                         dma_release_channel(dc);
 590         }
 591 }
 592
 593 static void cppi41_dma_controller_stop(struct cppi41_dma_controller *controller)
 594 {
 595         cppi41_release_all_dma_chans(controller);
 596 }
 597
 598 static int cppi41_dma_controller_start(struct cppi41_dma_controller *controller)
 599 {
 600         struct musb *musb = controller->musb;
 601         struct device *dev = musb->controller;
 602         struct device_node *np = dev->of_node;
 603         struct cppi41_dma_channel *cppi41_channel;
 604         int count;
 605         int i;
 606         int ret;
 607
 608         count = of_property_count_strings(np, "dma-names");
 609         if (count < 0)
 610                 return count;
 611
 612         for (i = 0; i < count; i++) {
 613                 struct dma_chan *dc;
 614                 struct dma_channel *musb_dma;
 615                 const char *str;
 616                 unsigned is_tx;
 617                 unsigned int port;
 618
 619                 ret = of_property_read_string_index(np, "dma-names", i, &str);
 620                 if (ret)
 621                         goto err;
 622                 if (!strncmp(str, "tx", 2))
 623                         is_tx = 1;
 624                 else if (!strncmp(str, "rx", 2))
 625                         is_tx = 0;
 626                 else {
 627                         dev_err(dev, "Wrong dmatype %s\n", str);
 628                         goto err;
 629                 }
 630                 ret = kstrtouint(str + 2, 0, &port);
 631                 if (ret)
 632                         goto err;
 633
 634                 ret = -EINVAL;
 635                 if (port > MUSB_DMA_NUM_CHANNELS || !port)
 636                         goto err;
 637                 if (is_tx)
 638                         cppi41_channel = &controller->tx_channel[port - 1];
 639                 else
 640                         cppi41_channel = &controller->rx_channel[port - 1];
 641
 642                 cppi41_channel->controller = controller;
 643                 cppi41_channel->port_num = port;
 644                 cppi41_channel->is_tx = is_tx;
 645                 INIT_LIST_HEAD(&cppi41_channel->tx_check);
 646
 647                 musb_dma = &cppi41_channel->channel;
 648                 musb_dma->private_data = cppi41_channel;
 649                 musb_dma->status = MUSB_DMA_STATUS_FREE;
 650                 musb_dma->max_len = SZ_4M;
 651
 652                 dc = dma_request_slave_channel(dev, str);
 653                 if (!dc) {
 654                         dev_err(dev, "Failed to request %s.\n", str);
 655                         ret = -EPROBE_DEFER;
 656                         goto err;
 657                 }
 658                 cppi41_channel->dc = dc;
 659         }
 660         return 0;
 661 err:
 662         cppi41_release_all_dma_chans(controller);
 663         return ret;
 664 }
 665
 666 void dma_controller_destroy(struct dma_controller *c)
 667 {
 668         struct cppi41_dma_controller *controller = container_of(c,
 669                         struct cppi41_dma_controller, controller);
 670
 671         hrtimer_cancel(&controller->early_tx);
 672         cppi41_dma_controller_stop(controller);
 673         kfree(controller);
 674 }
 675
 676 struct dma_controller *dma_controller_create(struct musb *musb,
 677                                         void __iomem *base)
 678 {
 679         struct cppi41_dma_controller *controller;
 680         int ret = 0;
 681
 682         if (!musb->controller->of_node) {
 683                 dev_err(musb->controller, "Need DT for the DMA engine.\n");
 684                 return NULL;
 685         }
 686
 687         controller = kzalloc(sizeof(*controller), GFP_KERNEL);
 688         if (!controller)
 689                 goto kzalloc_fail;
 690
 691         hrtimer_init(&controller->early_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
 692         controller->early_tx.function = cppi41_recheck_tx_req;
 693         INIT_LIST_HEAD(&controller->early_tx_list);
 694         controller->musb = musb;
 695
 696         controller->controller.channel_alloc = cppi41_dma_channel_allocate;
 697         controller->controller.channel_release = cppi41_dma_channel_release;
 698         controller->controller.channel_program = cppi41_dma_channel_program;
 699         controller->controller.channel_abort = cppi41_dma_channel_abort;
 700         controller->controller.is_compatible = cppi41_is_compatible;
 701
 702         ret = cppi41_dma_controller_start(controller);
 703         if (ret)
 704                 goto plat_get_fail;
 705         return &controller->controller;
 706
 707 plat_get_fail:
 708         kfree(controller);
 709 kzalloc_fail:
 710         if (ret == -EPROBE_DEFER)
 711                 return ERR_PTR(ret);
 712         return NULL;
 713 }