2 * Samsung SoC DP (Display Port) interface driver.
4 * Copyright (C) 2012 Samsung Electronics Co., Ltd.
5 * Author: Jingoo Han <jg1.han@samsung.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
13 #include <linux/module.h>
14 #include <linux/platform_device.h>
15 #include <linux/slab.h>
16 #include <linux/err.h>
17 #include <linux/clk.h>
19 #include <linux/interrupt.h>
20 #include <linux/delay.h>
23 #include <video/exynos_dp.h>
25 #include "exynos_dp_core.h"
27 static int exynos_dp_init_dp(struct exynos_dp_device *dp)
31 exynos_dp_swreset(dp);
33 exynos_dp_init_analog_param(dp);
34 exynos_dp_init_interrupt(dp);
36 /* SW defined function Normal operation */
37 exynos_dp_enable_sw_function(dp);
39 exynos_dp_config_interrupt(dp);
40 exynos_dp_init_analog_func(dp);
42 exynos_dp_init_hpd(dp);
43 exynos_dp_init_aux(dp);
48 static int exynos_dp_detect_hpd(struct exynos_dp_device *dp)
52 while (exynos_dp_get_plug_in_status(dp) != 0) {
54 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
55 dev_err(dp->dev, "failed to get hpd plug status\n");
64 static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data)
67 unsigned char sum = 0;
69 for (i = 0; i < EDID_BLOCK_LENGTH; i++)
70 sum = sum + edid_data[i];
75 static int exynos_dp_read_edid(struct exynos_dp_device *dp)
77 unsigned char edid[EDID_BLOCK_LENGTH * 2];
78 unsigned int extend_block = 0;
80 unsigned char test_vector;
84 * EDID device address is 0x50.
85 * However, if necessary, you must have set upper address
86 * into E-EDID in I2C device, 0x30.
89 /* Read Extension Flag, Number of 128-byte EDID extension blocks */
90 retval = exynos_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
96 if (extend_block > 0) {
97 dev_dbg(dp->dev, "EDID data includes a single extension!\n");
100 retval = exynos_dp_read_bytes_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
103 &edid[EDID_HEADER_PATTERN]);
105 dev_err(dp->dev, "EDID Read failed!\n");
108 sum = exynos_dp_calc_edid_check_sum(edid);
110 dev_err(dp->dev, "EDID bad checksum!\n");
114 /* Read additional EDID data */
115 retval = exynos_dp_read_bytes_from_i2c(dp,
116 I2C_EDID_DEVICE_ADDR,
119 &edid[EDID_BLOCK_LENGTH]);
121 dev_err(dp->dev, "EDID Read failed!\n");
124 sum = exynos_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH]);
126 dev_err(dp->dev, "EDID bad checksum!\n");
130 exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_TEST_REQUEST,
132 if (test_vector & DPCD_TEST_EDID_READ) {
133 exynos_dp_write_byte_to_dpcd(dp,
134 DPCD_ADDR_TEST_EDID_CHECKSUM,
135 edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
136 exynos_dp_write_byte_to_dpcd(dp,
137 DPCD_ADDR_TEST_RESPONSE,
138 DPCD_TEST_EDID_CHECKSUM_WRITE);
141 dev_info(dp->dev, "EDID data does not include any extensions.\n");
144 retval = exynos_dp_read_bytes_from_i2c(dp,
145 I2C_EDID_DEVICE_ADDR,
148 &edid[EDID_HEADER_PATTERN]);
150 dev_err(dp->dev, "EDID Read failed!\n");
153 sum = exynos_dp_calc_edid_check_sum(edid);
155 dev_err(dp->dev, "EDID bad checksum!\n");
159 exynos_dp_read_byte_from_dpcd(dp,
160 DPCD_ADDR_TEST_REQUEST,
162 if (test_vector & DPCD_TEST_EDID_READ) {
163 exynos_dp_write_byte_to_dpcd(dp,
164 DPCD_ADDR_TEST_EDID_CHECKSUM,
165 edid[EDID_CHECKSUM]);
166 exynos_dp_write_byte_to_dpcd(dp,
167 DPCD_ADDR_TEST_RESPONSE,
168 DPCD_TEST_EDID_CHECKSUM_WRITE);
172 dev_err(dp->dev, "EDID Read success!\n");
176 static int exynos_dp_handle_edid(struct exynos_dp_device *dp)
182 /* Read DPCD DPCD_ADDR_DPCD_REV~RECEIVE_PORT1_CAP_1 */
183 retval = exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_DPCD_REV,
189 for (i = 0; i < 3; i++) {
190 retval = exynos_dp_read_edid(dp);
198 static void exynos_dp_enable_rx_to_enhanced_mode(struct exynos_dp_device *dp,
203 exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET, &data);
206 exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET,
207 DPCD_ENHANCED_FRAME_EN |
208 DPCD_LANE_COUNT_SET(data));
210 exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET,
211 DPCD_LANE_COUNT_SET(data));
214 static int exynos_dp_is_enhanced_mode_available(struct exynos_dp_device *dp)
219 exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_MAX_LANE_COUNT, &data);
220 retval = DPCD_ENHANCED_FRAME_CAP(data);
225 static void exynos_dp_set_enhanced_mode(struct exynos_dp_device *dp)
229 data = exynos_dp_is_enhanced_mode_available(dp);
230 exynos_dp_enable_rx_to_enhanced_mode(dp, data);
231 exynos_dp_enable_enhanced_mode(dp, data);
234 static void exynos_dp_training_pattern_dis(struct exynos_dp_device *dp)
236 exynos_dp_set_training_pattern(dp, DP_NONE);
238 exynos_dp_write_byte_to_dpcd(dp,
239 DPCD_ADDR_TRAINING_PATTERN_SET,
240 DPCD_TRAINING_PATTERN_DISABLED);
243 static void exynos_dp_set_lane_lane_pre_emphasis(struct exynos_dp_device *dp,
244 int pre_emphasis, int lane)
248 exynos_dp_set_lane0_pre_emphasis(dp, pre_emphasis);
251 exynos_dp_set_lane1_pre_emphasis(dp, pre_emphasis);
255 exynos_dp_set_lane2_pre_emphasis(dp, pre_emphasis);
259 exynos_dp_set_lane3_pre_emphasis(dp, pre_emphasis);
264 static int exynos_dp_link_start(struct exynos_dp_device *dp)
267 int lane, lane_count, pll_tries, retval;
269 lane_count = dp->link_train.lane_count;
271 dp->link_train.lt_state = CLOCK_RECOVERY;
272 dp->link_train.eq_loop = 0;
274 for (lane = 0; lane < lane_count; lane++)
275 dp->link_train.cr_loop[lane] = 0;
277 /* Set link rate and count as you want to establish*/
278 exynos_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
279 exynos_dp_set_lane_count(dp, dp->link_train.lane_count);
281 /* Setup RX configuration */
282 buf[0] = dp->link_train.link_rate;
283 buf[1] = dp->link_train.lane_count;
284 retval = exynos_dp_write_bytes_to_dpcd(dp, DPCD_ADDR_LINK_BW_SET,
289 /* Set TX pre-emphasis to minimum */
290 for (lane = 0; lane < lane_count; lane++)
291 exynos_dp_set_lane_lane_pre_emphasis(dp,
292 PRE_EMPHASIS_LEVEL_0, lane);
294 /* Wait for PLL lock */
296 while (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
297 if (pll_tries == DP_TIMEOUT_LOOP_COUNT) {
298 dev_err(dp->dev, "Wait for PLL lock timed out\n");
303 usleep_range(90, 120);
306 /* Set training pattern 1 */
307 exynos_dp_set_training_pattern(dp, TRAINING_PTN1);
309 /* Set RX training pattern */
310 retval = exynos_dp_write_byte_to_dpcd(dp,
311 DPCD_ADDR_TRAINING_PATTERN_SET,
312 DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_1);
316 for (lane = 0; lane < lane_count; lane++)
317 buf[lane] = DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0 |
318 DPCD_VOLTAGE_SWING_PATTERN1_LEVEL0;
320 retval = exynos_dp_write_bytes_to_dpcd(dp, DPCD_ADDR_TRAINING_LANE0_SET,
326 static unsigned char exynos_dp_get_lane_status(u8 link_status[2], int lane)
328 int shift = (lane & 1) * 4;
329 u8 link_value = link_status[lane>>1];
331 return (link_value >> shift) & 0xf;
334 static int exynos_dp_clock_recovery_ok(u8 link_status[2], int lane_count)
339 for (lane = 0; lane < lane_count; lane++) {
340 lane_status = exynos_dp_get_lane_status(link_status, lane);
341 if ((lane_status & DPCD_LANE_CR_DONE) == 0)
347 static int exynos_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
353 if ((link_align & DPCD_INTERLANE_ALIGN_DONE) == 0)
356 for (lane = 0; lane < lane_count; lane++) {
357 lane_status = exynos_dp_get_lane_status(link_status, lane);
358 lane_status &= DPCD_CHANNEL_EQ_BITS;
359 if (lane_status != DPCD_CHANNEL_EQ_BITS)
366 static unsigned char exynos_dp_get_adjust_request_voltage(u8 adjust_request[2],
369 int shift = (lane & 1) * 4;
370 u8 link_value = adjust_request[lane>>1];
372 return (link_value >> shift) & 0x3;
375 static unsigned char exynos_dp_get_adjust_request_pre_emphasis(
376 u8 adjust_request[2],
379 int shift = (lane & 1) * 4;
380 u8 link_value = adjust_request[lane>>1];
382 return ((link_value >> shift) & 0xc) >> 2;
385 static void exynos_dp_set_lane_link_training(struct exynos_dp_device *dp,
386 u8 training_lane_set, int lane)
390 exynos_dp_set_lane0_link_training(dp, training_lane_set);
393 exynos_dp_set_lane1_link_training(dp, training_lane_set);
397 exynos_dp_set_lane2_link_training(dp, training_lane_set);
401 exynos_dp_set_lane3_link_training(dp, training_lane_set);
406 static unsigned int exynos_dp_get_lane_link_training(
407 struct exynos_dp_device *dp,
414 reg = exynos_dp_get_lane0_link_training(dp);
417 reg = exynos_dp_get_lane1_link_training(dp);
420 reg = exynos_dp_get_lane2_link_training(dp);
423 reg = exynos_dp_get_lane3_link_training(dp);
433 static void exynos_dp_reduce_link_rate(struct exynos_dp_device *dp)
435 exynos_dp_training_pattern_dis(dp);
436 exynos_dp_set_enhanced_mode(dp);
438 dp->link_train.lt_state = FAILED;
441 static void exynos_dp_get_adjust_training_lane(struct exynos_dp_device *dp,
442 u8 adjust_request[2])
444 int lane, lane_count;
445 u8 voltage_swing, pre_emphasis, training_lane;
447 lane_count = dp->link_train.lane_count;
448 for (lane = 0; lane < lane_count; lane++) {
449 voltage_swing = exynos_dp_get_adjust_request_voltage(
450 adjust_request, lane);
451 pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
452 adjust_request, lane);
453 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
454 DPCD_PRE_EMPHASIS_SET(pre_emphasis);
456 if (voltage_swing == VOLTAGE_LEVEL_3)
457 training_lane |= DPCD_MAX_SWING_REACHED;
458 if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
459 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
461 dp->link_train.training_lane[lane] = training_lane;
465 static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
467 int lane, lane_count, retval;
468 u8 voltage_swing, pre_emphasis, training_lane;
469 u8 link_status[2], adjust_request[2];
471 usleep_range(100, 101);
473 lane_count = dp->link_train.lane_count;
475 retval = exynos_dp_read_bytes_from_dpcd(dp,
476 DPCD_ADDR_LANE0_1_STATUS, 2, link_status);
480 retval = exynos_dp_read_bytes_from_dpcd(dp,
481 DPCD_ADDR_ADJUST_REQUEST_LANE0_1, 2, adjust_request);
485 if (exynos_dp_clock_recovery_ok(link_status, lane_count) == 0) {
486 /* set training pattern 2 for EQ */
487 exynos_dp_set_training_pattern(dp, TRAINING_PTN2);
489 retval = exynos_dp_write_byte_to_dpcd(dp,
490 DPCD_ADDR_TRAINING_PATTERN_SET,
491 DPCD_SCRAMBLING_DISABLED |
492 DPCD_TRAINING_PATTERN_2);
496 dev_info(dp->dev, "Link Training Clock Recovery success\n");
497 dp->link_train.lt_state = EQUALIZER_TRAINING;
499 for (lane = 0; lane < lane_count; lane++) {
500 training_lane = exynos_dp_get_lane_link_training(
502 voltage_swing = exynos_dp_get_adjust_request_voltage(
503 adjust_request, lane);
504 pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
505 adjust_request, lane);
507 if (DPCD_VOLTAGE_SWING_GET(training_lane) ==
509 DPCD_PRE_EMPHASIS_GET(training_lane) ==
511 dp->link_train.cr_loop[lane]++;
513 if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP ||
514 voltage_swing == VOLTAGE_LEVEL_3 ||
515 pre_emphasis == PRE_EMPHASIS_LEVEL_3) {
516 dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n",
517 dp->link_train.cr_loop[lane],
518 voltage_swing, pre_emphasis);
519 exynos_dp_reduce_link_rate(dp);
525 exynos_dp_get_adjust_training_lane(dp, adjust_request);
527 for (lane = 0; lane < lane_count; lane++)
528 exynos_dp_set_lane_link_training(dp,
529 dp->link_train.training_lane[lane], lane);
531 retval = exynos_dp_write_bytes_to_dpcd(dp,
532 DPCD_ADDR_TRAINING_LANE0_SET, lane_count,
533 dp->link_train.training_lane);
540 static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
542 int lane, lane_count, retval;
544 u8 link_align, link_status[2], adjust_request[2];
546 usleep_range(400, 401);
548 lane_count = dp->link_train.lane_count;
550 retval = exynos_dp_read_bytes_from_dpcd(dp,
551 DPCD_ADDR_LANE0_1_STATUS, 2, link_status);
555 if (exynos_dp_clock_recovery_ok(link_status, lane_count)) {
556 exynos_dp_reduce_link_rate(dp);
560 retval = exynos_dp_read_bytes_from_dpcd(dp,
561 DPCD_ADDR_ADJUST_REQUEST_LANE0_1, 2, adjust_request);
565 retval = exynos_dp_read_byte_from_dpcd(dp,
566 DPCD_ADDR_LANE_ALIGN_STATUS_UPDATED, &link_align);
570 exynos_dp_get_adjust_training_lane(dp, adjust_request);
572 if (!exynos_dp_channel_eq_ok(link_status, link_align, lane_count)) {
573 /* traing pattern Set to Normal */
574 exynos_dp_training_pattern_dis(dp);
576 dev_info(dp->dev, "Link Training success!\n");
578 exynos_dp_get_link_bandwidth(dp, ®);
579 dp->link_train.link_rate = reg;
580 dev_dbg(dp->dev, "final bandwidth = %.2x\n",
581 dp->link_train.link_rate);
583 exynos_dp_get_lane_count(dp, ®);
584 dp->link_train.lane_count = reg;
585 dev_dbg(dp->dev, "final lane count = %.2x\n",
586 dp->link_train.lane_count);
588 /* set enhanced mode if available */
589 exynos_dp_set_enhanced_mode(dp);
590 dp->link_train.lt_state = FINISHED;
596 dp->link_train.eq_loop++;
598 if (dp->link_train.eq_loop > MAX_EQ_LOOP) {
599 dev_err(dp->dev, "EQ Max loop\n");
600 exynos_dp_reduce_link_rate(dp);
604 for (lane = 0; lane < lane_count; lane++)
605 exynos_dp_set_lane_link_training(dp,
606 dp->link_train.training_lane[lane], lane);
608 retval = exynos_dp_write_bytes_to_dpcd(dp, DPCD_ADDR_TRAINING_LANE0_SET,
609 lane_count, dp->link_train.training_lane);
614 static void exynos_dp_get_max_rx_bandwidth(struct exynos_dp_device *dp,
620 * For DP rev.1.1, Maximum link rate of Main Link lanes
621 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
623 exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_MAX_LINK_RATE, &data);
627 static void exynos_dp_get_max_rx_lane_count(struct exynos_dp_device *dp,
633 * For DP rev.1.1, Maximum number of Main Link lanes
634 * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
636 exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_MAX_LANE_COUNT, &data);
637 *lane_count = DPCD_MAX_LANE_COUNT(data);
640 static void exynos_dp_init_training(struct exynos_dp_device *dp,
641 enum link_lane_count_type max_lane,
642 enum link_rate_type max_rate)
645 * MACRO_RST must be applied after the PLL_LOCK to avoid
646 * the DP inter pair skew issue for at least 10 us
648 exynos_dp_reset_macro(dp);
650 /* Initialize by reading RX's DPCD */
651 exynos_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
652 exynos_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
654 if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
655 (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
656 dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
657 dp->link_train.link_rate);
658 dp->link_train.link_rate = LINK_RATE_1_62GBPS;
661 if (dp->link_train.lane_count == 0) {
662 dev_err(dp->dev, "Rx Max Lane count is abnormal :%x !\n",
663 dp->link_train.lane_count);
664 dp->link_train.lane_count = (u8)LANE_COUNT1;
667 /* Setup TX lane count & rate */
668 if (dp->link_train.lane_count > max_lane)
669 dp->link_train.lane_count = max_lane;
670 if (dp->link_train.link_rate > max_rate)
671 dp->link_train.link_rate = max_rate;
673 /* All DP analog module power up */
674 exynos_dp_set_analog_power_down(dp, POWER_ALL, 0);
677 static int exynos_dp_sw_link_training(struct exynos_dp_device *dp)
679 int retval = 0, training_finished = 0;
681 dp->link_train.lt_state = START;
684 while (!retval && !training_finished) {
685 switch (dp->link_train.lt_state) {
687 retval = exynos_dp_link_start(dp);
689 dev_err(dp->dev, "LT link start failed!\n");
692 retval = exynos_dp_process_clock_recovery(dp);
694 dev_err(dp->dev, "LT CR failed!\n");
696 case EQUALIZER_TRAINING:
697 retval = exynos_dp_process_equalizer_training(dp);
699 dev_err(dp->dev, "LT EQ failed!\n");
702 training_finished = 1;
709 dev_err(dp->dev, "eDP link training failed (%d)\n", retval);
714 static int exynos_dp_set_link_train(struct exynos_dp_device *dp,
721 for (i = 0; i < DP_TIMEOUT_LOOP_COUNT; i++) {
722 exynos_dp_init_training(dp, count, bwtype);
723 retval = exynos_dp_sw_link_training(dp);
727 usleep_range(100, 110);
733 static int exynos_dp_config_video(struct exynos_dp_device *dp)
736 int timeout_loop = 0;
739 exynos_dp_config_video_slave_mode(dp);
741 exynos_dp_set_video_color_format(dp);
743 if (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
744 dev_err(dp->dev, "PLL is not locked yet.\n");
750 if (exynos_dp_is_slave_video_stream_clock_on(dp) == 0)
752 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
753 dev_err(dp->dev, "Timeout of video streamclk ok\n");
760 /* Set to use the register calculated M/N video */
761 exynos_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0);
763 /* For video bist, Video timing must be generated by register */
764 exynos_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE);
766 /* Disable video mute */
767 exynos_dp_enable_video_mute(dp, 0);
769 /* Configure video slave mode */
770 exynos_dp_enable_video_master(dp, 0);
773 exynos_dp_start_video(dp);
779 if (exynos_dp_is_video_stream_on(dp) == 0) {
783 } else if (done_count) {
786 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
787 dev_err(dp->dev, "Timeout of video streamclk ok\n");
791 usleep_range(1000, 1001);
795 dev_err(dp->dev, "Video stream is not detected!\n");
800 static void exynos_dp_enable_scramble(struct exynos_dp_device *dp, bool enable)
805 exynos_dp_enable_scrambling(dp);
807 exynos_dp_read_byte_from_dpcd(dp,
808 DPCD_ADDR_TRAINING_PATTERN_SET,
810 exynos_dp_write_byte_to_dpcd(dp,
811 DPCD_ADDR_TRAINING_PATTERN_SET,
812 (u8)(data & ~DPCD_SCRAMBLING_DISABLED));
814 exynos_dp_disable_scrambling(dp);
816 exynos_dp_read_byte_from_dpcd(dp,
817 DPCD_ADDR_TRAINING_PATTERN_SET,
819 exynos_dp_write_byte_to_dpcd(dp,
820 DPCD_ADDR_TRAINING_PATTERN_SET,
821 (u8)(data | DPCD_SCRAMBLING_DISABLED));
825 static irqreturn_t exynos_dp_irq_handler(int irq, void *arg)
827 struct exynos_dp_device *dp = arg;
829 enum dp_irq_type irq_type;
831 irq_type = exynos_dp_get_irq_type(dp);
833 case DP_IRQ_TYPE_HP_CABLE_IN:
834 dev_dbg(dp->dev, "Received irq - cable in\n");
835 schedule_work(&dp->hotplug_work);
836 exynos_dp_clear_hotplug_interrupts(dp);
838 case DP_IRQ_TYPE_HP_CABLE_OUT:
839 dev_dbg(dp->dev, "Received irq - cable out\n");
840 exynos_dp_clear_hotplug_interrupts(dp);
842 case DP_IRQ_TYPE_HP_CHANGE:
844 * We get these change notifications once in a while, but there
845 * is nothing we can do with them. Just ignore it for now and
846 * only handle cable changes.
848 dev_dbg(dp->dev, "Received irq - hotplug change; ignoring.\n");
849 exynos_dp_clear_hotplug_interrupts(dp);
852 dev_err(dp->dev, "Received irq - unknown type!\n");
858 static void exynos_dp_hotplug(struct work_struct *work)
860 struct exynos_dp_device *dp;
863 dp = container_of(work, struct exynos_dp_device, hotplug_work);
865 ret = exynos_dp_detect_hpd(dp);
867 /* Cable has been disconnected, we're done */
871 ret = exynos_dp_handle_edid(dp);
873 dev_err(dp->dev, "unable to handle edid\n");
877 ret = exynos_dp_set_link_train(dp, dp->video_info->lane_count,
878 dp->video_info->link_rate);
880 dev_err(dp->dev, "unable to do link train\n");
884 exynos_dp_enable_scramble(dp, 1);
885 exynos_dp_enable_rx_to_enhanced_mode(dp, 1);
886 exynos_dp_enable_enhanced_mode(dp, 1);
888 exynos_dp_set_lane_count(dp, dp->video_info->lane_count);
889 exynos_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
891 exynos_dp_init_video(dp);
892 ret = exynos_dp_config_video(dp);
894 dev_err(dp->dev, "unable to config video\n");
898 static struct exynos_dp_platdata *exynos_dp_dt_parse_pdata(struct device *dev)
900 struct device_node *dp_node = dev->of_node;
901 struct exynos_dp_platdata *pd;
902 struct video_info *dp_video_config;
904 pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
906 dev_err(dev, "memory allocation for pdata failed\n");
907 return ERR_PTR(-ENOMEM);
909 dp_video_config = devm_kzalloc(dev,
910 sizeof(*dp_video_config), GFP_KERNEL);
912 if (!dp_video_config) {
913 dev_err(dev, "memory allocation for video config failed\n");
914 return ERR_PTR(-ENOMEM);
916 pd->video_info = dp_video_config;
918 dp_video_config->h_sync_polarity =
919 of_property_read_bool(dp_node, "hsync-active-high");
921 dp_video_config->v_sync_polarity =
922 of_property_read_bool(dp_node, "vsync-active-high");
924 dp_video_config->interlaced =
925 of_property_read_bool(dp_node, "interlaced");
927 if (of_property_read_u32(dp_node, "samsung,color-space",
928 &dp_video_config->color_space)) {
929 dev_err(dev, "failed to get color-space\n");
930 return ERR_PTR(-EINVAL);
933 if (of_property_read_u32(dp_node, "samsung,dynamic-range",
934 &dp_video_config->dynamic_range)) {
935 dev_err(dev, "failed to get dynamic-range\n");
936 return ERR_PTR(-EINVAL);
939 if (of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
940 &dp_video_config->ycbcr_coeff)) {
941 dev_err(dev, "failed to get ycbcr-coeff\n");
942 return ERR_PTR(-EINVAL);
945 if (of_property_read_u32(dp_node, "samsung,color-depth",
946 &dp_video_config->color_depth)) {
947 dev_err(dev, "failed to get color-depth\n");
948 return ERR_PTR(-EINVAL);
951 if (of_property_read_u32(dp_node, "samsung,link-rate",
952 &dp_video_config->link_rate)) {
953 dev_err(dev, "failed to get link-rate\n");
954 return ERR_PTR(-EINVAL);
957 if (of_property_read_u32(dp_node, "samsung,lane-count",
958 &dp_video_config->lane_count)) {
959 dev_err(dev, "failed to get lane-count\n");
960 return ERR_PTR(-EINVAL);
966 static int exynos_dp_dt_parse_phydata(struct exynos_dp_device *dp)
968 struct device_node *dp_phy_node;
971 dp_phy_node = of_find_node_by_name(dp->dev->of_node, "dptx-phy");
973 dev_err(dp->dev, "could not find dptx-phy node\n");
977 if (of_property_read_u32(dp_phy_node, "reg", &phy_base)) {
978 dev_err(dp->dev, "faild to get reg for dptx-phy\n");
982 if (of_property_read_u32(dp_phy_node, "samsung,enable-mask",
984 dev_err(dp->dev, "faild to get enable-mask for dptx-phy\n");
988 dp->phy_addr = ioremap(phy_base, SZ_4);
990 dev_err(dp->dev, "failed to ioremap dp-phy\n");
997 static void exynos_dp_phy_init(struct exynos_dp_device *dp)
1001 reg = __raw_readl(dp->phy_addr);
1002 reg |= dp->enable_mask;
1003 __raw_writel(reg, dp->phy_addr);
1006 static void exynos_dp_phy_exit(struct exynos_dp_device *dp)
1010 reg = __raw_readl(dp->phy_addr);
1011 reg &= ~(dp->enable_mask);
1012 __raw_writel(reg, dp->phy_addr);
1015 static struct exynos_dp_platdata *exynos_dp_dt_parse_pdata(struct device *dev)
1020 static int exynos_dp_dt_parse_phydata(struct exynos_dp_device *dp)
1025 static void exynos_dp_phy_init(struct exynos_dp_device *dp)
1030 static void exynos_dp_phy_exit(struct exynos_dp_device *dp)
1034 #endif /* CONFIG_OF */
1036 static int exynos_dp_probe(struct platform_device *pdev)
1038 struct resource *res;
1039 struct exynos_dp_device *dp;
1040 struct exynos_dp_platdata *pdata;
1044 dp = devm_kzalloc(&pdev->dev, sizeof(struct exynos_dp_device),
1047 dev_err(&pdev->dev, "no memory for device data\n");
1051 dp->dev = &pdev->dev;
1053 if (pdev->dev.of_node) {
1054 pdata = exynos_dp_dt_parse_pdata(&pdev->dev);
1056 return PTR_ERR(pdata);
1058 ret = exynos_dp_dt_parse_phydata(dp);
1062 pdata = pdev->dev.platform_data;
1064 dev_err(&pdev->dev, "no platform data\n");
1069 dp->clock = devm_clk_get(&pdev->dev, "dp");
1070 if (IS_ERR(dp->clock)) {
1071 dev_err(&pdev->dev, "failed to get clock\n");
1072 return PTR_ERR(dp->clock);
1075 clk_prepare_enable(dp->clock);
1077 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1079 dp->reg_base = devm_request_and_ioremap(&pdev->dev, res);
1080 if (!dp->reg_base) {
1081 dev_err(&pdev->dev, "failed to ioremap\n");
1085 dp->irq = platform_get_irq(pdev, 0);
1086 if (dp->irq == -ENXIO) {
1087 dev_err(&pdev->dev, "failed to get irq\n");
1091 INIT_WORK(&dp->hotplug_work, exynos_dp_hotplug);
1093 dp->video_info = pdata->video_info;
1095 if (pdev->dev.of_node) {
1097 exynos_dp_phy_init(dp);
1099 if (pdata->phy_init)
1103 exynos_dp_init_dp(dp);
1105 ret = devm_request_irq(&pdev->dev, dp->irq, exynos_dp_irq_handler, 0,
1108 dev_err(&pdev->dev, "failed to request irq\n");
1112 platform_set_drvdata(pdev, dp);
1117 static int exynos_dp_remove(struct platform_device *pdev)
1119 struct exynos_dp_platdata *pdata = pdev->dev.platform_data;
1120 struct exynos_dp_device *dp = platform_get_drvdata(pdev);
1122 disable_irq(dp->irq);
1124 if (work_pending(&dp->hotplug_work))
1125 flush_work(&dp->hotplug_work);
1127 if (pdev->dev.of_node) {
1129 exynos_dp_phy_exit(dp);
1131 if (pdata->phy_exit)
1135 clk_disable_unprepare(dp->clock);
1141 #ifdef CONFIG_PM_SLEEP
1142 static int exynos_dp_suspend(struct device *dev)
1144 struct exynos_dp_platdata *pdata = dev->platform_data;
1145 struct exynos_dp_device *dp = dev_get_drvdata(dev);
1147 if (work_pending(&dp->hotplug_work))
1148 flush_work(&dp->hotplug_work);
1152 exynos_dp_phy_exit(dp);
1154 if (pdata->phy_exit)
1158 clk_disable_unprepare(dp->clock);
1163 static int exynos_dp_resume(struct device *dev)
1165 struct exynos_dp_platdata *pdata = dev->platform_data;
1166 struct exynos_dp_device *dp = dev_get_drvdata(dev);
1170 exynos_dp_phy_init(dp);
1172 if (pdata->phy_init)
1176 clk_prepare_enable(dp->clock);
1178 exynos_dp_init_dp(dp);
1180 enable_irq(dp->irq);
1186 static const struct dev_pm_ops exynos_dp_pm_ops = {
1187 SET_SYSTEM_SLEEP_PM_OPS(exynos_dp_suspend, exynos_dp_resume)
1190 static const struct of_device_id exynos_dp_match[] = {
1191 { .compatible = "samsung,exynos5-dp" },
1194 MODULE_DEVICE_TABLE(of, exynos_dp_match);
1196 static struct platform_driver exynos_dp_driver = {
1197 .probe = exynos_dp_probe,
1198 .remove = exynos_dp_remove,
1200 .name = "exynos-dp",
1201 .owner = THIS_MODULE,
1202 .pm = &exynos_dp_pm_ops,
1203 .of_match_table = of_match_ptr(exynos_dp_match),
1207 module_platform_driver(exynos_dp_driver);
1209 MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
1210 MODULE_DESCRIPTION("Samsung SoC DP Driver");
1211 MODULE_LICENSE("GPL");