2 * Copyright (C) 2012 Samsung Electronics
4 * Author: Donghwa Lee <dh09.lee@samsung.com>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <linux/err.h>
25 #include <asm/arch/cpu.h>
26 #include <asm/arch/dp_info.h>
27 #include <asm/arch/dp.h>
29 static void exynos_dp_enable_video_input(unsigned int enable)
32 struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
34 reg = readl(&dp_regs->video_ctl1);
35 reg &= ~VIDEO_EN_MASK;
37 /* enable video input*/
41 writel(reg, &dp_regs->video_ctl1);
46 void exynos_dp_enable_video_bist(unsigned int enable)
50 struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
52 reg = readl(&dp_regs->video_ctl4);
53 reg &= ~VIDEO_BIST_MASK;
57 reg |= VIDEO_BIST_MASK;
59 writel(reg, &dp_regs->video_ctl4);
64 void exynos_dp_enable_video_mute(unsigned int enable)
67 struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
69 reg = readl(&dp_regs->video_ctl1);
70 reg &= ~(VIDEO_MUTE_MASK);
72 reg |= VIDEO_MUTE_MASK;
74 writel(reg, &dp_regs->video_ctl1);
80 static void exynos_dp_init_analog_param(void)
83 struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
87 * Normal bandgap, Normal swing, Tx terminal registor 61 ohm
88 * 24M Phy clock, TX digital logic power is 100:1.0625V
90 reg = SEL_BG_NEW_BANDGAP | TX_TERMINAL_CTRL_61_OHM |
91 SWING_A_30PER_G_NORMAL;
92 writel(reg, &dp_regs->analog_ctl1);
94 reg = SEL_24M | TX_DVDD_BIT_1_0625V;
95 writel(reg, &dp_regs->analog_ctl2);
98 * Set power source for internal clk driver to 1.0625v.
99 * Select current reference of TX driver current to 00:Ipp/2+Ic/2.
100 * Set VCO range of PLL +- 0uA
102 reg = DRIVE_DVDD_BIT_1_0625V | SEL_CURRENT_DEFAULT | VCO_BIT_000_MICRO;
103 writel(reg, &dp_regs->analog_ctl3);
106 * Set AUX TX terminal resistor to 102 ohm
107 * Set AUX channel amplitude control
109 reg = PD_RING_OSC | AUX_TERMINAL_CTRL_52_OHM | TX_CUR1_2X | TX_CUR_4_MA;
110 writel(reg, &dp_regs->pll_filter_ctl1);
113 * PLL loop filter bandwidth
114 * For 2.7Gbps: 175KHz, For 1.62Gbps: 234KHz
115 * PLL digital power select: 1.2500V
117 reg = CH3_AMP_0_MV | CH2_AMP_0_MV | CH1_AMP_0_MV | CH0_AMP_0_MV;
119 writel(reg, &dp_regs->amp_tuning_ctl);
122 * PLL loop filter bandwidth
123 * For 2.7Gbps: 175KHz, For 1.62Gbps: 234KHz
124 * PLL digital power select: 1.1250V
126 reg = DP_PLL_LOOP_BIT_DEFAULT | DP_PLL_REF_BIT_1_1250V;
127 writel(reg, &dp_regs->pll_ctl);
130 static void exynos_dp_init_interrupt(void)
132 struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
133 /* Set interrupt registers to initial states */
137 * INT pin assertion polarity. It must be configured
138 * correctly according to ICU setting.
139 * 1 = assert high, 0 = assert low
141 writel(INT_POL, &dp_regs->int_ctl);
143 /* Clear pending regisers */
144 writel(0xff, &dp_regs->common_int_sta1);
145 writel(0xff, &dp_regs->common_int_sta2);
146 writel(0xff, &dp_regs->common_int_sta3);
147 writel(0xff, &dp_regs->common_int_sta4);
148 writel(0xff, &dp_regs->int_sta);
150 /* 0:mask,1: unmask */
151 writel(0x00, &dp_regs->int_sta_mask1);
152 writel(0x00, &dp_regs->int_sta_mask2);
153 writel(0x00, &dp_regs->int_sta_mask3);
154 writel(0x00, &dp_regs->int_sta_mask4);
155 writel(0x00, &dp_regs->int_sta_mask);
158 void exynos_dp_reset(void)
160 unsigned int reg_func_1;
161 struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
164 writel(RESET_DP_TX, &dp_regs->tx_sw_reset);
166 exynos_dp_enable_video_input(DP_DISABLE);
167 exynos_dp_enable_video_bist(DP_DISABLE);
168 exynos_dp_enable_video_mute(DP_DISABLE);
171 reg_func_1 = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N |
172 AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N |
173 HDCP_FUNC_EN_N | SW_FUNC_EN_N;
175 writel(reg_func_1, &dp_regs->func_en1);
176 writel(reg_func_1, &dp_regs->func_en2);
180 exynos_dp_init_analog_param();
181 exynos_dp_init_interrupt();
186 void exynos_dp_enable_sw_func(unsigned int enable)
189 struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
191 reg = readl(&dp_regs->func_en1);
192 reg &= ~(SW_FUNC_EN_N);
197 writel(reg, &dp_regs->func_en1);
202 unsigned int exynos_dp_set_analog_power_down(unsigned int block, u32 enable)
205 struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
207 reg = readl(&dp_regs->phy_pd);
240 reg &= ~(PHY_PD | AUX_PD | CH0_PD | CH1_PD | CH2_PD |
243 reg |= (PHY_PD | AUX_PD | CH0_PD | CH1_PD |
247 printf("DP undefined block number : %d\n", block);
251 writel(reg, &dp_regs->phy_pd);
256 unsigned int exynos_dp_get_pll_lock_status(void)
259 struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
261 reg = readl(&dp_regs->debug_ctl);
269 static void exynos_dp_set_pll_power(unsigned int enable)
272 struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
274 reg = readl(&dp_regs->pll_ctl);
280 writel(reg, &dp_regs->pll_ctl);
283 int exynos_dp_init_analog_func(void)
285 int ret = EXYNOS_DP_SUCCESS;
286 unsigned int retry_cnt = 10;
288 struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
290 /*Power On All Analog block */
291 exynos_dp_set_analog_power_down(POWER_ALL, DP_DISABLE);
294 writel(reg, &dp_regs->common_int_sta1);
296 reg = readl(&dp_regs->debug_ctl);
297 reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL);
298 writel(reg, &dp_regs->debug_ctl);
300 /*Assert DP PLL Reset*/
301 reg = readl(&dp_regs->pll_ctl);
303 writel(reg, &dp_regs->pll_ctl);
307 /*Deassert DP PLL Reset*/
308 reg = readl(&dp_regs->pll_ctl);
309 reg &= ~(DP_PLL_RESET);
310 writel(reg, &dp_regs->pll_ctl);
312 exynos_dp_set_pll_power(DP_ENABLE);
314 while (exynos_dp_get_pll_lock_status() == PLL_UNLOCKED) {
317 if (retry_cnt == 0) {
318 printf("DP dp's pll lock failed : retry : %d\n",
324 debug("dp's pll lock success(%d)\n", retry_cnt);
326 /* Enable Serdes FIFO function and Link symbol clock domain module */
327 reg = readl(&dp_regs->func_en2);
328 reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N
330 writel(reg, &dp_regs->func_en2);
335 void exynos_dp_init_hpd(void)
338 struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
340 /* Clear interrupts releated to Hot Plug Dectect */
341 reg = HOTPLUG_CHG | HPD_LOST | PLUG;
342 writel(reg, &dp_regs->common_int_sta4);
345 writel(reg, &dp_regs->int_sta);
347 reg = readl(&dp_regs->sys_ctl3);
348 reg &= ~(F_HPD | HPD_CTRL);
349 writel(reg, &dp_regs->sys_ctl3);
354 static inline void exynos_dp_reset_aux(void)
357 struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
359 /* Disable AUX channel module */
360 reg = readl(&dp_regs->func_en2);
361 reg |= AUX_FUNC_EN_N;
362 writel(reg, &dp_regs->func_en2);
367 void exynos_dp_init_aux(void)
370 struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
372 /* Clear inerrupts related to AUX channel */
373 reg = RPLY_RECEIV | AUX_ERR;
374 writel(reg, &dp_regs->int_sta);
376 exynos_dp_reset_aux();
378 /* Disable AUX transaction H/W retry */
379 reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(3)|
380 AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
381 writel(reg, &dp_regs->aux_hw_retry_ctl);
383 /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
384 reg = DEFER_CTRL_EN | DEFER_COUNT(1);
385 writel(reg, &dp_regs->aux_ch_defer_ctl);
387 /* Enable AUX channel module */
388 reg = readl(&dp_regs->func_en2);
389 reg &= ~AUX_FUNC_EN_N;
390 writel(reg, &dp_regs->func_en2);
395 void exynos_dp_config_interrupt(void)
398 struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
400 /* 0: mask, 1: unmask */
401 reg = COMMON_INT_MASK_1;
402 writel(reg, &dp_regs->common_int_mask1);
404 reg = COMMON_INT_MASK_2;
405 writel(reg, &dp_regs->common_int_mask2);
407 reg = COMMON_INT_MASK_3;
408 writel(reg, &dp_regs->common_int_mask3);
410 reg = COMMON_INT_MASK_4;
411 writel(reg, &dp_regs->common_int_mask4);
414 writel(reg, &dp_regs->int_sta_mask);
419 unsigned int exynos_dp_get_plug_in_status(void)
422 struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
424 reg = readl(&dp_regs->sys_ctl3);
425 if (reg & HPD_STATUS)
431 unsigned int exynos_dp_detect_hpd(void)
433 int timeout_loop = DP_TIMEOUT_LOOP_COUNT;
437 while (exynos_dp_get_plug_in_status() != 0) {
438 if (timeout_loop == 0)
444 return EXYNOS_DP_SUCCESS;
447 unsigned int exynos_dp_start_aux_transaction(void)
450 unsigned int ret = 0;
451 unsigned int retry_cnt;
452 struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
454 /* Enable AUX CH operation */
455 reg = readl(&dp_regs->aux_ch_ctl2);
457 writel(reg, &dp_regs->aux_ch_ctl2);
461 reg = readl(&dp_regs->int_sta);
462 if (!(reg & RPLY_RECEIV)) {
463 if (retry_cnt == 0) {
464 printf("DP Reply Timeout!!\n");
474 /* Clear interrupt source for AUX CH command reply */
475 writel(reg, &dp_regs->int_sta);
477 /* Clear interrupt source for AUX CH access error */
478 reg = readl(&dp_regs->int_sta);
480 printf("DP Aux Access Error\n");
481 writel(AUX_ERR, &dp_regs->int_sta);
486 /* Check AUX CH error access status */
487 reg = readl(&dp_regs->aux_ch_sta);
488 if ((reg & AUX_STATUS_MASK) != 0) {
489 debug("DP AUX CH error happens: %x\n", reg & AUX_STATUS_MASK);
494 return EXYNOS_DP_SUCCESS;
497 unsigned int exynos_dp_write_byte_to_dpcd(unsigned int reg_addr,
500 unsigned int reg, ret;
501 struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
503 /* Clear AUX CH data buffer */
505 writel(reg, &dp_regs->buffer_data_ctl);
507 /* Select DPCD device address */
508 reg = AUX_ADDR_7_0(reg_addr);
509 writel(reg, &dp_regs->aux_addr_7_0);
510 reg = AUX_ADDR_15_8(reg_addr);
511 writel(reg, &dp_regs->aux_addr_15_8);
512 reg = AUX_ADDR_19_16(reg_addr);
513 writel(reg, &dp_regs->aux_addr_19_16);
515 /* Write data buffer */
516 reg = (unsigned int)data;
517 writel(reg, &dp_regs->buf_data0);
520 * Set DisplayPort transaction and write 1 byte
521 * If bit 3 is 1, DisplayPort transaction.
522 * If Bit 3 is 0, I2C transaction.
524 reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
525 writel(reg, &dp_regs->aux_ch_ctl1);
527 /* Start AUX transaction */
528 ret = exynos_dp_start_aux_transaction();
529 if (ret != EXYNOS_DP_SUCCESS) {
530 printf("DP Aux transaction failed\n");
537 unsigned int exynos_dp_read_byte_from_dpcd(unsigned int reg_addr,
542 struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
544 /* Clear AUX CH data buffer */
546 writel(reg, &dp_regs->buffer_data_ctl);
548 /* Select DPCD device address */
549 reg = AUX_ADDR_7_0(reg_addr);
550 writel(reg, &dp_regs->aux_addr_7_0);
551 reg = AUX_ADDR_15_8(reg_addr);
552 writel(reg, &dp_regs->aux_addr_15_8);
553 reg = AUX_ADDR_19_16(reg_addr);
554 writel(reg, &dp_regs->aux_addr_19_16);
557 * Set DisplayPort transaction and read 1 byte
558 * If bit 3 is 1, DisplayPort transaction.
559 * If Bit 3 is 0, I2C transaction.
561 reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
562 writel(reg, &dp_regs->aux_ch_ctl1);
564 /* Start AUX transaction */
565 retval = exynos_dp_start_aux_transaction();
567 debug("DP Aux Transaction fail!\n");
569 /* Read data buffer */
570 reg = readl(&dp_regs->buf_data0);
571 *data = (unsigned char)(reg & 0xff);
576 unsigned int exynos_dp_write_bytes_to_dpcd(unsigned int reg_addr,
578 unsigned char data[])
581 unsigned int start_offset;
582 unsigned int cur_data_count;
583 unsigned int cur_data_idx;
584 unsigned int retry_cnt;
585 unsigned int ret = 0;
586 struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
588 /* Clear AUX CH data buffer */
590 writel(reg, &dp_regs->buffer_data_ctl);
593 while (start_offset < count) {
594 /* Buffer size of AUX CH is 16 * 4bytes */
595 if ((count - start_offset) > 16)
598 cur_data_count = count - start_offset;
602 /* Select DPCD device address */
603 reg = AUX_ADDR_7_0(reg_addr + start_offset);
604 writel(reg, &dp_regs->aux_addr_7_0);
605 reg = AUX_ADDR_15_8(reg_addr + start_offset);
606 writel(reg, &dp_regs->aux_addr_15_8);
607 reg = AUX_ADDR_19_16(reg_addr + start_offset);
608 writel(reg, &dp_regs->aux_addr_19_16);
610 for (cur_data_idx = 0; cur_data_idx < cur_data_count;
612 reg = data[start_offset + cur_data_idx];
613 writel(reg, (unsigned int)&dp_regs->buf_data0 +
617 * Set DisplayPort transaction and write
618 * If bit 3 is 1, DisplayPort transaction.
619 * If Bit 3 is 0, I2C transaction.
621 reg = AUX_LENGTH(cur_data_count) |
622 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
623 writel(reg, &dp_regs->aux_ch_ctl1);
625 /* Start AUX transaction */
626 ret = exynos_dp_start_aux_transaction();
627 if (ret != EXYNOS_DP_SUCCESS) {
628 if (retry_cnt == 0) {
629 printf("DP Aux Transaction failed\n");
636 start_offset += cur_data_count;
642 unsigned int exynos_dp_read_bytes_from_dpcd(unsigned int reg_addr,
644 unsigned char data[])
647 unsigned int start_offset;
648 unsigned int cur_data_count;
649 unsigned int cur_data_idx;
650 unsigned int retry_cnt;
651 unsigned int ret = 0;
652 struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
654 /* Clear AUX CH data buffer */
656 writel(reg, &dp_regs->buffer_data_ctl);
659 while (start_offset < count) {
660 /* Buffer size of AUX CH is 16 * 4bytes */
661 if ((count - start_offset) > 16)
664 cur_data_count = count - start_offset;
668 /* Select DPCD device address */
669 reg = AUX_ADDR_7_0(reg_addr + start_offset);
670 writel(reg, &dp_regs->aux_addr_7_0);
671 reg = AUX_ADDR_15_8(reg_addr + start_offset);
672 writel(reg, &dp_regs->aux_addr_15_8);
673 reg = AUX_ADDR_19_16(reg_addr + start_offset);
674 writel(reg, &dp_regs->aux_addr_19_16);
676 * Set DisplayPort transaction and read
677 * If bit 3 is 1, DisplayPort transaction.
678 * If Bit 3 is 0, I2C transaction.
680 reg = AUX_LENGTH(cur_data_count) |
681 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
682 writel(reg, &dp_regs->aux_ch_ctl1);
684 /* Start AUX transaction */
685 ret = exynos_dp_start_aux_transaction();
686 if (ret != EXYNOS_DP_SUCCESS) {
687 if (retry_cnt == 0) {
688 printf("DP Aux Transaction failed\n");
696 for (cur_data_idx = 0; cur_data_idx < cur_data_count;
698 reg = readl((unsigned int)&dp_regs->buf_data0 +
700 data[start_offset + cur_data_idx] = (unsigned char)reg;
703 start_offset += cur_data_count;
709 int exynos_dp_select_i2c_device(unsigned int device_addr,
710 unsigned int reg_addr)
714 struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
716 /* Set EDID device address */
718 writel(reg, &dp_regs->aux_addr_7_0);
719 writel(0x0, &dp_regs->aux_addr_15_8);
720 writel(0x0, &dp_regs->aux_addr_19_16);
722 /* Set offset from base address of EDID device */
723 writel(reg_addr, &dp_regs->buf_data0);
726 * Set I2C transaction and write address
727 * If bit 3 is 1, DisplayPort transaction.
728 * If Bit 3 is 0, I2C transaction.
730 reg = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT |
732 writel(reg, &dp_regs->aux_ch_ctl1);
734 /* Start AUX transaction */
735 retval = exynos_dp_start_aux_transaction();
737 printf("%s: DP Aux Transaction fail!\n", __func__);
742 int exynos_dp_read_byte_from_i2c(unsigned int device_addr,
743 unsigned int reg_addr,
749 struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
751 for (i = 0; i < 10; i++) {
752 /* Clear AUX CH data buffer */
754 writel(reg, &dp_regs->buffer_data_ctl);
756 /* Select EDID device */
757 retval = exynos_dp_select_i2c_device(device_addr, reg_addr);
759 printf("DP Select EDID device fail. retry !\n");
764 * Set I2C transaction and read data
765 * If bit 3 is 1, DisplayPort transaction.
766 * If Bit 3 is 0, I2C transaction.
768 reg = AUX_TX_COMM_I2C_TRANSACTION |
770 writel(reg, &dp_regs->aux_ch_ctl1);
772 /* Start AUX transaction */
773 retval = exynos_dp_start_aux_transaction();
774 if (retval != EXYNOS_DP_SUCCESS)
775 printf("%s: DP Aux Transaction fail!\n", __func__);
780 *data = readl(&dp_regs->buf_data0);
785 int exynos_dp_read_bytes_from_i2c(unsigned int device_addr,
786 unsigned int reg_addr, unsigned int count, unsigned char edid[])
790 unsigned int cur_data_idx;
791 unsigned int defer = 0;
793 struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
795 for (i = 0; i < count; i += 16) { /* use 16 burst */
796 for (j = 0; j < 100; j++) {
797 /* Clear AUX CH data buffer */
799 writel(reg, &dp_regs->buffer_data_ctl);
801 /* Set normal AUX CH command */
802 reg = readl(&dp_regs->aux_ch_ctl2);
804 writel(reg, &dp_regs->aux_ch_ctl2);
807 * If Rx sends defer, Tx sends only reads
808 * request without sending addres
812 exynos_dp_select_i2c_device(device_addr,
817 if (retval == EXYNOS_DP_SUCCESS) {
819 * Set I2C transaction and write data
820 * If bit 3 is 1, DisplayPort transaction.
821 * If Bit 3 is 0, I2C transaction.
823 reg = AUX_LENGTH(16) |
824 AUX_TX_COMM_I2C_TRANSACTION |
826 writel(reg, &dp_regs->aux_ch_ctl1);
828 /* Start AUX transaction */
829 retval = exynos_dp_start_aux_transaction();
833 printf("DP Aux Transaction fail!\n");
835 /* Check if Rx sends defer */
836 reg = readl(&dp_regs->aux_rx_comm);
837 if (reg == AUX_RX_COMM_AUX_DEFER ||
838 reg == AUX_RX_COMM_I2C_DEFER) {
839 printf("DP Defer: %d\n\n", reg);
844 for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) {
845 reg = readl((unsigned int)&dp_regs->buf_data0
847 edid[i + cur_data_idx] = (unsigned char)reg;
854 void exynos_dp_reset_macro(void)
857 struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
859 reg = readl(&dp_regs->phy_test);
861 writel(reg, &dp_regs->phy_test);
863 /* 10 us is the minimum Macro reset time. */
867 writel(reg, &dp_regs->phy_test);
870 void exynos_dp_set_link_bandwidth(unsigned char bwtype)
873 struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
875 reg = (unsigned int)bwtype;
877 /* Set bandwidth to 2.7G or 1.62G */
878 if ((bwtype == DP_LANE_BW_1_62) || (bwtype == DP_LANE_BW_2_70))
879 writel(reg, &dp_regs->link_bw_set);
882 unsigned char exynos_dp_get_link_bandwidth(void)
886 struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
888 reg = readl(&dp_regs->link_bw_set);
889 ret = (unsigned char)reg;
894 void exynos_dp_set_lane_count(unsigned char count)
897 struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
899 reg = (unsigned int)count;
901 if ((count == DP_LANE_CNT_1) || (count == DP_LANE_CNT_2) ||
902 (count == DP_LANE_CNT_4))
903 writel(reg, &dp_regs->lane_count_set);
906 unsigned int exynos_dp_get_lane_count(void)
909 struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
911 reg = readl(&dp_regs->lane_count_set);
916 unsigned char exynos_dp_get_lanex_pre_emphasis(unsigned char lanecnt)
918 struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
919 unsigned int reg_list[DP_LANE_CNT_4] = {
920 (unsigned int)&dp_regs->ln0_link_training_ctl,
921 (unsigned int)&dp_regs->ln1_link_training_ctl,
922 (unsigned int)&dp_regs->ln2_link_training_ctl,
923 (unsigned int)&dp_regs->ln3_link_training_ctl,
926 return readl(reg_list[lanecnt]);
929 void exynos_dp_set_lanex_pre_emphasis(unsigned char request_val,
930 unsigned char lanecnt)
932 struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
933 unsigned int reg_list[DP_LANE_CNT_4] = {
934 (unsigned int)&dp_regs->ln0_link_training_ctl,
935 (unsigned int)&dp_regs->ln1_link_training_ctl,
936 (unsigned int)&dp_regs->ln2_link_training_ctl,
937 (unsigned int)&dp_regs->ln3_link_training_ctl,
940 writel(request_val, reg_list[lanecnt]);
943 void exynos_dp_set_lane_pre_emphasis(unsigned int level, unsigned char lanecnt)
947 struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
948 unsigned int reg_list[DP_LANE_CNT_4] = {
949 (unsigned int)&dp_regs->ln0_link_training_ctl,
950 (unsigned int)&dp_regs->ln1_link_training_ctl,
951 (unsigned int)&dp_regs->ln2_link_training_ctl,
952 (unsigned int)&dp_regs->ln3_link_training_ctl,
954 unsigned int reg_shift[DP_LANE_CNT_4] = {
955 PRE_EMPHASIS_SET_0_SHIFT,
956 PRE_EMPHASIS_SET_1_SHIFT,
957 PRE_EMPHASIS_SET_2_SHIFT,
958 PRE_EMPHASIS_SET_3_SHIFT
961 for (i = 0; i < lanecnt; i++) {
962 reg = level << reg_shift[i];
963 writel(reg, reg_list[i]);
967 void exynos_dp_set_training_pattern(unsigned int pattern)
969 unsigned int reg = 0;
970 struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
974 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7;
977 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2;
980 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1;
983 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2;
986 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_DISABLE |
987 SW_TRAINING_PATTERN_SET_NORMAL;
993 writel(reg, &dp_regs->training_ptn_set);
996 void exynos_dp_enable_enhanced_mode(unsigned char enable)
999 struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
1001 reg = readl(&dp_regs->sys_ctl4);
1007 writel(reg, &dp_regs->sys_ctl4);
1010 void exynos_dp_enable_scrambling(unsigned int enable)
1013 struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
1015 reg = readl(&dp_regs->training_ptn_set);
1016 reg &= ~(SCRAMBLING_DISABLE);
1019 reg |= SCRAMBLING_DISABLE;
1021 writel(reg, &dp_regs->training_ptn_set);
1024 int exynos_dp_init_video(void)
1027 struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
1029 /* Clear VID_CLK_CHG[1] and VID_FORMAT_CHG[3] and VSYNC_DET[7] */
1030 reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG;
1031 writel(reg, &dp_regs->common_int_sta1);
1033 /* I_STRM__CLK detect : DE_CTL : Auto detect */
1035 writel(reg, &dp_regs->sys_ctl1);
1040 void exynos_dp_config_video_slave_mode(struct edp_video_info *video_info)
1043 struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
1045 /* Video Slave mode setting */
1046 reg = readl(&dp_regs->func_en1);
1047 reg &= ~(MASTER_VID_FUNC_EN_N|SLAVE_VID_FUNC_EN_N);
1048 reg |= MASTER_VID_FUNC_EN_N;
1049 writel(reg, &dp_regs->func_en1);
1051 /* Configure Interlaced for slave mode video */
1052 reg = readl(&dp_regs->video_ctl10);
1053 reg &= ~INTERACE_SCAN_CFG;
1054 reg |= (video_info->interlaced << INTERACE_SCAN_CFG_SHIFT);
1055 writel(reg, &dp_regs->video_ctl10);
1057 /* Configure V sync polarity for slave mode video */
1058 reg = readl(&dp_regs->video_ctl10);
1059 reg &= ~VSYNC_POLARITY_CFG;
1060 reg |= (video_info->v_sync_polarity << V_S_POLARITY_CFG_SHIFT);
1061 writel(reg, &dp_regs->video_ctl10);
1063 /* Configure H sync polarity for slave mode video */
1064 reg = readl(&dp_regs->video_ctl10);
1065 reg &= ~HSYNC_POLARITY_CFG;
1066 reg |= (video_info->h_sync_polarity << H_S_POLARITY_CFG_SHIFT);
1067 writel(reg, &dp_regs->video_ctl10);
1069 /*Set video mode to slave mode */
1070 reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
1071 writel(reg, &dp_regs->soc_general_ctl);
1074 void exynos_dp_set_video_color_format(struct edp_video_info *video_info)
1077 struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
1079 /* Configure the input color depth, color space, dynamic range */
1080 reg = (video_info->dynamic_range << IN_D_RANGE_SHIFT) |
1081 (video_info->color_depth << IN_BPC_SHIFT) |
1082 (video_info->color_space << IN_COLOR_F_SHIFT);
1083 writel(reg, &dp_regs->video_ctl2);
1085 /* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
1086 reg = readl(&dp_regs->video_ctl3);
1087 reg &= ~IN_YC_COEFFI_MASK;
1088 if (video_info->ycbcr_coeff)
1089 reg |= IN_YC_COEFFI_ITU709;
1091 reg |= IN_YC_COEFFI_ITU601;
1092 writel(reg, &dp_regs->video_ctl3);
1095 int exynos_dp_config_video_bist(struct edp_device_info *edp_info)
1098 unsigned int bist_type = 0;
1099 struct edp_video_info video_info = edp_info->video_info;
1100 struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
1102 /* For master mode, you don't need to set the video format */
1103 if (video_info.master_mode == 0) {
1104 writel(TOTAL_LINE_CFG_L(edp_info->disp_info.v_total),
1105 &dp_regs->total_ln_cfg_l);
1106 writel(TOTAL_LINE_CFG_H(edp_info->disp_info.v_total),
1107 &dp_regs->total_ln_cfg_h);
1108 writel(ACTIVE_LINE_CFG_L(edp_info->disp_info.v_res),
1109 &dp_regs->active_ln_cfg_l);
1110 writel(ACTIVE_LINE_CFG_H(edp_info->disp_info.v_res),
1111 &dp_regs->active_ln_cfg_h);
1112 writel(edp_info->disp_info.v_sync_width,
1114 writel(edp_info->disp_info.v_back_porch,
1116 writel(edp_info->disp_info.v_front_porch,
1119 writel(TOTAL_PIXEL_CFG_L(edp_info->disp_info.h_total),
1120 &dp_regs->total_pix_cfg_l);
1121 writel(TOTAL_PIXEL_CFG_H(edp_info->disp_info.h_total),
1122 &dp_regs->total_pix_cfg_h);
1123 writel(ACTIVE_PIXEL_CFG_L(edp_info->disp_info.h_res),
1124 &dp_regs->active_pix_cfg_l);
1125 writel(ACTIVE_PIXEL_CFG_H(edp_info->disp_info.h_res),
1126 &dp_regs->active_pix_cfg_h);
1127 writel(H_F_PORCH_CFG_L(edp_info->disp_info.h_front_porch),
1128 &dp_regs->hfp_cfg_l);
1129 writel(H_F_PORCH_CFG_H(edp_info->disp_info.h_front_porch),
1130 &dp_regs->hfp_cfg_h);
1131 writel(H_SYNC_PORCH_CFG_L(edp_info->disp_info.h_sync_width),
1132 &dp_regs->hsw_cfg_l);
1133 writel(H_SYNC_PORCH_CFG_H(edp_info->disp_info.h_sync_width),
1134 &dp_regs->hsw_cfg_h);
1135 writel(H_B_PORCH_CFG_L(edp_info->disp_info.h_back_porch),
1136 &dp_regs->hbp_cfg_l);
1137 writel(H_B_PORCH_CFG_H(edp_info->disp_info.h_back_porch),
1138 &dp_regs->hbp_cfg_h);
1141 * Set SLAVE_I_SCAN_CFG[2], VSYNC_P_CFG[1],
1142 * HSYNC_P_CFG[0] properly
1144 reg = (video_info.interlaced << INTERACE_SCAN_CFG_SHIFT |
1145 video_info.v_sync_polarity << V_S_POLARITY_CFG_SHIFT |
1146 video_info.h_sync_polarity << H_S_POLARITY_CFG_SHIFT);
1147 writel(reg, &dp_regs->video_ctl10);
1150 /* BIST color bar width set--set to each bar is 32 pixel width */
1151 switch (video_info.bist_pattern) {
1153 bist_type = BIST_WIDTH_BAR_32_PIXEL |
1154 BIST_TYPE_COLOR_BAR;
1157 bist_type = BIST_WIDTH_BAR_64_PIXEL |
1158 BIST_TYPE_COLOR_BAR;
1160 case WHITE_GRAY_BALCKBAR_32:
1161 bist_type = BIST_WIDTH_BAR_32_PIXEL |
1162 BIST_TYPE_WHITE_GRAY_BLACK_BAR;
1164 case WHITE_GRAY_BALCKBAR_64:
1165 bist_type = BIST_WIDTH_BAR_64_PIXEL |
1166 BIST_TYPE_WHITE_GRAY_BLACK_BAR;
1168 case MOBILE_WHITEBAR_32:
1169 bist_type = BIST_WIDTH_BAR_32_PIXEL |
1170 BIST_TYPE_MOBILE_WHITE_BAR;
1172 case MOBILE_WHITEBAR_64:
1173 bist_type = BIST_WIDTH_BAR_64_PIXEL |
1174 BIST_TYPE_MOBILE_WHITE_BAR;
1181 writel(reg, &dp_regs->video_ctl4);
1186 unsigned int exynos_dp_is_slave_video_stream_clock_on(void)
1189 struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
1191 /* Update Video stream clk detect status */
1192 reg = readl(&dp_regs->sys_ctl1);
1193 writel(reg, &dp_regs->sys_ctl1);
1195 reg = readl(&dp_regs->sys_ctl1);
1197 if (!(reg & DET_STA)) {
1198 debug("DP Input stream clock not detected.\n");
1202 return EXYNOS_DP_SUCCESS;
1205 void exynos_dp_set_video_cr_mn(unsigned int type, unsigned int m_value,
1206 unsigned int n_value)
1209 struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
1211 if (type == REGISTER_M) {
1212 reg = readl(&dp_regs->sys_ctl4);
1214 writel(reg, &dp_regs->sys_ctl4);
1215 reg = M_VID0_CFG(m_value);
1216 writel(reg, &dp_regs->m_vid0);
1217 reg = M_VID1_CFG(m_value);
1218 writel(reg, &dp_regs->m_vid1);
1219 reg = M_VID2_CFG(m_value);
1220 writel(reg, &dp_regs->m_vid2);
1222 reg = N_VID0_CFG(n_value);
1223 writel(reg, &dp_regs->n_vid0);
1224 reg = N_VID1_CFG(n_value);
1225 writel(reg, &dp_regs->n_vid1);
1226 reg = N_VID2_CFG(n_value);
1227 writel(reg, &dp_regs->n_vid2);
1229 reg = readl(&dp_regs->sys_ctl4);
1231 writel(reg, &dp_regs->sys_ctl4);
1235 void exynos_dp_set_video_timing_mode(unsigned int type)
1238 struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
1240 reg = readl(&dp_regs->video_ctl10);
1243 if (type != VIDEO_TIMING_FROM_CAPTURE)
1246 writel(reg, &dp_regs->video_ctl10);
1249 void exynos_dp_enable_video_master(unsigned int enable)
1252 struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
1254 reg = readl(&dp_regs->soc_general_ctl);
1256 reg &= ~VIDEO_MODE_MASK;
1257 reg |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE;
1259 reg &= ~VIDEO_MODE_MASK;
1260 reg |= VIDEO_MODE_SLAVE_MODE;
1263 writel(reg, &dp_regs->soc_general_ctl);
1266 void exynos_dp_start_video(void)
1269 struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
1271 /* Enable Video input and disable Mute */
1272 reg = readl(&dp_regs->video_ctl1);
1274 writel(reg, &dp_regs->video_ctl1);
1277 unsigned int exynos_dp_is_video_stream_on(void)
1280 struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
1282 /* Update STRM_VALID */
1283 reg = readl(&dp_regs->sys_ctl3);
1284 writel(reg, &dp_regs->sys_ctl3);
1286 reg = readl(&dp_regs->sys_ctl3);
1287 if (!(reg & STRM_VALID))
1290 return EXYNOS_DP_SUCCESS;