2 * linux/drivers/video/amba-clcd.c
4 * Copyright (C) 2001 ARM Limited, by David A Rusling
5 * Updated to 2.5, Deep Blue Solutions Ltd.
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file COPYING in the main directory of this archive
11 * ARM PrimeCell PL110 Color LCD Controller
13 #include <linux/dma-mapping.h>
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/errno.h>
17 #include <linux/string.h>
18 #include <linux/slab.h>
19 #include <linux/delay.h>
22 #include <linux/init.h>
23 #include <linux/ioport.h>
24 #include <linux/list.h>
25 #include <linux/amba/bus.h>
26 #include <linux/amba/clcd.h>
27 #include <linux/bitops.h>
28 #include <linux/clk.h>
29 #include <linux/hardirq.h>
30 #include <linux/dma-mapping.h>
32 #include <linux/of_address.h>
33 #include <linux/of_graph.h>
34 #include <video/display_timing.h>
35 #include <video/of_display_timing.h>
36 #include <video/videomode.h>
38 #include <asm/sizes.h>
40 #define to_clcd(info) container_of(info, struct clcd_fb, fb)
42 /* This is limited to 16 characters when displayed by X startup */
43 static const char *clcd_name = "CLCD FB";
46 * Unfortunately, the enable/disable functions may be called either from
47 * process or IRQ context, and we _need_ to delay. This is _not_ good.
49 static inline void clcdfb_sleep(unsigned int ms)
58 static inline void clcdfb_set_start(struct clcd_fb *fb)
60 unsigned long ustart = fb->fb.fix.smem_start;
63 ustart += fb->fb.var.yoffset * fb->fb.fix.line_length;
64 lstart = ustart + fb->fb.var.yres * fb->fb.fix.line_length / 2;
66 writel(ustart, fb->regs + CLCD_UBAS);
67 writel(lstart, fb->regs + CLCD_LBAS);
70 static void clcdfb_disable(struct clcd_fb *fb)
74 if (fb->board->disable)
75 fb->board->disable(fb);
77 val = readl(fb->regs + fb->off_cntl);
78 if (val & CNTL_LCDPWR) {
80 writel(val, fb->regs + fb->off_cntl);
84 if (val & CNTL_LCDEN) {
86 writel(val, fb->regs + fb->off_cntl);
90 * Disable CLCD clock source.
92 if (fb->clk_enabled) {
93 fb->clk_enabled = false;
98 static void clcdfb_enable(struct clcd_fb *fb, u32 cntl)
101 * Enable the CLCD clock source.
103 if (!fb->clk_enabled) {
104 fb->clk_enabled = true;
109 * Bring up by first enabling..
112 writel(cntl, fb->regs + fb->off_cntl);
117 * and now apply power.
120 writel(cntl, fb->regs + fb->off_cntl);
123 * finally, enable the interface.
125 if (fb->board->enable)
126 fb->board->enable(fb);
130 clcdfb_set_bitfields(struct clcd_fb *fb, struct fb_var_screeninfo *var)
135 if (fb->panel->caps && fb->board->caps)
136 caps = fb->panel->caps & fb->board->caps;
138 /* Old way of specifying what can be used */
139 caps = fb->panel->cntl & CNTL_BGR ?
140 CLCD_CAP_BGR : CLCD_CAP_RGB;
141 /* But mask out 444 modes as they weren't supported */
142 caps &= ~CLCD_CAP_444;
145 /* Only TFT panels can do RGB888/BGR888 */
146 if (!(fb->panel->cntl & CNTL_LCDTFT))
147 caps &= ~CLCD_CAP_888;
149 memset(&var->transp, 0, sizeof(var->transp));
151 var->red.msb_right = 0;
152 var->green.msb_right = 0;
153 var->blue.msb_right = 0;
155 switch (var->bits_per_pixel) {
160 /* If we can't do 5551, reject */
161 caps &= CLCD_CAP_5551;
167 var->red.length = var->bits_per_pixel;
169 var->green.length = var->bits_per_pixel;
170 var->green.offset = 0;
171 var->blue.length = var->bits_per_pixel;
172 var->blue.offset = 0;
176 /* If we can't do 444, 5551 or 565, reject */
177 if (!(caps & (CLCD_CAP_444 | CLCD_CAP_5551 | CLCD_CAP_565))) {
183 * Green length can be 4, 5 or 6 depending whether
184 * we're operating in 444, 5551 or 565 mode.
186 if (var->green.length == 4 && caps & CLCD_CAP_444)
187 caps &= CLCD_CAP_444;
188 if (var->green.length == 5 && caps & CLCD_CAP_5551)
189 caps &= CLCD_CAP_5551;
190 else if (var->green.length == 6 && caps & CLCD_CAP_565)
191 caps &= CLCD_CAP_565;
194 * PL110 officially only supports RGB555,
195 * but may be wired up to allow RGB565.
197 if (caps & CLCD_CAP_565) {
198 var->green.length = 6;
199 caps &= CLCD_CAP_565;
200 } else if (caps & CLCD_CAP_5551) {
201 var->green.length = 5;
202 caps &= CLCD_CAP_5551;
204 var->green.length = 4;
205 caps &= CLCD_CAP_444;
209 if (var->green.length >= 5) {
211 var->blue.length = 5;
214 var->blue.length = 4;
218 /* If we can't do 888, reject */
219 caps &= CLCD_CAP_888;
226 var->green.length = 8;
227 var->blue.length = 8;
235 * >= 16bpp displays have separate colour component bitfields
236 * encoded in the pixel data. Calculate their position from
237 * the bitfield length defined above.
239 if (ret == 0 && var->bits_per_pixel >= 16) {
242 bgr = caps & CLCD_CAP_BGR && var->blue.offset == 0;
243 rgb = caps & CLCD_CAP_RGB && var->red.offset == 0;
247 * The requested format was not possible, try just
248 * our capabilities. One of BGR or RGB must be
251 bgr = caps & CLCD_CAP_BGR;
254 var->blue.offset = 0;
255 var->green.offset = var->blue.offset + var->blue.length;
256 var->red.offset = var->green.offset + var->green.length;
259 var->green.offset = var->red.offset + var->red.length;
260 var->blue.offset = var->green.offset + var->green.length;
267 static int clcdfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
269 struct clcd_fb *fb = to_clcd(info);
272 if (fb->board->check)
273 ret = fb->board->check(fb, var);
276 var->xres_virtual * var->bits_per_pixel / 8 *
277 var->yres_virtual > fb->fb.fix.smem_len)
281 ret = clcdfb_set_bitfields(fb, var);
286 static int clcdfb_set_par(struct fb_info *info)
288 struct clcd_fb *fb = to_clcd(info);
289 struct clcd_regs regs;
291 fb->fb.fix.line_length = fb->fb.var.xres_virtual *
292 fb->fb.var.bits_per_pixel / 8;
294 if (fb->fb.var.bits_per_pixel <= 8)
295 fb->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
297 fb->fb.fix.visual = FB_VISUAL_TRUECOLOR;
299 fb->board->decode(fb, ®s);
303 writel(regs.tim0, fb->regs + CLCD_TIM0);
304 writel(regs.tim1, fb->regs + CLCD_TIM1);
305 writel(regs.tim2, fb->regs + CLCD_TIM2);
306 writel(regs.tim3, fb->regs + CLCD_TIM3);
308 clcdfb_set_start(fb);
310 clk_set_rate(fb->clk, (1000000000 / regs.pixclock) * 1000);
312 fb->clcd_cntl = regs.cntl;
314 clcdfb_enable(fb, regs.cntl);
318 "CLCD: Registers set to\n"
319 " %08x %08x %08x %08x\n"
320 " %08x %08x %08x %08x\n",
321 readl(fb->regs + CLCD_TIM0), readl(fb->regs + CLCD_TIM1),
322 readl(fb->regs + CLCD_TIM2), readl(fb->regs + CLCD_TIM3),
323 readl(fb->regs + CLCD_UBAS), readl(fb->regs + CLCD_LBAS),
324 readl(fb->regs + fb->off_ienb), readl(fb->regs + fb->off_cntl));
330 static inline u32 convert_bitfield(int val, struct fb_bitfield *bf)
332 unsigned int mask = (1 << bf->length) - 1;
334 return (val >> (16 - bf->length) & mask) << bf->offset;
338 * Set a single color register. The values supplied have a 16 bit
339 * magnitude. Return != 0 for invalid regno.
342 clcdfb_setcolreg(unsigned int regno, unsigned int red, unsigned int green,
343 unsigned int blue, unsigned int transp, struct fb_info *info)
345 struct clcd_fb *fb = to_clcd(info);
348 fb->cmap[regno] = convert_bitfield(transp, &fb->fb.var.transp) |
349 convert_bitfield(blue, &fb->fb.var.blue) |
350 convert_bitfield(green, &fb->fb.var.green) |
351 convert_bitfield(red, &fb->fb.var.red);
353 if (fb->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR && regno < 256) {
354 int hw_reg = CLCD_PALETTE + ((regno * 2) & ~3);
355 u32 val, mask, newval;
357 newval = (red >> 11) & 0x001f;
358 newval |= (green >> 6) & 0x03e0;
359 newval |= (blue >> 1) & 0x7c00;
362 * 3.2.11: if we're configured for big endian
363 * byte order, the palette entries are swapped.
365 if (fb->clcd_cntl & CNTL_BEBO)
375 val = readl(fb->regs + hw_reg) & mask;
376 writel(val | newval, fb->regs + hw_reg);
383 * Blank the screen if blank_mode != 0, else unblank. If blank == NULL
384 * then the caller blanks by setting the CLUT (Color Look Up Table) to all
385 * black. Return 0 if blanking succeeded, != 0 if un-/blanking failed due
386 * to e.g. a video mode which doesn't support it. Implements VESA suspend
387 * and powerdown modes on hardware that supports disabling hsync/vsync:
388 * blank_mode == 2: suspend vsync
389 * blank_mode == 3: suspend hsync
390 * blank_mode == 4: powerdown
392 static int clcdfb_blank(int blank_mode, struct fb_info *info)
394 struct clcd_fb *fb = to_clcd(info);
396 if (blank_mode != 0) {
399 clcdfb_enable(fb, fb->clcd_cntl);
404 static int clcdfb_mmap(struct fb_info *info,
405 struct vm_area_struct *vma)
407 struct clcd_fb *fb = to_clcd(info);
408 unsigned long len, off = vma->vm_pgoff << PAGE_SHIFT;
411 len = info->fix.smem_len;
413 if (off <= len && vma->vm_end - vma->vm_start <= len - off &&
415 ret = fb->board->mmap(fb, vma);
420 static struct fb_ops clcdfb_ops = {
421 .owner = THIS_MODULE,
422 .fb_check_var = clcdfb_check_var,
423 .fb_set_par = clcdfb_set_par,
424 .fb_setcolreg = clcdfb_setcolreg,
425 .fb_blank = clcdfb_blank,
426 .fb_fillrect = cfb_fillrect,
427 .fb_copyarea = cfb_copyarea,
428 .fb_imageblit = cfb_imageblit,
429 .fb_mmap = clcdfb_mmap,
432 static int clcdfb_register(struct clcd_fb *fb)
437 * ARM PL111 always has IENB at 0x1c; it's only PL110
438 * which is reversed on some platforms.
440 if (amba_manf(fb->dev) == 0x41 && amba_part(fb->dev) == 0x111) {
441 fb->off_ienb = CLCD_PL111_IENB;
442 fb->off_cntl = CLCD_PL111_CNTL;
444 #ifdef CONFIG_ARCH_VERSATILE
445 fb->off_ienb = CLCD_PL111_IENB;
446 fb->off_cntl = CLCD_PL111_CNTL;
448 fb->off_ienb = CLCD_PL110_IENB;
449 fb->off_cntl = CLCD_PL110_CNTL;
453 fb->clk = clk_get(&fb->dev->dev, NULL);
454 if (IS_ERR(fb->clk)) {
455 ret = PTR_ERR(fb->clk);
459 ret = clk_prepare(fb->clk);
463 fb->fb.device = &fb->dev->dev;
465 fb->fb.fix.mmio_start = fb->dev->res.start;
466 fb->fb.fix.mmio_len = resource_size(&fb->dev->res);
468 fb->regs = ioremap(fb->fb.fix.mmio_start, fb->fb.fix.mmio_len);
470 printk(KERN_ERR "CLCD: unable to remap registers\n");
475 fb->fb.fbops = &clcdfb_ops;
476 fb->fb.flags = FBINFO_FLAG_DEFAULT;
477 fb->fb.pseudo_palette = fb->cmap;
479 strncpy(fb->fb.fix.id, clcd_name, sizeof(fb->fb.fix.id));
480 fb->fb.fix.type = FB_TYPE_PACKED_PIXELS;
481 fb->fb.fix.type_aux = 0;
482 fb->fb.fix.xpanstep = 0;
483 fb->fb.fix.ypanstep = 0;
484 fb->fb.fix.ywrapstep = 0;
485 fb->fb.fix.accel = FB_ACCEL_NONE;
487 fb->fb.var.xres = fb->panel->mode.xres;
488 fb->fb.var.yres = fb->panel->mode.yres;
489 fb->fb.var.xres_virtual = fb->panel->mode.xres;
490 fb->fb.var.yres_virtual = fb->panel->mode.yres;
491 fb->fb.var.bits_per_pixel = fb->panel->bpp;
492 fb->fb.var.grayscale = fb->panel->grayscale;
493 fb->fb.var.pixclock = fb->panel->mode.pixclock;
494 fb->fb.var.left_margin = fb->panel->mode.left_margin;
495 fb->fb.var.right_margin = fb->panel->mode.right_margin;
496 fb->fb.var.upper_margin = fb->panel->mode.upper_margin;
497 fb->fb.var.lower_margin = fb->panel->mode.lower_margin;
498 fb->fb.var.hsync_len = fb->panel->mode.hsync_len;
499 fb->fb.var.vsync_len = fb->panel->mode.vsync_len;
500 fb->fb.var.sync = fb->panel->mode.sync;
501 fb->fb.var.vmode = fb->panel->mode.vmode;
502 fb->fb.var.activate = FB_ACTIVATE_NOW;
503 fb->fb.var.nonstd = 0;
504 fb->fb.var.height = fb->panel->height;
505 fb->fb.var.width = fb->panel->width;
506 fb->fb.var.accel_flags = 0;
508 fb->fb.monspecs.hfmin = 0;
509 fb->fb.monspecs.hfmax = 100000;
510 fb->fb.monspecs.vfmin = 0;
511 fb->fb.monspecs.vfmax = 400;
512 fb->fb.monspecs.dclkmin = 1000000;
513 fb->fb.monspecs.dclkmax = 100000000;
516 * Make sure that the bitfields are set appropriately.
518 clcdfb_set_bitfields(fb, &fb->fb.var);
521 * Allocate colourmap.
523 ret = fb_alloc_cmap(&fb->fb.cmap, 256, 0);
528 * Ensure interrupts are disabled.
530 writel(0, fb->regs + fb->off_ienb);
532 fb_set_var(&fb->fb, &fb->fb.var);
534 dev_info(&fb->dev->dev, "%s hardware, %s display\n",
535 fb->board->name, fb->panel->mode.name);
537 ret = register_framebuffer(&fb->fb);
541 printk(KERN_ERR "CLCD: cannot register framebuffer (%d)\n", ret);
543 fb_dealloc_cmap(&fb->fb.cmap);
547 clk_unprepare(fb->clk);
555 static int clcdfb_of_get_dpi_panel_mode(struct device_node *node,
556 struct fb_videomode *mode)
559 struct display_timing timing;
560 struct videomode video;
562 err = of_get_display_timing(node, "panel-timing", &timing);
566 videomode_from_timing(&timing, &video);
568 err = fb_videomode_from_videomode(&video, mode);
575 static int clcdfb_snprintf_mode(char *buf, int size, struct fb_videomode *mode)
577 return snprintf(buf, size, "%ux%u@%u", mode->xres, mode->yres,
581 static int clcdfb_of_get_mode(struct device *dev, struct device_node *endpoint,
582 struct fb_videomode *mode)
585 struct device_node *panel;
589 panel = of_graph_get_remote_port_parent(endpoint);
593 /* Only directly connected DPI panels supported for now */
594 if (of_device_is_compatible(panel, "panel-dpi"))
595 err = clcdfb_of_get_dpi_panel_mode(panel, mode);
601 len = clcdfb_snprintf_mode(NULL, 0, mode);
602 name = devm_kzalloc(dev, len + 1, GFP_KERNEL);
603 clcdfb_snprintf_mode(name, len + 1, mode);
609 static int clcdfb_of_init_tft_panel(struct clcd_fb *fb, u32 r0, u32 g0, u32 b0)
616 { 0x110, 1, 7, 13, CLCD_CAP_5551 },
617 { 0x110, 0, 8, 16, CLCD_CAP_888 },
618 { 0x111, 4, 14, 20, CLCD_CAP_444 },
619 { 0x111, 3, 11, 19, CLCD_CAP_444 | CLCD_CAP_5551 },
620 { 0x111, 3, 10, 19, CLCD_CAP_444 | CLCD_CAP_5551 |
622 { 0x111, 0, 8, 16, CLCD_CAP_444 | CLCD_CAP_5551 |
623 CLCD_CAP_565 | CLCD_CAP_888 },
627 /* Bypass pixel clock divider, data output on the falling edge */
628 fb->panel->tim2 = TIM2_BCD | TIM2_IPC;
630 /* TFT display, vert. comp. interrupt at the start of the back porch */
631 fb->panel->cntl |= CNTL_LCDTFT | CNTL_LCDVCOMP(1);
635 /* Match the setup with known variants */
636 for (i = 0; i < ARRAY_SIZE(panels) && !fb->panel->caps; i++) {
637 if (amba_part(fb->dev) != panels[i].part)
639 if (g0 != panels[i].g0)
641 if (r0 == panels[i].r0 && b0 == panels[i].b0)
642 fb->panel->caps = panels[i].caps & CLCD_CAP_RGB;
643 if (r0 == panels[i].b0 && b0 == panels[i].r0)
644 fb->panel->caps = panels[i].caps & CLCD_CAP_BGR;
647 return fb->panel->caps ? 0 : -EINVAL;
650 static int clcdfb_of_init_display(struct clcd_fb *fb)
652 struct device_node *endpoint;
658 fb->panel = devm_kzalloc(&fb->dev->dev, sizeof(*fb->panel), GFP_KERNEL);
662 endpoint = of_graph_get_next_endpoint(fb->dev->dev.of_node, NULL);
666 err = clcdfb_of_get_mode(&fb->dev->dev, endpoint, &fb->panel->mode);
670 err = of_property_read_u32(fb->dev->dev.of_node, "max-memory-bandwidth",
674 * max_bandwidth is in bytes per second and pixclock in
675 * pico-seconds, so the maximum allowed bits per pixel is
676 * 8 * max_bandwidth / (PICOS2KHZ(pixclock) * 1000)
677 * Rearrange this calculation to avoid overflow and then ensure
678 * result is a valid format.
680 bpp = max_bandwidth / (1000 / 8)
681 / PICOS2KHZ(fb->panel->mode.pixclock);
682 bpp = rounddown_pow_of_two(bpp);
687 fb->panel->bpp = bpp;
689 #ifdef CONFIG_CPU_BIG_ENDIAN
690 fb->panel->cntl |= CNTL_BEBO;
692 fb->panel->width = -1;
693 fb->panel->height = -1;
695 if (of_property_read_u32_array(endpoint,
696 "arm,pl11x,tft-r0g0b0-pads",
697 tft_r0b0g0, ARRAY_SIZE(tft_r0b0g0)) == 0)
698 return clcdfb_of_init_tft_panel(fb, tft_r0b0g0[0],
699 tft_r0b0g0[1], tft_r0b0g0[2]);
704 static int clcdfb_of_vram_setup(struct clcd_fb *fb)
707 struct device_node *memory;
710 err = clcdfb_of_init_display(fb);
714 memory = of_parse_phandle(fb->dev->dev.of_node, "memory-region", 0);
718 fb->fb.screen_base = of_iomap(memory, 0);
719 if (!fb->fb.screen_base)
722 fb->fb.fix.smem_start = of_translate_address(memory,
723 of_get_address(memory, 0, &size, NULL));
724 fb->fb.fix.smem_len = size;
729 static int clcdfb_of_vram_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
731 unsigned long off, user_size, kernel_size;
734 off = vma->vm_pgoff << PAGE_SHIFT;
735 user_size = vma->vm_end - vma->vm_start;
736 kernel_size = fb->fb.fix.smem_len;
738 if (off >= kernel_size || user_size > (kernel_size - off))
741 return remap_pfn_range(vma, vma->vm_start,
742 __phys_to_pfn(fb->fb.fix.smem_start) + vma->vm_pgoff,
744 pgprot_writecombine(vma->vm_page_prot));
747 static void clcdfb_of_vram_remove(struct clcd_fb *fb)
749 iounmap(fb->fb.screen_base);
752 static int clcdfb_of_dma_setup(struct clcd_fb *fb)
754 unsigned long framesize;
758 err = clcdfb_of_init_display(fb);
762 framesize = fb->panel->mode.xres * fb->panel->mode.yres *
764 fb->fb.screen_base = dma_alloc_coherent(&fb->dev->dev, framesize,
766 if (!fb->fb.screen_base)
769 fb->fb.fix.smem_start = dma;
770 fb->fb.fix.smem_len = framesize;
775 static int clcdfb_of_dma_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
777 return dma_mmap_writecombine(&fb->dev->dev, vma, fb->fb.screen_base,
778 fb->fb.fix.smem_start, fb->fb.fix.smem_len);
781 static void clcdfb_of_dma_remove(struct clcd_fb *fb)
783 dma_free_coherent(&fb->dev->dev, fb->fb.fix.smem_len,
784 fb->fb.screen_base, fb->fb.fix.smem_start);
787 static struct clcd_board *clcdfb_of_get_board(struct amba_device *dev)
789 struct clcd_board *board = devm_kzalloc(&dev->dev, sizeof(*board),
791 struct device_node *node = dev->dev.of_node;
796 board->name = of_node_full_name(node);
797 board->caps = CLCD_CAP_ALL;
798 board->check = clcdfb_check;
799 board->decode = clcdfb_decode;
800 if (of_find_property(node, "memory-region", NULL)) {
801 board->setup = clcdfb_of_vram_setup;
802 board->mmap = clcdfb_of_vram_mmap;
803 board->remove = clcdfb_of_vram_remove;
805 board->setup = clcdfb_of_dma_setup;
806 board->mmap = clcdfb_of_dma_mmap;
807 board->remove = clcdfb_of_dma_remove;
813 static struct clcd_board *clcdfb_of_get_board(struct amba_device *dev)
819 static int clcdfb_probe(struct amba_device *dev, const struct amba_id *id)
821 struct clcd_board *board = dev_get_platdata(&dev->dev);
826 board = clcdfb_of_get_board(dev);
831 ret = dma_set_mask_and_coherent(&dev->dev, DMA_BIT_MASK(32));
835 ret = amba_request_regions(dev, NULL);
837 printk(KERN_ERR "CLCD: unable to reserve regs region\n");
841 fb = kzalloc(sizeof(struct clcd_fb), GFP_KERNEL);
843 printk(KERN_INFO "CLCD: could not allocate new clcd_fb struct\n");
851 dev_info(&fb->dev->dev, "PL%03x rev%u at 0x%08llx\n",
852 amba_part(dev), amba_rev(dev),
853 (unsigned long long)dev->res.start);
855 ret = fb->board->setup(fb);
859 ret = clcdfb_register(fb);
861 amba_set_drvdata(dev, fb);
865 fb->board->remove(fb);
869 amba_release_regions(dev);
874 static int clcdfb_remove(struct amba_device *dev)
876 struct clcd_fb *fb = amba_get_drvdata(dev);
879 unregister_framebuffer(&fb->fb);
881 fb_dealloc_cmap(&fb->fb.cmap);
883 clk_unprepare(fb->clk);
886 fb->board->remove(fb);
890 amba_release_regions(dev);
895 static struct amba_id clcdfb_id_table[] = {
903 MODULE_DEVICE_TABLE(amba, clcdfb_id_table);
905 static struct amba_driver clcd_driver = {
907 .name = "clcd-pl11x",
909 .probe = clcdfb_probe,
910 .remove = clcdfb_remove,
911 .id_table = clcdfb_id_table,
914 static int __init amba_clcdfb_init(void)
916 if (fb_get_options("ambafb", NULL))
919 return amba_driver_register(&clcd_driver);
922 module_init(amba_clcdfb_init);
924 static void __exit amba_clcdfb_exit(void)
926 amba_driver_unregister(&clcd_driver);
929 module_exit(amba_clcdfb_exit);
931 MODULE_DESCRIPTION("ARM PrimeCell PL110 CLCD core driver");
932 MODULE_LICENSE("GPL");