drivers/video/fbdev/omap2/dss/hdmi.h

   1 /*
   2  * HDMI driver definition for TI OMAP4 Processor.
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published by
   8  * the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #ifndef _HDMI_H
  20 #define _HDMI_H
  21
  22 #include <linux/delay.h>
  23 #include <linux/io.h>
  24 #include <linux/platform_device.h>
  25 #include <video/omapdss.h>
  26
  27 #include "dss.h"
  28
  29 /* HDMI Wrapper */
  30
  31 #define HDMI_WP_REVISION                        0x0
  32 #define HDMI_WP_SYSCONFIG                       0x10
  33 #define HDMI_WP_IRQSTATUS_RAW                   0x24
  34 #define HDMI_WP_IRQSTATUS                       0x28
  35 #define HDMI_WP_IRQENABLE_SET                   0x2C
  36 #define HDMI_WP_IRQENABLE_CLR                   0x30
  37 #define HDMI_WP_IRQWAKEEN                       0x34
  38 #define HDMI_WP_PWR_CTRL                        0x40
  39 #define HDMI_WP_DEBOUNCE                        0x44
  40 #define HDMI_WP_VIDEO_CFG                       0x50
  41 #define HDMI_WP_VIDEO_SIZE                      0x60
  42 #define HDMI_WP_VIDEO_TIMING_H                  0x68
  43 #define HDMI_WP_VIDEO_TIMING_V                  0x6C
  44 #define HDMI_WP_CLK                             0x70
  45 #define HDMI_WP_AUDIO_CFG                       0x80
  46 #define HDMI_WP_AUDIO_CFG2                      0x84
  47 #define HDMI_WP_AUDIO_CTRL                      0x88
  48 #define HDMI_WP_AUDIO_DATA                      0x8C
  49
  50 /* HDMI WP IRQ flags */
  51 #define HDMI_IRQ_CORE                           (1 << 0)
  52 #define HDMI_IRQ_OCP_TIMEOUT                    (1 << 4)
  53 #define HDMI_IRQ_AUDIO_FIFO_UNDERFLOW           (1 << 8)
  54 #define HDMI_IRQ_AUDIO_FIFO_OVERFLOW            (1 << 9)
  55 #define HDMI_IRQ_AUDIO_FIFO_SAMPLE_REQ          (1 << 10)
  56 #define HDMI_IRQ_VIDEO_VSYNC                    (1 << 16)
  57 #define HDMI_IRQ_VIDEO_FRAME_DONE               (1 << 17)
  58 #define HDMI_IRQ_PHY_LINE5V_ASSERT              (1 << 24)
  59 #define HDMI_IRQ_LINK_CONNECT                   (1 << 25)
  60 #define HDMI_IRQ_LINK_DISCONNECT                (1 << 26)
  61 #define HDMI_IRQ_PLL_LOCK                       (1 << 29)
  62 #define HDMI_IRQ_PLL_UNLOCK                     (1 << 30)
  63 #define HDMI_IRQ_PLL_RECAL                      (1 << 31)
  64
  65 /* HDMI PLL */
  66
  67 #define PLLCTRL_PLL_CONTROL                     0x0
  68 #define PLLCTRL_PLL_STATUS                      0x4
  69 #define PLLCTRL_PLL_GO                          0x8
  70 #define PLLCTRL_CFG1                            0xC
  71 #define PLLCTRL_CFG2                            0x10
  72 #define PLLCTRL_CFG3                            0x14
  73 #define PLLCTRL_SSC_CFG1                        0x18
  74 #define PLLCTRL_SSC_CFG2                        0x1C
  75 #define PLLCTRL_CFG4                            0x20
  76
  77 /* HDMI PHY */
  78
  79 #define HDMI_TXPHY_TX_CTRL                      0x0
  80 #define HDMI_TXPHY_DIGITAL_CTRL                 0x4
  81 #define HDMI_TXPHY_POWER_CTRL                   0x8
  82 #define HDMI_TXPHY_PAD_CFG_CTRL                 0xC
  83 #define HDMI_TXPHY_BIST_CONTROL                 0x1C
  84
  85 enum hdmi_pll_pwr {
  86         HDMI_PLLPWRCMD_ALLOFF = 0,
  87         HDMI_PLLPWRCMD_PLLONLY = 1,
  88         HDMI_PLLPWRCMD_BOTHON_ALLCLKS = 2,
  89         HDMI_PLLPWRCMD_BOTHON_NOPHYCLK = 3
  90 };
  91
  92 enum hdmi_phy_pwr {
  93         HDMI_PHYPWRCMD_OFF = 0,
  94         HDMI_PHYPWRCMD_LDOON = 1,
  95         HDMI_PHYPWRCMD_TXON = 2
  96 };
  97
  98 enum hdmi_core_hdmi_dvi {
  99         HDMI_DVI = 0,
 100         HDMI_HDMI = 1
 101 };
 102
 103 enum hdmi_clk_refsel {
 104         HDMI_REFSEL_PCLK = 0,
 105         HDMI_REFSEL_REF1 = 1,
 106         HDMI_REFSEL_REF2 = 2,
 107         HDMI_REFSEL_SYSCLK = 3
 108 };
 109
 110 enum hdmi_packing_mode {
 111         HDMI_PACK_10b_RGB_YUV444 = 0,
 112         HDMI_PACK_24b_RGB_YUV444_YUV422 = 1,
 113         HDMI_PACK_20b_YUV422 = 2,
 114         HDMI_PACK_ALREADYPACKED = 7
 115 };
 116
 117 enum hdmi_stereo_channels {
 118         HDMI_AUDIO_STEREO_NOCHANNELS = 0,
 119         HDMI_AUDIO_STEREO_ONECHANNEL = 1,
 120         HDMI_AUDIO_STEREO_TWOCHANNELS = 2,
 121         HDMI_AUDIO_STEREO_THREECHANNELS = 3,
 122         HDMI_AUDIO_STEREO_FOURCHANNELS = 4
 123 };
 124
 125 enum hdmi_audio_type {
 126         HDMI_AUDIO_TYPE_LPCM = 0,
 127         HDMI_AUDIO_TYPE_IEC = 1
 128 };
 129
 130 enum hdmi_audio_justify {
 131         HDMI_AUDIO_JUSTIFY_LEFT = 0,
 132         HDMI_AUDIO_JUSTIFY_RIGHT = 1
 133 };
 134
 135 enum hdmi_audio_sample_order {
 136         HDMI_AUDIO_SAMPLE_RIGHT_FIRST = 0,
 137         HDMI_AUDIO_SAMPLE_LEFT_FIRST = 1
 138 };
 139
 140 enum hdmi_audio_samples_perword {
 141         HDMI_AUDIO_ONEWORD_ONESAMPLE = 0,
 142         HDMI_AUDIO_ONEWORD_TWOSAMPLES = 1
 143 };
 144
 145 enum hdmi_audio_sample_size {
 146         HDMI_AUDIO_SAMPLE_16BITS = 0,
 147         HDMI_AUDIO_SAMPLE_24BITS = 1
 148 };
 149
 150 enum hdmi_audio_transf_mode {
 151         HDMI_AUDIO_TRANSF_DMA = 0,
 152         HDMI_AUDIO_TRANSF_IRQ = 1
 153 };
 154
 155 enum hdmi_audio_blk_strt_end_sig {
 156         HDMI_AUDIO_BLOCK_SIG_STARTEND_ON = 0,
 157         HDMI_AUDIO_BLOCK_SIG_STARTEND_OFF = 1
 158 };
 159
 160 enum hdmi_core_audio_layout {
 161         HDMI_AUDIO_LAYOUT_2CH = 0,
 162         HDMI_AUDIO_LAYOUT_8CH = 1
 163 };
 164
 165 enum hdmi_core_cts_mode {
 166         HDMI_AUDIO_CTS_MODE_HW = 0,
 167         HDMI_AUDIO_CTS_MODE_SW = 1
 168 };
 169
 170 enum hdmi_audio_mclk_mode {
 171         HDMI_AUDIO_MCLK_128FS = 0,
 172         HDMI_AUDIO_MCLK_256FS = 1,
 173         HDMI_AUDIO_MCLK_384FS = 2,
 174         HDMI_AUDIO_MCLK_512FS = 3,
 175         HDMI_AUDIO_MCLK_768FS = 4,
 176         HDMI_AUDIO_MCLK_1024FS = 5,
 177         HDMI_AUDIO_MCLK_1152FS = 6,
 178         HDMI_AUDIO_MCLK_192FS = 7
 179 };
 180
 181 /* INFOFRAME_AVI_ and INFOFRAME_AUDIO_ definitions */
 182 enum hdmi_core_infoframe {
 183         HDMI_INFOFRAME_AVI_DB1Y_RGB = 0,
 184         HDMI_INFOFRAME_AVI_DB1Y_YUV422 = 1,
 185         HDMI_INFOFRAME_AVI_DB1Y_YUV444 = 2,
 186         HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_OFF = 0,
 187         HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_ON =  1,
 188         HDMI_INFOFRAME_AVI_DB1B_NO = 0,
 189         HDMI_INFOFRAME_AVI_DB1B_VERT = 1,
 190         HDMI_INFOFRAME_AVI_DB1B_HORI = 2,
 191         HDMI_INFOFRAME_AVI_DB1B_VERTHORI = 3,
 192         HDMI_INFOFRAME_AVI_DB1S_0 = 0,
 193         HDMI_INFOFRAME_AVI_DB1S_1 = 1,
 194         HDMI_INFOFRAME_AVI_DB1S_2 = 2,
 195         HDMI_INFOFRAME_AVI_DB2C_NO = 0,
 196         HDMI_INFOFRAME_AVI_DB2C_ITU601 = 1,
 197         HDMI_INFOFRAME_AVI_DB2C_ITU709 = 2,
 198         HDMI_INFOFRAME_AVI_DB2C_EC_EXTENDED = 3,
 199         HDMI_INFOFRAME_AVI_DB2M_NO = 0,
 200         HDMI_INFOFRAME_AVI_DB2M_43 = 1,
 201         HDMI_INFOFRAME_AVI_DB2M_169 = 2,
 202         HDMI_INFOFRAME_AVI_DB2R_SAME = 8,
 203         HDMI_INFOFRAME_AVI_DB2R_43 = 9,
 204         HDMI_INFOFRAME_AVI_DB2R_169 = 10,
 205         HDMI_INFOFRAME_AVI_DB2R_149 = 11,
 206         HDMI_INFOFRAME_AVI_DB3ITC_NO = 0,
 207         HDMI_INFOFRAME_AVI_DB3ITC_YES = 1,
 208         HDMI_INFOFRAME_AVI_DB3EC_XVYUV601 = 0,
 209         HDMI_INFOFRAME_AVI_DB3EC_XVYUV709 = 1,
 210         HDMI_INFOFRAME_AVI_DB3Q_DEFAULT = 0,
 211         HDMI_INFOFRAME_AVI_DB3Q_LR = 1,
 212         HDMI_INFOFRAME_AVI_DB3Q_FR = 2,
 213         HDMI_INFOFRAME_AVI_DB3SC_NO = 0,
 214         HDMI_INFOFRAME_AVI_DB3SC_HORI = 1,
 215         HDMI_INFOFRAME_AVI_DB3SC_VERT = 2,
 216         HDMI_INFOFRAME_AVI_DB3SC_HORIVERT = 3,
 217         HDMI_INFOFRAME_AVI_DB5PR_NO = 0,
 218         HDMI_INFOFRAME_AVI_DB5PR_2 = 1,
 219         HDMI_INFOFRAME_AVI_DB5PR_3 = 2,
 220         HDMI_INFOFRAME_AVI_DB5PR_4 = 3,
 221         HDMI_INFOFRAME_AVI_DB5PR_5 = 4,
 222         HDMI_INFOFRAME_AVI_DB5PR_6 = 5,
 223         HDMI_INFOFRAME_AVI_DB5PR_7 = 6,
 224         HDMI_INFOFRAME_AVI_DB5PR_8 = 7,
 225         HDMI_INFOFRAME_AVI_DB5PR_9 = 8,
 226         HDMI_INFOFRAME_AVI_DB5PR_10 = 9,
 227 };
 228
 229 struct hdmi_cm {
 230         int     code;
 231         int     mode;
 232 };
 233
 234 struct hdmi_video_format {
 235         enum hdmi_packing_mode  packing_mode;
 236         u32                     y_res;  /* Line per panel */
 237         u32                     x_res;  /* pixel per line */
 238 };
 239
 240 struct hdmi_config {
 241         struct omap_video_timings timings;
 242         struct hdmi_cm cm;
 243 };
 244
 245 /* HDMI PLL structure */
 246 struct hdmi_pll_info {
 247         u16 regn;
 248         u16 regm;
 249         u32 regmf;
 250         u16 regm2;
 251         u16 regsd;
 252         u16 dcofreq;
 253         enum hdmi_clk_refsel refsel;
 254 };
 255
 256 struct hdmi_audio_format {
 257         enum hdmi_stereo_channels               stereo_channels;
 258         u8                                      active_chnnls_msk;
 259         enum hdmi_audio_type                    type;
 260         enum hdmi_audio_justify                 justification;
 261         enum hdmi_audio_sample_order            sample_order;
 262         enum hdmi_audio_samples_perword         samples_per_word;
 263         enum hdmi_audio_sample_size             sample_size;
 264         enum hdmi_audio_blk_strt_end_sig        en_sig_blk_strt_end;
 265 };
 266
 267 struct hdmi_audio_dma {
 268         u8                              transfer_size;
 269         u8                              block_size;
 270         enum hdmi_audio_transf_mode     mode;
 271         u16                             fifo_threshold;
 272 };
 273
 274 struct hdmi_core_audio_i2s_config {
 275         u8 in_length_bits;
 276         u8 justification;
 277         u8 sck_edge_mode;
 278         u8 vbit;
 279         u8 direction;
 280         u8 shift;
 281         u8 active_sds;
 282 };
 283
 284 struct hdmi_core_audio_config {
 285         struct hdmi_core_audio_i2s_config       i2s_cfg;
 286         struct snd_aes_iec958                   *iec60958_cfg;
 287         bool                                    fs_override;
 288         u32                                     n;
 289         u32                                     cts;
 290         u32                                     aud_par_busclk;
 291         enum hdmi_core_audio_layout             layout;
 292         enum hdmi_core_cts_mode                 cts_mode;
 293         bool                                    use_mclk;
 294         enum hdmi_audio_mclk_mode               mclk_mode;
 295         bool                                    en_acr_pkt;
 296         bool                                    en_dsd_audio;
 297         bool                                    en_parallel_aud_input;
 298         bool                                    en_spdif;
 299 };
 300
 301 /*
 302  * Refer to section 8.2 in HDMI 1.3 specification for
 303  * details about infoframe databytes
 304  */
 305 struct hdmi_core_infoframe_avi {
 306         /* Y0, Y1 rgb,yCbCr */
 307         u8      db1_format;
 308         /* A0  Active information Present */
 309         u8      db1_active_info;
 310         /* B0, B1 Bar info data valid */
 311         u8      db1_bar_info_dv;
 312         /* S0, S1 scan information */
 313         u8      db1_scan_info;
 314         /* C0, C1 colorimetry */
 315         u8      db2_colorimetry;
 316         /* M0, M1 Aspect ratio (4:3, 16:9) */
 317         u8      db2_aspect_ratio;
 318         /* R0...R3 Active format aspect ratio */
 319         u8      db2_active_fmt_ar;
 320         /* ITC IT content. */
 321         u8      db3_itc;
 322         /* EC0, EC1, EC2 Extended colorimetry */
 323         u8      db3_ec;
 324         /* Q1, Q0 Quantization range */
 325         u8      db3_q_range;
 326         /* SC1, SC0 Non-uniform picture scaling */
 327         u8      db3_nup_scaling;
 328         /* VIC0..6 Video format identification */
 329         u8      db4_videocode;
 330         /* PR0..PR3 Pixel repetition factor */
 331         u8      db5_pixel_repeat;
 332         /* Line number end of top bar */
 333         u16     db6_7_line_eoftop;
 334         /* Line number start of bottom bar */
 335         u16     db8_9_line_sofbottom;
 336         /* Pixel number end of left bar */
 337         u16     db10_11_pixel_eofleft;
 338         /* Pixel number start of right bar */
 339         u16     db12_13_pixel_sofright;
 340 };
 341
 342 struct hdmi_wp_data {
 343         void __iomem *base;
 344 };
 345
 346 struct hdmi_pll_data {
 347         void __iomem *base;
 348
 349         struct hdmi_pll_info info;
 350 };
 351
 352 struct hdmi_phy_data {
 353         void __iomem *base;
 354
 355         u8 lane_function[4];
 356         u8 lane_polarity[4];
 357 };
 358
 359 struct hdmi_core_data {
 360         void __iomem *base;
 361
 362         struct hdmi_core_infoframe_avi avi_cfg;
 363 };
 364
 365 static inline void hdmi_write_reg(void __iomem *base_addr, const u32 idx,
 366                 u32 val)
 367 {
 368         __raw_writel(val, base_addr + idx);
 369 }
 370
 371 static inline u32 hdmi_read_reg(void __iomem *base_addr, const u32 idx)
 372 {
 373         return __raw_readl(base_addr + idx);
 374 }
 375
 376 #define REG_FLD_MOD(base, idx, val, start, end) \
 377         hdmi_write_reg(base, idx, FLD_MOD(hdmi_read_reg(base, idx),\
 378                                                         val, start, end))
 379 #define REG_GET(base, idx, start, end) \
 380         FLD_GET(hdmi_read_reg(base, idx), start, end)
 381
 382 static inline int hdmi_wait_for_bit_change(void __iomem *base_addr,
 383                 const u32 idx, int b2, int b1, u32 val)
 384 {
 385         u32 t = 0, v;
 386         while (val != (v = REG_GET(base_addr, idx, b2, b1))) {
 387                 if (t++ > 10000)
 388                         return v;
 389                 udelay(1);
 390         }
 391         return v;
 392 }
 393
 394 /* HDMI wrapper funcs */
 395 int hdmi_wp_video_start(struct hdmi_wp_data *wp);
 396 void hdmi_wp_video_stop(struct hdmi_wp_data *wp);
 397 void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s);
 398 u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp);
 399 void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus);
 400 void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask);
 401 void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask);
 402 int hdmi_wp_set_phy_pwr(struct hdmi_wp_data *wp, enum hdmi_phy_pwr val);
 403 int hdmi_wp_set_pll_pwr(struct hdmi_wp_data *wp, enum hdmi_pll_pwr val);
 404 void hdmi_wp_video_config_format(struct hdmi_wp_data *wp,
 405                 struct hdmi_video_format *video_fmt);
 406 void hdmi_wp_video_config_interface(struct hdmi_wp_data *wp,
 407                 struct omap_video_timings *timings);
 408 void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp,
 409                 struct omap_video_timings *timings);
 410 void hdmi_wp_init_vid_fmt_timings(struct hdmi_video_format *video_fmt,
 411                 struct omap_video_timings *timings, struct hdmi_config *param);
 412 int hdmi_wp_init(struct platform_device *pdev, struct hdmi_wp_data *wp);
 413
 414 /* HDMI PLL funcs */
 415 int hdmi_pll_enable(struct hdmi_pll_data *pll, struct hdmi_wp_data *wp);
 416 void hdmi_pll_disable(struct hdmi_pll_data *pll, struct hdmi_wp_data *wp);
 417 void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s);
 418 void hdmi_pll_compute(struct hdmi_pll_data *pll, unsigned long clkin, int phy);
 419 int hdmi_pll_init(struct platform_device *pdev, struct hdmi_pll_data *pll);
 420
 421 /* HDMI PHY funcs */
 422 int hdmi_phy_configure(struct hdmi_phy_data *phy, struct hdmi_config *cfg);
 423 void hdmi_phy_dump(struct hdmi_phy_data *phy, struct seq_file *s);
 424 int hdmi_phy_init(struct platform_device *pdev, struct hdmi_phy_data *phy);
 425 int hdmi_phy_parse_lanes(struct hdmi_phy_data *phy, const u32 *lanes);
 426
 427 /* HDMI common funcs */
 428 const struct hdmi_config *hdmi_default_timing(void);
 429 const struct hdmi_config *hdmi_get_timings(int mode, int code);
 430 struct hdmi_cm hdmi_get_code(struct omap_video_timings *timing);
 431 int hdmi_parse_lanes_of(struct platform_device *pdev, struct device_node *ep,
 432         struct hdmi_phy_data *phy);
 433
 434 #if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO) || defined(CONFIG_OMAP5_DSS_HDMI_AUDIO)
 435 int hdmi_compute_acr(u32 pclk, u32 sample_freq, u32 *n, u32 *cts);
 436 int hdmi_wp_audio_enable(struct hdmi_wp_data *wp, bool enable);
 437 int hdmi_wp_audio_core_req_enable(struct hdmi_wp_data *wp, bool enable);
 438 void hdmi_wp_audio_config_format(struct hdmi_wp_data *wp,
 439                 struct hdmi_audio_format *aud_fmt);
 440 void hdmi_wp_audio_config_dma(struct hdmi_wp_data *wp,
 441                 struct hdmi_audio_dma *aud_dma);
 442 static inline bool hdmi_mode_has_audio(int mode)
 443 {
 444         return mode == HDMI_HDMI ? true : false;
 445 }
 446 #endif
 447 #endif