drivers/video/ipu_disp.c

   1 /*
   2  * Porting to u-boot:
   3  *
   4  * (C) Copyright 2010
   5  * Stefano Babic, DENX Software Engineering, sbabic@denx.de
   6  *
   7  * Linux IPU driver
   8  *
   9  * (C) Copyright 2005-2011 Freescale Semiconductor, Inc.
  10  *
  11  * See file CREDITS for list of people who contributed to this
  12  * project.
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27  * MA 02111-1307 USA
  28  */
  29
  30 /* #define DEBUG */
  31
  32 #include <common.h>
  33 #include <ipu.h>
  34 #include <linux/types.h>
  35 #include <asm/errno.h>
  36 #include <asm/io.h>
  37 #include <asm/arch/imx-regs.h>
  38
  39 #include "ipu_regs.h"
  40
  41 enum csc_type_t {
  42         RGB2YUV = 0,
  43         YUV2RGB,
  44         RGB2RGB,
  45         YUV2YUV,
  46         CSC_NONE,
  47         CSC_NUM
  48 };
  49
  50 struct dp_csc_param_t {
  51         int mode;
  52         void *coeff;
  53 };
  54
  55 #define SYNC_WAVE 0
  56
  57 /* DC display ID assignments */
  58 #define DC_DISP_ID_SYNC(di)     (di)
  59 #define DC_DISP_ID_SERIAL       2
  60 #define DC_DISP_ID_ASYNC        3
  61
  62 static int dmfc_type_setup;
  63 static int dmfc_size_28, dmfc_size_29, dmfc_size_24, dmfc_size_27, dmfc_size_23;
  64 static int g_di1_tvout;
  65
  66 void ipu_dmfc_init(int dmfc_type, int first)
  67 {
  68         u32 dmfc_wr_chan, dmfc_dp_chan;
  69
  70         if (first) {
  71                 if (dmfc_type_setup > dmfc_type)
  72                         dmfc_type = dmfc_type_setup;
  73                 else
  74                         dmfc_type_setup = dmfc_type;
  75
  76                 /* disable DMFC-IC channel*/
  77                 __raw_writel(0x2, DMFC_IC_CTRL);
  78         } else if (dmfc_type_setup >= DMFC_HIGH_RESOLUTION_DC) {
  79                 printf("DMFC high resolution has set, will not change\n");
  80                 return;
  81         } else
  82                 dmfc_type_setup = dmfc_type;
  83
  84         if (dmfc_type == DMFC_HIGH_RESOLUTION_DC) {
  85                 /* 1 - segment 0~3;
  86                  * 5B - segement 4, 5;
  87                  * 5F - segement 6, 7;
  88                  * 1C, 2C and 6B, 6F unused;
  89                  */
  90                 debug("IPU DMFC DC HIGH RES: 1(0~3), 5B(4,5), 5F(6,7)\n");
  91                 dmfc_wr_chan = 0x00000088;
  92                 dmfc_dp_chan = 0x00009694;
  93                 dmfc_size_28 = 256 * 4;
  94                 dmfc_size_29 = 0;
  95                 dmfc_size_24 = 0;
  96                 dmfc_size_27 = 128 * 4;
  97                 dmfc_size_23 = 128 * 4;
  98         } else if (dmfc_type == DMFC_HIGH_RESOLUTION_DP) {
  99                 /* 1 - segment 0, 1;
 100                  * 5B - segement 2~5;
 101                  * 5F - segement 6,7;
 102                  * 1C, 2C and 6B, 6F unused;
 103                  */
 104                 debug("IPU DMFC DP HIGH RES: 1(0,1), 5B(2~5), 5F(6,7)\n");
 105                 dmfc_wr_chan = 0x00000090;
 106                 dmfc_dp_chan = 0x0000968a;
 107                 dmfc_size_28 = 128 * 4;
 108                 dmfc_size_29 = 0;
 109                 dmfc_size_24 = 0;
 110                 dmfc_size_27 = 128 * 4;
 111                 dmfc_size_23 = 256 * 4;
 112         } else if (dmfc_type == DMFC_HIGH_RESOLUTION_ONLY_DP) {
 113                 /* 5B - segement 0~3;
 114                  * 5F - segement 4~7;
 115                  * 1, 1C, 2C and 6B, 6F unused;
 116                  */
 117                 debug("IPU DMFC ONLY-DP HIGH RES: 5B(0~3), 5F(4~7)\n");
 118                 dmfc_wr_chan = 0x00000000;
 119                 dmfc_dp_chan = 0x00008c88;
 120                 dmfc_size_28 = 0;
 121                 dmfc_size_29 = 0;
 122                 dmfc_size_24 = 0;
 123                 dmfc_size_27 = 256 * 4;
 124                 dmfc_size_23 = 256 * 4;
 125         } else {
 126                 /* 1 - segment 0, 1;
 127                  * 5B - segement 4, 5;
 128                  * 5F - segement 6, 7;
 129                  * 1C, 2C and 6B, 6F unused;
 130                  */
 131                 debug("IPU DMFC NORMAL mode: 1(0~1), 5B(4,5), 5F(6,7)\n");
 132                 dmfc_wr_chan = 0x00000090;
 133                 dmfc_dp_chan = 0x00009694;
 134                 dmfc_size_28 = 128 * 4;
 135                 dmfc_size_29 = 0;
 136                 dmfc_size_24 = 0;
 137                 dmfc_size_27 = 128 * 4;
 138                 dmfc_size_23 = 128 * 4;
 139         }
 140         __raw_writel(dmfc_wr_chan, DMFC_WR_CHAN);
 141         __raw_writel(0x202020F6, DMFC_WR_CHAN_DEF);
 142         __raw_writel(dmfc_dp_chan, DMFC_DP_CHAN);
 143         /* Enable chan 5 watermark set at 5 bursts and clear at 7 bursts */
 144         __raw_writel(0x2020F6F6, DMFC_DP_CHAN_DEF);
 145 }
 146
 147 void ipu_dmfc_set_wait4eot(int dma_chan, int width)
 148 {
 149         u32 dmfc_gen1 = __raw_readl(DMFC_GENERAL1);
 150
 151         if (width >= HIGH_RESOLUTION_WIDTH) {
 152                 if (dma_chan == 23)
 153                         ipu_dmfc_init(DMFC_HIGH_RESOLUTION_DP, 0);
 154                 else if (dma_chan == 28)
 155                         ipu_dmfc_init(DMFC_HIGH_RESOLUTION_DC, 0);
 156         }
 157
 158         if (dma_chan == 23) { /*5B*/
 159                 if (dmfc_size_23 / width > 3)
 160                         dmfc_gen1 |= 1UL << 20;
 161                 else
 162                         dmfc_gen1 &= ~(1UL << 20);
 163         } else if (dma_chan == 24) { /*6B*/
 164                 if (dmfc_size_24 / width > 1)
 165                         dmfc_gen1 |= 1UL << 22;
 166                 else
 167                         dmfc_gen1 &= ~(1UL << 22);
 168         } else if (dma_chan == 27) { /*5F*/
 169                 if (dmfc_size_27 / width > 2)
 170                         dmfc_gen1 |= 1UL << 21;
 171                 else
 172                         dmfc_gen1 &= ~(1UL << 21);
 173         } else if (dma_chan == 28) { /*1*/
 174                 if (dmfc_size_28 / width > 2)
 175                         dmfc_gen1 |= 1UL << 16;
 176                 else
 177                         dmfc_gen1 &= ~(1UL << 16);
 178         } else if (dma_chan == 29) { /*6F*/
 179                 if (dmfc_size_29 / width > 1)
 180                         dmfc_gen1 |= 1UL << 23;
 181                 else
 182                         dmfc_gen1 &= ~(1UL << 23);
 183         }
 184
 185         __raw_writel(dmfc_gen1, DMFC_GENERAL1);
 186 }
 187
 188 static void ipu_di_data_wave_config(int di,
 189                                      int wave_gen,
 190                                      int access_size, int component_size)
 191 {
 192         u32 reg;
 193         reg = (access_size << DI_DW_GEN_ACCESS_SIZE_OFFSET) |
 194             (component_size << DI_DW_GEN_COMPONENT_SIZE_OFFSET);
 195         __raw_writel(reg, DI_DW_GEN(di, wave_gen));
 196 }
 197
 198 static void ipu_di_data_pin_config(int di, int wave_gen, int di_pin, int set,
 199                                     int up, int down)
 200 {
 201         u32 reg;
 202
 203         reg = __raw_readl(DI_DW_GEN(di, wave_gen));
 204         reg &= ~(0x3 << (di_pin * 2));
 205         reg |= set << (di_pin * 2);
 206         __raw_writel(reg, DI_DW_GEN(di, wave_gen));
 207
 208         __raw_writel((down << 16) | up, DI_DW_SET(di, wave_gen, set));
 209 }
 210
 211 static void ipu_di_sync_config(int di, int wave_gen,
 212                                 int run_count, int run_src,
 213                                 int offset_count, int offset_src,
 214                                 int repeat_count, int cnt_clr_src,
 215                                 int cnt_polarity_gen_en,
 216                                 int cnt_polarity_clr_src,
 217                                 int cnt_polarity_trigger_src,
 218                                 int cnt_up, int cnt_down)
 219 {
 220         u32 reg;
 221
 222         if ((run_count >= 0x1000) || (offset_count >= 0x1000) ||
 223                 (repeat_count >= 0x1000) ||
 224                 (cnt_up >= 0x400) || (cnt_down >= 0x400)) {
 225                 printf("DI%d counters out of range.\n", di);
 226                 return;
 227         }
 228
 229         reg = (run_count << 19) | (++run_src << 16) |
 230             (offset_count << 3) | ++offset_src;
 231         __raw_writel(reg, DI_SW_GEN0(di, wave_gen));
 232         reg = (cnt_polarity_gen_en << 29) | (++cnt_clr_src << 25) |
 233             (++cnt_polarity_trigger_src << 12) | (++cnt_polarity_clr_src << 9);
 234         reg |= (cnt_down << 16) | cnt_up;
 235         if (repeat_count == 0) {
 236                 /* Enable auto reload */
 237                 reg |= 0x10000000;
 238         }
 239         __raw_writel(reg, DI_SW_GEN1(di, wave_gen));
 240         reg = __raw_readl(DI_STP_REP(di, wave_gen));
 241         reg &= ~(0xFFFF << (16 * ((wave_gen - 1) & 0x1)));
 242         reg |= repeat_count << (16 * ((wave_gen - 1) & 0x1));
 243         __raw_writel(reg, DI_STP_REP(di, wave_gen));
 244 }
 245
 246 static void ipu_dc_map_config(int map, int byte_num, int offset, int mask)
 247 {
 248         int ptr = map * 3 + byte_num;
 249         u32 reg;
 250
 251         reg = __raw_readl(DC_MAP_CONF_VAL(ptr));
 252         reg &= ~(0xFFFF << (16 * (ptr & 0x1)));
 253         reg |= ((offset << 8) | mask) << (16 * (ptr & 0x1));
 254         __raw_writel(reg, DC_MAP_CONF_VAL(ptr));
 255
 256         reg = __raw_readl(DC_MAP_CONF_PTR(map));
 257         reg &= ~(0x1F << ((16 * (map & 0x1)) + (5 * byte_num)));
 258         reg |= ptr << ((16 * (map & 0x1)) + (5 * byte_num));
 259         __raw_writel(reg, DC_MAP_CONF_PTR(map));
 260 }
 261
 262 static void ipu_dc_map_clear(int map)
 263 {
 264         u32 reg = __raw_readl(DC_MAP_CONF_PTR(map));
 265         __raw_writel(reg & ~(0xFFFF << (16 * (map & 0x1))),
 266                      DC_MAP_CONF_PTR(map));
 267 }
 268
 269 static void ipu_dc_write_tmpl(int word, u32 opcode, u32 operand, int map,
 270                                int wave, int glue, int sync)
 271 {
 272         u32 reg;
 273         int stop = 1;
 274
 275         reg = sync;
 276         reg |= (glue << 4);
 277         reg |= (++wave << 11);
 278         reg |= (++map << 15);
 279         reg |= (operand << 20) & 0xFFF00000;
 280         __raw_writel(reg, ipu_dc_tmpl_reg + word * 2);
 281
 282         reg = (operand >> 12);
 283         reg |= opcode << 4;
 284         reg |= (stop << 9);
 285         __raw_writel(reg, ipu_dc_tmpl_reg + word * 2 + 1);
 286 }
 287
 288 static void ipu_dc_link_event(int chan, int event, int addr, int priority)
 289 {
 290         u32 reg;
 291
 292         reg = __raw_readl(DC_RL_CH(chan, event));
 293         reg &= ~(0xFFFF << (16 * (event & 0x1)));
 294         reg |= ((addr << 8) | priority) << (16 * (event & 0x1));
 295         __raw_writel(reg, DC_RL_CH(chan, event));
 296 }
 297
 298 /* Y = R *  1.200 + G *  2.343 + B *  .453 + 0.250;
 299  * U = R * -.672 + G * -1.328 + B *  2.000 + 512.250.;
 300  * V = R *  2.000 + G * -1.672 + B * -.328 + 512.250.;
 301  */
 302 static const int rgb2ycbcr_coeff[5][3] = {
 303         {0x4D, 0x96, 0x1D},
 304         {0x3D5, 0x3AB, 0x80},
 305         {0x80, 0x395, 0x3EB},
 306         {0x0000, 0x0200, 0x0200},       /* B0, B1, B2 */
 307         {0x2, 0x2, 0x2},        /* S0, S1, S2 */
 308 };
 309
 310 /* R = (1.164 * (Y - 16)) + (1.596 * (Cr - 128));
 311  * G = (1.164 * (Y - 16)) - (0.392 * (Cb - 128)) - (0.813 * (Cr - 128));
 312  * B = (1.164 * (Y - 16)) + (2.017 * (Cb - 128);
 313  */
 314 static const int ycbcr2rgb_coeff[5][3] = {
 315         {0x095, 0x000, 0x0CC},
 316         {0x095, 0x3CE, 0x398},
 317         {0x095, 0x0FF, 0x000},
 318         {0x3E42, 0x010A, 0x3DD6},       /*B0,B1,B2 */
 319         {0x1, 0x1, 0x1},        /*S0,S1,S2 */
 320 };
 321
 322 #define mask_a(a) ((u32)(a) & 0x3FF)
 323 #define mask_b(b) ((u32)(b) & 0x3FFF)
 324
 325 /* Pls keep S0, S1 and S2 as 0x2 by using this convertion */
 326 static int rgb_to_yuv(int n, int red, int green, int blue)
 327 {
 328         int c;
 329         c = red * rgb2ycbcr_coeff[n][0];
 330         c += green * rgb2ycbcr_coeff[n][1];
 331         c += blue * rgb2ycbcr_coeff[n][2];
 332         c /= 16;
 333         c += rgb2ycbcr_coeff[3][n] * 4;
 334         c += 8;
 335         c /= 16;
 336         if (c < 0)
 337                 c = 0;
 338         if (c > 255)
 339                 c = 255;
 340         return c;
 341 }
 342
 343 /*
 344  * Row is for BG:       RGB2YUV YUV2RGB RGB2RGB YUV2YUV CSC_NONE
 345  * Column is for FG:    RGB2YUV YUV2RGB RGB2RGB YUV2YUV CSC_NONE
 346  */
 347 static struct dp_csc_param_t dp_csc_array[CSC_NUM][CSC_NUM] = {
 348         {
 349                 {DP_COM_CONF_CSC_DEF_BOTH, &rgb2ycbcr_coeff},
 350                 {0, 0},
 351                 {0, 0},
 352                 {DP_COM_CONF_CSC_DEF_BG, &rgb2ycbcr_coeff},
 353                 {DP_COM_CONF_CSC_DEF_BG, &rgb2ycbcr_coeff}
 354         },
 355         {
 356                 {0, 0},
 357                 {DP_COM_CONF_CSC_DEF_BOTH, &ycbcr2rgb_coeff},
 358                 {DP_COM_CONF_CSC_DEF_BG, &ycbcr2rgb_coeff},
 359                 {0, 0},
 360                 {DP_COM_CONF_CSC_DEF_BG, &ycbcr2rgb_coeff}
 361         },
 362         {
 363                 {0, 0},
 364                 {DP_COM_CONF_CSC_DEF_FG, &ycbcr2rgb_coeff},
 365                 {0, 0},
 366                 {0, 0},
 367                 {0, 0}
 368         },
 369         {
 370                 {DP_COM_CONF_CSC_DEF_FG, &rgb2ycbcr_coeff},
 371                 {0, 0},
 372                 {0, 0},
 373                 {0, 0},
 374                 {0, 0}
 375         },
 376         {
 377                 {DP_COM_CONF_CSC_DEF_FG, &rgb2ycbcr_coeff},
 378                 {DP_COM_CONF_CSC_DEF_FG, &ycbcr2rgb_coeff},
 379                 {0, 0},
 380                 {0, 0},
 381                 {0, 0}
 382         }
 383 };
 384
 385 static enum csc_type_t fg_csc_type = CSC_NONE, bg_csc_type = CSC_NONE;
 386 static int color_key_4rgb = 1;
 387
 388 void ipu_dp_csc_setup(int dp, struct dp_csc_param_t dp_csc_param,
 389                         unsigned char srm_mode_update)
 390 {
 391         u32 reg;
 392         const int (*coeff)[5][3];
 393
 394         if (dp_csc_param.mode >= 0) {
 395                 reg = __raw_readl(DP_COM_CONF());
 396                 reg &= ~DP_COM_CONF_CSC_DEF_MASK;
 397                 reg |= dp_csc_param.mode;
 398                 __raw_writel(reg, DP_COM_CONF());
 399         }
 400
 401         coeff = dp_csc_param.coeff;
 402
 403         if (coeff) {
 404                 __raw_writel(mask_a((*coeff)[0][0]) |
 405                                 (mask_a((*coeff)[0][1]) << 16), DP_CSC_A_0());
 406                 __raw_writel(mask_a((*coeff)[0][2]) |
 407                                 (mask_a((*coeff)[1][0]) << 16), DP_CSC_A_1());
 408                 __raw_writel(mask_a((*coeff)[1][1]) |
 409                                 (mask_a((*coeff)[1][2]) << 16), DP_CSC_A_2());
 410                 __raw_writel(mask_a((*coeff)[2][0]) |
 411                                 (mask_a((*coeff)[2][1]) << 16), DP_CSC_A_3());
 412                 __raw_writel(mask_a((*coeff)[2][2]) |
 413                                 (mask_b((*coeff)[3][0]) << 16) |
 414                                 ((*coeff)[4][0] << 30), DP_CSC_0());
 415                 __raw_writel(mask_b((*coeff)[3][1]) | ((*coeff)[4][1] << 14) |
 416                                 (mask_b((*coeff)[3][2]) << 16) |
 417                                 ((*coeff)[4][2] << 30), DP_CSC_1());
 418         }
 419
 420         if (srm_mode_update) {
 421                 reg = __raw_readl(IPU_SRM_PRI2) | 0x8;
 422                 __raw_writel(reg, IPU_SRM_PRI2);
 423         }
 424 }
 425
 426 int ipu_dp_init(ipu_channel_t channel, uint32_t in_pixel_fmt,
 427                  uint32_t out_pixel_fmt)
 428 {
 429         int in_fmt, out_fmt;
 430         int dp;
 431         int partial = 0;
 432         uint32_t reg;
 433
 434         if (channel == MEM_FG_SYNC) {
 435                 dp = DP_SYNC;
 436                 partial = 1;
 437         } else if (channel == MEM_BG_SYNC) {
 438                 dp = DP_SYNC;
 439                 partial = 0;
 440         } else if (channel == MEM_BG_ASYNC0) {
 441                 dp = DP_ASYNC0;
 442                 partial = 0;
 443         } else {
 444                 return -EINVAL;
 445         }
 446
 447         in_fmt = format_to_colorspace(in_pixel_fmt);
 448         out_fmt = format_to_colorspace(out_pixel_fmt);
 449
 450         if (partial) {
 451                 if (in_fmt == RGB) {
 452                         if (out_fmt == RGB)
 453                                 fg_csc_type = RGB2RGB;
 454                         else
 455                                 fg_csc_type = RGB2YUV;
 456                 } else {
 457                         if (out_fmt == RGB)
 458                                 fg_csc_type = YUV2RGB;
 459                         else
 460                                 fg_csc_type = YUV2YUV;
 461                 }
 462         } else {
 463                 if (in_fmt == RGB) {
 464                         if (out_fmt == RGB)
 465                                 bg_csc_type = RGB2RGB;
 466                         else
 467                                 bg_csc_type = RGB2YUV;
 468                 } else {
 469                         if (out_fmt == RGB)
 470                                 bg_csc_type = YUV2RGB;
 471                         else
 472                                 bg_csc_type = YUV2YUV;
 473                 }
 474         }
 475
 476         /* Transform color key from rgb to yuv if CSC is enabled */
 477         reg = __raw_readl(DP_COM_CONF());
 478         if (color_key_4rgb && (reg & DP_COM_CONF_GWCKE) &&
 479                 (((fg_csc_type == RGB2YUV) && (bg_csc_type == YUV2YUV)) ||
 480                 ((fg_csc_type == YUV2YUV) && (bg_csc_type == RGB2YUV)) ||
 481                 ((fg_csc_type == YUV2YUV) && (bg_csc_type == YUV2YUV)) ||
 482                 ((fg_csc_type == YUV2RGB) && (bg_csc_type == YUV2RGB)))) {
 483                 int red, green, blue;
 484                 int y, u, v;
 485                 uint32_t color_key = __raw_readl(DP_GRAPH_WIND_CTRL()) &
 486                         0xFFFFFFL;
 487
 488                 debug("_ipu_dp_init color key 0x%x need change to yuv fmt!\n",
 489                         color_key);
 490
 491                 red = (color_key >> 16) & 0xFF;
 492                 green = (color_key >> 8) & 0xFF;
 493                 blue = color_key & 0xFF;
 494
 495                 y = rgb_to_yuv(0, red, green, blue);
 496                 u = rgb_to_yuv(1, red, green, blue);
 497                 v = rgb_to_yuv(2, red, green, blue);
 498                 color_key = (y << 16) | (u << 8) | v;
 499
 500                 reg = __raw_readl(DP_GRAPH_WIND_CTRL()) & 0xFF000000L;
 501                 __raw_writel(reg | color_key, DP_GRAPH_WIND_CTRL());
 502                 color_key_4rgb = 0;
 503
 504                 debug("_ipu_dp_init color key change to yuv fmt 0x%x!\n",
 505                         color_key);
 506         }
 507
 508         ipu_dp_csc_setup(dp, dp_csc_array[bg_csc_type][fg_csc_type], 1);
 509
 510         return 0;
 511 }
 512
 513 void ipu_dp_uninit(ipu_channel_t channel)
 514 {
 515         int dp;
 516         int partial = 0;
 517
 518         if (channel == MEM_FG_SYNC) {
 519                 dp = DP_SYNC;
 520                 partial = 1;
 521         } else if (channel == MEM_BG_SYNC) {
 522                 dp = DP_SYNC;
 523                 partial = 0;
 524         } else if (channel == MEM_BG_ASYNC0) {
 525                 dp = DP_ASYNC0;
 526                 partial = 0;
 527         } else {
 528                 return;
 529         }
 530
 531         if (partial)
 532                 fg_csc_type = CSC_NONE;
 533         else
 534                 bg_csc_type = CSC_NONE;
 535
 536         ipu_dp_csc_setup(dp, dp_csc_array[bg_csc_type][fg_csc_type], 0);
 537 }
 538
 539 void ipu_dc_init(int dc_chan, int di, unsigned char interlaced)
 540 {
 541         u32 reg = 0;
 542
 543         if ((dc_chan == 1) || (dc_chan == 5)) {
 544                 if (interlaced) {
 545                         ipu_dc_link_event(dc_chan, DC_EVT_NL, 0, 3);
 546                         ipu_dc_link_event(dc_chan, DC_EVT_EOL, 0, 2);
 547                         ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA, 0, 1);
 548                 } else {
 549                         if (di) {
 550                                 ipu_dc_link_event(dc_chan, DC_EVT_NL, 2, 3);
 551                                 ipu_dc_link_event(dc_chan, DC_EVT_EOL, 3, 2);
 552                                 ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA,
 553                                         4, 1);
 554                         } else {
 555                                 ipu_dc_link_event(dc_chan, DC_EVT_NL, 5, 3);
 556                                 ipu_dc_link_event(dc_chan, DC_EVT_EOL, 6, 2);
 557                                 ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA,
 558                                         7, 1);
 559                         }
 560                 }
 561                 ipu_dc_link_event(dc_chan, DC_EVT_NF, 0, 0);
 562                 ipu_dc_link_event(dc_chan, DC_EVT_NFIELD, 0, 0);
 563                 ipu_dc_link_event(dc_chan, DC_EVT_EOF, 0, 0);
 564                 ipu_dc_link_event(dc_chan, DC_EVT_EOFIELD, 0, 0);
 565                 ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN, 0, 0);
 566                 ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR, 0, 0);
 567
 568                 reg = 0x2;
 569                 reg |= DC_DISP_ID_SYNC(di) << DC_WR_CH_CONF_PROG_DISP_ID_OFFSET;
 570                 reg |= di << 2;
 571                 if (interlaced)
 572                         reg |= DC_WR_CH_CONF_FIELD_MODE;
 573         } else if ((dc_chan == 8) || (dc_chan == 9)) {
 574                 /* async channels */
 575                 ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_W_0, 0x64, 1);
 576                 ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_W_1, 0x64, 1);
 577
 578                 reg = 0x3;
 579                 reg |= DC_DISP_ID_SERIAL << DC_WR_CH_CONF_PROG_DISP_ID_OFFSET;
 580         }
 581         __raw_writel(reg, DC_WR_CH_CONF(dc_chan));
 582
 583         __raw_writel(0x00000000, DC_WR_CH_ADDR(dc_chan));
 584
 585         __raw_writel(0x00000084, DC_GEN);
 586 }
 587
 588 void ipu_dc_uninit(int dc_chan)
 589 {
 590         if ((dc_chan == 1) || (dc_chan == 5)) {
 591                 ipu_dc_link_event(dc_chan, DC_EVT_NL, 0, 0);
 592                 ipu_dc_link_event(dc_chan, DC_EVT_EOL, 0, 0);
 593                 ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA, 0, 0);
 594                 ipu_dc_link_event(dc_chan, DC_EVT_NF, 0, 0);
 595                 ipu_dc_link_event(dc_chan, DC_EVT_NFIELD, 0, 0);
 596                 ipu_dc_link_event(dc_chan, DC_EVT_EOF, 0, 0);
 597                 ipu_dc_link_event(dc_chan, DC_EVT_EOFIELD, 0, 0);
 598                 ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN, 0, 0);
 599                 ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR, 0, 0);
 600         } else if ((dc_chan == 8) || (dc_chan == 9)) {
 601                 ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR_W_0, 0, 0);
 602                 ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR_W_1, 0, 0);
 603                 ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN_W_0, 0, 0);
 604                 ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN_W_1, 0, 0);
 605                 ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_W_0, 0, 0);
 606                 ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_W_1, 0, 0);
 607                 ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR_R_0, 0, 0);
 608                 ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR_R_1, 0, 0);
 609                 ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN_R_0, 0, 0);
 610                 ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN_R_1, 0, 0);
 611                 ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_R_0, 0, 0);
 612                 ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_R_1, 0, 0);
 613         }
 614 }
 615
 616 int ipu_chan_is_interlaced(ipu_channel_t channel)
 617 {
 618         if (channel == MEM_DC_SYNC)
 619                 return !!(__raw_readl(DC_WR_CH_CONF_1) &
 620                           DC_WR_CH_CONF_FIELD_MODE);
 621         else if ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC))
 622                 return !!(__raw_readl(DC_WR_CH_CONF_5) &
 623                           DC_WR_CH_CONF_FIELD_MODE);
 624         return 0;
 625 }
 626
 627 void ipu_dp_dc_enable(ipu_channel_t channel)
 628 {
 629         int di;
 630         uint32_t reg;
 631         uint32_t dc_chan;
 632
 633         if (channel == MEM_FG_SYNC)
 634                 dc_chan = 5;
 635         if (channel == MEM_DC_SYNC)
 636                 dc_chan = 1;
 637         else if (channel == MEM_BG_SYNC)
 638                 dc_chan = 5;
 639         else
 640                 return;
 641
 642         if (channel == MEM_FG_SYNC) {
 643                 /* Enable FG channel */
 644                 reg = __raw_readl(DP_COM_CONF());
 645                 __raw_writel(reg | DP_COM_CONF_FG_EN, DP_COM_CONF());
 646
 647                 reg = __raw_readl(IPU_SRM_PRI2) | 0x8;
 648                 __raw_writel(reg, IPU_SRM_PRI2);
 649                 return;
 650         }
 651
 652         di = g_dc_di_assignment[dc_chan];
 653
 654         /* Make sure other DC sync channel is not assigned same DI */
 655         reg = __raw_readl(DC_WR_CH_CONF(6 - dc_chan));
 656         if ((di << 2) == (reg & DC_WR_CH_CONF_PROG_DI_ID)) {
 657                 reg &= ~DC_WR_CH_CONF_PROG_DI_ID;
 658                 reg |= di ? 0 : DC_WR_CH_CONF_PROG_DI_ID;
 659                 __raw_writel(reg, DC_WR_CH_CONF(6 - dc_chan));
 660         }
 661
 662         reg = __raw_readl(DC_WR_CH_CONF(dc_chan));
 663         reg |= 4 << DC_WR_CH_CONF_PROG_TYPE_OFFSET;
 664         __raw_writel(reg, DC_WR_CH_CONF(dc_chan));
 665
 666         clk_enable(g_pixel_clk[di]);
 667 }
 668
 669 static unsigned char dc_swap;
 670
 671 void ipu_dp_dc_disable(ipu_channel_t channel, unsigned char swap)
 672 {
 673         uint32_t reg;
 674         uint32_t csc;
 675         uint32_t dc_chan = 0;
 676         int timeout = 50;
 677
 678         dc_swap = swap;
 679
 680         if (channel == MEM_DC_SYNC) {
 681                 dc_chan = 1;
 682         } else if (channel == MEM_BG_SYNC) {
 683                 dc_chan = 5;
 684         } else if (channel == MEM_FG_SYNC) {
 685                 /* Disable FG channel */
 686                 dc_chan = 5;
 687
 688                 reg = __raw_readl(DP_COM_CONF());
 689                 csc = reg & DP_COM_CONF_CSC_DEF_MASK;
 690                 if (csc == DP_COM_CONF_CSC_DEF_FG)
 691                         reg &= ~DP_COM_CONF_CSC_DEF_MASK;
 692
 693                 reg &= ~DP_COM_CONF_FG_EN;
 694                 __raw_writel(reg, DP_COM_CONF());
 695
 696                 reg = __raw_readl(IPU_SRM_PRI2) | 0x8;
 697                 __raw_writel(reg, IPU_SRM_PRI2);
 698
 699                 timeout = 50;
 700
 701                 /*
 702                  * Wait for DC triple buffer to empty,
 703                  * this check is useful for tv overlay.
 704                  */
 705                 if (g_dc_di_assignment[dc_chan] == 0)
 706                         while ((__raw_readl(DC_STAT) & 0x00000002)
 707                                != 0x00000002) {
 708                                 udelay(2000);
 709                                 timeout -= 2;
 710                                 if (timeout <= 0)
 711                                         break;
 712                         }
 713                 else if (g_dc_di_assignment[dc_chan] == 1)
 714                         while ((__raw_readl(DC_STAT) & 0x00000020)
 715                                != 0x00000020) {
 716                                 udelay(2000);
 717                                 timeout -= 2;
 718                                 if (timeout <= 0)
 719                                         break;
 720                         }
 721                 return;
 722         } else {
 723                 return;
 724         }
 725
 726         if (dc_swap) {
 727                 /* Swap DC channel 1 and 5 settings, and disable old dc chan */
 728                 reg = __raw_readl(DC_WR_CH_CONF(dc_chan));
 729                 __raw_writel(reg, DC_WR_CH_CONF(6 - dc_chan));
 730                 reg &= ~DC_WR_CH_CONF_PROG_TYPE_MASK;
 731                 reg ^= DC_WR_CH_CONF_PROG_DI_ID;
 732                 __raw_writel(reg, DC_WR_CH_CONF(dc_chan));
 733         } else {
 734                 timeout = 50;
 735
 736                 /* Wait for DC triple buffer to empty */
 737                 if (g_dc_di_assignment[dc_chan] == 0)
 738                         while ((__raw_readl(DC_STAT) & 0x00000002)
 739                                 != 0x00000002) {
 740                                 udelay(2000);
 741                                 timeout -= 2;
 742                                 if (timeout <= 0)
 743                                         break;
 744                         }
 745                 else if (g_dc_di_assignment[dc_chan] == 1)
 746                         while ((__raw_readl(DC_STAT) & 0x00000020)
 747                                 != 0x00000020) {
 748                                 udelay(2000);
 749                                 timeout -= 2;
 750                                 if (timeout <= 0)
 751                                         break;
 752                         }
 753
 754                 reg = __raw_readl(DC_WR_CH_CONF(dc_chan));
 755                 reg &= ~DC_WR_CH_CONF_PROG_TYPE_MASK;
 756                 __raw_writel(reg, DC_WR_CH_CONF(dc_chan));
 757
 758                 reg = __raw_readl(IPU_DISP_GEN);
 759                 if (g_dc_di_assignment[dc_chan])
 760                         reg &= ~DI1_COUNTER_RELEASE;
 761                 else
 762                         reg &= ~DI0_COUNTER_RELEASE;
 763                 __raw_writel(reg, IPU_DISP_GEN);
 764
 765                 /* Clock is already off because it must be done quickly, but
 766                    we need to fix the ref count */
 767                 clk_disable(g_pixel_clk[g_dc_di_assignment[dc_chan]]);
 768         }
 769 }
 770
 771 void ipu_init_dc_mappings(void)
 772 {
 773         /* IPU_PIX_FMT_RGB24 */
 774         ipu_dc_map_clear(0);
 775         ipu_dc_map_config(0, 0, 7, 0xFF);
 776         ipu_dc_map_config(0, 1, 15, 0xFF);
 777         ipu_dc_map_config(0, 2, 23, 0xFF);
 778
 779         /* IPU_PIX_FMT_RGB666 */
 780         ipu_dc_map_clear(1);
 781         ipu_dc_map_config(1, 0, 5, 0xFC);
 782         ipu_dc_map_config(1, 1, 11, 0xFC);
 783         ipu_dc_map_config(1, 2, 17, 0xFC);
 784
 785         /* IPU_PIX_FMT_YUV444 */
 786         ipu_dc_map_clear(2);
 787         ipu_dc_map_config(2, 0, 15, 0xFF);
 788         ipu_dc_map_config(2, 1, 23, 0xFF);
 789         ipu_dc_map_config(2, 2, 7, 0xFF);
 790
 791         /* IPU_PIX_FMT_RGB565 */
 792         ipu_dc_map_clear(3);
 793         ipu_dc_map_config(3, 0, 4, 0xF8);
 794         ipu_dc_map_config(3, 1, 10, 0xFC);
 795         ipu_dc_map_config(3, 2, 15, 0xF8);
 796
 797         /* IPU_PIX_FMT_LVDS666 */
 798         ipu_dc_map_clear(4);
 799         ipu_dc_map_config(4, 0, 5, 0xFC);
 800         ipu_dc_map_config(4, 1, 11, 0xFC);
 801         ipu_dc_map_config(4, 2, 17, 0xFC);
 802 }
 803
 804 int ipu_pixfmt_to_map(uint32_t fmt)
 805 {
 806         switch (fmt) {
 807         case IPU_PIX_FMT_GENERIC:
 808         case IPU_PIX_FMT_RGB24:
 809         case IPU_PIX_FMT_LVDS888:
 810                 return 0;
 811         case IPU_PIX_FMT_RGB666:
 812                 return 1;
 813         case IPU_PIX_FMT_YUV444:
 814                 return 2;
 815         case IPU_PIX_FMT_RGB565:
 816                 return 3;
 817         case IPU_PIX_FMT_LVDS666:
 818                 return 4;
 819         }
 820
 821         return -1;
 822 }
 823
 824 /*
 825  * This function is called to adapt synchronous LCD panel to IPU restriction.
 826  */
 827 void adapt_panel_to_ipu_restricitions(uint32_t *pixel_clk,
 828                                       uint16_t width, uint16_t height,
 829                                       uint16_t h_start_width,
 830                                       uint16_t h_end_width,
 831                                       uint16_t v_start_width,
 832                                       uint16_t *v_end_width)
 833 {
 834         if (*v_end_width < 2) {
 835                 uint16_t total_width = width + h_start_width + h_end_width;
 836                 uint16_t total_height_old = height + v_start_width +
 837                         (*v_end_width);
 838                 uint16_t total_height_new = height + v_start_width + 2;
 839                 *v_end_width = 2;
 840                 *pixel_clk = (*pixel_clk) * total_width * total_height_new /
 841                         (total_width * total_height_old);
 842                 printf("WARNING: adapt panel end blank lines\n");
 843         }
 844 }
 845
 846 /*
 847  * This function is called to initialize a synchronous LCD panel.
 848  *
 849  * @param       disp            The DI the panel is attached to.
 850  *
 851  * @param       pixel_clk       Desired pixel clock frequency in Hz.
 852  *
 853  * @param       pixel_fmt       Input parameter for pixel format of buffer.
 854  *                              Pixel format is a FOURCC ASCII code.
 855  *
 856  * @param       width           The width of panel in pixels.
 857  *
 858  * @param       height          The height of panel in pixels.
 859  *
 860  * @param       hStartWidth     The number of pixel clocks between the HSYNC
 861  *                              signal pulse and the start of valid data.
 862  *
 863  * @param       hSyncWidth      The width of the HSYNC signal in units of pixel
 864  *                              clocks.
 865  *
 866  * @param       hEndWidth       The number of pixel clocks between the end of
 867  *                              valid data and the HSYNC signal for next line.
 868  *
 869  * @param       vStartWidth     The number of lines between the VSYNC
 870  *                              signal pulse and the start of valid data.
 871  *
 872  * @param       vSyncWidth      The width of the VSYNC signal in units of lines
 873  *
 874  * @param       vEndWidth       The number of lines between the end of valid
 875  *                              data and the VSYNC signal for next frame.
 876  *
 877  * @param       sig             Bitfield of signal polarities for LCD interface.
 878  *
 879  * @return      This function returns 0 on success or negative error code on
 880  *              fail.
 881  */
 882
 883 int ipu_init_sync_panel(int disp, uint32_t pixel_clk,
 884                         uint16_t width, uint16_t height,
 885                         uint32_t pixel_fmt,
 886                         uint16_t h_start_width, uint16_t h_sync_width,
 887                         uint16_t h_end_width, uint16_t v_start_width,
 888                         uint16_t v_sync_width, uint16_t v_end_width,
 889                         uint32_t v_to_h_sync, ipu_di_signal_cfg_t sig)
 890 {
 891         uint32_t reg;
 892         uint32_t di_gen, vsync_cnt;
 893         uint32_t div, rounded_pixel_clk;
 894         uint32_t h_total, v_total;
 895         int map;
 896         struct clk *di_parent;
 897
 898         debug("panel size = %d x %d\n", width, height);
 899
 900         if ((v_sync_width == 0) || (h_sync_width == 0))
 901                 return -EINVAL;
 902
 903         adapt_panel_to_ipu_restricitions(&pixel_clk, width, height,
 904                                          h_start_width, h_end_width,
 905                                          v_start_width, &v_end_width);
 906         h_total = width + h_sync_width + h_start_width + h_end_width;
 907         v_total = height + v_sync_width + v_start_width + v_end_width;
 908
 909         /* Init clocking */
 910         debug("pixel clk = %d\n", pixel_clk);
 911
 912         if (sig.ext_clk) {
 913                 if (!(g_di1_tvout && (disp == 1))) { /* don't round div for tvout */
 914                         /*
 915                          * Set the  PLL to be an even multiple
 916                          * of the pixel clock.
 917                          */
 918                         if ((clk_get_usecount(g_pixel_clk[0]) == 0) &&
 919                                 (clk_get_usecount(g_pixel_clk[1]) == 0)) {
 920                                 di_parent = clk_get_parent(g_di_clk[disp]);
 921                                 rounded_pixel_clk =
 922                                         clk_round_rate(g_pixel_clk[disp],
 923                                                 pixel_clk);
 924                                 if (di_parent != NULL) {
 925                                         div  = clk_get_rate(di_parent) /
 926                                                 rounded_pixel_clk;
 927                                         if (div % 2)
 928                                                 div++;
 929                                         if (clk_get_rate(di_parent) != div *
 930                                                 rounded_pixel_clk)
 931                                                 clk_set_rate(di_parent,
 932                                                         div * rounded_pixel_clk);
 933                                         udelay(10000);
 934                                         clk_set_rate(g_di_clk[disp],
 935                                                 2 * rounded_pixel_clk);
 936                                         udelay(10000);
 937                                 }
 938                         }
 939                 }
 940                 clk_set_parent(g_pixel_clk[disp], g_di_clk[disp]);
 941         } else {
 942                 if (clk_get_usecount(g_pixel_clk[disp]) != 0)
 943                         clk_set_parent(g_pixel_clk[disp], g_ipu_clk);
 944         }
 945         rounded_pixel_clk = clk_round_rate(g_pixel_clk[disp], pixel_clk);
 946         clk_set_rate(g_pixel_clk[disp], rounded_pixel_clk);
 947         udelay(5000);
 948         /* Get integer portion of divider */
 949         div = clk_get_rate(clk_get_parent(g_pixel_clk[disp])) /
 950                 rounded_pixel_clk;
 951
 952         /* Enable for a divide by 2 clock change. */
 953         reg = __raw_readl(IPU_PM);
 954         reg &= ~(0x7f << 7);
 955         reg |= 0x20 << 7;
 956         reg &= ~(0x7f << 23);
 957         reg |= 0x20 << 23;
 958         __raw_writel(reg, IPU_PM);
 959
 960         di_gen = 0;
 961
 962         if (pixel_fmt != IPU_PIX_FMT_LVDS666 &&
 963                         pixel_fmt != IPU_PIX_FMT_LVDS888) {
 964                 clk_set_rate(g_pixel_clk[disp], rounded_pixel_clk);
 965                 udelay(5000);
 966                 /* Get integer portion of divider */
 967                 div = clk_get_rate(clk_get_parent(g_pixel_clk[disp])) /
 968                         rounded_pixel_clk;
 969                 ipu_di_data_wave_config(disp, SYNC_WAVE, div - 1, div - 1);
 970         } else {
 971                 clk_set_rate(g_pixel_clk[disp], clk_get_rate(g_ipu_clk));
 972                 div = 1;
 973                 ipu_di_data_wave_config(disp, SYNC_WAVE, 0, 0);
 974                 di_gen |= (6 << 24);
 975                 di_gen |= DI_GEN_DI_CLK_EXT;
 976         }
 977         ipu_di_data_pin_config(disp, SYNC_WAVE, DI_PIN15, 3, 0, div * 2);
 978
 979         map = ipu_pixfmt_to_map(pixel_fmt);
 980         if (map < 0) {
 981                 debug("IPU_DISP: No MAP\n");
 982                 return -EINVAL;
 983         }
 984
 985         if (sig.interlaced) {
 986                 /* Setup internal HSYNC waveform */
 987                 ipu_di_sync_config(
 988                                 disp,           /* display */
 989                                 1,              /* counter */
 990                                 h_total / 2 - 1,/* run count */
 991                                 DI_SYNC_CLK,    /* run_resolution */
 992                                 0,              /* offset */
 993                                 DI_SYNC_NONE,   /* offset resolution */
 994                                 0,              /* repeat count */
 995                                 DI_SYNC_NONE,   /* CNT_CLR_SEL */
 996                                 0,              /* CNT_POLARITY_GEN_EN */
 997                                 DI_SYNC_NONE,   /* CNT_POLARITY_CLR_SEL */
 998                                 DI_SYNC_NONE,   /* CNT_POLARITY_TRIGGER_SEL */
 999                                 0,              /* COUNT UP */
1000                                 0               /* COUNT DOWN */
1001                                 );
1002
1003                 /* Field 1 VSYNC waveform */
1004                 ipu_di_sync_config(
1005                                 disp,           /* display */
1006                                 2,              /* counter */
1007                                 h_total - 1,    /* run count */
1008                                 DI_SYNC_CLK,    /* run_resolution */
1009                                 0,              /* offset */
1010                                 DI_SYNC_NONE,   /* offset resolution */
1011                                 0,              /* repeat count */
1012                                 DI_SYNC_NONE,   /* CNT_CLR_SEL */
1013                                 0,              /* CNT_POLARITY_GEN_EN */
1014                                 DI_SYNC_NONE,   /* CNT_POLARITY_CLR_SEL */
1015                                 DI_SYNC_NONE,   /* CNT_POLARITY_TRIGGER_SEL */
1016                                 0,              /* COUNT UP */
1017                                 4               /* COUNT DOWN */
1018                                 );
1019
1020                 /* Setup internal HSYNC waveform */
1021                 ipu_di_sync_config(
1022                                 disp,           /* display */
1023                                 3,              /* counter */
1024                                 v_total * 2 - 1,/* run count */
1025                                 DI_SYNC_INT_HSYNC,      /* run_resolution */
1026                                 1,              /* offset */
1027                                 DI_SYNC_INT_HSYNC,      /* offset resolution */
1028                                 0,              /* repeat count */
1029                                 DI_SYNC_NONE,   /* CNT_CLR_SEL */
1030                                 0,              /* CNT_POLARITY_GEN_EN */
1031                                 DI_SYNC_NONE,   /* CNT_POLARITY_CLR_SEL */
1032                                 DI_SYNC_NONE,   /* CNT_POLARITY_TRIGGER_SEL */
1033                                 0,              /* COUNT UP */
1034                                 4               /* COUNT DOWN */
1035                                 );
1036
1037                 /* Active Field ? */
1038                 ipu_di_sync_config(
1039                                 disp,           /* display */
1040                                 4,              /* counter */
1041                                 v_total / 2 - 1,/* run count */
1042                                 DI_SYNC_HSYNC,  /* run_resolution */
1043                                 v_start_width,  /*  offset */
1044                                 DI_SYNC_HSYNC,  /* offset resolution */
1045                                 2,              /* repeat count */
1046                                 DI_SYNC_VSYNC,  /* CNT_CLR_SEL */
1047                                 0,              /* CNT_POLARITY_GEN_EN */
1048                                 DI_SYNC_NONE,   /* CNT_POLARITY_CLR_SEL */
1049                                 DI_SYNC_NONE,   /* CNT_POLARITY_TRIGGER_SEL */
1050                                 0,              /* COUNT UP */
1051                                 0               /* COUNT DOWN */
1052                                 );
1053
1054                 /* Active Line */
1055                 ipu_di_sync_config(
1056                                 disp,           /* display */
1057                                 5,              /* counter */
1058                                 0,              /* run count */
1059                                 DI_SYNC_HSYNC,  /* run_resolution */
1060                                 0,              /*  offset */
1061                                 DI_SYNC_NONE,   /* offset resolution */
1062                                 height / 2,     /* repeat count */
1063                                 4,              /* CNT_CLR_SEL */
1064                                 0,              /* CNT_POLARITY_GEN_EN */
1065                                 DI_SYNC_NONE,   /* CNT_POLARITY_CLR_SEL */
1066                                 DI_SYNC_NONE,   /* CNT_POLARITY_TRIGGER_SEL */
1067                                 0,              /* COUNT UP */
1068                                 0               /* COUNT DOWN */
1069                                 );
1070
1071                 /* Field 0 VSYNC waveform */
1072                 ipu_di_sync_config(
1073                                 disp,           /* display */
1074                                 6,              /* counter */
1075                                 v_total - 1,    /* run count */
1076                                 DI_SYNC_HSYNC,  /* run_resolution */
1077                                 0,              /* offset */
1078                                 DI_SYNC_NONE,   /* offset resolution */
1079                                 0,              /* repeat count */
1080                                 DI_SYNC_NONE,   /* CNT_CLR_SEL  */
1081                                 0,              /* CNT_POLARITY_GEN_EN */
1082                                 DI_SYNC_NONE,   /* CNT_POLARITY_CLR_SEL */
1083                                 DI_SYNC_NONE,   /* CNT_POLARITY_TRIGGER_SEL */
1084                                 0,              /* COUNT UP */
1085                                 0               /* COUNT DOWN */
1086                                 );
1087
1088                 /* DC VSYNC waveform */
1089                 vsync_cnt = 7;
1090                 ipu_di_sync_config(
1091                                 disp,           /* display */
1092                                 7,              /* counter */
1093                                 v_total / 2 - 1,/* run count */
1094                                 DI_SYNC_HSYNC,  /* run_resolution  */
1095                                 9,              /* offset  */
1096                                 DI_SYNC_HSYNC,  /* offset resolution */
1097                                 2,              /* repeat count */
1098                                 DI_SYNC_VSYNC,  /* CNT_CLR_SEL */
1099                                 0,              /* CNT_POLARITY_GEN_EN */
1100                                 DI_SYNC_NONE,   /* CNT_POLARITY_CLR_SEL */
1101                                 DI_SYNC_NONE,   /* CNT_POLARITY_TRIGGER_SEL */
1102                                 0,              /* COUNT UP */
1103                                 0               /* COUNT DOWN */
1104                                 );
1105
1106                 /* active pixel waveform */
1107                 ipu_di_sync_config(
1108                                 disp,           /* display */
1109                                 8,              /* counter */
1110                                 0,              /* run count  */
1111                                 DI_SYNC_CLK,    /* run_resolution */
1112                                 h_start_width,  /* offset  */
1113                                 DI_SYNC_CLK,    /* offset resolution */
1114                                 width,          /* repeat count  */
1115                                 5,              /* CNT_CLR_SEL  */
1116                                 0,              /* CNT_POLARITY_GEN_EN  */
1117                                 DI_SYNC_NONE,   /* CNT_POLARITY_CLR_SEL */
1118                                 DI_SYNC_NONE,   /* CNT_POLARITY_TRIGGER_SEL  */
1119                                 0,              /* COUNT UP  */
1120                                 0               /* COUNT DOWN */
1121                                 );
1122
1123                 ipu_di_sync_config(
1124                                 disp,           /* display */
1125                                 9,              /* counter */
1126                                 v_total - 1,    /* run count */
1127                                 DI_SYNC_INT_HSYNC,/* run_resolution */
1128                                 v_total / 2,    /* offset  */
1129                                 DI_SYNC_INT_HSYNC,/* offset resolution  */
1130                                 0,              /* repeat count */
1131                                 DI_SYNC_HSYNC,  /* CNT_CLR_SEL */
1132                                 0,              /* CNT_POLARITY_GEN_EN  */
1133                                 DI_SYNC_NONE,   /* CNT_POLARITY_CLR_SEL  */
1134                                 DI_SYNC_NONE,   /* CNT_POLARITY_TRIGGER_SEL */
1135                                 0,              /* COUNT UP */
1136                                 4               /* COUNT DOWN */
1137                                 );
1138
1139                 /* set gentime select and tag sel */
1140                 reg = __raw_readl(DI_SW_GEN1(disp, 9));
1141                 reg &= 0x1FFFFFFF;
1142                 reg |= ((3 - 1) << 29) | 0x00008000;
1143                 __raw_writel(reg, DI_SW_GEN1(disp, 9));
1144
1145                 __raw_writel(v_total / 2 - 1, DI_SCR_CONF(disp));
1146
1147                 /* set y_sel = 1 */
1148                 di_gen |= 0x10000000;
1149                 di_gen |= DI_GEN_POLARITY_5;
1150                 di_gen |= DI_GEN_POLARITY_8;
1151         } else {
1152                 /* Setup internal HSYNC waveform */
1153                 ipu_di_sync_config(disp, 1, h_total - 1, DI_SYNC_CLK,
1154                                 0, DI_SYNC_NONE, 0, DI_SYNC_NONE,
1155                                 0, DI_SYNC_NONE,
1156                                 DI_SYNC_NONE, 0, 0);
1157
1158                 /* Setup external (delayed) HSYNC waveform */
1159                 ipu_di_sync_config(disp, DI_SYNC_HSYNC, h_total - 1,
1160                                 DI_SYNC_CLK, div * v_to_h_sync, DI_SYNC_CLK,
1161                                 0, DI_SYNC_NONE, 1, DI_SYNC_NONE,
1162                                 DI_SYNC_CLK, 0, h_sync_width * 2);
1163                 /* Setup VSYNC waveform */
1164                 vsync_cnt = DI_SYNC_VSYNC;
1165                 ipu_di_sync_config(disp, DI_SYNC_VSYNC, v_total - 1,
1166                                 DI_SYNC_INT_HSYNC, 0, DI_SYNC_NONE, 0,
1167                                 DI_SYNC_NONE, 1, DI_SYNC_NONE,
1168                                 DI_SYNC_INT_HSYNC, 0, v_sync_width * 2);
1169                 __raw_writel(v_total - 1, DI_SCR_CONF(disp));
1170
1171                 /* Setup active data waveform to sync with DC */
1172                 ipu_di_sync_config(disp, 4, 0, DI_SYNC_HSYNC,
1173                                 v_sync_width + v_start_width, DI_SYNC_HSYNC,
1174                                 height,
1175                                 DI_SYNC_VSYNC, 0, DI_SYNC_NONE,
1176                                 DI_SYNC_NONE, 0, 0);
1177                 ipu_di_sync_config(disp, 5, 0, DI_SYNC_CLK,
1178                                 h_sync_width + h_start_width, DI_SYNC_CLK,
1179                                 width, 4, 0, DI_SYNC_NONE, DI_SYNC_NONE, 0,
1180                                 0);
1181
1182                 /* reset all unused counters */
1183                 __raw_writel(0, DI_SW_GEN0(disp, 6));
1184                 __raw_writel(0, DI_SW_GEN1(disp, 6));
1185                 __raw_writel(0, DI_SW_GEN0(disp, 7));
1186                 __raw_writel(0, DI_SW_GEN1(disp, 7));
1187                 __raw_writel(0, DI_SW_GEN0(disp, 8));
1188                 __raw_writel(0, DI_SW_GEN1(disp, 8));
1189                 __raw_writel(0, DI_SW_GEN0(disp, 9));
1190                 __raw_writel(0, DI_SW_GEN1(disp, 9));
1191
1192                 reg = __raw_readl(DI_STP_REP(disp, 6));
1193                 reg &= 0x0000FFFF;
1194                 __raw_writel(reg, DI_STP_REP(disp, 6));
1195                 __raw_writel(0, DI_STP_REP(disp, 7));
1196                 __raw_writel(0, DI_STP_REP(disp, 9));
1197
1198                 h_total = ((width + h_start_width + h_sync_width) / 2) - 2;
1199                 ipu_di_sync_config(disp, 6, 1, 0, 2, DI_SYNC_CLK, h_total,
1200                                 DI_SYNC_INT_HSYNC, 0, DI_SYNC_NONE,
1201                                 DI_SYNC_NONE, 0, 0);
1202
1203                 /* Init template microcode */
1204                 if (disp) {
1205                         ipu_dc_write_tmpl(2, WROD(0), 0, map, SYNC_WAVE, 8, 5);
1206                         ipu_dc_write_tmpl(3, WROD(0), 0, map, SYNC_WAVE, 4, 5);
1207                         ipu_dc_write_tmpl(4, WROD(0), 0, map, SYNC_WAVE, 0, 5);
1208                 } else {
1209                         ipu_dc_write_tmpl(5, WROD(0), 0, map, SYNC_WAVE, 8, 5);
1210                         ipu_dc_write_tmpl(6, WROD(0), 0, map, SYNC_WAVE, 4, 5);
1211                         ipu_dc_write_tmpl(7, WROD(0), 0, map, SYNC_WAVE, 0, 5);
1212                 }
1213
1214                 if (sig.Hsync_pol)
1215                         di_gen |= DI_GEN_POLARITY_2;
1216                 if (sig.Vsync_pol)
1217                         di_gen |= DI_GEN_POLARITY_3;
1218
1219                 if (sig.clk_pol)
1220                         di_gen |= DI_GEN_POL_CLK;
1221
1222                 /* Set the clock to stop at counter 6. */
1223                 di_gen |= 0x6000000;
1224         }
1225
1226         __raw_writel(di_gen, DI_GENERAL(disp));
1227
1228         if (sig.interlaced)
1229                 __raw_writel((--vsync_cnt << DI_VSYNC_SEL_OFFSET) |
1230                                 0x00000002, DI_SYNC_AS_GEN(disp));
1231         else
1232                 __raw_writel((--vsync_cnt << DI_VSYNC_SEL_OFFSET),
1233                                 DI_SYNC_AS_GEN(disp));
1234
1235         reg = __raw_readl(DI_POL(disp));
1236         reg &= ~(DI_POL_DRDY_DATA_POLARITY | DI_POL_DRDY_POLARITY_15);
1237         if (sig.enable_pol)
1238                 reg |= DI_POL_DRDY_POLARITY_15;
1239         if (sig.data_pol)
1240                 reg |= DI_POL_DRDY_DATA_POLARITY;
1241         __raw_writel(reg, DI_POL(disp));
1242
1243         __raw_writel(width, DC_DISP_CONF2(DC_DISP_ID_SYNC(disp)));
1244
1245         return 0;
1246 }
1247
1248 /*
1249  * This function sets the foreground and background plane global alpha blending
1250  * modes. This function also sets the DP graphic plane according to the
1251  * parameter of IPUv3 DP channel.
1252  *
1253  * @param       channel         IPUv3 DP channel
1254  *
1255  * @param       enable          Boolean to enable or disable global alpha
1256  *                              blending. If disabled, local blending is used.
1257  *
1258  * @param       alpha           Global alpha value.
1259  *
1260  * @return      Returns 0 on success or negative error code on fail
1261  */
1262 int ipu_disp_set_global_alpha(ipu_channel_t channel, unsigned char enable,
1263                                   uint8_t alpha)
1264 {
1265         int ret;
1266         uint32_t reg;
1267
1268         unsigned char bg_chan;
1269
1270         if (!((channel == MEM_BG_SYNC || channel == MEM_FG_SYNC) ||
1271                 (channel == MEM_BG_ASYNC0 || channel == MEM_FG_ASYNC0) ||
1272                 (channel == MEM_BG_ASYNC1 || channel == MEM_FG_ASYNC1)))
1273                 return -EINVAL;
1274
1275         if (channel == MEM_BG_SYNC || channel == MEM_BG_ASYNC0 ||
1276             channel == MEM_BG_ASYNC1)
1277                 bg_chan = 1;
1278         else
1279                 bg_chan = 0;
1280
1281         ret = clk_enable(g_ipu_clk);
1282         if (ret)
1283                 return ret;
1284
1285         if (bg_chan) {
1286                 reg = __raw_readl(DP_COM_CONF());
1287                 __raw_writel(reg & ~DP_COM_CONF_GWSEL, DP_COM_CONF());
1288         } else {
1289                 reg = __raw_readl(DP_COM_CONF());
1290                 __raw_writel(reg | DP_COM_CONF_GWSEL, DP_COM_CONF());
1291         }
1292
1293         if (enable) {
1294                 reg = __raw_readl(DP_GRAPH_WIND_CTRL()) & 0x00FFFFFFL;
1295                 __raw_writel(reg | ((uint32_t) alpha << 24),
1296                              DP_GRAPH_WIND_CTRL());
1297
1298                 reg = __raw_readl(DP_COM_CONF());
1299                 __raw_writel(reg | DP_COM_CONF_GWAM, DP_COM_CONF());
1300         } else {
1301                 reg = __raw_readl(DP_COM_CONF());
1302                 __raw_writel(reg & ~DP_COM_CONF_GWAM, DP_COM_CONF());
1303         }
1304
1305         reg = __raw_readl(IPU_SRM_PRI2) | 0x8;
1306         __raw_writel(reg, IPU_SRM_PRI2);
1307
1308         clk_disable(g_ipu_clk);
1309
1310         return 0;
1311 }
1312
1313 /*
1314  * This function sets the transparent color key for SDC graphic plane.
1315  *
1316  * @param       channel         Input parameter for the logical channel ID.
1317  *
1318  * @param       enable          Boolean to enable or disable color key
1319  *
1320  * @param       colorKey        24-bit RGB color for transparent color key.
1321  *
1322  * @return      Returns 0 on success or negative error code on fail
1323  */
1324 int ipu_disp_set_color_key(ipu_channel_t channel, unsigned char enable,
1325                                uint32_t color_key)
1326 {
1327         int ret;
1328         uint32_t reg;
1329         int y, u, v;
1330         int red, green, blue;
1331
1332         if (!((channel == MEM_BG_SYNC || channel == MEM_FG_SYNC) ||
1333                 (channel == MEM_BG_ASYNC0 || channel == MEM_FG_ASYNC0) ||
1334                 (channel == MEM_BG_ASYNC1 || channel == MEM_FG_ASYNC1)))
1335                 return -EINVAL;
1336
1337         ret = clk_enable(g_ipu_clk);
1338         if (ret)
1339                 return ret;
1340
1341         color_key_4rgb = 1;
1342         /* Transform color key from rgb to yuv if CSC is enabled */
1343         if (((fg_csc_type == RGB2YUV) && (bg_csc_type == YUV2YUV)) ||
1344                 ((fg_csc_type == YUV2YUV) && (bg_csc_type == RGB2YUV)) ||
1345                 ((fg_csc_type == YUV2YUV) && (bg_csc_type == YUV2YUV)) ||
1346                 ((fg_csc_type == YUV2RGB) && (bg_csc_type == YUV2RGB))) {
1347
1348                 debug("color key 0x%x need change to yuv fmt\n", color_key);
1349
1350                 red = (color_key >> 16) & 0xFF;
1351                 green = (color_key >> 8) & 0xFF;
1352                 blue = color_key & 0xFF;
1353
1354                 y = rgb_to_yuv(0, red, green, blue);
1355                 u = rgb_to_yuv(1, red, green, blue);
1356                 v = rgb_to_yuv(2, red, green, blue);
1357                 color_key = (y << 16) | (u << 8) | v;
1358
1359                 color_key_4rgb = 0;
1360
1361                 debug("color key change to yuv fmt 0x%x\n", color_key);
1362         }
1363
1364         if (enable) {
1365                 reg = __raw_readl(DP_GRAPH_WIND_CTRL()) & 0xFF000000L;
1366                 __raw_writel(reg | color_key, DP_GRAPH_WIND_CTRL());
1367
1368                 reg = __raw_readl(DP_COM_CONF());
1369                 __raw_writel(reg | DP_COM_CONF_GWCKE, DP_COM_CONF());
1370         } else {
1371                 reg = __raw_readl(DP_COM_CONF());
1372                 __raw_writel(reg & ~DP_COM_CONF_GWCKE, DP_COM_CONF());
1373         }
1374
1375         reg = __raw_readl(IPU_SRM_PRI2) | 0x8;
1376         __raw_writel(reg, IPU_SRM_PRI2);
1377
1378         clk_disable(g_ipu_clk);
1379
1380         return 0;
1381 }