drivers/video/mmp/hw/mmp_ctrl.c

   1 /*
   2  * linux/drivers/video/mmp/hw/mmp_ctrl.c
   3  * Marvell MMP series Display Controller support
   4  *
   5  * Copyright (C) 2012 Marvell Technology Group Ltd.
   6  * Authors:  Guoqing Li <ligq@marvell.com>
   7  *          Lisa Du <cldu@marvell.com>
   8  *          Zhou Zhu <zzhu3@marvell.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License as published by the
  12  * Free Software Foundation; either version 2 of the License, or (at your
  13  * option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful, but WITHOUT
  16  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  17  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  18  * more details.
  19  *
  20  * You should have received a copy of the GNU General Public License along with
  21  * this program.  If not, see <http://www.gnu.org/licenses/>.
  22  *
  23  */
  24 #include <linux/module.h>
  25 #include <linux/moduleparam.h>
  26 #include <linux/kernel.h>
  27 #include <linux/errno.h>
  28 #include <linux/string.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/slab.h>
  31 #include <linux/delay.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/dma-mapping.h>
  34 #include <linux/clk.h>
  35 #include <linux/err.h>
  36 #include <linux/vmalloc.h>
  37 #include <linux/uaccess.h>
  38 #include <linux/kthread.h>
  39 #include <linux/io.h>
  40
  41 #include "mmp_ctrl.h"
  42
  43 static irqreturn_t ctrl_handle_irq(int irq, void *dev_id)
  44 {
  45         struct mmphw_ctrl *ctrl = (struct mmphw_ctrl *)dev_id;
  46         u32 isr, imask, tmp;
  47
  48         isr = readl_relaxed(ctrl->reg_base + SPU_IRQ_ISR);
  49         imask = readl_relaxed(ctrl->reg_base + SPU_IRQ_ENA);
  50
  51         do {
  52                 /* clear clock only */
  53                 tmp = readl_relaxed(ctrl->reg_base + SPU_IRQ_ISR);
  54                 if (tmp & isr)
  55                         writel_relaxed(~isr, ctrl->reg_base + SPU_IRQ_ISR);
  56         } while ((isr = readl_relaxed(ctrl->reg_base + SPU_IRQ_ISR)) & imask);
  57
  58         return IRQ_HANDLED;
  59 }
  60
  61 static u32 fmt_to_reg(struct mmp_overlay *overlay, int pix_fmt)
  62 {
  63         u32 rbswap = 0, uvswap = 0, yuvswap = 0,
  64                 csc_en = 0, val = 0,
  65                 vid = overlay_is_vid(overlay);
  66
  67         switch (pix_fmt) {
  68         case PIXFMT_RGB565:
  69         case PIXFMT_RGB1555:
  70         case PIXFMT_RGB888PACK:
  71         case PIXFMT_RGB888UNPACK:
  72         case PIXFMT_RGBA888:
  73                 rbswap = 1;
  74                 break;
  75         case PIXFMT_VYUY:
  76         case PIXFMT_YVU422P:
  77         case PIXFMT_YVU420P:
  78                 uvswap = 1;
  79                 break;
  80         case PIXFMT_YUYV:
  81                 yuvswap = 1;
  82                 break;
  83         default:
  84                 break;
  85         }
  86
  87         switch (pix_fmt) {
  88         case PIXFMT_RGB565:
  89         case PIXFMT_BGR565:
  90                 break;
  91         case PIXFMT_RGB1555:
  92         case PIXFMT_BGR1555:
  93                 val = 0x1;
  94                 break;
  95         case PIXFMT_RGB888PACK:
  96         case PIXFMT_BGR888PACK:
  97                 val = 0x2;
  98                 break;
  99         case PIXFMT_RGB888UNPACK:
 100         case PIXFMT_BGR888UNPACK:
 101                 val = 0x3;
 102                 break;
 103         case PIXFMT_RGBA888:
 104         case PIXFMT_BGRA888:
 105                 val = 0x4;
 106                 break;
 107         case PIXFMT_UYVY:
 108         case PIXFMT_VYUY:
 109         case PIXFMT_YUYV:
 110                 val = 0x5;
 111                 csc_en = 1;
 112                 break;
 113         case PIXFMT_YUV422P:
 114         case PIXFMT_YVU422P:
 115                 val = 0x6;
 116                 csc_en = 1;
 117                 break;
 118         case PIXFMT_YUV420P:
 119         case PIXFMT_YVU420P:
 120                 val = 0x7;
 121                 csc_en = 1;
 122                 break;
 123         default:
 124                 break;
 125         }
 126
 127         return (dma_palette(0) | dma_fmt(vid, val) |
 128                 dma_swaprb(vid, rbswap) | dma_swapuv(vid, uvswap) |
 129                 dma_swapyuv(vid, yuvswap) | dma_csc(vid, csc_en));
 130 }
 131
 132 static void dmafetch_set_fmt(struct mmp_overlay *overlay)
 133 {
 134         u32 tmp;
 135         struct mmp_path *path = overlay->path;
 136         tmp = readl_relaxed(ctrl_regs(path) + dma_ctrl(0, path->id));
 137         tmp &= ~dma_mask(overlay_is_vid(overlay));
 138         tmp |= fmt_to_reg(overlay, overlay->win.pix_fmt);
 139         writel_relaxed(tmp, ctrl_regs(path) + dma_ctrl(0, path->id));
 140 }
 141
 142 static void overlay_set_win(struct mmp_overlay *overlay, struct mmp_win *win)
 143 {
 144         struct lcd_regs *regs = path_regs(overlay->path);
 145         u32 pitch;
 146
 147         /* assert win supported */
 148         memcpy(&overlay->win, win, sizeof(struct mmp_win));
 149
 150         mutex_lock(&overlay->access_ok);
 151         pitch = win->xsrc * pixfmt_to_stride(win->pix_fmt);
 152         writel_relaxed(pitch, &regs->g_pitch);
 153         writel_relaxed((win->ysrc << 16) | win->xsrc, &regs->g_size);
 154         writel_relaxed((win->ydst << 16) | win->xdst, &regs->g_size_z);
 155         writel_relaxed(0, &regs->g_start);
 156
 157         dmafetch_set_fmt(overlay);
 158         mutex_unlock(&overlay->access_ok);
 159 }
 160
 161 static void dmafetch_onoff(struct mmp_overlay *overlay, int on)
 162 {
 163         u32 mask = overlay_is_vid(overlay) ? CFG_DMA_ENA_MASK :
 164                    CFG_GRA_ENA_MASK;
 165         u32 enable = overlay_is_vid(overlay) ? CFG_DMA_ENA(1) : CFG_GRA_ENA(1);
 166         u32 tmp;
 167         struct mmp_path *path = overlay->path;
 168
 169         mutex_lock(&overlay->access_ok);
 170         tmp = readl_relaxed(ctrl_regs(path) + dma_ctrl(0, path->id));
 171         tmp &= ~mask;
 172         tmp |= (on ? enable : 0);
 173         writel(tmp, ctrl_regs(path) + dma_ctrl(0, path->id));
 174         mutex_unlock(&overlay->access_ok);
 175 }
 176
 177 static void path_enabledisable(struct mmp_path *path, int on)
 178 {
 179         u32 tmp;
 180         mutex_lock(&path->access_ok);
 181         tmp = readl_relaxed(ctrl_regs(path) + LCD_SCLK(path));
 182         if (on)
 183                 tmp &= ~SCLK_DISABLE;
 184         else
 185                 tmp |= SCLK_DISABLE;
 186         writel_relaxed(tmp, ctrl_regs(path) + LCD_SCLK(path));
 187         mutex_unlock(&path->access_ok);
 188 }
 189
 190 static void path_onoff(struct mmp_path *path, int on)
 191 {
 192         if (path->status == on) {
 193                 dev_info(path->dev, "path %s is already %s\n",
 194                                 path->name, stat_name(path->status));
 195                 return;
 196         }
 197
 198         if (on) {
 199                 path_enabledisable(path, 1);
 200
 201                 if (path->panel && path->panel->set_onoff)
 202                         path->panel->set_onoff(path->panel, 1);
 203         } else {
 204                 if (path->panel && path->panel->set_onoff)
 205                         path->panel->set_onoff(path->panel, 0);
 206
 207                 path_enabledisable(path, 0);
 208         }
 209         path->status = on;
 210 }
 211
 212 static void overlay_set_onoff(struct mmp_overlay *overlay, int on)
 213 {
 214         if (overlay->status == on) {
 215                 dev_info(overlay_to_ctrl(overlay)->dev, "overlay %s is already %s\n",
 216                         overlay->path->name, stat_name(overlay->status));
 217                 return;
 218         }
 219         overlay->status = on;
 220         dmafetch_onoff(overlay, on);
 221         if (overlay->path->ops.check_status(overlay->path)
 222                         != overlay->path->status)
 223                 path_onoff(overlay->path, on);
 224 }
 225
 226 static void overlay_set_fetch(struct mmp_overlay *overlay, int fetch_id)
 227 {
 228         overlay->dmafetch_id = fetch_id;
 229 }
 230
 231 static int overlay_set_addr(struct mmp_overlay *overlay, struct mmp_addr *addr)
 232 {
 233         struct lcd_regs *regs = path_regs(overlay->path);
 234
 235         /* FIXME: assert addr supported */
 236         memcpy(&overlay->addr, addr, sizeof(struct mmp_addr));
 237         writel(addr->phys[0], &regs->g_0);
 238
 239         return overlay->addr.phys[0];
 240 }
 241
 242 static void path_set_mode(struct mmp_path *path, struct mmp_mode *mode)
 243 {
 244         struct lcd_regs *regs = path_regs(path);
 245         u32 total_x, total_y, vsync_ctrl, tmp, sclk_src, sclk_div,
 246                 link_config = path_to_path_plat(path)->link_config,
 247                 dsi_rbswap = path_to_path_plat(path)->link_config;
 248
 249         /* FIXME: assert videomode supported */
 250         memcpy(&path->mode, mode, sizeof(struct mmp_mode));
 251
 252         mutex_lock(&path->access_ok);
 253
 254         /* polarity of timing signals */
 255         tmp = readl_relaxed(ctrl_regs(path) + intf_ctrl(path->id)) & 0x1;
 256         tmp |= mode->vsync_invert ? 0 : 0x8;
 257         tmp |= mode->hsync_invert ? 0 : 0x4;
 258         tmp |= link_config & CFG_DUMBMODE_MASK;
 259         tmp |= CFG_DUMB_ENA(1);
 260         writel_relaxed(tmp, ctrl_regs(path) + intf_ctrl(path->id));
 261
 262         /* interface rb_swap setting */
 263         tmp = readl_relaxed(ctrl_regs(path) + intf_rbswap_ctrl(path->id)) &
 264                 (~(CFG_INTFRBSWAP_MASK));
 265         tmp |= dsi_rbswap & CFG_INTFRBSWAP_MASK;
 266         writel_relaxed(tmp, ctrl_regs(path) + intf_rbswap_ctrl(path->id));
 267
 268         writel_relaxed((mode->yres << 16) | mode->xres, &regs->screen_active);
 269         writel_relaxed((mode->left_margin << 16) | mode->right_margin,
 270                 &regs->screen_h_porch);
 271         writel_relaxed((mode->upper_margin << 16) | mode->lower_margin,
 272                 &regs->screen_v_porch);
 273         total_x = mode->xres + mode->left_margin + mode->right_margin +
 274                 mode->hsync_len;
 275         total_y = mode->yres + mode->upper_margin + mode->lower_margin +
 276                 mode->vsync_len;
 277         writel_relaxed((total_y << 16) | total_x, &regs->screen_size);
 278
 279         /* vsync ctrl */
 280         if (path->output_type == PATH_OUT_DSI)
 281                 vsync_ctrl = 0x01330133;
 282         else
 283                 vsync_ctrl = ((mode->xres + mode->right_margin) << 16)
 284                                         | (mode->xres + mode->right_margin);
 285         writel_relaxed(vsync_ctrl, &regs->vsync_ctrl);
 286
 287         /* set pixclock div */
 288         sclk_src = clk_get_rate(path_to_ctrl(path)->clk);
 289         sclk_div = sclk_src / mode->pixclock_freq;
 290         if (sclk_div * mode->pixclock_freq < sclk_src)
 291                 sclk_div++;
 292
 293         dev_info(path->dev, "%s sclk_src %d sclk_div 0x%x pclk %d\n",
 294                         __func__, sclk_src, sclk_div, mode->pixclock_freq);
 295
 296         tmp = readl_relaxed(ctrl_regs(path) + LCD_SCLK(path));
 297         tmp &= ~CLK_INT_DIV_MASK;
 298         tmp |= sclk_div;
 299         writel_relaxed(tmp, ctrl_regs(path) + LCD_SCLK(path));
 300
 301         mutex_unlock(&path->access_ok);
 302 }
 303
 304 static struct mmp_overlay_ops mmphw_overlay_ops = {
 305         .set_fetch = overlay_set_fetch,
 306         .set_onoff = overlay_set_onoff,
 307         .set_win = overlay_set_win,
 308         .set_addr = overlay_set_addr,
 309 };
 310
 311 static void ctrl_set_default(struct mmphw_ctrl *ctrl)
 312 {
 313         u32 tmp, irq_mask;
 314
 315         /*
 316          * LCD Global control(LCD_TOP_CTRL) should be configed before
 317          * any other LCD registers read/write, or there maybe issues.
 318          */
 319         tmp = readl_relaxed(ctrl->reg_base + LCD_TOP_CTRL);
 320         tmp |= 0xfff0;
 321         writel_relaxed(tmp, ctrl->reg_base + LCD_TOP_CTRL);
 322
 323
 324         /* disable all interrupts */
 325         irq_mask = path_imasks(0) | err_imask(0) |
 326                    path_imasks(1) | err_imask(1);
 327         tmp = readl_relaxed(ctrl->reg_base + SPU_IRQ_ENA);
 328         tmp &= ~irq_mask;
 329         tmp |= irq_mask;
 330         writel_relaxed(tmp, ctrl->reg_base + SPU_IRQ_ENA);
 331 }
 332
 333 static void path_set_default(struct mmp_path *path)
 334 {
 335         struct lcd_regs *regs = path_regs(path);
 336         u32 dma_ctrl1, mask, tmp, path_config;
 337
 338         path_config = path_to_path_plat(path)->path_config;
 339
 340         /* Configure IOPAD: should be parallel only */
 341         if (PATH_OUT_PARALLEL == path->output_type) {
 342                 mask = CFG_IOPADMODE_MASK | CFG_BURST_MASK | CFG_BOUNDARY_MASK;
 343                 tmp = readl_relaxed(ctrl_regs(path) + SPU_IOPAD_CONTROL);
 344                 tmp &= ~mask;
 345                 tmp |= path_config;
 346                 writel_relaxed(tmp, ctrl_regs(path) + SPU_IOPAD_CONTROL);
 347         }
 348
 349         /* Select path clock source */
 350         tmp = readl_relaxed(ctrl_regs(path) + LCD_SCLK(path));
 351         tmp &= ~SCLK_SRC_SEL_MASK;
 352         tmp |= path_config;
 353         writel_relaxed(tmp, ctrl_regs(path) + LCD_SCLK(path));
 354
 355         /*
 356          * Configure default bits: vsync triggers DMA,
 357          * power save enable, configure alpha registers to
 358          * display 100% graphics, and set pixel command.
 359          */
 360         dma_ctrl1 = 0x2032ff81;
 361
 362         dma_ctrl1 |= CFG_VSYNC_INV_MASK;
 363         writel_relaxed(dma_ctrl1, ctrl_regs(path) + dma_ctrl(1, path->id));
 364
 365         /* Configure default register values */
 366         writel_relaxed(0x00000000, &regs->blank_color);
 367         writel_relaxed(0x00000000, &regs->g_1);
 368         writel_relaxed(0x00000000, &regs->g_start);
 369
 370         /*
 371          * 1.enable multiple burst request in DMA AXI
 372          * bus arbiter for faster read if not tv path;
 373          * 2.enable horizontal smooth filter;
 374          */
 375         mask = CFG_GRA_HSMOOTH_MASK | CFG_DMA_HSMOOTH_MASK | CFG_ARBFAST_ENA(1);
 376         tmp = readl_relaxed(ctrl_regs(path) + dma_ctrl(0, path->id));
 377         tmp |= mask;
 378         if (PATH_TV == path->id)
 379                 tmp &= ~CFG_ARBFAST_ENA(1);
 380         writel_relaxed(tmp, ctrl_regs(path) + dma_ctrl(0, path->id));
 381 }
 382
 383 static int path_init(struct mmphw_path_plat *path_plat,
 384                 struct mmp_mach_path_config *config)
 385 {
 386         struct mmphw_ctrl *ctrl = path_plat->ctrl;
 387         struct mmp_path_info *path_info;
 388         struct mmp_path *path = NULL;
 389
 390         dev_info(ctrl->dev, "%s: %s\n", __func__, config->name);
 391
 392         /* init driver data */
 393         path_info = kzalloc(sizeof(struct mmp_path_info), GFP_KERNEL);
 394         if (!path_info) {
 395                 dev_err(ctrl->dev, "%s: unable to alloc path_info for %s\n",
 396                                 __func__, config->name);
 397                 return 0;
 398         }
 399         path_info->name = config->name;
 400         path_info->id = path_plat->id;
 401         path_info->dev = ctrl->dev;
 402         path_info->overlay_num = config->overlay_num;
 403         path_info->overlay_ops = &mmphw_overlay_ops;
 404         path_info->set_mode = path_set_mode;
 405         path_info->plat_data = path_plat;
 406
 407         /* create/register platform device */
 408         path = mmp_register_path(path_info);
 409         if (!path) {
 410                 kfree(path_info);
 411                 return 0;
 412         }
 413         path_plat->path = path;
 414         path_plat->path_config = config->path_config;
 415         path_plat->link_config = config->link_config;
 416         path_plat->dsi_rbswap = config->dsi_rbswap;
 417         path_set_default(path);
 418
 419         kfree(path_info);
 420         return 1;
 421 }
 422
 423 static void path_deinit(struct mmphw_path_plat *path_plat)
 424 {
 425         if (!path_plat)
 426                 return;
 427
 428         if (path_plat->path)
 429                 mmp_unregister_path(path_plat->path);
 430 }
 431
 432 static int mmphw_probe(struct platform_device *pdev)
 433 {
 434         struct mmp_mach_plat_info *mi;
 435         struct resource *res;
 436         int ret, i, size, irq;
 437         struct mmphw_path_plat *path_plat;
 438         struct mmphw_ctrl *ctrl = NULL;
 439
 440         /* get resources from platform data */
 441         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 442         if (res == NULL) {
 443                 dev_err(&pdev->dev, "%s: no IO memory defined\n", __func__);
 444                 ret = -ENOENT;
 445                 goto failed;
 446         }
 447
 448         irq = platform_get_irq(pdev, 0);
 449         if (irq < 0) {
 450                 dev_err(&pdev->dev, "%s: no IRQ defined\n", __func__);
 451                 ret = -ENOENT;
 452                 goto failed;
 453         }
 454
 455         /* get configs from platform data */
 456         mi = pdev->dev.platform_data;
 457         if (mi == NULL || !mi->path_num || !mi->paths) {
 458                 dev_err(&pdev->dev, "%s: no platform data defined\n", __func__);
 459                 ret = -EINVAL;
 460                 goto failed;
 461         }
 462
 463         /* allocate */
 464         size = sizeof(struct mmphw_ctrl) + sizeof(struct mmphw_path_plat) *
 465                mi->path_num;
 466         ctrl = devm_kzalloc(&pdev->dev, size, GFP_KERNEL);
 467         if (!ctrl) {
 468                 ret = -ENOMEM;
 469                 goto failed;
 470         }
 471
 472         ctrl->name = mi->name;
 473         ctrl->path_num = mi->path_num;
 474         ctrl->dev = &pdev->dev;
 475         ctrl->irq = irq;
 476         platform_set_drvdata(pdev, ctrl);
 477         mutex_init(&ctrl->access_ok);
 478
 479         /* map registers.*/
 480         if (!devm_request_mem_region(ctrl->dev, res->start,
 481                         resource_size(res), ctrl->name)) {
 482                 dev_err(ctrl->dev,
 483                         "can't request region for resource %pR\n", res);
 484                 ret = -EINVAL;
 485                 goto failed;
 486         }
 487
 488         ctrl->reg_base = devm_ioremap_nocache(ctrl->dev,
 489                         res->start, resource_size(res));
 490         if (ctrl->reg_base == NULL) {
 491                 dev_err(ctrl->dev, "%s: res %x - %x map failed\n", __func__,
 492                         res->start, res->end);
 493                 ret = -ENOMEM;
 494                 goto failed;
 495         }
 496
 497         /* request irq */
 498         ret = devm_request_irq(ctrl->dev, ctrl->irq, ctrl_handle_irq,
 499                 IRQF_SHARED, "lcd_controller", ctrl);
 500         if (ret < 0) {
 501                 dev_err(ctrl->dev, "%s unable to request IRQ %d\n",
 502                                 __func__, ctrl->irq);
 503                 ret = -ENXIO;
 504                 goto failed;
 505         }
 506
 507         /* get clock */
 508         ctrl->clk = devm_clk_get(ctrl->dev, mi->clk_name);
 509         if (IS_ERR(ctrl->clk)) {
 510                 dev_err(ctrl->dev, "unable to get clk %s\n", mi->clk_name);
 511                 ret = -ENOENT;
 512                 goto failed_get_clk;
 513         }
 514         clk_prepare_enable(ctrl->clk);
 515
 516         /* init global regs */
 517         ctrl_set_default(ctrl);
 518
 519         /* init pathes from machine info and register them */
 520         for (i = 0; i < ctrl->path_num; i++) {
 521                 /* get from config and machine info */
 522                 path_plat = &ctrl->path_plats[i];
 523                 path_plat->id = i;
 524                 path_plat->ctrl = ctrl;
 525
 526                 /* path init */
 527                 if (!path_init(path_plat, &mi->paths[i])) {
 528                         ret = -EINVAL;
 529                         goto failed_path_init;
 530                 }
 531         }
 532
 533 #ifdef CONFIG_MMP_DISP_SPI
 534         ret = lcd_spi_register(ctrl);
 535         if (ret < 0)
 536                 goto failed_path_init;
 537 #endif
 538
 539         dev_info(ctrl->dev, "device init done\n");
 540
 541         return 0;
 542
 543 failed_path_init:
 544         for (i = 0; i < ctrl->path_num; i++) {
 545                 path_plat = &ctrl->path_plats[i];
 546                 path_deinit(path_plat);
 547         }
 548
 549         if (ctrl->clk) {
 550                 devm_clk_put(ctrl->dev, ctrl->clk);
 551                 clk_disable_unprepare(ctrl->clk);
 552         }
 553 failed_get_clk:
 554         devm_free_irq(ctrl->dev, ctrl->irq, ctrl);
 555 failed:
 556         if (ctrl) {
 557                 if (ctrl->reg_base)
 558                         devm_iounmap(ctrl->dev, ctrl->reg_base);
 559                 devm_release_mem_region(ctrl->dev, res->start,
 560                                 resource_size(res));
 561                 devm_kfree(ctrl->dev, ctrl);
 562         }
 563
 564         dev_err(&pdev->dev, "device init failed\n");
 565
 566         return ret;
 567 }
 568
 569 static struct platform_driver mmphw_driver = {
 570         .driver         = {
 571                 .name   = "mmp-disp",
 572                 .owner  = THIS_MODULE,
 573         },
 574         .probe          = mmphw_probe,
 575 };
 576
 577 static int mmphw_init(void)
 578 {
 579         return platform_driver_register(&mmphw_driver);
 580 }
 581 module_init(mmphw_init);
 582
 583 MODULE_AUTHOR("Li Guoqing<ligq@marvell.com>");
 584 MODULE_DESCRIPTION("Framebuffer driver for mmp");
 585 MODULE_LICENSE("GPL");