2 * Copyright (C) 2011-2014 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 * SH-Mobile High-Definition Multimedia Interface (HDMI) driver
21 * for SLISHDMI13T and SLIPHDMIT IP cores
23 * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
25 * This program is free software; you can redistribute it and/or modify
26 * it under the terms of the GNU General Public License version 2 as
27 * published by the Free Software Foundation.
29 #include <linux/module.h>
30 #include <linux/kernel.h>
31 #include <linux/device.h>
32 #include <linux/platform_device.h>
33 #include <linux/input.h>
34 #include <linux/interrupt.h>
35 #include <linux/irq.h>
38 #include <linux/init.h>
39 #include <linux/list.h>
40 #include <linux/delay.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/err.h>
43 #include <linux/clk.h>
44 #include <linux/uaccess.h>
45 #include <linux/cpufreq.h>
46 #include <linux/firmware.h>
47 #include <linux/kthread.h>
48 #include <linux/regulator/driver.h>
49 #include <linux/fsl_devices.h>
50 #include <linux/ipu.h>
51 #include <linux/regmap.h>
52 #include <linux/pinctrl/consumer.h>
53 #include <linux/of_device.h>
55 #include <linux/console.h>
56 #include <linux/types.h>
59 #include <video/mxc_edid.h>
60 #include <video/mxc_hdmi.h>
61 #include "mxc_dispdrv.h"
63 #include <linux/mfd/mxc-hdmi-core.h>
65 #define DISPDRV_HDMI "hdmi"
66 #define HDMI_EDID_LEN 512
68 /* status codes for reading edid */
69 #define HDMI_EDID_SUCCESS 0
70 #define HDMI_EDID_FAIL -1
71 #define HDMI_EDID_SAME -2
72 #define HDMI_EDID_NO_MODES -3
74 #define NUM_CEA_VIDEO_MODES 64
75 #define DEFAULT_VIDEO_MODE 16 /* 1080P */
79 #define YCBCR422_16BITS 2
80 #define YCBCR422_8BITS 3
84 * We follow a flowchart which is in the "Synopsys DesignWare Courses
85 * HDMI Transmitter Controller User Guide, 1.30a", section 3.1
86 * (dwc_hdmi_tx_user.pdf)
88 * Below are notes that say "HDMI Initialization Step X"
89 * These correspond to the flowchart.
93 * We are required to configure VGA mode before reading edid
94 * in HDMI Initialization Step B
96 static const struct fb_videomode vga_mode = {
97 /* 640x480 @ 60 Hz, 31.5 kHz hsync */
98 NULL, 60, 640, 480, 39721, 48, 16, 33, 10, 96, 2, 0,
99 FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_4_3, FB_MODE_IS_VESA,
116 enum hdmi_colorimetry {
126 bool mDataEnablePolarity;
128 unsigned int mPixelClock;
129 unsigned int mPixelRepetitionInput;
130 unsigned int mPixelRepetitionOutput;
133 struct hdmi_data_info {
134 unsigned int enc_in_format;
135 unsigned int enc_out_format;
136 unsigned int enc_color_depth;
137 unsigned int colorimetry;
138 unsigned int pix_repet_factor;
139 unsigned int hdcp_enable;
140 unsigned int rgb_out_enable;
141 struct hdmi_vmode video_mode;
144 struct hdmi_phy_reg_config {
145 /* HDMI PHY register config for pass HCT */
151 struct platform_device *pdev;
152 struct platform_device *core_pdev;
153 struct mxc_dispdrv_handle *disp_mxc_hdmi;
155 struct clk *hdmi_isfr_clk;
156 struct clk *hdmi_iahb_clk;
157 struct delayed_work hotplug_work;
158 struct delayed_work hdcp_hdp_work;
160 struct notifier_block nb;
162 struct hdmi_data_info hdmi_data;
164 struct mxc_edid_cfg edid_cfg;
165 u8 edid[HDMI_EDID_LEN];
176 struct fb_videomode default_mode;
177 struct fb_videomode previous_non_vga_mode;
178 bool requesting_vga_for_initialization;
185 struct hdmi_phy_reg_config phy_config;
187 struct pinctrl *pinctrl;
190 static int hdmi_major;
191 static struct class *hdmi_class;
193 struct i2c_client *hdmi_i2c;
194 struct mxc_hdmi *g_hdmi;
196 static bool hdmi_inited;
197 static bool hdcp_init;
199 extern const struct fb_videomode mxc_cea_mode[64];
200 extern void mxc_hdmi_cec_handle(u16 cec_stat);
202 static void mxc_hdmi_setup(struct mxc_hdmi *hdmi, unsigned long event);
203 static void hdmi_enable_overflow_interrupts(void);
204 static void hdmi_disable_overflow_interrupts(void);
206 static struct platform_device_id imx_hdmi_devtype[] = {
208 .name = "hdmi-imx6DL",
209 .driver_data = IMX6DL_HDMI,
211 .name = "hdmi-imx6Q",
212 .driver_data = IMX6Q_HDMI,
217 MODULE_DEVICE_TABLE(platform, imx_hdmi_devtype);
219 static const struct of_device_id imx_hdmi_dt_ids[] = {
220 { .compatible = "fsl,imx6dl-hdmi-video", .data = &imx_hdmi_devtype[IMX6DL_HDMI], },
221 { .compatible = "fsl,imx6q-hdmi-video", .data = &imx_hdmi_devtype[IMX6Q_HDMI], },
224 MODULE_DEVICE_TABLE(of, imx_hdmi_dt_ids);
226 static inline int cpu_is_imx6dl(struct mxc_hdmi *hdmi)
228 return hdmi->cpu_type == IMX6DL_HDMI;
231 static void dump_fb_videomode(struct fb_videomode *m)
233 pr_debug("fb_videomode = %d %d %d %d %d %d %d %d %d %d %d %d %d\n",
234 m->refresh, m->xres, m->yres, m->pixclock, m->left_margin,
235 m->right_margin, m->upper_margin, m->lower_margin,
236 m->hsync_len, m->vsync_len, m->sync, m->vmode, m->flag);
239 static void dump_fb_videomode(struct fb_videomode *m)
243 static ssize_t mxc_hdmi_show_name(struct device *dev,
244 struct device_attribute *attr, char *buf)
246 struct mxc_hdmi *hdmi = dev_get_drvdata(dev);
248 strcpy(buf, hdmi->fbi->fix.id);
249 sprintf(buf+strlen(buf), "\n");
254 static DEVICE_ATTR(fb_name, S_IRUGO, mxc_hdmi_show_name, NULL);
256 static ssize_t mxc_hdmi_show_state(struct device *dev,
257 struct device_attribute *attr, char *buf)
259 struct mxc_hdmi *hdmi = dev_get_drvdata(dev);
261 if (hdmi->cable_plugin == false)
262 strcpy(buf, "plugout\n");
264 strcpy(buf, "plugin\n");
269 static DEVICE_ATTR(cable_state, S_IRUGO, mxc_hdmi_show_state, NULL);
271 static ssize_t mxc_hdmi_show_edid(struct device *dev,
272 struct device_attribute *attr, char *buf)
274 struct mxc_hdmi *hdmi = dev_get_drvdata(dev);
277 for (j = 0; j < HDMI_EDID_LEN/16; j++) {
278 for (i = 0; i < 16; i++)
279 len += sprintf(buf+len, "0x%02X ",
280 hdmi->edid[j*16 + i]);
281 len += sprintf(buf+len, "\n");
287 static DEVICE_ATTR(edid, S_IRUGO, mxc_hdmi_show_edid, NULL);
289 static ssize_t mxc_hdmi_show_rgb_out_enable(struct device *dev,
290 struct device_attribute *attr, char *buf)
292 struct mxc_hdmi *hdmi = dev_get_drvdata(dev);
294 if (hdmi->hdmi_data.rgb_out_enable == true)
295 strcpy(buf, "RGB out\n");
297 strcpy(buf, "YCbCr out\n");
302 static ssize_t mxc_hdmi_store_rgb_out_enable(struct device *dev,
303 struct device_attribute *attr, const char *buf, size_t count)
305 struct mxc_hdmi *hdmi = dev_get_drvdata(dev);
309 ret = strict_strtoul(buf, 10, &value);
313 hdmi->hdmi_data.rgb_out_enable = value;
315 /* Reconfig HDMI for output color space change */
316 mxc_hdmi_setup(hdmi, 0);
321 static DEVICE_ATTR(rgb_out_enable, S_IRUGO | S_IWUSR,
322 mxc_hdmi_show_rgb_out_enable,
323 mxc_hdmi_store_rgb_out_enable);
325 static ssize_t mxc_hdmi_show_hdcp_enable(struct device *dev,
326 struct device_attribute *attr, char *buf)
328 struct mxc_hdmi *hdmi = dev_get_drvdata(dev);
330 if (hdmi->hdmi_data.hdcp_enable == false)
331 strcpy(buf, "hdcp disable\n");
333 strcpy(buf, "hdcp enable\n");
339 static ssize_t mxc_hdmi_store_hdcp_enable(struct device *dev,
340 struct device_attribute *attr, const char *buf, size_t count)
342 struct mxc_hdmi *hdmi = dev_get_drvdata(dev);
343 char event_string[32];
344 char *envp[] = { event_string, NULL };
348 ret = strict_strtoul(buf, 10, &value);
352 hdmi->hdmi_data.hdcp_enable = value;
354 /* Reconfig HDMI for HDCP */
355 mxc_hdmi_setup(hdmi, 0);
357 if (hdmi->hdmi_data.hdcp_enable == false) {
358 sprintf(event_string, "EVENT=hdcpdisable");
359 kobject_uevent_env(&hdmi->pdev->dev.kobj, KOBJ_CHANGE, envp);
361 sprintf(event_string, "EVENT=hdcpenable");
362 kobject_uevent_env(&hdmi->pdev->dev.kobj, KOBJ_CHANGE, envp);
369 static DEVICE_ATTR(hdcp_enable, S_IRUGO | S_IWUSR,
370 mxc_hdmi_show_hdcp_enable, mxc_hdmi_store_hdcp_enable);
373 * this submodule is responsible for the video data synchronization.
374 * for example, for RGB 4:4:4 input, the data map is defined as
375 * pin{47~40} <==> R[7:0]
376 * pin{31~24} <==> G[7:0]
377 * pin{15~8} <==> B[7:0]
379 static void hdmi_video_sample(struct mxc_hdmi *hdmi)
381 int color_format = 0;
384 if (hdmi->hdmi_data.enc_in_format == RGB) {
385 if (hdmi->hdmi_data.enc_color_depth == 8)
387 else if (hdmi->hdmi_data.enc_color_depth == 10)
389 else if (hdmi->hdmi_data.enc_color_depth == 12)
391 else if (hdmi->hdmi_data.enc_color_depth == 16)
395 } else if (hdmi->hdmi_data.enc_in_format == YCBCR444) {
396 if (hdmi->hdmi_data.enc_color_depth == 8)
398 else if (hdmi->hdmi_data.enc_color_depth == 10)
400 else if (hdmi->hdmi_data.enc_color_depth == 12)
402 else if (hdmi->hdmi_data.enc_color_depth == 16)
406 } else if (hdmi->hdmi_data.enc_in_format == YCBCR422_8BITS) {
407 if (hdmi->hdmi_data.enc_color_depth == 8)
409 else if (hdmi->hdmi_data.enc_color_depth == 10)
411 else if (hdmi->hdmi_data.enc_color_depth == 12)
417 val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
418 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
419 HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
420 hdmi_writeb(val, HDMI_TX_INVID0);
422 /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
423 val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
424 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
425 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
426 hdmi_writeb(val, HDMI_TX_INSTUFFING);
427 hdmi_writeb(0x0, HDMI_TX_GYDATA0);
428 hdmi_writeb(0x0, HDMI_TX_GYDATA1);
429 hdmi_writeb(0x0, HDMI_TX_RCRDATA0);
430 hdmi_writeb(0x0, HDMI_TX_RCRDATA1);
431 hdmi_writeb(0x0, HDMI_TX_BCBDATA0);
432 hdmi_writeb(0x0, HDMI_TX_BCBDATA1);
435 static int isColorSpaceConversion(struct mxc_hdmi *hdmi)
437 return (hdmi->hdmi_data.enc_in_format !=
438 hdmi->hdmi_data.enc_out_format);
441 static int isColorSpaceDecimation(struct mxc_hdmi *hdmi)
443 return ((hdmi->hdmi_data.enc_out_format == YCBCR422_8BITS) &&
444 (hdmi->hdmi_data.enc_in_format == RGB ||
445 hdmi->hdmi_data.enc_in_format == YCBCR444));
448 static int isColorSpaceInterpolation(struct mxc_hdmi *hdmi)
450 return ((hdmi->hdmi_data.enc_in_format == YCBCR422_8BITS) &&
451 (hdmi->hdmi_data.enc_out_format == RGB
452 || hdmi->hdmi_data.enc_out_format == YCBCR444));
456 * update the color space conversion coefficients.
458 static void update_csc_coeffs(struct mxc_hdmi *hdmi)
460 unsigned short csc_coeff[3][4];
461 unsigned int csc_scale = 1;
463 bool coeff_selected = false;
465 if (isColorSpaceConversion(hdmi)) { /* csc needed */
466 if (hdmi->hdmi_data.enc_out_format == RGB) {
467 if (hdmi->hdmi_data.colorimetry == eITU601) {
468 csc_coeff[0][0] = 0x2000;
469 csc_coeff[0][1] = 0x6926;
470 csc_coeff[0][2] = 0x74fd;
471 csc_coeff[0][3] = 0x010e;
473 csc_coeff[1][0] = 0x2000;
474 csc_coeff[1][1] = 0x2cdd;
475 csc_coeff[1][2] = 0x0000;
476 csc_coeff[1][3] = 0x7e9a;
478 csc_coeff[2][0] = 0x2000;
479 csc_coeff[2][1] = 0x0000;
480 csc_coeff[2][2] = 0x38b4;
481 csc_coeff[2][3] = 0x7e3b;
484 coeff_selected = true;
485 } else if (hdmi->hdmi_data.colorimetry == eITU709) {
486 csc_coeff[0][0] = 0x2000;
487 csc_coeff[0][1] = 0x7106;
488 csc_coeff[0][2] = 0x7a02;
489 csc_coeff[0][3] = 0x00a7;
491 csc_coeff[1][0] = 0x2000;
492 csc_coeff[1][1] = 0x3264;
493 csc_coeff[1][2] = 0x0000;
494 csc_coeff[1][3] = 0x7e6d;
496 csc_coeff[2][0] = 0x2000;
497 csc_coeff[2][1] = 0x0000;
498 csc_coeff[2][2] = 0x3b61;
499 csc_coeff[2][3] = 0x7e25;
502 coeff_selected = true;
504 } else if (hdmi->hdmi_data.enc_in_format == RGB) {
505 if (hdmi->hdmi_data.colorimetry == eITU601) {
506 csc_coeff[0][0] = 0x2591;
507 csc_coeff[0][1] = 0x1322;
508 csc_coeff[0][2] = 0x074b;
509 csc_coeff[0][3] = 0x0000;
511 csc_coeff[1][0] = 0x6535;
512 csc_coeff[1][1] = 0x2000;
513 csc_coeff[1][2] = 0x7acc;
514 csc_coeff[1][3] = 0x0200;
516 csc_coeff[2][0] = 0x6acd;
517 csc_coeff[2][1] = 0x7534;
518 csc_coeff[2][2] = 0x2000;
519 csc_coeff[2][3] = 0x0200;
522 coeff_selected = true;
523 } else if (hdmi->hdmi_data.colorimetry == eITU709) {
524 csc_coeff[0][0] = 0x2dc5;
525 csc_coeff[0][1] = 0x0d9b;
526 csc_coeff[0][2] = 0x049e;
527 csc_coeff[0][3] = 0x0000;
529 csc_coeff[1][0] = 0x62f0;
530 csc_coeff[1][1] = 0x2000;
531 csc_coeff[1][2] = 0x7d11;
532 csc_coeff[1][3] = 0x0200;
534 csc_coeff[2][0] = 0x6756;
535 csc_coeff[2][1] = 0x78ab;
536 csc_coeff[2][2] = 0x2000;
537 csc_coeff[2][3] = 0x0200;
540 coeff_selected = true;
545 if (!coeff_selected) {
546 csc_coeff[0][0] = 0x2000;
547 csc_coeff[0][1] = 0x0000;
548 csc_coeff[0][2] = 0x0000;
549 csc_coeff[0][3] = 0x0000;
551 csc_coeff[1][0] = 0x0000;
552 csc_coeff[1][1] = 0x2000;
553 csc_coeff[1][2] = 0x0000;
554 csc_coeff[1][3] = 0x0000;
556 csc_coeff[2][0] = 0x0000;
557 csc_coeff[2][1] = 0x0000;
558 csc_coeff[2][2] = 0x2000;
559 csc_coeff[2][3] = 0x0000;
564 /* Update CSC parameters in HDMI CSC registers */
565 hdmi_writeb((unsigned char)(csc_coeff[0][0] & 0xFF),
566 HDMI_CSC_COEF_A1_LSB);
567 hdmi_writeb((unsigned char)(csc_coeff[0][0] >> 8),
568 HDMI_CSC_COEF_A1_MSB);
569 hdmi_writeb((unsigned char)(csc_coeff[0][1] & 0xFF),
570 HDMI_CSC_COEF_A2_LSB);
571 hdmi_writeb((unsigned char)(csc_coeff[0][1] >> 8),
572 HDMI_CSC_COEF_A2_MSB);
573 hdmi_writeb((unsigned char)(csc_coeff[0][2] & 0xFF),
574 HDMI_CSC_COEF_A3_LSB);
575 hdmi_writeb((unsigned char)(csc_coeff[0][2] >> 8),
576 HDMI_CSC_COEF_A3_MSB);
577 hdmi_writeb((unsigned char)(csc_coeff[0][3] & 0xFF),
578 HDMI_CSC_COEF_A4_LSB);
579 hdmi_writeb((unsigned char)(csc_coeff[0][3] >> 8),
580 HDMI_CSC_COEF_A4_MSB);
582 hdmi_writeb((unsigned char)(csc_coeff[1][0] & 0xFF),
583 HDMI_CSC_COEF_B1_LSB);
584 hdmi_writeb((unsigned char)(csc_coeff[1][0] >> 8),
585 HDMI_CSC_COEF_B1_MSB);
586 hdmi_writeb((unsigned char)(csc_coeff[1][1] & 0xFF),
587 HDMI_CSC_COEF_B2_LSB);
588 hdmi_writeb((unsigned char)(csc_coeff[1][1] >> 8),
589 HDMI_CSC_COEF_B2_MSB);
590 hdmi_writeb((unsigned char)(csc_coeff[1][2] & 0xFF),
591 HDMI_CSC_COEF_B3_LSB);
592 hdmi_writeb((unsigned char)(csc_coeff[1][2] >> 8),
593 HDMI_CSC_COEF_B3_MSB);
594 hdmi_writeb((unsigned char)(csc_coeff[1][3] & 0xFF),
595 HDMI_CSC_COEF_B4_LSB);
596 hdmi_writeb((unsigned char)(csc_coeff[1][3] >> 8),
597 HDMI_CSC_COEF_B4_MSB);
599 hdmi_writeb((unsigned char)(csc_coeff[2][0] & 0xFF),
600 HDMI_CSC_COEF_C1_LSB);
601 hdmi_writeb((unsigned char)(csc_coeff[2][0] >> 8),
602 HDMI_CSC_COEF_C1_MSB);
603 hdmi_writeb((unsigned char)(csc_coeff[2][1] & 0xFF),
604 HDMI_CSC_COEF_C2_LSB);
605 hdmi_writeb((unsigned char)(csc_coeff[2][1] >> 8),
606 HDMI_CSC_COEF_C2_MSB);
607 hdmi_writeb((unsigned char)(csc_coeff[2][2] & 0xFF),
608 HDMI_CSC_COEF_C3_LSB);
609 hdmi_writeb((unsigned char)(csc_coeff[2][2] >> 8),
610 HDMI_CSC_COEF_C3_MSB);
611 hdmi_writeb((unsigned char)(csc_coeff[2][3] & 0xFF),
612 HDMI_CSC_COEF_C4_LSB);
613 hdmi_writeb((unsigned char)(csc_coeff[2][3] >> 8),
614 HDMI_CSC_COEF_C4_MSB);
616 val = hdmi_readb(HDMI_CSC_SCALE);
617 val &= ~HDMI_CSC_SCALE_CSCSCALE_MASK;
618 val |= csc_scale & HDMI_CSC_SCALE_CSCSCALE_MASK;
619 hdmi_writeb(val, HDMI_CSC_SCALE);
622 static void hdmi_video_csc(struct mxc_hdmi *hdmi)
625 int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
629 /* YCC422 interpolation to 444 mode */
630 if (isColorSpaceInterpolation(hdmi))
631 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
632 else if (isColorSpaceDecimation(hdmi))
633 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;
635 if (hdmi->hdmi_data.enc_color_depth == 8)
636 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
637 else if (hdmi->hdmi_data.enc_color_depth == 10)
638 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
639 else if (hdmi->hdmi_data.enc_color_depth == 12)
640 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
641 else if (hdmi->hdmi_data.enc_color_depth == 16)
642 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
646 /*configure the CSC registers */
647 hdmi_writeb(interpolation | decimation, HDMI_CSC_CFG);
648 val = hdmi_readb(HDMI_CSC_SCALE);
649 val &= ~HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK;
651 hdmi_writeb(val, HDMI_CSC_SCALE);
653 update_csc_coeffs(hdmi);
657 * HDMI video packetizer is used to packetize the data.
658 * for example, if input is YCC422 mode or repeater is used,
659 * data should be repacked this module can be bypassed.
661 static void hdmi_video_packetize(struct mxc_hdmi *hdmi)
663 unsigned int color_depth = 0;
664 unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;
665 unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
666 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
669 if (hdmi_data->enc_out_format == RGB
670 || hdmi_data->enc_out_format == YCBCR444) {
671 if (hdmi_data->enc_color_depth == 0)
672 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
673 else if (hdmi_data->enc_color_depth == 8) {
675 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
676 } else if (hdmi_data->enc_color_depth == 10)
678 else if (hdmi_data->enc_color_depth == 12)
680 else if (hdmi_data->enc_color_depth == 16)
684 } else if (hdmi_data->enc_out_format == YCBCR422_8BITS) {
685 if (hdmi_data->enc_color_depth == 0 ||
686 hdmi_data->enc_color_depth == 8)
687 remap_size = HDMI_VP_REMAP_YCC422_16bit;
688 else if (hdmi_data->enc_color_depth == 10)
689 remap_size = HDMI_VP_REMAP_YCC422_20bit;
690 else if (hdmi_data->enc_color_depth == 12)
691 remap_size = HDMI_VP_REMAP_YCC422_24bit;
694 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;
698 /* HDMI not support deep color,
699 * because IPU MAX support color depth is 24bit */
702 /* set the packetizer registers */
703 val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
704 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
705 ((hdmi_data->pix_repet_factor <<
706 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
707 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
708 hdmi_writeb(val, HDMI_VP_PR_CD);
710 val = hdmi_readb(HDMI_VP_STUFF);
711 val &= ~HDMI_VP_STUFF_PR_STUFFING_MASK;
712 val |= HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE;
713 hdmi_writeb(val, HDMI_VP_STUFF);
715 /* Data from pixel repeater block */
716 if (hdmi_data->pix_repet_factor > 1) {
717 val = hdmi_readb(HDMI_VP_CONF);
718 val &= ~(HDMI_VP_CONF_PR_EN_MASK |
719 HDMI_VP_CONF_BYPASS_SELECT_MASK);
720 val |= HDMI_VP_CONF_PR_EN_ENABLE |
721 HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;
722 hdmi_writeb(val, HDMI_VP_CONF);
723 } else { /* data from packetizer block */
724 val = hdmi_readb(HDMI_VP_CONF);
725 val &= ~(HDMI_VP_CONF_PR_EN_MASK |
726 HDMI_VP_CONF_BYPASS_SELECT_MASK);
727 val |= HDMI_VP_CONF_PR_EN_DISABLE |
728 HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
729 hdmi_writeb(val, HDMI_VP_CONF);
732 val = hdmi_readb(HDMI_VP_STUFF);
733 val &= ~HDMI_VP_STUFF_IDEFAULT_PHASE_MASK;
734 val |= 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET;
735 hdmi_writeb(val, HDMI_VP_STUFF);
737 hdmi_writeb(remap_size, HDMI_VP_REMAP);
739 if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
740 val = hdmi_readb(HDMI_VP_CONF);
741 val &= ~(HDMI_VP_CONF_BYPASS_EN_MASK |
742 HDMI_VP_CONF_PP_EN_ENMASK |
743 HDMI_VP_CONF_YCC422_EN_MASK);
744 val |= HDMI_VP_CONF_BYPASS_EN_DISABLE |
745 HDMI_VP_CONF_PP_EN_ENABLE |
746 HDMI_VP_CONF_YCC422_EN_DISABLE;
747 hdmi_writeb(val, HDMI_VP_CONF);
748 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {
749 val = hdmi_readb(HDMI_VP_CONF);
750 val &= ~(HDMI_VP_CONF_BYPASS_EN_MASK |
751 HDMI_VP_CONF_PP_EN_ENMASK |
752 HDMI_VP_CONF_YCC422_EN_MASK);
753 val |= HDMI_VP_CONF_BYPASS_EN_DISABLE |
754 HDMI_VP_CONF_PP_EN_DISABLE |
755 HDMI_VP_CONF_YCC422_EN_ENABLE;
756 hdmi_writeb(val, HDMI_VP_CONF);
757 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {
758 val = hdmi_readb(HDMI_VP_CONF);
759 val &= ~(HDMI_VP_CONF_BYPASS_EN_MASK |
760 HDMI_VP_CONF_PP_EN_ENMASK |
761 HDMI_VP_CONF_YCC422_EN_MASK);
762 val |= HDMI_VP_CONF_BYPASS_EN_ENABLE |
763 HDMI_VP_CONF_PP_EN_DISABLE |
764 HDMI_VP_CONF_YCC422_EN_DISABLE;
765 hdmi_writeb(val, HDMI_VP_CONF);
770 val = hdmi_readb(HDMI_VP_STUFF);
771 val &= ~(HDMI_VP_STUFF_PP_STUFFING_MASK |
772 HDMI_VP_STUFF_YCC422_STUFFING_MASK);
773 val |= HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
774 HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE;
775 hdmi_writeb(val, HDMI_VP_STUFF);
777 val = hdmi_readb(HDMI_VP_CONF);
778 val &= ~HDMI_VP_CONF_OUTPUT_SELECTOR_MASK;
779 val |= output_select;
780 hdmi_writeb(val, HDMI_VP_CONF);
784 /* Force a fixed color screen */
785 static void hdmi_video_force_output(struct mxc_hdmi *hdmi, unsigned char force)
789 dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
792 hdmi_writeb(0x00, HDMI_FC_DBGTMDS2); /* R */
793 hdmi_writeb(0x00, HDMI_FC_DBGTMDS1); /* G */
794 hdmi_writeb(0xFF, HDMI_FC_DBGTMDS0); /* B */
795 val = hdmi_readb(HDMI_FC_DBGFORCE);
796 val |= HDMI_FC_DBGFORCE_FORCEVIDEO;
797 hdmi_writeb(val, HDMI_FC_DBGFORCE);
799 val = hdmi_readb(HDMI_FC_DBGFORCE);
800 val &= ~HDMI_FC_DBGFORCE_FORCEVIDEO;
801 hdmi_writeb(val, HDMI_FC_DBGFORCE);
802 hdmi_writeb(0x00, HDMI_FC_DBGTMDS2); /* R */
803 hdmi_writeb(0x00, HDMI_FC_DBGTMDS1); /* G */
804 hdmi_writeb(0x00, HDMI_FC_DBGTMDS0); /* B */
809 static inline void hdmi_phy_test_clear(struct mxc_hdmi *hdmi,
812 u8 val = hdmi_readb(HDMI_PHY_TST0);
813 val &= ~HDMI_PHY_TST0_TSTCLR_MASK;
814 val |= (bit << HDMI_PHY_TST0_TSTCLR_OFFSET) &
815 HDMI_PHY_TST0_TSTCLR_MASK;
816 hdmi_writeb(val, HDMI_PHY_TST0);
819 static inline void hdmi_phy_test_enable(struct mxc_hdmi *hdmi,
822 u8 val = hdmi_readb(HDMI_PHY_TST0);
823 val &= ~HDMI_PHY_TST0_TSTEN_MASK;
824 val |= (bit << HDMI_PHY_TST0_TSTEN_OFFSET) &
825 HDMI_PHY_TST0_TSTEN_MASK;
826 hdmi_writeb(val, HDMI_PHY_TST0);
829 static inline void hdmi_phy_test_clock(struct mxc_hdmi *hdmi,
832 u8 val = hdmi_readb(HDMI_PHY_TST0);
833 val &= ~HDMI_PHY_TST0_TSTCLK_MASK;
834 val |= (bit << HDMI_PHY_TST0_TSTCLK_OFFSET) &
835 HDMI_PHY_TST0_TSTCLK_MASK;
836 hdmi_writeb(val, HDMI_PHY_TST0);
839 static inline void hdmi_phy_test_din(struct mxc_hdmi *hdmi,
842 hdmi_writeb(bit, HDMI_PHY_TST1);
845 static inline void hdmi_phy_test_dout(struct mxc_hdmi *hdmi,
848 hdmi_writeb(bit, HDMI_PHY_TST2);
851 static bool hdmi_phy_wait_i2c_done(struct mxc_hdmi *hdmi, int msec)
853 unsigned char val = 0;
854 val = hdmi_readb(HDMI_IH_I2CMPHY_STAT0) & 0x3;
859 val = hdmi_readb(HDMI_IH_I2CMPHY_STAT0) & 0x3;
864 static void hdmi_phy_i2c_write(struct mxc_hdmi *hdmi, unsigned short data,
867 hdmi_writeb(0xFF, HDMI_IH_I2CMPHY_STAT0);
868 hdmi_writeb(addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
869 hdmi_writeb((unsigned char)(data >> 8),
870 HDMI_PHY_I2CM_DATAO_1_ADDR);
871 hdmi_writeb((unsigned char)(data >> 0),
872 HDMI_PHY_I2CM_DATAO_0_ADDR);
873 hdmi_writeb(HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
874 HDMI_PHY_I2CM_OPERATION_ADDR);
875 hdmi_phy_wait_i2c_done(hdmi, 1000);
879 static unsigned short hdmi_phy_i2c_read(struct mxc_hdmi *hdmi,
883 unsigned char msb = 0, lsb = 0;
884 hdmi_writeb(0xFF, HDMI_IH_I2CMPHY_STAT0);
885 hdmi_writeb(addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
886 hdmi_writeb(HDMI_PHY_I2CM_OPERATION_ADDR_READ,
887 HDMI_PHY_I2CM_OPERATION_ADDR);
888 hdmi_phy_wait_i2c_done(hdmi, 1000);
889 msb = hdmi_readb(HDMI_PHY_I2CM_DATAI_1_ADDR);
890 lsb = hdmi_readb(HDMI_PHY_I2CM_DATAI_0_ADDR);
891 data = (msb << 8) | lsb;
895 static int hdmi_phy_i2c_write_verify(struct mxc_hdmi *hdmi, unsigned short data,
898 unsigned short val = 0;
899 hdmi_phy_i2c_write(hdmi, data, addr);
900 val = hdmi_phy_i2c_read(hdmi, addr);
901 return (val == data);
905 static bool hdmi_edid_wait_i2c_done(struct mxc_hdmi *hdmi, int msec)
907 unsigned char val = 0;
908 val = hdmi_readb(HDMI_IH_I2CM_STAT0) & 0x2;
913 dev_dbg(&hdmi->pdev->dev,
914 "HDMI EDID i2c operation time out!!\n");
917 val = hdmi_readb(HDMI_IH_I2CM_STAT0) & 0x2;
922 static u8 hdmi_edid_i2c_read(struct mxc_hdmi *hdmi,
925 u8 spointer = blockno / 2;
926 u8 edidaddress = ((blockno % 2) * 0x80) + addr;
929 hdmi_writeb(0xFF, HDMI_IH_I2CM_STAT0);
930 hdmi_writeb(edidaddress, HDMI_I2CM_ADDRESS);
931 hdmi_writeb(spointer, HDMI_I2CM_SEGADDR);
933 hdmi_writeb(HDMI_I2CM_OPERATION_READ,
934 HDMI_I2CM_OPERATION);
936 hdmi_writeb(HDMI_I2CM_OPERATION_READ_EXT,
937 HDMI_I2CM_OPERATION);
939 hdmi_edid_wait_i2c_done(hdmi, 1000);
940 data = hdmi_readb(HDMI_I2CM_DATAI);
941 hdmi_writeb(0xFF, HDMI_IH_I2CM_STAT0);
946 /* "Power-down enable (active low)"
947 * That mean that power up == 1! */
948 static void mxc_hdmi_phy_enable_power(u8 enable)
950 hdmi_mask_writeb(enable, HDMI_PHY_CONF0,
951 HDMI_PHY_CONF0_PDZ_OFFSET,
952 HDMI_PHY_CONF0_PDZ_MASK);
955 static void mxc_hdmi_phy_enable_tmds(u8 enable)
957 hdmi_mask_writeb(enable, HDMI_PHY_CONF0,
958 HDMI_PHY_CONF0_ENTMDS_OFFSET,
959 HDMI_PHY_CONF0_ENTMDS_MASK);
962 static void mxc_hdmi_phy_gen2_pddq(u8 enable)
964 hdmi_mask_writeb(enable, HDMI_PHY_CONF0,
965 HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET,
966 HDMI_PHY_CONF0_GEN2_PDDQ_MASK);
969 static void mxc_hdmi_phy_gen2_txpwron(u8 enable)
971 hdmi_mask_writeb(enable, HDMI_PHY_CONF0,
972 HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,
973 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
977 static void mxc_hdmi_phy_gen2_enhpdrxsense(u8 enable)
979 hdmi_mask_writeb(enable, HDMI_PHY_CONF0,
980 HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE_OFFSET,
981 HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE_MASK);
985 static void mxc_hdmi_phy_sel_data_en_pol(u8 enable)
987 hdmi_mask_writeb(enable, HDMI_PHY_CONF0,
988 HDMI_PHY_CONF0_SELDATAENPOL_OFFSET,
989 HDMI_PHY_CONF0_SELDATAENPOL_MASK);
992 static void mxc_hdmi_phy_sel_interface_control(u8 enable)
994 hdmi_mask_writeb(enable, HDMI_PHY_CONF0,
995 HDMI_PHY_CONF0_SELDIPIF_OFFSET,
996 HDMI_PHY_CONF0_SELDIPIF_MASK);
999 static int hdmi_phy_configure(struct mxc_hdmi *hdmi, unsigned char pRep,
1000 unsigned char cRes, int cscOn)
1005 dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
1007 /* color resolution 0 is 8 bit colour depth */
1013 else if (cRes != 8 && cRes != 12)
1016 /* Enable csc path */
1018 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH;
1020 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS;
1022 hdmi_writeb(val, HDMI_MC_FLOWCTRL);
1024 /* gen2 tx power off */
1025 mxc_hdmi_phy_gen2_txpwron(0);
1028 mxc_hdmi_phy_gen2_pddq(1);
1031 hdmi_writeb(HDMI_MC_PHYRSTZ_DEASSERT, HDMI_MC_PHYRSTZ);
1032 hdmi_writeb(HDMI_MC_PHYRSTZ_ASSERT, HDMI_MC_PHYRSTZ);
1034 hdmi_writeb(HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
1036 hdmi_phy_test_clear(hdmi, 1);
1037 hdmi_writeb(HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2,
1038 HDMI_PHY_I2CM_SLAVE_ADDR);
1039 hdmi_phy_test_clear(hdmi, 0);
1041 if (hdmi->hdmi_data.video_mode.mPixelClock < 0) {
1042 dev_dbg(&hdmi->pdev->dev, "Pixel clock (%d) must be positive\n",
1043 hdmi->hdmi_data.video_mode.mPixelClock);
1047 if (hdmi->hdmi_data.video_mode.mPixelClock <= 45250000) {
1051 hdmi_phy_i2c_write(hdmi, 0x01e0, 0x06);
1052 hdmi_phy_i2c_write(hdmi, 0x0000, 0x15); /* GMPCTRL */
1055 hdmi_phy_i2c_write(hdmi, 0x21e1, 0x06);
1056 hdmi_phy_i2c_write(hdmi, 0x0000, 0x15);
1059 hdmi_phy_i2c_write(hdmi, 0x41e2, 0x06);
1060 hdmi_phy_i2c_write(hdmi, 0x0000, 0x15);
1065 } else if (hdmi->hdmi_data.video_mode.mPixelClock <= 92500000) {
1068 hdmi_phy_i2c_write(hdmi, 0x0140, 0x06);
1069 hdmi_phy_i2c_write(hdmi, 0x0005, 0x15);
1072 hdmi_phy_i2c_write(hdmi, 0x2141, 0x06);
1073 hdmi_phy_i2c_write(hdmi, 0x0005, 0x15);
1076 hdmi_phy_i2c_write(hdmi, 0x4142, 0x06);
1077 hdmi_phy_i2c_write(hdmi, 0x0005, 0x15);
1081 } else if (hdmi->hdmi_data.video_mode.mPixelClock <= 148500000) {
1084 hdmi_phy_i2c_write(hdmi, 0x00a0, 0x06);
1085 hdmi_phy_i2c_write(hdmi, 0x000a, 0x15);
1088 hdmi_phy_i2c_write(hdmi, 0x20a1, 0x06);
1089 hdmi_phy_i2c_write(hdmi, 0x000a, 0x15);
1092 hdmi_phy_i2c_write(hdmi, 0x40a2, 0x06);
1093 hdmi_phy_i2c_write(hdmi, 0x000a, 0x15);
1100 hdmi_phy_i2c_write(hdmi, 0x00a0, 0x06);
1101 hdmi_phy_i2c_write(hdmi, 0x000a, 0x15);
1104 hdmi_phy_i2c_write(hdmi, 0x2001, 0x06);
1105 hdmi_phy_i2c_write(hdmi, 0x000f, 0x15);
1108 hdmi_phy_i2c_write(hdmi, 0x4002, 0x06);
1109 hdmi_phy_i2c_write(hdmi, 0x000f, 0x15);
1115 if (hdmi->hdmi_data.video_mode.mPixelClock <= 54000000) {
1118 hdmi_phy_i2c_write(hdmi, 0x091c, 0x10); /* CURRCTRL */
1121 hdmi_phy_i2c_write(hdmi, 0x091c, 0x10);
1124 hdmi_phy_i2c_write(hdmi, 0x06dc, 0x10);
1129 } else if (hdmi->hdmi_data.video_mode.mPixelClock <= 58400000) {
1132 hdmi_phy_i2c_write(hdmi, 0x091c, 0x10);
1135 hdmi_phy_i2c_write(hdmi, 0x06dc, 0x10);
1138 hdmi_phy_i2c_write(hdmi, 0x06dc, 0x10);
1143 } else if (hdmi->hdmi_data.video_mode.mPixelClock <= 72000000) {
1146 hdmi_phy_i2c_write(hdmi, 0x06dc, 0x10);
1149 hdmi_phy_i2c_write(hdmi, 0x06dc, 0x10);
1152 hdmi_phy_i2c_write(hdmi, 0x091c, 0x10);
1157 } else if (hdmi->hdmi_data.video_mode.mPixelClock <= 74250000) {
1160 hdmi_phy_i2c_write(hdmi, 0x06dc, 0x10);
1163 hdmi_phy_i2c_write(hdmi, 0x0b5c, 0x10);
1166 hdmi_phy_i2c_write(hdmi, 0x091c, 0x10);
1171 } else if (hdmi->hdmi_data.video_mode.mPixelClock <= 118800000) {
1174 hdmi_phy_i2c_write(hdmi, 0x091c, 0x10);
1177 hdmi_phy_i2c_write(hdmi, 0x091c, 0x10);
1180 hdmi_phy_i2c_write(hdmi, 0x06dc, 0x10);
1185 } else if (hdmi->hdmi_data.video_mode.mPixelClock <= 216000000) {
1188 hdmi_phy_i2c_write(hdmi, 0x06dc, 0x10);
1191 hdmi_phy_i2c_write(hdmi, 0x0b5c, 0x10);
1194 hdmi_phy_i2c_write(hdmi, 0x091c, 0x10);
1200 dev_err(&hdmi->pdev->dev,
1201 "Pixel clock %d - unsupported by HDMI\n",
1202 hdmi->hdmi_data.video_mode.mPixelClock);
1206 hdmi_phy_i2c_write(hdmi, 0x0000, 0x13); /* PLLPHBYCTRL */
1207 hdmi_phy_i2c_write(hdmi, 0x0006, 0x17);
1208 /* RESISTANCE TERM 133Ohm Cfg */
1209 hdmi_phy_i2c_write(hdmi, 0x0005, 0x19); /* TXTERM */
1210 /* PREEMP Cgf 0.00 */
1211 hdmi_phy_i2c_write(hdmi, 0x800d, 0x09); /* CKSYMTXCTRL */
1213 hdmi_phy_i2c_write(hdmi, 0x01ad, 0x0E); /* VLEVCTRL */
1215 /* Board specific setting for PHY register 0x09, 0x0e to pass HCT */
1216 if (hdmi->phy_config.reg_cksymtx != 0)
1217 hdmi_phy_i2c_write(hdmi, hdmi->phy_config.reg_cksymtx, 0x09);
1219 if (hdmi->phy_config.reg_vlev != 0)
1220 hdmi_phy_i2c_write(hdmi, hdmi->phy_config.reg_vlev, 0x0E);
1222 /* REMOVE CLK TERM */
1223 hdmi_phy_i2c_write(hdmi, 0x8000, 0x05); /* CKCALCTRL */
1225 if (hdmi->hdmi_data.video_mode.mPixelClock > 148500000) {
1226 hdmi_phy_i2c_write(hdmi, 0x800b, 0x09);
1227 hdmi_phy_i2c_write(hdmi, 0x0129, 0x0E);
1230 mxc_hdmi_phy_enable_power(1);
1232 /* toggle TMDS enable */
1233 mxc_hdmi_phy_enable_tmds(0);
1234 mxc_hdmi_phy_enable_tmds(1);
1236 /* gen2 tx power on */
1237 mxc_hdmi_phy_gen2_txpwron(1);
1238 mxc_hdmi_phy_gen2_pddq(0);
1240 /*Wait for PHY PLL lock */
1242 val = hdmi_readb(HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
1246 dev_dbg(&hdmi->pdev->dev, "PHY PLL not locked\n");
1249 val = hdmi_readb(HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
1255 static void mxc_hdmi_phy_init(struct mxc_hdmi *hdmi)
1260 dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
1262 /* Never do phy init if pixel clock is gated.
1263 * Otherwise HDMI PHY will get messed up and generate an overflow
1264 * interrupt that can't be cleared or detected by accessing the
1265 * status register. */
1266 if (!hdmi->fb_reg || !hdmi->cable_plugin
1267 || (hdmi->blank != FB_BLANK_UNBLANK))
1270 if (!hdmi->hdmi_data.video_mode.mDVI)
1271 hdmi_enable_overflow_interrupts();
1273 /*check csc whether needed activated in HDMI mode */
1274 cscon = (isColorSpaceConversion(hdmi) &&
1275 !hdmi->hdmi_data.video_mode.mDVI);
1277 /* HDMI Phy spec says to do the phy initialization sequence twice */
1278 for (i = 0 ; i < 2 ; i++) {
1279 mxc_hdmi_phy_sel_data_en_pol(1);
1280 mxc_hdmi_phy_sel_interface_control(0);
1281 mxc_hdmi_phy_enable_tmds(0);
1282 mxc_hdmi_phy_enable_power(0);
1285 hdmi_phy_configure(hdmi, 0, 8, cscon);
1288 hdmi->phy_enabled = true;
1291 static void hdmi_config_AVI(struct mxc_hdmi *hdmi)
1296 u8 act_ratio, coded_ratio, colorimetry, ext_colorimetry;
1297 struct fb_videomode mode;
1298 const struct fb_videomode *edid_mode;
1301 dev_dbg(&hdmi->pdev->dev, "set up AVI frame\n");
1303 fb_var_to_videomode(&mode, &hdmi->fbi->var);
1304 /* Use mode from list extracted from EDID to get aspect ratio */
1305 if (!list_empty(&hdmi->fbi->modelist)) {
1306 edid_mode = fb_find_nearest_mode(&mode, &hdmi->fbi->modelist);
1307 if (edid_mode->vmode & FB_VMODE_ASPECT_16_9)
1310 aspect_16_9 = false;
1312 aspect_16_9 = false;
1314 /********************************************
1316 ********************************************/
1317 if (hdmi->hdmi_data.enc_out_format == YCBCR444)
1318 pix_fmt = HDMI_FC_AVICONF0_PIX_FMT_YCBCR444;
1319 else if (hdmi->hdmi_data.enc_out_format == YCBCR422_8BITS)
1320 pix_fmt = HDMI_FC_AVICONF0_PIX_FMT_YCBCR422;
1322 pix_fmt = HDMI_FC_AVICONF0_PIX_FMT_RGB;
1324 if (hdmi->edid_cfg.cea_underscan)
1325 under_scan = HDMI_FC_AVICONF0_SCAN_INFO_UNDERSCAN;
1327 under_scan = HDMI_FC_AVICONF0_SCAN_INFO_NODATA;
1330 * Active format identification data is present in the AVI InfoFrame.
1331 * Under scan info, no bar data
1333 val = pix_fmt | under_scan |
1334 HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT |
1335 HDMI_FC_AVICONF0_BAR_DATA_NO_DATA;
1337 hdmi_writeb(val, HDMI_FC_AVICONF0);
1339 /********************************************
1341 ********************************************/
1343 /* Set the Aspect Ratio */
1345 act_ratio = HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9;
1346 coded_ratio = HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9;
1348 act_ratio = HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3;
1349 coded_ratio = HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3;
1352 /* Set up colorimetry */
1353 if (hdmi->hdmi_data.enc_out_format == XVYCC444) {
1354 colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO;
1355 if (hdmi->hdmi_data.colorimetry == eITU601)
1357 HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601;
1358 else /* hdmi->hdmi_data.colorimetry == eITU709 */
1360 HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709;
1361 } else if (hdmi->hdmi_data.enc_out_format != RGB) {
1362 if (hdmi->hdmi_data.colorimetry == eITU601)
1363 colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_SMPTE;
1364 else /* hdmi->hdmi_data.colorimetry == eITU709 */
1365 colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_ITUR;
1366 ext_colorimetry = HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601;
1367 } else { /* Carries no data */
1368 colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA;
1369 ext_colorimetry = HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601;
1372 val = colorimetry | coded_ratio | act_ratio;
1373 hdmi_writeb(val, HDMI_FC_AVICONF1);
1375 /********************************************
1377 ********************************************/
1379 val = HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA | ext_colorimetry |
1380 HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT |
1381 HDMI_FC_AVICONF2_SCALING_NONE;
1382 hdmi_writeb(val, HDMI_FC_AVICONF2);
1384 /********************************************
1386 ********************************************/
1387 hdmi_writeb(hdmi->vic, HDMI_FC_AVIVID);
1389 /********************************************
1391 ********************************************/
1393 /* Set up input and output pixel repetition */
1394 val = (((hdmi->hdmi_data.video_mode.mPixelRepetitionInput + 1) <<
1395 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) &
1396 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) |
1397 ((hdmi->hdmi_data.video_mode.mPixelRepetitionOutput <<
1398 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) &
1399 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK);
1400 hdmi_writeb(val, HDMI_FC_PRCONF);
1402 /* IT Content and quantization range = don't care */
1403 val = HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GRAPHICS |
1404 HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED;
1405 hdmi_writeb(val, HDMI_FC_AVICONF3);
1407 /********************************************
1408 * AVI Data Bytes 6-13
1409 ********************************************/
1410 hdmi_writeb(0, HDMI_FC_AVIETB0);
1411 hdmi_writeb(0, HDMI_FC_AVIETB1);
1412 hdmi_writeb(0, HDMI_FC_AVISBB0);
1413 hdmi_writeb(0, HDMI_FC_AVISBB1);
1414 hdmi_writeb(0, HDMI_FC_AVIELB0);
1415 hdmi_writeb(0, HDMI_FC_AVIELB1);
1416 hdmi_writeb(0, HDMI_FC_AVISRB0);
1417 hdmi_writeb(0, HDMI_FC_AVISRB1);
1421 * this submodule is responsible for the video/audio data composition.
1423 static void hdmi_av_composer(struct mxc_hdmi *hdmi)
1426 struct fb_info *fbi = hdmi->fbi;
1427 struct fb_videomode fb_mode;
1428 struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
1431 dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
1433 fb_var_to_videomode(&fb_mode, &fbi->var);
1435 vmode->mHSyncPolarity = ((fb_mode.sync & FB_SYNC_HOR_HIGH_ACT) != 0);
1436 vmode->mVSyncPolarity = ((fb_mode.sync & FB_SYNC_VERT_HIGH_ACT) != 0);
1437 vmode->mInterlaced = ((fb_mode.vmode & FB_VMODE_INTERLACED) != 0);
1438 vmode->mPixelClock = (fb_mode.xres + fb_mode.left_margin +
1439 fb_mode.right_margin + fb_mode.hsync_len) * (fb_mode.yres +
1440 fb_mode.upper_margin + fb_mode.lower_margin +
1441 fb_mode.vsync_len) * fb_mode.refresh;
1443 dev_dbg(&hdmi->pdev->dev, "final pixclk = %d\n", vmode->mPixelClock);
1445 /* Set up HDMI_FC_INVIDCONF */
1446 inv_val = (vmode->mVSyncPolarity ?
1447 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
1448 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW);
1450 inv_val |= (vmode->mHSyncPolarity ?
1451 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
1452 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW);
1454 inv_val |= (vmode->mDataEnablePolarity ?
1455 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
1456 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
1458 if (hdmi->vic == 39)
1459 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH;
1461 inv_val |= (vmode->mInterlaced ?
1462 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH :
1463 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW);
1465 inv_val |= (vmode->mInterlaced ?
1466 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED :
1467 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE);
1469 inv_val |= (vmode->mDVI ?
1470 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE :
1471 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE);
1473 hdmi_writeb(inv_val, HDMI_FC_INVIDCONF);
1475 /* Set up horizontal active pixel region width */
1476 hdmi_writeb(fb_mode.xres >> 8, HDMI_FC_INHACTV1);
1477 hdmi_writeb(fb_mode.xres, HDMI_FC_INHACTV0);
1479 /* Set up vertical blanking pixel region width */
1480 hdmi_writeb(fb_mode.yres >> 8, HDMI_FC_INVACTV1);
1481 hdmi_writeb(fb_mode.yres, HDMI_FC_INVACTV0);
1483 /* Set up horizontal blanking pixel region width */
1484 hblank = fb_mode.left_margin + fb_mode.right_margin +
1486 hdmi_writeb(hblank >> 8, HDMI_FC_INHBLANK1);
1487 hdmi_writeb(hblank, HDMI_FC_INHBLANK0);
1489 /* Set up vertical blanking pixel region width */
1490 vblank = fb_mode.upper_margin + fb_mode.lower_margin +
1492 hdmi_writeb(vblank, HDMI_FC_INVBLANK);
1494 /* Set up HSYNC active edge delay width (in pixel clks) */
1495 hdmi_writeb(fb_mode.right_margin >> 8, HDMI_FC_HSYNCINDELAY1);
1496 hdmi_writeb(fb_mode.right_margin, HDMI_FC_HSYNCINDELAY0);
1498 /* Set up VSYNC active edge delay (in pixel clks) */
1499 hdmi_writeb(fb_mode.lower_margin, HDMI_FC_VSYNCINDELAY);
1501 /* Set up HSYNC active pulse width (in pixel clks) */
1502 hdmi_writeb(fb_mode.hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);
1503 hdmi_writeb(fb_mode.hsync_len, HDMI_FC_HSYNCINWIDTH0);
1505 /* Set up VSYNC active edge delay (in pixel clks) */
1506 hdmi_writeb(fb_mode.vsync_len, HDMI_FC_VSYNCINWIDTH);
1508 dev_dbg(&hdmi->pdev->dev, "%s exit\n", __func__);
1511 static int mxc_edid_read_internal(struct mxc_hdmi *hdmi, unsigned char *edid,
1512 struct mxc_edid_cfg *cfg, struct fb_info *fbi)
1516 unsigned char *ediddata = edid;
1517 unsigned char tmpedid[EDID_LENGTH];
1519 dev_info(&hdmi->pdev->dev, "%s\n", __func__);
1521 if (!edid || !cfg || !fbi)
1524 /* init HDMI I2CM for read edid*/
1525 hdmi_writeb(0x0, HDMI_I2CM_DIV);
1526 hdmi_writeb(0x00, HDMI_I2CM_SS_SCL_HCNT_1_ADDR);
1527 hdmi_writeb(0x79, HDMI_I2CM_SS_SCL_HCNT_0_ADDR);
1528 hdmi_writeb(0x00, HDMI_I2CM_SS_SCL_LCNT_1_ADDR);
1529 hdmi_writeb(0x91, HDMI_I2CM_SS_SCL_LCNT_0_ADDR);
1531 hdmi_writeb(0x00, HDMI_I2CM_FS_SCL_HCNT_1_ADDR);
1532 hdmi_writeb(0x0F, HDMI_I2CM_FS_SCL_HCNT_0_ADDR);
1533 hdmi_writeb(0x00, HDMI_I2CM_FS_SCL_LCNT_1_ADDR);
1534 hdmi_writeb(0x21, HDMI_I2CM_FS_SCL_LCNT_0_ADDR);
1536 hdmi_writeb(0x50, HDMI_I2CM_SLAVE);
1537 hdmi_writeb(0x30, HDMI_I2CM_SEGADDR);
1539 /* Umask edid interrupt */
1540 hdmi_writeb(HDMI_I2CM_INT_DONE_POL,
1543 hdmi_writeb(HDMI_I2CM_CTLINT_NAC_POL |
1544 HDMI_I2CM_CTLINT_ARBITRATION_POL,
1547 /* reset edid data zero */
1548 memset(edid, 0, EDID_LENGTH*4);
1549 memset(cfg, 0, sizeof(struct mxc_edid_cfg));
1551 /* Check first three byte of EDID head */
1552 if (!(hdmi_edid_i2c_read(hdmi, 0, 0) == 0x00) ||
1553 !(hdmi_edid_i2c_read(hdmi, 1, 0) == 0xFF) ||
1554 !(hdmi_edid_i2c_read(hdmi, 2, 0) == 0xFF)) {
1555 dev_info(&hdmi->pdev->dev, "EDID head check failed!");
1559 for (i = 0; i < 128; i++) {
1560 *ediddata = hdmi_edid_i2c_read(hdmi, i, 0);
1564 extblknum = edid[0x7E];
1569 ediddata = edid + EDID_LENGTH;
1570 for (i = 0; i < 128; i++) {
1571 *ediddata = hdmi_edid_i2c_read(hdmi, i, 1);
1576 /* edid first block parsing */
1577 memset(&fbi->monspecs, 0, sizeof(fbi->monspecs));
1578 fb_edid_to_monspecs(edid, &fbi->monspecs);
1580 ret = mxc_edid_parse_ext_blk(edid + EDID_LENGTH,
1581 cfg, &fbi->monspecs);
1585 /* need read segment block? */
1586 if (extblknum > 1) {
1587 for (j = 1; j <= extblknum; j++) {
1588 for (i = 0; i < 128; i++)
1589 *(tmpedid + 1) = hdmi_edid_i2c_read(hdmi, i, j);
1591 /* edid ext block parsing */
1592 ret = mxc_edid_parse_ext_blk(tmpedid + EDID_LENGTH,
1593 cfg, &fbi->monspecs);
1602 static int mxc_hdmi_read_edid(struct mxc_hdmi *hdmi)
1605 u8 edid_old[HDMI_EDID_LEN];
1608 dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
1611 memcpy(edid_old, hdmi->edid, HDMI_EDID_LEN);
1613 /* Read EDID via HDMI DDC when HDCP Enable */
1615 ret = mxc_edid_read(hdmi_i2c->adapter, hdmi_i2c->addr,
1616 hdmi->edid, &hdmi->edid_cfg, hdmi->fbi);
1619 /* Disable HDCP clk */
1620 if (hdmi->hdmi_data.hdcp_enable) {
1621 clkdis = hdmi_readb(HDMI_MC_CLKDIS);
1622 clkdis |= HDMI_MC_CLKDIS_HDCPCLK_DISABLE;
1623 hdmi_writeb(clkdis, HDMI_MC_CLKDIS);
1626 ret = mxc_edid_read_internal(hdmi, hdmi->edid,
1627 &hdmi->edid_cfg, hdmi->fbi);
1629 /* Enable HDCP clk */
1630 if (hdmi->hdmi_data.hdcp_enable) {
1631 clkdis = hdmi_readb(HDMI_MC_CLKDIS);
1632 clkdis &= ~HDMI_MC_CLKDIS_HDCPCLK_DISABLE;
1633 hdmi_writeb(clkdis, HDMI_MC_CLKDIS);
1638 return HDMI_EDID_FAIL;
1640 /* Save edid cfg for audio driver */
1641 hdmi_set_edid_cfg(&hdmi->edid_cfg);
1643 if (!memcmp(edid_old, hdmi->edid, HDMI_EDID_LEN)) {
1644 dev_info(&hdmi->pdev->dev, "same edid\n");
1645 return HDMI_EDID_SAME;
1648 if (hdmi->fbi->monspecs.modedb_len == 0) {
1649 dev_info(&hdmi->pdev->dev, "No modes read from edid\n");
1650 return HDMI_EDID_NO_MODES;
1653 return HDMI_EDID_SUCCESS;
1656 static void mxc_hdmi_phy_disable(struct mxc_hdmi *hdmi)
1658 dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
1660 if (!hdmi->phy_enabled)
1663 hdmi_disable_overflow_interrupts();
1665 /* Setting PHY to reset status */
1666 hdmi_writeb(HDMI_MC_PHYRSTZ_DEASSERT, HDMI_MC_PHYRSTZ);
1668 /* Power down PHY */
1669 mxc_hdmi_phy_enable_tmds(0);
1670 mxc_hdmi_phy_enable_power(0);
1671 mxc_hdmi_phy_gen2_txpwron(0);
1672 mxc_hdmi_phy_gen2_pddq(1);
1674 hdmi->phy_enabled = false;
1675 dev_dbg(&hdmi->pdev->dev, "%s - exit\n", __func__);
1678 /* HDMI Initialization Step B.4 */
1679 static void mxc_hdmi_enable_video_path(struct mxc_hdmi *hdmi)
1683 dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
1685 /* control period minimum duration */
1686 hdmi_writeb(12, HDMI_FC_CTRLDUR);
1687 hdmi_writeb(32, HDMI_FC_EXCTRLDUR);
1688 hdmi_writeb(1, HDMI_FC_EXCTRLSPAC);
1690 /* Set to fill TMDS data channels */
1691 hdmi_writeb(0x0B, HDMI_FC_CH0PREAM);
1692 hdmi_writeb(0x16, HDMI_FC_CH1PREAM);
1693 hdmi_writeb(0x21, HDMI_FC_CH2PREAM);
1695 /* Enable pixel clock and tmds data path */
1697 clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
1698 hdmi_writeb(clkdis, HDMI_MC_CLKDIS);
1700 clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
1701 hdmi_writeb(clkdis, HDMI_MC_CLKDIS);
1703 /* Enable csc path */
1704 if (isColorSpaceConversion(hdmi)) {
1705 clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
1706 hdmi_writeb(clkdis, HDMI_MC_CLKDIS);
1710 static void hdmi_enable_audio_clk(struct mxc_hdmi *hdmi)
1714 dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
1716 clkdis = hdmi_readb(HDMI_MC_CLKDIS);
1717 clkdis &= ~HDMI_MC_CLKDIS_AUDCLK_DISABLE;
1718 hdmi_writeb(clkdis, HDMI_MC_CLKDIS);
1721 /* Workaround to clear the overflow condition */
1722 static void mxc_hdmi_clear_overflow(struct mxc_hdmi *hdmi)
1727 /* TMDS software reset */
1728 hdmi_writeb((u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
1730 val = hdmi_readb(HDMI_FC_INVIDCONF);
1732 if (cpu_is_imx6dl(hdmi)) {
1733 hdmi_writeb(val, HDMI_FC_INVIDCONF);
1737 for (count = 0 ; count < 5 ; count++)
1738 hdmi_writeb(val, HDMI_FC_INVIDCONF);
1741 static void hdmi_enable_overflow_interrupts(void)
1743 pr_debug("%s\n", __func__);
1744 hdmi_writeb(0, HDMI_FC_MASK2);
1745 hdmi_writeb(0, HDMI_IH_MUTE_FC_STAT2);
1748 static void hdmi_disable_overflow_interrupts(void)
1750 pr_debug("%s\n", __func__);
1751 hdmi_writeb(HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,
1752 HDMI_IH_MUTE_FC_STAT2);
1753 hdmi_writeb(0xff, HDMI_FC_MASK2);
1756 static void mxc_hdmi_notify_fb(struct mxc_hdmi *hdmi)
1758 dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
1760 /* Don't notify if we aren't registered yet */
1761 WARN_ON(!hdmi->fb_reg);
1763 /* disable the phy before ipu changes mode */
1764 mxc_hdmi_phy_disable(hdmi);
1767 * Note that fb_set_var will block. During this time,
1768 * FB_EVENT_MODE_CHANGE callback will happen.
1769 * So by the end of this function, mxc_hdmi_setup()
1772 hdmi->fbi->var.activate |= FB_ACTIVATE_FORCE;
1774 hdmi->fbi->flags |= FBINFO_MISC_USEREVENT;
1775 fb_set_var(hdmi->fbi, &hdmi->fbi->var);
1776 hdmi->fbi->flags &= ~FBINFO_MISC_USEREVENT;
1779 dev_dbg(&hdmi->pdev->dev, "%s exit\n", __func__);
1782 static void mxc_hdmi_edid_rebuild_modelist(struct mxc_hdmi *hdmi)
1785 struct fb_videomode *mode;
1787 dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
1791 fb_destroy_modelist(&hdmi->fbi->modelist);
1792 fb_add_videomode(&vga_mode, &hdmi->fbi->modelist);
1794 for (i = 0; i < hdmi->fbi->monspecs.modedb_len; i++) {
1796 * We might check here if mode is supported by HDMI.
1797 * We do not currently support interlaced modes.
1798 * And add CEA modes in the modelist.
1800 mode = &hdmi->fbi->monspecs.modedb[i];
1802 if (!(mode->vmode & FB_VMODE_INTERLACED) &&
1803 (mxc_edid_mode_to_vic(mode) != 0)) {
1805 dev_dbg(&hdmi->pdev->dev, "Added mode %d:", i);
1806 dev_dbg(&hdmi->pdev->dev,
1807 "xres = %d, yres = %d, freq = %d, vmode = %d, flag = %d\n",
1808 hdmi->fbi->monspecs.modedb[i].xres,
1809 hdmi->fbi->monspecs.modedb[i].yres,
1810 hdmi->fbi->monspecs.modedb[i].refresh,
1811 hdmi->fbi->monspecs.modedb[i].vmode,
1812 hdmi->fbi->monspecs.modedb[i].flag);
1814 fb_add_videomode(mode, &hdmi->fbi->modelist);
1821 static void mxc_hdmi_default_edid_cfg(struct mxc_hdmi *hdmi)
1823 /* Default setting HDMI working in HDMI mode */
1824 hdmi->edid_cfg.hdmi_cap = true;
1827 static void mxc_hdmi_default_modelist(struct mxc_hdmi *hdmi)
1830 const struct fb_videomode *mode;
1832 dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
1834 /* If not EDID data read, set up default modelist */
1835 dev_info(&hdmi->pdev->dev, "No modes read from edid\n");
1836 dev_info(&hdmi->pdev->dev, "create default modelist\n");
1840 fb_destroy_modelist(&hdmi->fbi->modelist);
1842 /*Add all no interlaced CEA mode to default modelist */
1843 for (i = 0; i < ARRAY_SIZE(mxc_cea_mode); i++) {
1844 mode = &mxc_cea_mode[i];
1845 if (!(mode->vmode & FB_VMODE_INTERLACED) && (mode->xres != 0))
1846 fb_add_videomode(mode, &hdmi->fbi->modelist);
1852 static void mxc_hdmi_set_mode_to_vga_dvi(struct mxc_hdmi *hdmi)
1854 dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
1856 hdmi_disable_overflow_interrupts();
1858 fb_videomode_to_var(&hdmi->fbi->var, &vga_mode);
1860 hdmi->requesting_vga_for_initialization = true;
1861 mxc_hdmi_notify_fb(hdmi);
1862 hdmi->requesting_vga_for_initialization = false;
1865 static void mxc_hdmi_set_mode(struct mxc_hdmi *hdmi)
1867 const struct fb_videomode *mode;
1868 struct fb_videomode m;
1869 struct fb_var_screeninfo var;
1871 dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
1873 /* Set the default mode only once. */
1874 if (!hdmi->dft_mode_set) {
1875 fb_videomode_to_var(&var, &hdmi->default_mode);
1876 hdmi->dft_mode_set = true;
1878 fb_videomode_to_var(&var, &hdmi->previous_non_vga_mode);
1880 fb_var_to_videomode(&m, &var);
1881 dump_fb_videomode(&m);
1883 mode = fb_find_nearest_mode(&m, &hdmi->fbi->modelist);
1885 pr_err("%s: could not find mode in modelist\n", __func__);
1889 /* If video mode same as previous, init HDMI again */
1890 if (fb_mode_is_equal(&hdmi->previous_non_vga_mode, mode)) {
1891 dev_dbg(&hdmi->pdev->dev,
1892 "%s: Video mode same as previous\n", __func__);
1893 /* update fbi mode in case modelist is updated */
1894 hdmi->fbi->mode = (struct fb_videomode *)mode;
1895 /* update hdmi setting in case EDID data updated */
1896 mxc_hdmi_setup(hdmi, 0);
1898 dev_dbg(&hdmi->pdev->dev, "%s: New video mode\n", __func__);
1899 mxc_hdmi_set_mode_to_vga_dvi(hdmi);
1900 fb_videomode_to_var(&hdmi->fbi->var, mode);
1901 dump_fb_videomode((struct fb_videomode *)mode);
1902 mxc_hdmi_notify_fb(hdmi);
1907 static void mxc_hdmi_cable_connected(struct mxc_hdmi *hdmi)
1911 dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
1913 hdmi->cable_plugin = true;
1915 /* HDMI Initialization Step C */
1916 edid_status = mxc_hdmi_read_edid(hdmi);
1918 /* Read EDID again if first EDID read failed */
1919 if (edid_status == HDMI_EDID_NO_MODES ||
1920 edid_status == HDMI_EDID_FAIL) {
1921 dev_info(&hdmi->pdev->dev, "Read EDID again\n");
1922 edid_status = mxc_hdmi_read_edid(hdmi);
1925 /* HDMI Initialization Steps D, E, F */
1926 switch (edid_status) {
1927 case HDMI_EDID_SUCCESS:
1928 mxc_hdmi_edid_rebuild_modelist(hdmi);
1931 /* Nothing to do if EDID same */
1932 case HDMI_EDID_SAME:
1935 case HDMI_EDID_FAIL:
1936 mxc_hdmi_default_edid_cfg(hdmi);
1938 case HDMI_EDID_NO_MODES:
1940 mxc_hdmi_default_modelist(hdmi);
1944 /* Setting video mode */
1945 mxc_hdmi_set_mode(hdmi);
1947 dev_dbg(&hdmi->pdev->dev, "%s exit\n", __func__);
1950 static int mxc_hdmi_power_on(struct mxc_dispdrv_handle *disp,
1951 struct fb_info *fbi)
1953 struct mxc_hdmi *hdmi = mxc_dispdrv_getdata(disp);
1954 mxc_hdmi_phy_init(hdmi);
1958 static void mxc_hdmi_power_off(struct mxc_dispdrv_handle *disp,
1959 struct fb_info *fbi)
1961 struct mxc_hdmi *hdmi = mxc_dispdrv_getdata(disp);
1962 mxc_hdmi_phy_disable(hdmi);
1965 static void mxc_hdmi_cable_disconnected(struct mxc_hdmi *hdmi)
1967 dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
1969 /* Disable All HDMI clock */
1970 hdmi_writeb(0xff, HDMI_MC_CLKDIS);
1972 mxc_hdmi_phy_disable(hdmi);
1974 hdmi_disable_overflow_interrupts();
1976 hdmi->cable_plugin = false;
1979 static void hotplug_worker(struct work_struct *work)
1981 struct delayed_work *delay_work = to_delayed_work(work);
1982 struct mxc_hdmi *hdmi =
1983 container_of(delay_work, struct mxc_hdmi, hotplug_work);
1984 u32 phy_int_stat, phy_int_pol, phy_int_mask;
1986 unsigned long flags;
1987 char event_string[32];
1988 char *envp[] = { event_string, NULL };
1990 phy_int_stat = hdmi->latest_intr_stat;
1991 phy_int_pol = hdmi_readb(HDMI_PHY_POL0);
1993 dev_dbg(&hdmi->pdev->dev, "phy_int_stat=0x%x, phy_int_pol=0x%x\n",
1994 phy_int_stat, phy_int_pol);
1996 /* check cable status */
1997 if (phy_int_stat & HDMI_IH_PHY_STAT0_HPD) {
1998 /* cable connection changes */
1999 if (phy_int_pol & HDMI_PHY_HPD) {
2001 dev_dbg(&hdmi->pdev->dev, "EVENT=plugin\n");
2002 mxc_hdmi_cable_connected(hdmi);
2004 /* Make HPD intr active low to capture unplug event */
2005 val = hdmi_readb(HDMI_PHY_POL0);
2006 val &= ~HDMI_PHY_HPD;
2007 hdmi_writeb(val, HDMI_PHY_POL0);
2009 hdmi_set_cable_state(1);
2011 sprintf(event_string, "EVENT=plugin");
2012 kobject_uevent_env(&hdmi->pdev->dev.kobj, KOBJ_CHANGE, envp);
2013 #ifdef CONFIG_MXC_HDMI_CEC
2014 mxc_hdmi_cec_handle(0x80);
2016 } else if (!(phy_int_pol & HDMI_PHY_HPD)) {
2018 dev_dbg(&hdmi->pdev->dev, "EVENT=plugout\n");
2019 hdmi_set_cable_state(0);
2020 mxc_hdmi_abort_stream();
2021 mxc_hdmi_cable_disconnected(hdmi);
2023 /* Make HPD intr active high to capture plugin event */
2024 val = hdmi_readb(HDMI_PHY_POL0);
2025 val |= HDMI_PHY_HPD;
2026 hdmi_writeb(val, HDMI_PHY_POL0);
2028 sprintf(event_string, "EVENT=plugout");
2029 kobject_uevent_env(&hdmi->pdev->dev.kobj, KOBJ_CHANGE, envp);
2030 #ifdef CONFIG_MXC_HDMI_CEC
2031 mxc_hdmi_cec_handle(0x100);
2035 dev_dbg(&hdmi->pdev->dev, "EVENT=none?\n");
2038 /* Lock here to ensure full powerdown sequence
2039 * completed before next interrupt processed */
2040 spin_lock_irqsave(&hdmi->irq_lock, flags);
2042 /* Re-enable HPD interrupts */
2043 phy_int_mask = hdmi_readb(HDMI_PHY_MASK0);
2044 phy_int_mask &= ~HDMI_PHY_HPD;
2045 hdmi_writeb(phy_int_mask, HDMI_PHY_MASK0);
2047 /* Unmute interrupts */
2048 hdmi_writeb(~HDMI_IH_MUTE_PHY_STAT0_HPD, HDMI_IH_MUTE_PHY_STAT0);
2050 if (hdmi_readb(HDMI_IH_FC_STAT2) & HDMI_IH_FC_STAT2_OVERFLOW_MASK)
2051 mxc_hdmi_clear_overflow(hdmi);
2053 spin_unlock_irqrestore(&hdmi->irq_lock, flags);
2056 static void hdcp_hdp_worker(struct work_struct *work)
2058 struct delayed_work *delay_work = to_delayed_work(work);
2059 struct mxc_hdmi *hdmi =
2060 container_of(delay_work, struct mxc_hdmi, hdcp_hdp_work);
2061 char event_string[32];
2062 char *envp[] = { event_string, NULL };
2064 /* HDCP interrupt */
2065 sprintf(event_string, "EVENT=hdcpint");
2066 kobject_uevent_env(&hdmi->pdev->dev.kobj, KOBJ_CHANGE, envp);
2068 /* Unmute interrupts in HDCP application*/
2071 static irqreturn_t mxc_hdmi_hotplug(int irq, void *data)
2073 struct mxc_hdmi *hdmi = data;
2075 unsigned long flags;
2077 spin_lock_irqsave(&hdmi->irq_lock, flags);
2079 /* Check and clean packet overflow interrupt.*/
2080 if (hdmi_readb(HDMI_IH_FC_STAT2) &
2081 HDMI_IH_FC_STAT2_OVERFLOW_MASK) {
2082 mxc_hdmi_clear_overflow(hdmi);
2084 dev_dbg(&hdmi->pdev->dev, "Overflow interrupt received\n");
2085 /* clear irq status */
2086 hdmi_writeb(HDMI_IH_FC_STAT2_OVERFLOW_MASK,
2091 * We could not disable the irq. Probably the audio driver
2092 * has enabled it. Masking off the HDMI interrupts using
2095 /* Capture status - used in hotplug_worker ISR */
2096 intr_stat = hdmi_readb(HDMI_IH_PHY_STAT0);
2098 if (intr_stat & HDMI_IH_PHY_STAT0_HPD) {
2100 dev_dbg(&hdmi->pdev->dev, "Hotplug interrupt received\n");
2101 hdmi->latest_intr_stat = intr_stat;
2103 /* Mute interrupts until handled */
2105 val = hdmi_readb(HDMI_IH_MUTE_PHY_STAT0);
2106 val |= HDMI_IH_MUTE_PHY_STAT0_HPD;
2107 hdmi_writeb(val, HDMI_IH_MUTE_PHY_STAT0);
2109 val = hdmi_readb(HDMI_PHY_MASK0);
2110 val |= HDMI_PHY_HPD;
2111 hdmi_writeb(val, HDMI_PHY_MASK0);
2113 /* Clear Hotplug interrupts */
2114 hdmi_writeb(HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0);
2116 schedule_delayed_work(&(hdmi->hotplug_work), msecs_to_jiffies(20));
2119 /* Check HDCP interrupt state */
2120 if (hdmi->hdmi_data.hdcp_enable) {
2121 val = hdmi_readb(HDMI_A_APIINTSTAT);
2123 /* Mute interrupts until interrupt handled */
2125 hdmi_writeb(val, HDMI_A_APIINTMSK);
2126 schedule_delayed_work(&(hdmi->hdcp_hdp_work), msecs_to_jiffies(50));
2130 spin_unlock_irqrestore(&hdmi->irq_lock, flags);
2134 static void mxc_hdmi_setup(struct mxc_hdmi *hdmi, unsigned long event)
2136 struct fb_videomode m;
2137 const struct fb_videomode *edid_mode;
2139 dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
2141 fb_var_to_videomode(&m, &hdmi->fbi->var);
2142 dump_fb_videomode(&m);
2144 dev_dbg(&hdmi->pdev->dev, "%s - video mode changed\n", __func__);
2147 if (!hdmi->requesting_vga_for_initialization) {
2148 /* Save mode if this isn't the result of requesting
2150 memcpy(&hdmi->previous_non_vga_mode, &m,
2151 sizeof(struct fb_videomode));
2152 if (!list_empty(&hdmi->fbi->modelist)) {
2153 edid_mode = fb_find_nearest_mode(&m, &hdmi->fbi->modelist);
2154 pr_debug("edid mode ");
2155 dump_fb_videomode((struct fb_videomode *)edid_mode);
2156 /* update fbi mode */
2157 hdmi->fbi->mode = (struct fb_videomode *)edid_mode;
2158 hdmi->vic = mxc_edid_mode_to_vic(edid_mode);
2162 hdmi_disable_overflow_interrupts();
2164 dev_dbg(&hdmi->pdev->dev, "CEA mode used vic=%d\n", hdmi->vic);
2165 if (hdmi->edid_cfg.hdmi_cap)
2166 hdmi->hdmi_data.video_mode.mDVI = false;
2168 dev_dbg(&hdmi->pdev->dev, "CEA mode vic=%d work in DVI\n", hdmi->vic);
2169 hdmi->hdmi_data.video_mode.mDVI = true;
2172 if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
2173 (hdmi->vic == 21) || (hdmi->vic == 22) ||
2174 (hdmi->vic == 2) || (hdmi->vic == 3) ||
2175 (hdmi->vic == 17) || (hdmi->vic == 18))
2176 hdmi->hdmi_data.colorimetry = eITU601;
2178 hdmi->hdmi_data.colorimetry = eITU709;
2180 if ((hdmi->vic == 10) || (hdmi->vic == 11) ||
2181 (hdmi->vic == 12) || (hdmi->vic == 13) ||
2182 (hdmi->vic == 14) || (hdmi->vic == 15) ||
2183 (hdmi->vic == 25) || (hdmi->vic == 26) ||
2184 (hdmi->vic == 27) || (hdmi->vic == 28) ||
2185 (hdmi->vic == 29) || (hdmi->vic == 30) ||
2186 (hdmi->vic == 35) || (hdmi->vic == 36) ||
2187 (hdmi->vic == 37) || (hdmi->vic == 38))
2188 hdmi->hdmi_data.video_mode.mPixelRepetitionOutput = 1;
2190 hdmi->hdmi_data.video_mode.mPixelRepetitionOutput = 0;
2192 hdmi->hdmi_data.video_mode.mPixelRepetitionInput = 0;
2194 /* TODO: Get input format from IPU (via FB driver iface) */
2195 hdmi->hdmi_data.enc_in_format = RGB;
2197 hdmi->hdmi_data.enc_out_format = RGB;
2199 /* YCbCr only enabled in HDMI mode */
2200 if (!hdmi->hdmi_data.video_mode.mDVI &&
2201 !hdmi->hdmi_data.rgb_out_enable) {
2202 if (hdmi->edid_cfg.cea_ycbcr444)
2203 hdmi->hdmi_data.enc_out_format = YCBCR444;
2204 else if (hdmi->edid_cfg.cea_ycbcr422)
2205 hdmi->hdmi_data.enc_out_format = YCBCR422_8BITS;
2208 /* IPU not support depth color output */
2209 hdmi->hdmi_data.enc_color_depth = 8;
2210 hdmi->hdmi_data.pix_repet_factor = 0;
2211 hdmi->hdmi_data.video_mode.mDataEnablePolarity = true;
2213 /* HDMI Initialization Step B.1 */
2214 hdmi_av_composer(hdmi);
2216 /* HDMI Initializateion Step B.2 */
2217 mxc_hdmi_phy_init(hdmi);
2219 /* HDMI Initialization Step B.3 */
2220 mxc_hdmi_enable_video_path(hdmi);
2222 /* not for DVI mode */
2223 if (hdmi->hdmi_data.video_mode.mDVI)
2224 dev_dbg(&hdmi->pdev->dev, "%s DVI mode\n", __func__);
2226 dev_dbg(&hdmi->pdev->dev, "%s CEA mode\n", __func__);
2228 /* HDMI Initialization Step E - Configure audio */
2229 hdmi_clk_regenerator_update_pixel_clock(hdmi->fbi->var.pixclock);
2230 hdmi_enable_audio_clk(hdmi);
2232 /* HDMI Initialization Step F - Configure AVI InfoFrame */
2233 hdmi_config_AVI(hdmi);
2236 hdmi_video_packetize(hdmi);
2237 hdmi_video_csc(hdmi);
2238 hdmi_video_sample(hdmi);
2240 mxc_hdmi_clear_overflow(hdmi);
2242 dev_dbg(&hdmi->pdev->dev, "%s exit\n\n", __func__);
2246 /* Wait until we are registered to enable interrupts */
2247 static void mxc_hdmi_fb_registered(struct mxc_hdmi *hdmi)
2249 unsigned long flags;
2254 spin_lock_irqsave(&hdmi->irq_lock, flags);
2256 dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
2258 hdmi_writeb(HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
2259 HDMI_PHY_I2CM_INT_ADDR);
2261 hdmi_writeb(HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
2262 HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
2263 HDMI_PHY_I2CM_CTLINT_ADDR);
2265 /* enable cable hot plug irq */
2266 hdmi_writeb((u8)~HDMI_PHY_HPD, HDMI_PHY_MASK0);
2268 /* Clear Hotplug interrupts */
2269 hdmi_writeb(HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0);
2271 /* Unmute interrupts */
2272 hdmi_writeb(~HDMI_IH_MUTE_PHY_STAT0_HPD, HDMI_IH_MUTE_PHY_STAT0);
2274 hdmi->fb_reg = true;
2276 spin_unlock_irqrestore(&hdmi->irq_lock, flags);
2280 static int mxc_hdmi_fb_event(struct notifier_block *nb,
2281 unsigned long val, void *v)
2283 struct fb_event *event = v;
2284 struct mxc_hdmi *hdmi = container_of(nb, struct mxc_hdmi, nb);
2286 if (strcmp(event->info->fix.id, hdmi->fbi->fix.id))
2290 case FB_EVENT_FB_REGISTERED:
2291 dev_dbg(&hdmi->pdev->dev, "event=FB_EVENT_FB_REGISTERED\n");
2292 mxc_hdmi_fb_registered(hdmi);
2293 hdmi_set_registered(1);
2296 case FB_EVENT_FB_UNREGISTERED:
2297 dev_dbg(&hdmi->pdev->dev, "event=FB_EVENT_FB_UNREGISTERED\n");
2298 hdmi->fb_reg = false;
2299 hdmi_set_registered(0);
2302 case FB_EVENT_MODE_CHANGE:
2303 dev_dbg(&hdmi->pdev->dev, "event=FB_EVENT_MODE_CHANGE\n");
2305 mxc_hdmi_setup(hdmi, val);
2308 case FB_EVENT_BLANK:
2309 if ((*((int *)event->data) == FB_BLANK_UNBLANK) &&
2310 (*((int *)event->data) != hdmi->blank)) {
2311 dev_dbg(&hdmi->pdev->dev,
2312 "event=FB_EVENT_BLANK - UNBLANK\n");
2314 hdmi->blank = *((int *)event->data);
2316 if (hdmi->fb_reg && hdmi->cable_plugin)
2317 mxc_hdmi_setup(hdmi, val);
2318 hdmi_set_blank_state(1);
2320 } else if (*((int *)event->data) != hdmi->blank) {
2321 dev_dbg(&hdmi->pdev->dev,
2322 "event=FB_EVENT_BLANK - BLANK\n");
2323 hdmi_set_blank_state(0);
2324 mxc_hdmi_abort_stream();
2326 mxc_hdmi_phy_disable(hdmi);
2328 hdmi->blank = *((int *)event->data);
2330 dev_dbg(&hdmi->pdev->dev,
2331 "FB BLANK state no changed!\n");
2335 case FB_EVENT_SUSPEND:
2336 dev_dbg(&hdmi->pdev->dev,
2337 "event=FB_EVENT_SUSPEND\n");
2339 if (hdmi->blank == FB_BLANK_UNBLANK) {
2340 mxc_hdmi_phy_disable(hdmi);
2341 clk_disable(hdmi->hdmi_iahb_clk);
2342 clk_disable(hdmi->hdmi_isfr_clk);
2346 case FB_EVENT_RESUME:
2347 dev_dbg(&hdmi->pdev->dev,
2348 "event=FB_EVENT_RESUME\n");
2350 if (hdmi->blank == FB_BLANK_UNBLANK) {
2351 clk_enable(hdmi->hdmi_iahb_clk);
2352 clk_enable(hdmi->hdmi_isfr_clk);
2353 mxc_hdmi_phy_init(hdmi);
2361 static void hdmi_init_route(struct mxc_hdmi *hdmi)
2363 uint32_t hdmi_mux_setting, reg;
2364 int ipu_id, disp_id;
2366 ipu_id = mxc_hdmi_ipu_id;
2367 disp_id = mxc_hdmi_disp_id;
2369 if ((ipu_id > 1) || (ipu_id < 0)) {
2370 pr_err("Invalid IPU select for HDMI: %d. Set to 0\n", ipu_id);
2374 if ((disp_id > 1) || (disp_id < 0)) {
2375 pr_err("Invalid DI select for HDMI: %d. Set to 0\n", disp_id);
2379 reg = readl(hdmi->gpr_hdmi_base);
2381 /* Configure the connection between IPU1/2 and HDMI */
2382 hdmi_mux_setting = 2*ipu_id + disp_id;
2384 /* GPR3, bits 2-3 = HDMI_MUX_CTL */
2386 reg |= hdmi_mux_setting << 2;
2388 writel(reg, hdmi->gpr_hdmi_base);
2390 /* Set HDMI event as SDMA event2 for HDMI audio */
2391 reg = readl(hdmi->gpr_sdma_base);
2393 writel(reg, hdmi->gpr_sdma_base);
2396 static void hdmi_hdcp_get_property(struct platform_device *pdev)
2398 struct device_node *np = pdev->dev.of_node;
2400 /* Check hdcp enable by dts.*/
2401 hdcp_init = of_property_read_bool(np, "fsl,hdcp");
2403 dev_dbg(&pdev->dev, "hdcp enable\n");
2405 dev_dbg(&pdev->dev, "hdcp disable\n");
2408 static void hdmi_get_of_property(struct mxc_hdmi *hdmi)
2410 struct platform_device *pdev = hdmi->pdev;
2411 struct device_node *np = pdev->dev.of_node;
2412 const struct of_device_id *of_id =
2413 of_match_device(imx_hdmi_dt_ids, &pdev->dev);
2415 u32 phy_reg_vlev = 0, phy_reg_cksymtx = 0;
2418 pdev->id_entry = of_id->data;
2419 hdmi->cpu_type = pdev->id_entry->driver_data;
2422 /* HDMI PHY register vlev and cksymtx preperty is optional.
2423 * It is for specific board to pass HCT electrical part.
2424 * Default value will been setting in HDMI PHY config function
2425 * if it is not define in device tree.
2427 ret = of_property_read_u32(np, "fsl,phy_reg_vlev", &phy_reg_vlev);
2429 dev_dbg(&pdev->dev, "No board specific HDMI PHY vlev\n");
2431 ret = of_property_read_u32(np, "fsl,phy_reg_cksymtx", &phy_reg_cksymtx);
2433 dev_dbg(&pdev->dev, "No board specific HDMI PHY cksymtx\n");
2435 /* Specific phy config */
2436 hdmi->phy_config.reg_cksymtx = phy_reg_cksymtx;
2437 hdmi->phy_config.reg_vlev = phy_reg_vlev;
2441 /* HDMI Initialization Step A */
2442 static int mxc_hdmi_disp_init(struct mxc_dispdrv_handle *disp,
2443 struct mxc_dispdrv_setting *setting)
2447 const struct fb_videomode *mode;
2448 struct fb_videomode m;
2449 struct mxc_hdmi *hdmi = mxc_dispdrv_getdata(disp);
2450 int irq = platform_get_irq(hdmi->pdev, 0);
2452 dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
2454 /* Check hdmi disp init once */
2456 dev_err(&hdmi->pdev->dev,
2457 "Error only one HDMI output support now!\n");
2461 hdmi_get_of_property(hdmi);
2466 /* Setting HDMI default to blank state */
2467 hdmi->blank = FB_BLANK_POWERDOWN;
2469 ret = ipu_di_to_crtc(&hdmi->pdev->dev, mxc_hdmi_ipu_id,
2470 mxc_hdmi_disp_id, &setting->crtc);
2474 setting->if_fmt = IPU_PIX_FMT_RGB24;
2476 hdmi->dft_mode_str = setting->dft_mode_str;
2477 hdmi->default_bpp = setting->default_bpp;
2478 dev_dbg(&hdmi->pdev->dev, "%s - default mode %s bpp=%d\n",
2479 __func__, hdmi->dft_mode_str, hdmi->default_bpp);
2481 hdmi->fbi = setting->fbi;
2483 hdmi_init_route(hdmi);
2485 hdmi->hdmi_isfr_clk = clk_get(&hdmi->pdev->dev, "hdmi_isfr");
2486 if (IS_ERR(hdmi->hdmi_isfr_clk)) {
2487 ret = PTR_ERR(hdmi->hdmi_isfr_clk);
2488 dev_err(&hdmi->pdev->dev,
2489 "Unable to get HDMI clk: %d\n", ret);
2493 ret = clk_prepare_enable(hdmi->hdmi_isfr_clk);
2495 dev_err(&hdmi->pdev->dev,
2496 "Cannot enable HDMI isfr clock: %d\n", ret);
2500 hdmi->hdmi_iahb_clk = clk_get(&hdmi->pdev->dev, "hdmi_iahb");
2501 if (IS_ERR(hdmi->hdmi_iahb_clk)) {
2502 ret = PTR_ERR(hdmi->hdmi_iahb_clk);
2503 dev_err(&hdmi->pdev->dev,
2504 "Unable to get HDMI clk: %d\n", ret);
2508 ret = clk_prepare_enable(hdmi->hdmi_iahb_clk);
2510 dev_err(&hdmi->pdev->dev,
2511 "Cannot enable HDMI iahb clock: %d\n", ret);
2515 dev_dbg(&hdmi->pdev->dev, "Enabled HDMI clocks\n");
2517 /* Init DDC pins for HDCP */
2519 hdmi->pinctrl = devm_pinctrl_get_select_default(&hdmi->pdev->dev);
2520 if (IS_ERR(hdmi->pinctrl)) {
2521 dev_err(&hdmi->pdev->dev, "can't get/select DDC pinctrl\n");
2526 /* Product and revision IDs */
2527 dev_info(&hdmi->pdev->dev,
2528 "Detected HDMI controller 0x%x:0x%x:0x%x:0x%x\n",
2529 hdmi_readb(HDMI_DESIGN_ID),
2530 hdmi_readb(HDMI_REVISION_ID),
2531 hdmi_readb(HDMI_PRODUCT_ID0),
2532 hdmi_readb(HDMI_PRODUCT_ID1));
2534 /* To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
2535 * N and cts values before enabling phy */
2536 hdmi_init_clk_regenerator();
2538 INIT_LIST_HEAD(&hdmi->fbi->modelist);
2540 spin_lock_init(&hdmi->irq_lock);
2542 /* Set the default mode and modelist when disp init. */
2543 fb_find_mode(&hdmi->fbi->var, hdmi->fbi,
2544 hdmi->dft_mode_str, NULL, 0, NULL,
2549 fb_destroy_modelist(&hdmi->fbi->modelist);
2551 /*Add all no interlaced CEA mode to default modelist */
2552 for (i = 0; i < ARRAY_SIZE(mxc_cea_mode); i++) {
2553 mode = &mxc_cea_mode[i];
2554 if (!(mode->vmode & FB_VMODE_INTERLACED) && (mode->xres != 0))
2555 fb_add_videomode(mode, &hdmi->fbi->modelist);
2560 /* Find a nearest mode in default modelist */
2561 fb_var_to_videomode(&m, &hdmi->fbi->var);
2562 dump_fb_videomode(&m);
2564 hdmi->dft_mode_set = false;
2565 /* Save default video mode */
2566 memcpy(&hdmi->default_mode, &m, sizeof(struct fb_videomode));
2568 mode = fb_find_nearest_mode(&m, &hdmi->fbi->modelist);
2570 pr_err("%s: could not find mode in modelist\n", __func__);
2574 fb_videomode_to_var(&hdmi->fbi->var, mode);
2576 /* update fbi mode */
2577 hdmi->fbi->mode = (struct fb_videomode *)mode;
2579 /* Default setting HDMI working in HDMI mode*/
2580 hdmi->edid_cfg.hdmi_cap = true;
2582 INIT_DELAYED_WORK(&hdmi->hotplug_work, hotplug_worker);
2583 INIT_DELAYED_WORK(&hdmi->hdcp_hdp_work, hdcp_hdp_worker);
2585 /* Configure registers related to HDMI interrupt
2586 * generation before registering IRQ. */
2587 hdmi_writeb(HDMI_PHY_HPD, HDMI_PHY_POL0);
2589 /* Clear Hotplug interrupts */
2590 hdmi_writeb(HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0);
2592 hdmi->nb.notifier_call = mxc_hdmi_fb_event;
2593 ret = fb_register_client(&hdmi->nb);
2597 memset(&hdmi->hdmi_data, 0, sizeof(struct hdmi_data_info));
2599 /* Default HDMI working in RGB mode */
2600 hdmi->hdmi_data.rgb_out_enable = true;
2602 ret = devm_request_irq(&hdmi->pdev->dev, irq, mxc_hdmi_hotplug, IRQF_SHARED,
2603 dev_name(&hdmi->pdev->dev), hdmi);
2605 dev_err(&hdmi->pdev->dev,
2606 "Unable to request irq: %d\n", ret);
2610 ret = device_create_file(&hdmi->pdev->dev, &dev_attr_fb_name);
2612 dev_warn(&hdmi->pdev->dev,
2613 "cound not create sys node for fb name\n");
2614 ret = device_create_file(&hdmi->pdev->dev, &dev_attr_cable_state);
2616 dev_warn(&hdmi->pdev->dev,
2617 "cound not create sys node for cable state\n");
2618 ret = device_create_file(&hdmi->pdev->dev, &dev_attr_edid);
2620 dev_warn(&hdmi->pdev->dev,
2621 "cound not create sys node for edid\n");
2623 ret = device_create_file(&hdmi->pdev->dev, &dev_attr_rgb_out_enable);
2625 dev_warn(&hdmi->pdev->dev,
2626 "cound not create sys node for rgb out enable\n");
2628 ret = device_create_file(&hdmi->pdev->dev, &dev_attr_hdcp_enable);
2630 dev_warn(&hdmi->pdev->dev,
2631 "cound not create sys node for hdcp enable\n");
2633 dev_dbg(&hdmi->pdev->dev, "%s exit\n", __func__);
2640 free_irq(irq, hdmi);
2642 clk_disable_unprepare(hdmi->hdmi_iahb_clk);
2644 clk_put(hdmi->hdmi_iahb_clk);
2646 clk_disable_unprepare(hdmi->hdmi_isfr_clk);
2648 clk_put(hdmi->hdmi_isfr_clk);
2650 dev_dbg(&hdmi->pdev->dev, "%s error exit\n", __func__);
2655 static void mxc_hdmi_disp_deinit(struct mxc_dispdrv_handle *disp)
2657 struct mxc_hdmi *hdmi = mxc_dispdrv_getdata(disp);
2659 dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
2661 fb_unregister_client(&hdmi->nb);
2663 clk_disable_unprepare(hdmi->hdmi_isfr_clk);
2664 clk_put(hdmi->hdmi_isfr_clk);
2665 clk_disable_unprepare(hdmi->hdmi_iahb_clk);
2666 clk_put(hdmi->hdmi_iahb_clk);
2668 platform_device_unregister(hdmi->pdev);
2670 hdmi_inited = false;
2673 static struct mxc_dispdrv_driver mxc_hdmi_drv = {
2674 .name = DISPDRV_HDMI,
2675 .init = mxc_hdmi_disp_init,
2676 .deinit = mxc_hdmi_disp_deinit,
2677 .enable = mxc_hdmi_power_on,
2678 .disable = mxc_hdmi_power_off,
2682 static int mxc_hdmi_open(struct inode *inode, struct file *file)
2687 static long mxc_hdmi_ioctl(struct file *file,
2688 unsigned int cmd, unsigned long arg)
2690 int __user *argp = (void __user *)arg;
2694 case HDMI_IOC_GET_RESOURCE:
2695 ret = copy_to_user(argp, &g_hdmi->hdmi_data,
2696 sizeof(g_hdmi->hdmi_data)) ? -EFAULT : 0;
2698 case HDMI_IOC_GET_CPU_TYPE:
2699 *argp = g_hdmi->cpu_type;
2702 pr_debug("Unsupport cmd %d\n", cmd);
2708 static int mxc_hdmi_release(struct inode *inode, struct file *file)
2713 static const struct file_operations mxc_hdmi_fops = {
2714 .owner = THIS_MODULE,
2715 .open = mxc_hdmi_open,
2716 .release = mxc_hdmi_release,
2717 .unlocked_ioctl = mxc_hdmi_ioctl,
2721 static int mxc_hdmi_probe(struct platform_device *pdev)
2723 struct mxc_hdmi *hdmi;
2724 struct device *temp_class;
2725 struct resource *res;
2728 /* Check I2C driver is loaded and available
2729 * check hdcp function is enable by dts */
2730 hdmi_hdcp_get_property(pdev);
2731 if (!hdmi_i2c && !hdcp_init)
2734 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2738 hdmi = devm_kzalloc(&pdev->dev,
2739 sizeof(struct mxc_hdmi),
2742 dev_err(&pdev->dev, "Cannot allocate device data\n");
2748 hdmi_major = register_chrdev(hdmi_major, "mxc_hdmi", &mxc_hdmi_fops);
2749 if (hdmi_major < 0) {
2750 printk(KERN_ERR "HDMI: unable to get a major for HDMI\n");
2755 hdmi_class = class_create(THIS_MODULE, "mxc_hdmi");
2756 if (IS_ERR(hdmi_class)) {
2757 ret = PTR_ERR(hdmi_class);
2758 goto err_out_chrdev;
2761 temp_class = device_create(hdmi_class, NULL, MKDEV(hdmi_major, 0),
2763 if (IS_ERR(temp_class)) {
2764 ret = PTR_ERR(temp_class);
2770 hdmi->core_pdev = platform_device_alloc("mxc_hdmi_core", -1);
2771 if (!hdmi->core_pdev) {
2772 pr_err("%s failed platform_device_alloc for hdmi core\n",
2778 hdmi->gpr_base = ioremap(res->start, resource_size(res));
2779 if (!hdmi->gpr_base) {
2780 dev_err(&pdev->dev, "ioremap failed\n");
2785 hdmi->gpr_hdmi_base = hdmi->gpr_base + 3;
2786 hdmi->gpr_sdma_base = hdmi->gpr_base;
2788 hdmi_inited = false;
2790 hdmi->disp_mxc_hdmi = mxc_dispdrv_register(&mxc_hdmi_drv);
2791 if (IS_ERR(hdmi->disp_mxc_hdmi)) {
2792 dev_err(&pdev->dev, "Failed to register dispdrv - 0x%x\n",
2793 (int)hdmi->disp_mxc_hdmi);
2794 ret = (int)hdmi->disp_mxc_hdmi;
2797 mxc_dispdrv_setdata(hdmi->disp_mxc_hdmi, hdmi);
2799 platform_set_drvdata(pdev, hdmi);
2803 iounmap(hdmi->gpr_base);
2805 platform_device_put(hdmi->core_pdev);
2809 device_destroy(hdmi_class, MKDEV(hdmi_major, 0));
2810 class_destroy(hdmi_class);
2812 unregister_chrdev(hdmi_major, "mxc_hdmi");
2817 static int mxc_hdmi_remove(struct platform_device *pdev)
2819 struct mxc_hdmi *hdmi = platform_get_drvdata(pdev);
2820 int irq = platform_get_irq(pdev, 0);
2822 fb_unregister_client(&hdmi->nb);
2824 mxc_dispdrv_puthandle(hdmi->disp_mxc_hdmi);
2825 mxc_dispdrv_unregister(hdmi->disp_mxc_hdmi);
2826 iounmap(hdmi->gpr_base);
2827 /* No new work will be scheduled, wait for running ISR */
2828 free_irq(irq, hdmi);
2835 static struct platform_driver mxc_hdmi_driver = {
2836 .probe = mxc_hdmi_probe,
2837 .remove = mxc_hdmi_remove,
2840 .of_match_table = imx_hdmi_dt_ids,
2841 .owner = THIS_MODULE,
2845 static int __init mxc_hdmi_init(void)
2847 return platform_driver_register(&mxc_hdmi_driver);
2849 module_init(mxc_hdmi_init);
2851 static void __exit mxc_hdmi_exit(void)
2853 if (hdmi_major > 0) {
2854 device_destroy(hdmi_class, MKDEV(hdmi_major, 0));
2855 class_destroy(hdmi_class);
2856 unregister_chrdev(hdmi_major, "mxc_hdmi");
2860 platform_driver_unregister(&mxc_hdmi_driver);
2862 module_exit(mxc_hdmi_exit);
2864 static int mxc_hdmi_i2c_probe(struct i2c_client *client,
2865 const struct i2c_device_id *id)
2867 if (!i2c_check_functionality(client->adapter,
2868 I2C_FUNC_SMBUS_BYTE | I2C_FUNC_I2C))
2876 static int mxc_hdmi_i2c_remove(struct i2c_client *client)
2882 static const struct of_device_id imx_hdmi_i2c_match[] = {
2883 { .compatible = "fsl,imx6-hdmi-i2c", },
2887 static const struct i2c_device_id mxc_hdmi_i2c_id[] = {
2888 { "mxc_hdmi_i2c", 0 },
2891 MODULE_DEVICE_TABLE(i2c, mxc_hdmi_i2c_id);
2893 static struct i2c_driver mxc_hdmi_i2c_driver = {
2895 .name = "mxc_hdmi_i2c",
2896 .of_match_table = imx_hdmi_i2c_match,
2898 .probe = mxc_hdmi_i2c_probe,
2899 .remove = mxc_hdmi_i2c_remove,
2900 .id_table = mxc_hdmi_i2c_id,
2903 static int __init mxc_hdmi_i2c_init(void)
2905 return i2c_add_driver(&mxc_hdmi_i2c_driver);
2908 static void __exit mxc_hdmi_i2c_exit(void)
2910 i2c_del_driver(&mxc_hdmi_i2c_driver);
2913 module_init(mxc_hdmi_i2c_init);
2914 module_exit(mxc_hdmi_i2c_exit);
2916 MODULE_AUTHOR("Freescale Semiconductor, Inc.");