drivers/watchdog/s3c2410_wdt.c

   1 /* linux/drivers/char/watchdog/s3c2410_wdt.c
   2  *
   3  * Copyright (c) 2004 Simtec Electronics
   4  *      Ben Dooks <ben@simtec.co.uk>
   5  *
   6  * S3C2410 Watchdog Timer Support
   7  *
   8  * Based on, softdog.c by Alan Cox,
   9  *     (c) Copyright 1996 Alan Cox <alan@lxorguk.ukuu.org.uk>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  24 */
  25
  26 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  27
  28 #include <linux/module.h>
  29 #include <linux/moduleparam.h>
  30 #include <linux/types.h>
  31 #include <linux/timer.h>
  32 #include <linux/watchdog.h>
  33 #include <linux/init.h>
  34 #include <linux/platform_device.h>
  35 #include <linux/interrupt.h>
  36 #include <linux/clk.h>
  37 #include <linux/uaccess.h>
  38 #include <linux/io.h>
  39 #include <linux/cpufreq.h>
  40 #include <linux/slab.h>
  41 #include <linux/err.h>
  42 #include <linux/of.h>
  43 #include <linux/mfd/syscon.h>
  44 #include <linux/regmap.h>
  45
  46 #define S3C2410_WTCON           0x00
  47 #define S3C2410_WTDAT           0x04
  48 #define S3C2410_WTCNT           0x08
  49
  50 #define S3C2410_WTCON_RSTEN     (1 << 0)
  51 #define S3C2410_WTCON_INTEN     (1 << 2)
  52 #define S3C2410_WTCON_ENABLE    (1 << 5)
  53
  54 #define S3C2410_WTCON_DIV16     (0 << 3)
  55 #define S3C2410_WTCON_DIV32     (1 << 3)
  56 #define S3C2410_WTCON_DIV64     (2 << 3)
  57 #define S3C2410_WTCON_DIV128    (3 << 3)
  58
  59 #define S3C2410_WTCON_PRESCALE(x)       ((x) << 8)
  60 #define S3C2410_WTCON_PRESCALE_MASK     (0xff << 8)
  61
  62 #define CONFIG_S3C2410_WATCHDOG_ATBOOT          (0)
  63 #define CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME    (15)
  64
  65 #define EXYNOS5_WDT_DISABLE_REG_OFFSET          0x0408
  66 #define EXYNOS5_WDT_MASK_RESET_REG_OFFSET       0x040c
  67 #define QUIRK_HAS_PMU_CONFIG                    (1 << 0)
  68
  69 static bool nowayout    = WATCHDOG_NOWAYOUT;
  70 static int tmr_margin;
  71 static int tmr_atboot   = CONFIG_S3C2410_WATCHDOG_ATBOOT;
  72 static int soft_noboot;
  73 static int debug;
  74
  75 module_param(tmr_margin,  int, 0);
  76 module_param(tmr_atboot,  int, 0);
  77 module_param(nowayout,   bool, 0);
  78 module_param(soft_noboot, int, 0);
  79 module_param(debug,       int, 0);
  80
  81 MODULE_PARM_DESC(tmr_margin, "Watchdog tmr_margin in seconds. (default="
  82                 __MODULE_STRING(CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME) ")");
  83 MODULE_PARM_DESC(tmr_atboot,
  84                 "Watchdog is started at boot time if set to 1, default="
  85                         __MODULE_STRING(CONFIG_S3C2410_WATCHDOG_ATBOOT));
  86 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
  87                         __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  88 MODULE_PARM_DESC(soft_noboot, "Watchdog action, set to 1 to ignore reboots, "
  89                         "0 to reboot (default 0)");
  90 MODULE_PARM_DESC(debug, "Watchdog debug, set to >1 for debug (default 0)");
  91
  92 /**
  93  * struct s3c2410_wdt_variant - Per-variant config data
  94  *
  95  * @disable_reg: Offset in pmureg for the register that disables the watchdog
  96  * timer reset functionality.
  97  * @mask_reset_reg: Offset in pmureg for the register that masks the watchdog
  98  * timer reset functionality.
  99  * @mask_bit: Bit number for the watchdog timer in the disable register and the
 100  * mask reset register.
 101  * @quirks: A bitfield of quirks.
 102  */
 103
 104 struct s3c2410_wdt_variant {
 105         int disable_reg;
 106         int mask_reset_reg;
 107         int mask_bit;
 108         u32 quirks;
 109 };
 110
 111 struct s3c2410_wdt {
 112         struct device           *dev;
 113         struct clk              *clock;
 114         void __iomem            *reg_base;
 115         unsigned int            count;
 116         spinlock_t              lock;
 117         unsigned long           wtcon_save;
 118         unsigned long           wtdat_save;
 119         struct watchdog_device  wdt_device;
 120         struct notifier_block   freq_transition;
 121         struct s3c2410_wdt_variant *drv_data;
 122         struct regmap *pmureg;
 123 };
 124
 125 static const struct s3c2410_wdt_variant drv_data_s3c2410 = {
 126         .quirks = 0
 127 };
 128
 129 #ifdef CONFIG_OF
 130 static const struct s3c2410_wdt_variant drv_data_exynos5250  = {
 131         .disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET,
 132         .mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET,
 133         .mask_bit = 20,
 134         .quirks = QUIRK_HAS_PMU_CONFIG
 135 };
 136
 137 static const struct s3c2410_wdt_variant drv_data_exynos5420 = {
 138         .disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET,
 139         .mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET,
 140         .mask_bit = 0,
 141         .quirks = QUIRK_HAS_PMU_CONFIG
 142 };
 143
 144 static const struct of_device_id s3c2410_wdt_match[] = {
 145         { .compatible = "samsung,s3c2410-wdt",
 146           .data = &drv_data_s3c2410 },
 147         { .compatible = "samsung,exynos5250-wdt",
 148           .data = &drv_data_exynos5250 },
 149         { .compatible = "samsung,exynos5420-wdt",
 150           .data = &drv_data_exynos5420 },
 151         {},
 152 };
 153 MODULE_DEVICE_TABLE(of, s3c2410_wdt_match);
 154 #endif
 155
 156 static const struct platform_device_id s3c2410_wdt_ids[] = {
 157         {
 158                 .name = "s3c2410-wdt",
 159                 .driver_data = (unsigned long)&drv_data_s3c2410,
 160         },
 161         {}
 162 };
 163 MODULE_DEVICE_TABLE(platform, s3c2410_wdt_ids);
 164
 165 /* watchdog control routines */
 166
 167 #define DBG(fmt, ...)                                   \
 168 do {                                                    \
 169         if (debug)                                      \
 170                 pr_info(fmt, ##__VA_ARGS__);            \
 171 } while (0)
 172
 173 /* functions */
 174
 175 static inline struct s3c2410_wdt *freq_to_wdt(struct notifier_block *nb)
 176 {
 177         return container_of(nb, struct s3c2410_wdt, freq_transition);
 178 }
 179
 180 static int s3c2410wdt_mask_and_disable_reset(struct s3c2410_wdt *wdt, bool mask)
 181 {
 182         int ret;
 183         u32 mask_val = 1 << wdt->drv_data->mask_bit;
 184         u32 val = 0;
 185
 186         /* No need to do anything if no PMU CONFIG needed */
 187         if (!(wdt->drv_data->quirks & QUIRK_HAS_PMU_CONFIG))
 188                 return 0;
 189
 190         if (mask)
 191                 val = mask_val;
 192
 193         ret = regmap_update_bits(wdt->pmureg,
 194                         wdt->drv_data->disable_reg,
 195                         mask_val, val);
 196         if (ret < 0)
 197                 goto error;
 198
 199         ret = regmap_update_bits(wdt->pmureg,
 200                         wdt->drv_data->mask_reset_reg,
 201                         mask_val, val);
 202  error:
 203         if (ret < 0)
 204                 dev_err(wdt->dev, "failed to update reg(%d)\n", ret);
 205
 206         return ret;
 207 }
 208
 209 static int s3c2410wdt_keepalive(struct watchdog_device *wdd)
 210 {
 211         struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
 212
 213         spin_lock(&wdt->lock);
 214         writel(wdt->count, wdt->reg_base + S3C2410_WTCNT);
 215         spin_unlock(&wdt->lock);
 216
 217         return 0;
 218 }
 219
 220 static void __s3c2410wdt_stop(struct s3c2410_wdt *wdt)
 221 {
 222         unsigned long wtcon;
 223
 224         wtcon = readl(wdt->reg_base + S3C2410_WTCON);
 225         wtcon &= ~(S3C2410_WTCON_ENABLE | S3C2410_WTCON_RSTEN);
 226         writel(wtcon, wdt->reg_base + S3C2410_WTCON);
 227 }
 228
 229 static int s3c2410wdt_stop(struct watchdog_device *wdd)
 230 {
 231         struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
 232
 233         spin_lock(&wdt->lock);
 234         __s3c2410wdt_stop(wdt);
 235         spin_unlock(&wdt->lock);
 236
 237         return 0;
 238 }
 239
 240 static int s3c2410wdt_start(struct watchdog_device *wdd)
 241 {
 242         unsigned long wtcon;
 243         struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
 244
 245         spin_lock(&wdt->lock);
 246
 247         __s3c2410wdt_stop(wdt);
 248
 249         wtcon = readl(wdt->reg_base + S3C2410_WTCON);
 250         wtcon |= S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128;
 251
 252         if (soft_noboot) {
 253                 wtcon |= S3C2410_WTCON_INTEN;
 254                 wtcon &= ~S3C2410_WTCON_RSTEN;
 255         } else {
 256                 wtcon &= ~S3C2410_WTCON_INTEN;
 257                 wtcon |= S3C2410_WTCON_RSTEN;
 258         }
 259
 260         DBG("%s: count=0x%08x, wtcon=%08lx\n",
 261             __func__, wdt->count, wtcon);
 262
 263         writel(wdt->count, wdt->reg_base + S3C2410_WTDAT);
 264         writel(wdt->count, wdt->reg_base + S3C2410_WTCNT);
 265         writel(wtcon, wdt->reg_base + S3C2410_WTCON);
 266         spin_unlock(&wdt->lock);
 267
 268         return 0;
 269 }
 270
 271 static inline int s3c2410wdt_is_running(struct s3c2410_wdt *wdt)
 272 {
 273         return readl(wdt->reg_base + S3C2410_WTCON) & S3C2410_WTCON_ENABLE;
 274 }
 275
 276 static int s3c2410wdt_set_heartbeat(struct watchdog_device *wdd, unsigned timeout)
 277 {
 278         struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
 279         unsigned long freq = clk_get_rate(wdt->clock);
 280         unsigned int count;
 281         unsigned int divisor = 1;
 282         unsigned long wtcon;
 283
 284         if (timeout < 1)
 285                 return -EINVAL;
 286
 287         freq = DIV_ROUND_UP(freq, 128);
 288         count = timeout * freq;
 289
 290         DBG("%s: count=%d, timeout=%d, freq=%lu\n",
 291             __func__, count, timeout, freq);
 292
 293         /* if the count is bigger than the watchdog register,
 294            then work out what we need to do (and if) we can
 295            actually make this value
 296         */
 297
 298         if (count >= 0x10000) {
 299                 divisor = DIV_ROUND_UP(count, 0xffff);
 300
 301                 if (divisor > 0x100) {
 302                         dev_err(wdt->dev, "timeout %d too big\n", timeout);
 303                         return -EINVAL;
 304                 }
 305         }
 306
 307         DBG("%s: timeout=%d, divisor=%d, count=%d (%08x)\n",
 308             __func__, timeout, divisor, count, DIV_ROUND_UP(count, divisor));
 309
 310         count = DIV_ROUND_UP(count, divisor);
 311         wdt->count = count;
 312
 313         /* update the pre-scaler */
 314         wtcon = readl(wdt->reg_base + S3C2410_WTCON);
 315         wtcon &= ~S3C2410_WTCON_PRESCALE_MASK;
 316         wtcon |= S3C2410_WTCON_PRESCALE(divisor-1);
 317
 318         writel(count, wdt->reg_base + S3C2410_WTDAT);
 319         writel(wtcon, wdt->reg_base + S3C2410_WTCON);
 320
 321         wdd->timeout = (count * divisor) / freq;
 322
 323         return 0;
 324 }
 325
 326 #define OPTIONS (WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE)
 327
 328 static const struct watchdog_info s3c2410_wdt_ident = {
 329         .options          =     OPTIONS,
 330         .firmware_version =     0,
 331         .identity         =     "S3C2410 Watchdog",
 332 };
 333
 334 static struct watchdog_ops s3c2410wdt_ops = {
 335         .owner = THIS_MODULE,
 336         .start = s3c2410wdt_start,
 337         .stop = s3c2410wdt_stop,
 338         .ping = s3c2410wdt_keepalive,
 339         .set_timeout = s3c2410wdt_set_heartbeat,
 340 };
 341
 342 static struct watchdog_device s3c2410_wdd = {
 343         .info = &s3c2410_wdt_ident,
 344         .ops = &s3c2410wdt_ops,
 345         .timeout = CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME,
 346 };
 347
 348 /* interrupt handler code */
 349
 350 static irqreturn_t s3c2410wdt_irq(int irqno, void *param)
 351 {
 352         struct s3c2410_wdt *wdt = platform_get_drvdata(param);
 353
 354         dev_info(wdt->dev, "watchdog timer expired (irq)\n");
 355
 356         s3c2410wdt_keepalive(&wdt->wdt_device);
 357         return IRQ_HANDLED;
 358 }
 359
 360 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ
 361
 362 static int s3c2410wdt_cpufreq_transition(struct notifier_block *nb,
 363                                           unsigned long val, void *data)
 364 {
 365         int ret;
 366         struct s3c2410_wdt *wdt = freq_to_wdt(nb);
 367
 368         if (!s3c2410wdt_is_running(wdt))
 369                 goto done;
 370
 371         if (val == CPUFREQ_PRECHANGE) {
 372                 /* To ensure that over the change we don't cause the
 373                  * watchdog to trigger, we perform an keep-alive if
 374                  * the watchdog is running.
 375                  */
 376
 377                 s3c2410wdt_keepalive(&wdt->wdt_device);
 378         } else if (val == CPUFREQ_POSTCHANGE) {
 379                 s3c2410wdt_stop(&wdt->wdt_device);
 380
 381                 ret = s3c2410wdt_set_heartbeat(&wdt->wdt_device,
 382                                                 wdt->wdt_device.timeout);
 383
 384                 if (ret >= 0)
 385                         s3c2410wdt_start(&wdt->wdt_device);
 386                 else
 387                         goto err;
 388         }
 389
 390 done:
 391         return 0;
 392
 393  err:
 394         dev_err(wdt->dev, "cannot set new value for timeout %d\n",
 395                                 wdt->wdt_device.timeout);
 396         return ret;
 397 }
 398
 399 static inline int s3c2410wdt_cpufreq_register(struct s3c2410_wdt *wdt)
 400 {
 401         wdt->freq_transition.notifier_call = s3c2410wdt_cpufreq_transition;
 402
 403         return cpufreq_register_notifier(&wdt->freq_transition,
 404                                          CPUFREQ_TRANSITION_NOTIFIER);
 405 }
 406
 407 static inline void s3c2410wdt_cpufreq_deregister(struct s3c2410_wdt *wdt)
 408 {
 409         wdt->freq_transition.notifier_call = s3c2410wdt_cpufreq_transition;
 410
 411         cpufreq_unregister_notifier(&wdt->freq_transition,
 412                                     CPUFREQ_TRANSITION_NOTIFIER);
 413 }
 414
 415 #else
 416
 417 static inline int s3c2410wdt_cpufreq_register(struct s3c2410_wdt *wdt)
 418 {
 419         return 0;
 420 }
 421
 422 static inline void s3c2410wdt_cpufreq_deregister(struct s3c2410_wdt *wdt)
 423 {
 424 }
 425 #endif
 426
 427 /* s3c2410_get_wdt_driver_data */
 428 static inline struct s3c2410_wdt_variant *
 429 get_wdt_drv_data(struct platform_device *pdev)
 430 {
 431         if (pdev->dev.of_node) {
 432                 const struct of_device_id *match;
 433                 match = of_match_node(s3c2410_wdt_match, pdev->dev.of_node);
 434                 return (struct s3c2410_wdt_variant *)match->data;
 435         } else {
 436                 return (struct s3c2410_wdt_variant *)
 437                         platform_get_device_id(pdev)->driver_data;
 438         }
 439 }
 440
 441 static int s3c2410wdt_probe(struct platform_device *pdev)
 442 {
 443         struct device *dev;
 444         struct s3c2410_wdt *wdt;
 445         struct resource *wdt_mem;
 446         struct resource *wdt_irq;
 447         unsigned int wtcon;
 448         int started = 0;
 449         int ret;
 450
 451         DBG("%s: probe=%p\n", __func__, pdev);
 452
 453         dev = &pdev->dev;
 454
 455         wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
 456         if (!wdt)
 457                 return -ENOMEM;
 458
 459         wdt->dev = &pdev->dev;
 460         spin_lock_init(&wdt->lock);
 461         wdt->wdt_device = s3c2410_wdd;
 462
 463         wdt->drv_data = get_wdt_drv_data(pdev);
 464         if (wdt->drv_data->quirks & QUIRK_HAS_PMU_CONFIG) {
 465                 wdt->pmureg = syscon_regmap_lookup_by_phandle(dev->of_node,
 466                                                 "samsung,syscon-phandle");
 467                 if (IS_ERR(wdt->pmureg)) {
 468                         dev_err(dev, "syscon regmap lookup failed.\n");
 469                         return PTR_ERR(wdt->pmureg);
 470                 }
 471         }
 472
 473         wdt_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 474         if (wdt_irq == NULL) {
 475                 dev_err(dev, "no irq resource specified\n");
 476                 ret = -ENOENT;
 477                 goto err;
 478         }
 479
 480         /* get the memory region for the watchdog timer */
 481         wdt_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 482         wdt->reg_base = devm_ioremap_resource(dev, wdt_mem);
 483         if (IS_ERR(wdt->reg_base)) {
 484                 ret = PTR_ERR(wdt->reg_base);
 485                 goto err;
 486         }
 487
 488         DBG("probe: mapped reg_base=%p\n", wdt->reg_base);
 489
 490         wdt->clock = devm_clk_get(dev, "watchdog");
 491         if (IS_ERR(wdt->clock)) {
 492                 dev_err(dev, "failed to find watchdog clock source\n");
 493                 ret = PTR_ERR(wdt->clock);
 494                 goto err;
 495         }
 496
 497         clk_prepare_enable(wdt->clock);
 498
 499         ret = s3c2410wdt_cpufreq_register(wdt);
 500         if (ret < 0) {
 501                 dev_err(dev, "failed to register cpufreq\n");
 502                 goto err_clk;
 503         }
 504
 505         watchdog_set_drvdata(&wdt->wdt_device, wdt);
 506
 507         /* see if we can actually set the requested timer margin, and if
 508          * not, try the default value */
 509
 510         watchdog_init_timeout(&wdt->wdt_device, tmr_margin, &pdev->dev);
 511         ret = s3c2410wdt_set_heartbeat(&wdt->wdt_device,
 512                                         wdt->wdt_device.timeout);
 513         if (ret) {
 514                 started = s3c2410wdt_set_heartbeat(&wdt->wdt_device,
 515                                         CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME);
 516
 517                 if (started == 0)
 518                         dev_info(dev,
 519                            "tmr_margin value out of range, default %d used\n",
 520                                CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME);
 521                 else
 522                         dev_info(dev, "default timer value is out of range, "
 523                                                         "cannot start\n");
 524         }
 525
 526         ret = devm_request_irq(dev, wdt_irq->start, s3c2410wdt_irq, 0,
 527                                 pdev->name, pdev);
 528         if (ret != 0) {
 529                 dev_err(dev, "failed to install irq (%d)\n", ret);
 530                 goto err_cpufreq;
 531         }
 532
 533         watchdog_set_nowayout(&wdt->wdt_device, nowayout);
 534
 535         ret = watchdog_register_device(&wdt->wdt_device);
 536         if (ret) {
 537                 dev_err(dev, "cannot register watchdog (%d)\n", ret);
 538                 goto err_cpufreq;
 539         }
 540
 541         ret = s3c2410wdt_mask_and_disable_reset(wdt, false);
 542         if (ret < 0)
 543                 goto err_unregister;
 544
 545         if (tmr_atboot && started == 0) {
 546                 dev_info(dev, "starting watchdog timer\n");
 547                 s3c2410wdt_start(&wdt->wdt_device);
 548         } else if (!tmr_atboot) {
 549                 /* if we're not enabling the watchdog, then ensure it is
 550                  * disabled if it has been left running from the bootloader
 551                  * or other source */
 552
 553                 s3c2410wdt_stop(&wdt->wdt_device);
 554         }
 555
 556         platform_set_drvdata(pdev, wdt);
 557
 558         /* print out a statement of readiness */
 559
 560         wtcon = readl(wdt->reg_base + S3C2410_WTCON);
 561
 562         dev_info(dev, "watchdog %sactive, reset %sabled, irq %sabled\n",
 563                  (wtcon & S3C2410_WTCON_ENABLE) ?  "" : "in",
 564                  (wtcon & S3C2410_WTCON_RSTEN) ? "en" : "dis",
 565                  (wtcon & S3C2410_WTCON_INTEN) ? "en" : "dis");
 566
 567         return 0;
 568
 569  err_unregister:
 570         watchdog_unregister_device(&wdt->wdt_device);
 571
 572  err_cpufreq:
 573         s3c2410wdt_cpufreq_deregister(wdt);
 574
 575  err_clk:
 576         clk_disable_unprepare(wdt->clock);
 577         wdt->clock = NULL;
 578
 579  err:
 580         return ret;
 581 }
 582
 583 static int s3c2410wdt_remove(struct platform_device *dev)
 584 {
 585         int ret;
 586         struct s3c2410_wdt *wdt = platform_get_drvdata(dev);
 587
 588         ret = s3c2410wdt_mask_and_disable_reset(wdt, true);
 589         if (ret < 0)
 590                 return ret;
 591
 592         watchdog_unregister_device(&wdt->wdt_device);
 593
 594         s3c2410wdt_cpufreq_deregister(wdt);
 595
 596         clk_disable_unprepare(wdt->clock);
 597         wdt->clock = NULL;
 598
 599         return 0;
 600 }
 601
 602 static void s3c2410wdt_shutdown(struct platform_device *dev)
 603 {
 604         struct s3c2410_wdt *wdt = platform_get_drvdata(dev);
 605
 606         s3c2410wdt_mask_and_disable_reset(wdt, true);
 607
 608         s3c2410wdt_stop(&wdt->wdt_device);
 609 }
 610
 611 #ifdef CONFIG_PM_SLEEP
 612
 613 static int s3c2410wdt_suspend(struct device *dev)
 614 {
 615         int ret;
 616         struct s3c2410_wdt *wdt = dev_get_drvdata(dev);
 617
 618         /* Save watchdog state, and turn it off. */
 619         wdt->wtcon_save = readl(wdt->reg_base + S3C2410_WTCON);
 620         wdt->wtdat_save = readl(wdt->reg_base + S3C2410_WTDAT);
 621
 622         ret = s3c2410wdt_mask_and_disable_reset(wdt, true);
 623         if (ret < 0)
 624                 return ret;
 625
 626         /* Note that WTCNT doesn't need to be saved. */
 627         s3c2410wdt_stop(&wdt->wdt_device);
 628
 629         return 0;
 630 }
 631
 632 static int s3c2410wdt_resume(struct device *dev)
 633 {
 634         int ret;
 635         struct s3c2410_wdt *wdt = dev_get_drvdata(dev);
 636
 637         /* Restore watchdog state. */
 638         writel(wdt->wtdat_save, wdt->reg_base + S3C2410_WTDAT);
 639         writel(wdt->wtdat_save, wdt->reg_base + S3C2410_WTCNT);/* Reset count */
 640         writel(wdt->wtcon_save, wdt->reg_base + S3C2410_WTCON);
 641
 642         ret = s3c2410wdt_mask_and_disable_reset(wdt, false);
 643         if (ret < 0)
 644                 return ret;
 645
 646         dev_info(dev, "watchdog %sabled\n",
 647                 (wdt->wtcon_save & S3C2410_WTCON_ENABLE) ? "en" : "dis");
 648
 649         return 0;
 650 }
 651 #endif
 652
 653 static SIMPLE_DEV_PM_OPS(s3c2410wdt_pm_ops, s3c2410wdt_suspend,
 654                         s3c2410wdt_resume);
 655
 656 static struct platform_driver s3c2410wdt_driver = {
 657         .probe          = s3c2410wdt_probe,
 658         .remove         = s3c2410wdt_remove,
 659         .shutdown       = s3c2410wdt_shutdown,
 660         .id_table       = s3c2410_wdt_ids,
 661         .driver         = {
 662                 .owner  = THIS_MODULE,
 663                 .name   = "s3c2410-wdt",
 664                 .pm     = &s3c2410wdt_pm_ops,
 665                 .of_match_table = of_match_ptr(s3c2410_wdt_match),
 666         },
 667 };
 668
 669 module_platform_driver(s3c2410wdt_driver);
 670
 671 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, "
 672               "Dimitry Andric <dimitry.andric@tomtom.com>");
 673 MODULE_DESCRIPTION("S3C2410 Watchdog Device Driver");
 674 MODULE_LICENSE("GPL");