3 * Texas Instruments, <www.ti.com>
4 * Richard Woodruff <r-woodruff2@ti.com>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 #ifndef _OMAP24XX_CLOCKS_H_
22 #define _OMAP24XX_CLOCKS_H_
24 #define COMMIT_DIVIDERS 0x1
26 #define MODE_BYPASS_FAST 0x2
29 #define DPLL_LOCK 0x1 /* stay in bypass mode */
31 #define DPLL_LOCK 0x3 /* DPLL lock */
34 /****************************************************************************;
37 ; Enable clocks and DPLL for:
38 ; DPLL=300, DPLLout=600 M=1,N=50 CM_CLKSEL1_PLL[21:8] 12/2*50
39 ; Core=600 (core domain) DPLLx2 CM_CLKSEL2_PLL[1:0]
40 ; MPUF=300 (mpu domain) 2 CM_CLKSEL_MPU[4:0]
41 ; DSPF=200 (dsp domain) 3 CM_CLKSEL_DSP[4:0]
42 ; DSPI=100 6 CM_CLKSEL_DSP[6:5]
43 ; DSP_S bypass CM_CLKSEL_DSP[7]
44 ; IVAF=200 (dsp domain) 3 CM_CLKSEL_DSP[12:8]
48 ; IVA_S bypass CM_CLKSEL_DSP[13]
49 ; GFXF=50 (gfx domain) 12 CM_CLKSEL_FGX[2:0]
50 ; SSI_SSRF=200 3 CM_CLKSEL1_CORE[24:20]
52 ; L3=100Mhz (sdram) 6 CM_CLKSEL1_CORE[4:0]
54 ; C_L4_USB=50 12 CM_CLKSEL1_CORE[6:5]
55 ***************************************************************************/
56 #define II_DPLL_OUT_X2 0x2 /* x2 core out */
57 #define II_MPU_DIV 0x2 /* mpu = core/2 */
58 #define II_DSP_DIV 0x343 /* dsp & iva divider */
59 #define II_GFX_DIV 0x2
60 #define II_BUS_DIV 0x04600C26
61 #define II_BUS_DIV_ES1 0x04601026
62 #define II_DPLL_300 0x01832100
64 /* set defaults for boot up */
66 #define DPLL_OUT II_DPLL_OUT_X2
67 #define MPU_DIV II_MPU_DIV
68 #define DSP_DIV II_DSP_DIV
69 #define GFX_DIV II_GFX_DIV
70 #define BUS_DIV II_BUS_DIV
71 #define BUS_DIV_ES1 II_BUS_DIV_ES1
72 #define DPLL_VAL II_DPLL_300
75 /* lock delay time out */
76 #define LDELAY 12000000