2 * linux/include/asm-arm/arch-netarm/netarm_registers.h
4 * Copyright (C) 2000, 2001 NETsilicon, Inc.
5 * Copyright (C) 2000, 2001 WireSpeed Communications Corporation
7 * This software is copyrighted by WireSpeed. LICENSEE agrees that
8 * it will not delete this copyright notice, trademarks or protective
9 * notices from any copy made by LICENSEE.
11 * This software is provided "AS-IS" and any express or implied
12 * warranties or conditions, including but not limited to any
13 * implied warranties of merchantability and fitness for a particular
14 * purpose regarding this software. In no event shall WireSpeed
15 * be liable for any indirect, consequential, or incidental damages,
16 * loss of profits or revenue, loss of use or data, or interruption
17 * of business, whether the alleged damages are labeled in contract,
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2 of the License, or
23 * (at your option) any later version.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
29 * author(s) : Joe deBlaquiere
32 #ifndef __NET_ARM_REGISTERS_H
33 #define __NET_ARM_REGISTERS_H
37 /* fundamental constants : */
38 /* the input crystal/clock frequency ( in Hz ) */
39 #define NETARM_XTAL_FREQ_25MHz (18432000)
40 #define NETARM_XTAL_FREQ_33MHz (23698000)
41 #define NETARM_XTAL_FREQ_EMLIN1 (20000000)
43 /* the frequency of SYS_CLK */
44 #if defined(CONFIG_NETARM_EMLIN)
46 /* EMLIN board: 33 MHz (exp.) */
47 #define NETARM_PLL_COUNT_VAL 6
48 #define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_25MHz
50 #elif defined(CONFIG_NETARM_NET40_REV2)
52 /* NET+40 Rev2 boards: 33 MHz (with NETARM_XTAL_FREQ_25MHz) */
53 #define NETARM_PLL_COUNT_VAL 6
54 #define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_25MHz
56 #elif defined(CONFIG_NETARM_NET40_REV4)
58 /* NET+40 Rev4 boards with EDO must clock slower: 25 MHz (with
59 NETARM_XTAL_FREQ_25MHz) 4 */
60 #define NETARM_PLL_COUNT_VAL 4
61 #define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_25MHz
63 #else /* CONFIG_NETARM_NET50 */
65 /* NET+50 boards: 40 MHz (with NETARM_XTAL_FREQ_25MHz) */
66 #define NETARM_PLL_COUNT_VAL 8
67 #define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_25MHz
71 /* #include "arm_registers.h" */
72 #include <asm/arch/netarm_gen_module.h>
73 #include <asm/arch/netarm_mem_module.h>
74 #include <asm/arch/netarm_ser_module.h>
75 #include <asm/arch/netarm_eni_module.h>
76 #include <asm/arch/netarm_dma_module.h>
77 #include <asm/arch/netarm_eth_module.h>