2 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
6 * ----------------------------------------------------------------------------
10 * TI DaVinci (DM644X) EMAC peripheral driver header for DV-EVM
12 * Copyright (C) 2005 Texas Instruments.
14 * ----------------------------------------------------------------------------
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
29 * ----------------------------------------------------------------------------
32 * ver. 1.0: Sep 2005, TI PSP Team - Created EMAC version for uBoot.
36 #ifndef _DM644X_EMAC_H_
37 #define _DM644X_EMAC_H_
39 #include <asm/arch/hardware.h>
41 #ifdef CONFIG_SOC_DM365
42 #define EMAC_BASE_ADDR (0x01d07000)
43 #define EMAC_WRAPPER_BASE_ADDR (0x01d0a000)
44 #define EMAC_WRAPPER_RAM_ADDR (0x01d08000)
45 #define EMAC_MDIO_BASE_ADDR (0x01d0b000)
47 #define EMAC_BASE_ADDR (0x01c80000)
48 #define EMAC_WRAPPER_BASE_ADDR (0x01c81000)
49 #define EMAC_WRAPPER_RAM_ADDR (0x01c82000)
50 #define EMAC_MDIO_BASE_ADDR (0x01c84000)
53 #ifdef CONFIG_SOC_DM646X
54 /* MDIO module input frequency */
55 #define EMAC_MDIO_BUS_FREQ 76500000
56 /* MDIO clock output frequency */
57 #define EMAC_MDIO_CLOCK_FREQ 2500000 /* 2.5 MHz */
58 #elif defined(CONFIG_SOC_DM365)
59 /* MDIO module input frequency */
60 #define EMAC_MDIO_BUS_FREQ 121500000
61 /* MDIO clock output frequency */
62 #define EMAC_MDIO_CLOCK_FREQ 2200000 /* 2.2 MHz */
64 /* MDIO module input frequency */
65 #define EMAC_MDIO_BUS_FREQ 99000000 /* PLL/6 - 99 MHz */
66 /* MDIO clock output frequency */
67 #define EMAC_MDIO_CLOCK_FREQ 2000000 /* 2.0 MHz */
70 /* PHY mask - set only those phy number bits where phy is/can be connected */
71 #define EMAC_MDIO_PHY_NUM 1
72 #define EMAC_MDIO_PHY_MASK (1 << EMAC_MDIO_PHY_NUM)
74 /* Ethernet Min/Max packet size */
75 #define EMAC_MIN_ETHERNET_PKT_SIZE 60
76 #define EMAC_MAX_ETHERNET_PKT_SIZE 1518
77 #define EMAC_PKT_ALIGN 18 /* 1518 + 18 = 1536 (packet aligned on 32 byte boundry) */
79 /* Number of RX packet buffers
80 * NOTE: Only 1 buffer supported as of now
82 #define EMAC_MAX_RX_BUFFERS 10
85 /***********************************************
86 ******** Internally used macros ***************
87 ***********************************************/
92 /* Each descriptor occupies 4 words, lets start RX desc's at 0 and
93 * reserve space for 64 descriptors max
95 #define EMAC_RX_DESC_BASE 0x0
96 #define EMAC_TX_DESC_BASE 0x1000
98 /* EMAC Teardown value */
99 #define EMAC_TEARDOWN_VALUE 0xfffffffc
101 /* MII Status Register */
102 #define MII_STATUS_REG 1
104 /* Number of statistics registers */
105 #define EMAC_NUM_STATS 36
108 /* EMAC Descriptor */
109 typedef volatile struct _emac_desc
111 u_int32_t next; /* Pointer to next descriptor in chain */
112 u_int8_t *buffer; /* Pointer to data buffer */
113 u_int32_t buff_off_len; /* Buffer Offset(MSW) and Length(LSW) */
114 u_int32_t pkt_flag_len; /* Packet Flags(MSW) and Length(LSW) */
117 /* CPPI bit positions */
118 #define EMAC_CPPI_SOP_BIT (0x80000000)
119 #define EMAC_CPPI_EOP_BIT (0x40000000)
120 #define EMAC_CPPI_OWNERSHIP_BIT (0x20000000)
121 #define EMAC_CPPI_EOQ_BIT (0x10000000)
122 #define EMAC_CPPI_TEARDOWN_COMPLETE_BIT (0x08000000)
123 #define EMAC_CPPI_PASS_CRC_BIT (0x04000000)
125 #define EMAC_CPPI_RX_ERROR_FRAME (0x03fc0000)
127 #define EMAC_MACCONTROL_MIIEN_ENABLE (0x20)
128 #define EMAC_MACCONTROL_FULLDUPLEX_ENABLE (0x1)
129 #define EMAC_MACCONTROL_GIGABIT_ENABLE (1 << 7)
130 #define EMAC_MACCONTROL_GIGFORCE (1 << 17)
132 #define EMAC_RXMBPENABLE_RXCAFEN_ENABLE (0x200000)
133 #define EMAC_RXMBPENABLE_RXBROADEN (0x2000)
136 #define MDIO_CONTROL_IDLE (0x80000000)
137 #define MDIO_CONTROL_ENABLE (0x40000000)
138 #define MDIO_CONTROL_FAULT_ENABLE (0x40000)
139 #define MDIO_CONTROL_FAULT (0x80000)
140 #define MDIO_USERACCESS0_GO (0x80000000)
141 #define MDIO_USERACCESS0_WRITE_READ (0x0)
142 #define MDIO_USERACCESS0_WRITE_WRITE (0x40000000)
143 #define MDIO_USERACCESS0_ACK (0x20000000)
145 /* Ethernet MAC Registers Structure */
156 dv_reg TXINTSTATMASKED;
158 dv_reg TXINTMASKCLEAR;
162 dv_reg RXINTSTATMASKED;
164 dv_reg RXINTMASKCLEAR;
165 dv_reg MACINTSTATRAW;
166 dv_reg MACINTSTATMASKED;
167 dv_reg MACINTMASKSET;
168 dv_reg MACINTMASKCLEAR;
172 dv_reg RXUNICASTCLEAR;
174 dv_reg RXBUFFEROFFSET;
175 dv_reg RXFILTERLOWTHRESH;
177 dv_reg RX0FLOWTHRESH;
178 dv_reg RX1FLOWTHRESH;
179 dv_reg RX2FLOWTHRESH;
180 dv_reg RX3FLOWTHRESH;
181 dv_reg RX4FLOWTHRESH;
182 dv_reg RX5FLOWTHRESH;
183 dv_reg RX6FLOWTHRESH;
184 dv_reg RX7FLOWTHRESH;
185 dv_reg RX0FREEBUFFER;
186 dv_reg RX1FREEBUFFER;
187 dv_reg RX2FREEBUFFER;
188 dv_reg RX3FREEBUFFER;
189 dv_reg RX4FREEBUFFER;
190 dv_reg RX5FREEBUFFER;
191 dv_reg RX6FREEBUFFER;
192 dv_reg RX7FREEBUFFER;
210 dv_reg RXBCASTFRAMES;
211 dv_reg RXMCASTFRAMES;
212 dv_reg RXPAUSEFRAMES;
214 dv_reg RXALIGNCODEERRORS;
220 dv_reg RXQOSFILTERED;
223 dv_reg TXBCASTFRAMES;
224 dv_reg TXMCASTFRAMES;
225 dv_reg TXPAUSEFRAMES;
230 dv_reg TXEXCESSIVECOLL;
233 dv_reg TXCARRIERSENSE;
239 dv_reg FRAME512T1023;
242 dv_reg RXSOFOVERRUNS;
243 dv_reg RXMOFOVERRUNS;
244 dv_reg RXDMAOVERRUNS;
284 /* EMAC Wrapper Registers Structure */
286 #if defined(CONFIG_SOC_DM646X) || defined(CONFIG_SOC_DM365)
291 u_int8_t RSVD0[4100];
297 /* EMAC MDIO Registers Structure */
304 dv_reg LINKINTMASKED;
307 dv_reg USERINTMASKED;
308 dv_reg USERINTMASKSET;
309 dv_reg USERINTMASKCLEAR;
317 int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data);
318 int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data);
323 int (*init)(int phy_addr);
324 int (*is_phy_connected)(int phy_addr);
325 int (*get_link_speed)(int phy_addr);
326 int (*auto_negotiate)(int phy_addr);
329 #define PHY_LXT972 (0x001378e2)
330 int lxt972_is_phy_connected(int phy_addr);
331 int lxt972_get_link_speed(int phy_addr);
332 int lxt972_init_phy(int phy_addr);
333 int lxt972_auto_negotiate(int phy_addr);
335 #define PHY_DP83848 (0x20005c90)
336 int dp83848_is_phy_connected(int phy_addr);
337 int dp83848_get_link_speed(int phy_addr);
338 int dp83848_init_phy(int phy_addr);
339 int dp83848_auto_negotiate(int phy_addr);
341 #endif /* _DM644X_EMAC_H_ */