2 * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
13 #ifndef __MACH_MX25_IOMUX_H__
14 #define __MACH_MX25_IOMUX_H__
16 #include <asm/arch/mx25.h>
19 * @file mach-mx25/iomux.h
21 * @brief I/O Muxing control definitions and functions
30 typedef enum iomux_pin_config {
31 MUX_CONFIG_FUNC = 0, /*!< used as function */
32 MUX_CONFIG_ALT1, /*!< used as alternate function 1 */
33 MUX_CONFIG_ALT2, /*!< used as alternate function 2 */
34 MUX_CONFIG_ALT3, /*!< used as alternate function 3 */
35 MUX_CONFIG_ALT4, /*!< used as alternate function 4 */
36 MUX_CONFIG_ALT5, /*!< used as alternate function 5 */
37 MUX_CONFIG_ALT6, /*!< used as alternate function 6 */
38 MUX_CONFIG_ALT7, /*!< used as alternate function 7 */
39 MUX_CONFIG_SION = 0x1 << 4, /*!< used as LOOPBACK:MUX SION bit */
40 MUX_CONFIG_GPIO = MUX_CONFIG_ALT5, /*!< used as GPIO */
47 typedef enum iomux_pad_config {
48 PAD_CTL_DRV_3_3V = 0x0 << 13,
49 PAD_CTL_DRV_1_8V = 0x1 << 13,
50 PAD_CTL_HYS_CMOS = 0x0 << 8,
51 PAD_CTL_HYS_SCHMITZ = 0x1 << 8,
52 PAD_CTL_PKE_NONE = 0x0 << 7,
53 PAD_CTL_PKE_ENABLE = 0x1 << 7,
54 PAD_CTL_PUE_KEEPER = 0x0 << 6,
55 PAD_CTL_PUE_PUD = 0x1 << 6,
56 PAD_CTL_100K_PD = 0x0 << 4,
57 PAD_CTL_47K_PU = 0x1 << 4,
58 PAD_CTL_100K_PU = 0x2 << 4,
59 PAD_CTL_22K_PU = 0x3 << 4,
60 PAD_CTL_ODE_CMOS = 0x0 << 3,
61 PAD_CTL_ODE_OpenDrain = 0x1 << 3,
62 PAD_CTL_DRV_NORMAL = 0x0 << 1,
63 PAD_CTL_DRV_HIGH = 0x1 << 1,
64 PAD_CTL_DRV_MAX = 0x2 << 1,
65 PAD_CTL_SRE_SLOW = 0x0 << 0,
66 PAD_CTL_SRE_FAST = 0x1 << 0
70 * IOMUX general purpose functions
73 typedef enum iomux_gp_func {
74 MUX_SDCTL_CSD0_SEL = 0x1 << 0,
75 MUX_SDCTL_CSD1_SEL = 0x1 << 1,
79 * IOMUX SELECT_INPUT register index
80 * Base register is IOMUXSW_INPUT_CTL in iomux.c
82 typedef enum iomux_input_select {
83 MUX_IN_AUDMUX_P4_INPUT_DA_AMX = 0,
84 MUX_IN_AUDMUX_P4_INPUT_DB_AMX,
85 MUX_IN_AUDMUX_P4_INPUT_RXCLK_AMX,
86 MUX_IN_AUDMUX_P4_INPUT_RXFS_AMX,
87 MUX_IN_AUDMUX_P4_INPUT_TXCLK_AMX,
88 MUX_IN_AUDMUX_P4_INPUT_TXFS_AMX,
89 MUX_IN_AUDMUX_P7_INPUT_DA_AMX,
90 MUX_IN_AUDMUX_P7_INPUT_TXFS_AMX,
91 MUX_IN_CAN1_IPP_IND_CANRX,
92 MUX_IN_CAN2_IPP_IND_CANRX,
93 MUX_IN_CSI_IPP_CSI_D_0,
94 MUX_IN_CSI_IPP_CSI_D_1,
95 MUX_IN_CSPI1_IPP_IND_SS3_B,
96 MUX_IN_CSPI2_IPP_CSPI_CLK_IN,
97 MUX_IN_CSPI2_IPP_IND_DATAREADY_B,
98 MUX_IN_CSPI2_IPP_IND_MISO,
99 MUX_IN_CSPI2_IPP_IND_MOSI,
100 MUX_IN_CSPI2_IPP_IND_SS0_B,
101 MUX_IN_CSPI2_IPP_IND_SS1_B,
102 MUX_IN_CSPI3_IPP_CSPI_CLK_IN,
103 MUX_IN_CSPI3_IPP_IND_DATAREADY_B,
104 MUX_IN_CSPI3_IPP_IND_MISO,
105 MUX_IN_CSPI3_IPP_IND_MOSI,
106 MUX_IN_CSPI3_IPP_IND_SS0_B,
107 MUX_IN_CSPI3_IPP_IND_SS1_B,
108 MUX_IN_CSPI3_IPP_IND_SS2_B,
109 MUX_IN_CSPI3_IPP_IND_SS3_B,
110 MUX_IN_ESDHC1_IPP_DAT4_IN,
111 MUX_IN_ESDHC1_IPP_DAT5_IN,
112 MUX_IN_ESDHC1_IPP_DAT6_IN,
113 MUX_IN_ESDHC1_IPP_DAT7_IN,
114 MUX_IN_ESDHC2_IPP_CARD_CLK_IN,
115 MUX_IN_ESDHC2_IPP_CMD_IN,
116 MUX_IN_ESDHC2_IPP_DAT0_IN,
117 MUX_IN_ESDHC2_IPP_DAT1_IN,
118 MUX_IN_ESDHC2_IPP_DAT2_IN,
119 MUX_IN_ESDHC2_IPP_DAT3_IN,
120 MUX_IN_ESDHC2_IPP_DAT4_IN,
121 MUX_IN_ESDHC2_IPP_DAT5_IN,
122 MUX_IN_ESDHC2_IPP_DAT6_IN,
123 MUX_IN_ESDHC2_IPP_DAT7_IN,
126 MUX_IN_FEC_FEC_RDATA_2,
127 MUX_IN_FEC_FEC_RDATA_3,
128 MUX_IN_FEC_FEC_RX_CLK,
129 MUX_IN_FEC_FEC_RX_ER,
130 MUX_IN_I2C2_IPP_SCL_IN,
131 MUX_IN_I2C2_IPP_SDA_IN,
132 MUX_IN_I2C3_IPP_SCL_IN,
133 MUX_IN_I2C3_IPP_SDA_IN,
134 MUX_IN_KPP_IPP_IND_COL_4,
135 MUX_IN_KPP_IPP_IND_COL_5,
136 MUX_IN_KPP_IPP_IND_COL_6,
137 MUX_IN_KPP_IPP_IND_COL_7,
138 MUX_IN_KPP_IPP_IND_ROW_4,
139 MUX_IN_KPP_IPP_IND_ROW_5,
140 MUX_IN_KPP_IPP_IND_ROW_6,
141 MUX_IN_KPP_IPP_IND_ROW_7,
142 MUX_IN_SIM1_PIN_SIM_RCVD1_IN,
143 MUX_IN_SIM1_PIN_SIM_SIMPD1,
144 MUX_IN_SIM1_SIM_RCVD1_IO,
145 MUX_IN_SIM2_PIN_SIM_RCVD1_IN,
146 MUX_IN_SIM2_PIN_SIM_SIMPD1,
147 MUX_IN_SIM2_SIM_RCVD1_IO,
148 MUX_IN_UART3_IPP_UART_RTS_B,
149 MUX_IN_UART3_IPP_UART_RXD_MUX,
150 MUX_IN_UART4_IPP_UART_RTS_B,
151 MUX_IN_UART4_IPP_UART_RXD_MUX,
152 MUX_IN_UART5_IPP_UART_RTS_B,
153 MUX_IN_UART5_IPP_UART_RXD_MUX,
154 MUX_IN_USB_TOP_IPP_IND_OTG_USB_OC,
155 MUX_IN_USB_TOP_IPP_IND_UH2_USB_OC,
156 } iomux_input_select_t;
159 * IOMUX input functions
160 * SW_SELECT_INPUT bits 2-0
162 typedef enum iomux_input_config {
163 INPUT_CTL_PATH0 = 0x0,
174 * Request ownership for an IO pin. This function has to be the first one
175 * being called before that pin is used. The caller has to check the
176 * return value to make sure it returns 0.
178 * @param pin a name defined by \b iomux_pin_name_t
179 * @param cfg an input function as defined in \b #iomux_pin_cfg_t
181 * @return 0 if successful; Non-zero otherwise
183 int mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg);
186 * Release ownership for an IO pin
188 * @param pin a name defined by \b iomux_pin_name_t
189 * @param cfg an input function as defined in \b #iomux_pin_cfg_t
191 void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg);
194 * This function enables/disables the general purpose function for a particular
197 * @param gp one signal as defined in \b #iomux_gp_func_t
198 * @param en \b #true to enable; \b #false to disable
200 void mxc_iomux_set_gpr(iomux_gp_func_t gp, int en);
203 * This function configures the pad value for a IOMUX pin.
205 * @param pin a pin number as defined in \b #iomux_pin_name_t
206 * @param config the ORed value of elements defined in \b
207 * #iomux_pad_config_t
209 void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config);
212 * This function configures input path.
214 * @param input index of input select register as defined in \b
215 * #iomux_input_select_t
216 * @param config the binary value of elements defined in \b
219 void mxc_iomux_set_input(iomux_input_select_t input, u32 config);