2 * fec.h -- Fast Ethernet Controller definitions
4 * Some definitions copied from commproc.h for MPC8xx:
5 * MPC8xx Communication Processor Module.
6 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
8 * Add FEC Structure and definitions
9 * Copyright 2004-2010 Freescale Semiconductor, Inc.
10 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
12 * See file CREDITS for list of people who contributed to this
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 extern int fec_get_mac_addr(unsigned char *mac);
38 /* Buffer descriptors used FEC.
40 typedef struct cpm_buf_desc {
41 ushort cbd_datlen; /* Data length in buffer */
42 ushort cbd_sc; /* Status and Control */
43 ulong cbd_bufaddr; /* Buffer address in host memory */
46 #define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */
47 #define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
48 #define BD_SC_WRAP ((ushort)0x2000)/* Last buffer descriptor */
49 #define BD_SC_INTRPT ((ushort)0x1000)/* Interrupt on change */
50 #define BD_SC_LAST ((ushort)0x0800)/* Last buffer in frame */
51 #define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */
52 #define BD_SC_CM ((ushort)0x0200) /* Continous mode */
53 #define BD_SC_ID ((ushort)0x0100)/* Rec'd too many idles */
54 #define BD_SC_P ((ushort)0x0100) /* xmt preamble */
55 #define BD_SC_BR ((ushort)0x0020) /* Break received */
56 #define BD_SC_FR ((ushort)0x0010) /* Framing error */
57 #define BD_SC_PR ((ushort)0x0008) /* Parity error */
58 #define BD_SC_OV ((ushort)0x0002) /* Overrun */
59 #define BD_SC_CD ((ushort)0x0001)/* Carrier Detect lost */
61 /* Buffer descriptor control/status used by Ethernet receive.
63 #define BD_ENET_RX_EMPTY ((ushort)0x8000)
64 #define BD_ENET_RX_RO1 ((ushort)0x4000)
65 #define BD_ENET_RX_WRAP ((ushort)0x2000)
66 #define BD_ENET_RX_INTR ((ushort)0x1000)
67 #define BD_ENET_RX_RO2 BD_ENET_RX_INTR
68 #define BD_ENET_RX_LAST ((ushort)0x0800)
69 #define BD_ENET_RX_FIRST ((ushort)0x0400)
70 #define BD_ENET_RX_MISS ((ushort)0x0100)
71 #define BD_ENET_RX_BC ((ushort)0x0080)
72 #define BD_ENET_RX_MC ((ushort)0x0040)
73 #define BD_ENET_RX_LG ((ushort)0x0020)
74 #define BD_ENET_RX_NO ((ushort)0x0010)
75 #define BD_ENET_RX_SH ((ushort)0x0008)
76 #define BD_ENET_RX_CR ((ushort)0x0004)
77 #define BD_ENET_RX_OV ((ushort)0x0002)
78 #define BD_ENET_RX_CL ((ushort)0x0001)
79 #define BD_ENET_RX_TR BD_ENET_RX_CL
80 #define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */
82 /* Buffer descriptor control/status used by Ethernet transmit.
84 #define BD_ENET_TX_READY ((ushort)0x8000)
85 #define BD_ENET_TX_PAD ((ushort)0x4000)
86 #define BD_ENET_TX_TO1 BD_ENET_TX_PAD
87 #define BD_ENET_TX_WRAP ((ushort)0x2000)
88 #define BD_ENET_TX_INTR ((ushort)0x1000)
89 #define BD_ENET_TX_TO2 BD_ENET_TX_INTR_
90 #define BD_ENET_TX_LAST ((ushort)0x0800)
91 #define BD_ENET_TX_TC ((ushort)0x0400)
92 #define BD_ENET_TX_DEF ((ushort)0x0200)
93 #define BD_ENET_TX_ABC BD_ENET_TX_DEF
94 #define BD_ENET_TX_HB ((ushort)0x0100)
95 #define BD_ENET_TX_LC ((ushort)0x0080)
96 #define BD_ENET_TX_RL ((ushort)0x0040)
97 #define BD_ENET_TX_RCMASK ((ushort)0x003c)
98 #define BD_ENET_TX_UN ((ushort)0x0002)
99 #define BD_ENET_TX_CSL ((ushort)0x0001)
100 #define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
102 /*********************************************************************
103 * Fast Ethernet Controller (FEC)
104 *********************************************************************/
105 /* FEC private information */
108 volatile void *iobase;
113 cbd_t *rxbd; /* Rx BD */
114 cbd_t *txbd; /* Tx BD */
118 #ifdef CONFIG_ARCH_MMU
119 char *rxbuf[PKTBUFSRX];
122 struct fec_info_s *next;
125 /* Register read/write struct */
168 /*********************************************************************
169 * Fast Ethernet Controller (FEC)
170 *********************************************************************/
171 /* Bit definitions and macros for FEC_EIR */
172 #define FEC_EIR_CLEAR_ALL (0xFFF80000)
173 #define FEC_EIR_HBERR (0x80000000)
174 #define FEC_EIR_BABR (0x40000000)
175 #define FEC_EIR_BABT (0x20000000)
176 #define FEC_EIR_GRA (0x10000000)
177 #define FEC_EIR_TXF (0x08000000)
178 #define FEC_EIR_TXB (0x04000000)
179 #define FEC_EIR_RXF (0x02000000)
180 #define FEC_EIR_RXB (0x01000000)
181 #define FEC_EIR_MII (0x00800000)
182 #define FEC_EIR_EBERR (0x00400000)
183 #define FEC_EIR_LC (0x00200000)
184 #define FEC_EIR_RL (0x00100000)
185 #define FEC_EIR_UN (0x00080000)
187 /* Bit definitions and macros for FEC_RDAR */
188 #define FEC_RDAR_R_DES_ACTIVE (0x01000000)
190 /* Bit definitions and macros for FEC_TDAR */
191 #define FEC_TDAR_X_DES_ACTIVE (0x01000000)
193 /* Bit definitions and macros for FEC_ECR */
194 #define FEC_ECR_ETHER_EN (0x00000002)
195 #define FEC_ECR_RESET (0x00000001)
197 /* Bit definitions and macros for FEC_MMFR */
198 #define FEC_MMFR_DATA(x) (((x)&0xFFFF))
199 #define FEC_MMFR_ST(x) (((x)&0x03)<<30)
200 #define FEC_MMFR_ST_01 (0x40000000)
201 #define FEC_MMFR_OP_RD (0x20000000)
202 #define FEC_MMFR_OP_WR (0x10000000)
203 #define FEC_MMFR_PA(x) (((x)&0x1F)<<23)
204 #define FEC_MMFR_RA(x) (((x)&0x1F)<<18)
205 #define FEC_MMFR_TA(x) (((x)&0x03)<<16)
206 #define FEC_MMFR_TA_10 (0x00020000)
208 /* Bit definitions and macros for FEC_MSCR */
209 #define FEC_MSCR_DIS_PREAMBLE (0x00000080)
210 #define FEC_MSCR_MII_SPEED(x) (((x)&0x3F)<<1)
212 /* Bit definitions and macros for FEC_MIBC */
213 #define FEC_MIBC_MIB_DISABLE (0x80000000)
214 #define FEC_MIBC_MIB_IDLE (0x40000000)
216 /* Bit definitions and macros for FEC_RCR */
217 #define FEC_RCR_GRS (0x80000000)
218 #define FEC_RCR_NO_LGTH_CHECK (0x40000000)
219 #define FEC_RCR_MAX_FL(x) (((x)&0x7FF)<<16)
220 #define FEC_RCR_CNTL_FRM_ENA (0x00008000)
221 #define FEC_RCR_CRC_FWD (0x00004000)
222 #define FEC_RCR_PAUSE_FWD (0x00002000)
223 #define FEC_RCR_PAD_EN (0x00001000)
224 #define FEC_RCR_RMII_ECHO (0x00000800)
225 #define FEC_RCR_RMII_LOOP (0x00000400)
226 #define FEC_RCR_RMII_10T (0x00000200)
227 #define FEC_RCR_RMII_MODE (0x00000100)
228 #define FEC_RCR_SGMII_ENA (0x00000080)
229 #define FEC_RCR_RGMII_ENA (0x00000040)
230 #define FEC_RCR_FCE (0x00000020)
231 #define FEC_RCR_BC_REJ (0x00000010)
232 #define FEC_RCR_PROM (0x00000008)
233 #define FEC_RCR_MII_MODE (0x00000004)
234 #define FEC_RCR_DRT (0x00000002)
235 #define FEC_RCR_LOOP (0x00000001)
237 /* Bit definitions and macros for FEC_TCR */
238 #define FEC_TCR_RFC_PAUSE (0x00000010)
239 #define FEC_TCR_TFC_PAUSE (0x00000008)
240 #define FEC_TCR_FDEN (0x00000004)
241 #define FEC_TCR_HBC (0x00000002)
242 #define FEC_TCR_GTS (0x00000001)
244 /* Bit definitions and macros for FEC_PAUR */
245 #define FEC_PAUR_PADDR2(x) (((x)&0xFFFF)<<16)
246 #define FEC_PAUR_TYPE(x) ((x)&0xFFFF)
248 /* Bit definitions and macros for FEC_OPD */
249 #define FEC_OPD_PAUSE_DUR(x) (((x)&0x0000FFFF)<<0)
250 #define FEC_OPD_OPCODE(x) (((x)&0x0000FFFF)<<16)
252 /* Bit definitions and macros for FEC_TFWR */
253 #define FEC_TFWR_X_WMRK(x) ((x)&0x03)
254 #define FEC_TFWR_X_WMRK_64 (0x01)
255 #define FEC_TFWR_X_WMRK_128 (0x02)
256 #define FEC_TFWR_X_WMRK_192 (0x03)
258 /* Bit definitions and macros for FEC_FRBR */
259 #define FEC_FRBR_R_BOUND(x) (((x)&0xFF)<<2)
261 /* Bit definitions and macros for FEC_FRSR */
262 #define FEC_FRSR_R_FSTART(x) (((x)&0xFF)<<2)
264 /* Bit definitions and macros for FEC_ERDSR */
265 #define FEC_ERDSR_R_DES_START(x) (((x)&0x3FFFFFFF)<<2)
267 /* Bit definitions and macros for FEC_ETDSR */
268 #define FEC_ETDSR_X_DES_START(x) (((x)&0x3FFFFFFF)<<2)
270 /* Bit definitions and macros for FEC_EMRBR */
271 #define FEC_EMRBR_R_BUF_SIZE(x) (((x)&0x7F)<<4)
273 #define FEC_RESET_DELAY 100
274 #define FEC_RX_TOUT 100
276 #define FEC_MAX_TIMEOUT 50000
277 #define FEC_TIMEOUT_TICKET 2
282 int mxc_fec_initialize(bd_t *bis);